Interconnect structures and methods of forming the same

Abstract

The present application provides an interconnection structure and a forming method thereof, at least one air gap is formed between adjacent first interconnection structure and second interconnection structure, the air gap penetrates the first covering layer and extends upward into the second dielectric layer, and extends downward into the first dielectric layer. At least one air gap is added on the metal atom diffusion path, the metal atom diffuses in the first dielectric layer or the second dielectric layer by bypassing the air gap, which plays a role in extending the metal atom diffusion path, which is equivalent to increasing the spacing between the adjacent first interconnection structure and the second interconnection structure, and achieving the purpose of improving the time breakdown of the intermetallic dielectric layer. And because the time breakdown of the intermetallic dielectric layer is improved, it means that the density of the first interconnection structure and the second interconnection structure can be improved, thereby the chip integration can be improved, and at the same time because the air gap is introduced, the dielectric constant of the air gap is less than the dielectric constant of the first dielectric layer and the dielectric constant of the second dielectric layer, the capacitive reactance is reduced, and the signal delay is reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an interconnect structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, inter-metal dielectric (IMD) layers serve to isolate metal interconnects, especially in advanced copper back-end processes. Electrically, the capacitance of these dielectric films is decreasing to reduce capacitive reactance, and the smallest dielectric material is vacuum or air, which has a dielectric constant (k) of 1. However, the processing of Cu damascene and subsequent packaging processes must be considered. Therefore, vacuum or air cannot be used exclusively for IMD layers, and mainstream processes primarily use low-k dielectric materials. From a reliability perspective, the failure of low-k dielectric layers is IMD TDDB (Time Dependent Dielectric Breakdown). As processes shrink, the metal space decreases, and the thickness of low-k dielectric layers also decreases. The issue of inter-metal dielectric breakdown over time will become a bottleneck in process miniaturization. Summary of the Invention

[0003] This invention provides an interconnection structure, comprising:

[0004] A first dielectric layer, wherein a first interconnect structure and a second interconnect structure are formed in the first dielectric layer, and the first interconnect structure and the second interconnect structure are separated from each other;

[0005] A first cover layer covers the upper surface of the first interconnect structure, the upper surface of the second interconnect structure, and the upper surface of the first dielectric layer;

[0006] A second dielectric layer covers the first cover layer; and

[0007] An air gap is located between the first interconnect structure and the second interconnect structure, extends through the first cover layer and upward into the second dielectric layer, and downward into the first dielectric layer.

[0008] Based on the same inventive concept, the present invention also provides a method for forming an interconnection structure, comprising:

[0009] A first dielectric layer is provided, in which a first interconnect structure and a second interconnect structure are formed, the first interconnect structure and the second interconnect structure are separated from each other, and a first cover layer covers the upper surface of the first interconnect structure, the upper surface of the second interconnect structure and the upper surface of the first dielectric layer.

[0010] An etching process is performed to form a trench between the first interconnect structure and the second interconnect structure, the trench penetrating the first cover layer and extending downward into the first dielectric layer;

[0011] A second dielectric layer is formed, which covers the first cover layer and partially fills the trench to form an air gap at the trench. The air gap extends through the first cover layer and upward into the second dielectric layer, and downward into the first dielectric layer.

[0012] Based on the same inventive concept, the present invention also provides a chip comprising an interconnect structure, the interconnect structure comprising: a first dielectric layer, wherein a first interconnect structure and a second interconnect structure are formed in the first dielectric layer, the first interconnect structure and the second interconnect structure being separate from each other; a first cover layer covering the upper surface of the first interconnect structure, the upper surface of the second interconnect structure and the upper surface of the first dielectric layer; a second dielectric layer covering the first cover layer; and an air gap located between the first interconnect structure and the second interconnect structure, penetrating the first cover layer and extending upward into the second dielectric layer, and downward into the first dielectric layer.

[0013] Based on the same inventive concept, the present invention also provides an electronic device comprising an interconnect structure, the interconnect structure comprising: a first dielectric layer, wherein a first interconnect structure and a second interconnect structure are formed in the first dielectric layer, the first interconnect structure and the second interconnect structure being separate from each other; a first cover layer covering the upper surface of the first interconnect structure, the upper surface of the second interconnect structure and the upper surface of the first dielectric layer; a second dielectric layer covering the first cover layer; and an air gap located between the first interconnect structure and the second interconnect structure, penetrating the first cover layer and extending upward into the second dielectric layer, and downward into the first dielectric layer. Attached Figure Description

[0014] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0015] Figure 1 A schematic diagram of an interconnect structure is shown;

[0016] Figure 2 , Figure 3 , Figure 4A and Figure 4B This diagram illustrates a structural schematic of an interconnect structure at an intermediate stage of the manufacturing process according to an embodiment of this application, wherein:

[0017] Figure 2 A schematic diagram showing the formation of a first dielectric layer and a first cover layer of an interconnect structure according to an embodiment of this application is shown.

[0018] Figure 3 A schematic diagram of the formation of trenches in the interconnect structure according to an embodiment of this application is shown.

[0019] Figure 4A and Figure 4B A schematic diagram showing the formation of a second dielectric layer and an air gap in an interconnect structure according to an embodiment of this application is shown, wherein... Figure 4B for Figure 4A The interconnection structure in the figure is a cross-sectional view along the AA direction.

[0020] Figure 5 A schematic diagram of the metal atom diffusion path of the interconnect structure according to an embodiment of this application is shown.

[0021] Figure 6 A schematic diagram showing the relationship between the metal spacing of the interconnect structure and the breakdown of the intermetallic dielectric layer over time according to an embodiment of this application is illustrated.

[0022] Figure 7 A schematic diagram of the capacitor configuration of the interconnect structure according to an embodiment of this application is shown.

[0023] Figure 8 A schematic diagram of another interconnection structure according to an embodiment of this application is shown.

[0024] Figure 9 A schematic diagram of another interconnection structure according to an embodiment of this application is shown.

[0025] Figure 10 A flowchart of a method for forming an interconnect structure according to an embodiment of this application is shown.

[0026] Explanation of reference numerals in the attached figures:

[0027] Figure 1 In the middle: 11-bottom dielectric layer; 12-barrier layer; 13-bottom interconnect structure; 14-bottom capping layer; 17-upper dielectric layer; 18-upper interconnect structure; 19-upper capping layer; A-diffusion path.

[0028] Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5 and Figure 7 In the middle: 201-first dielectric layer; 202-first diffusion barrier layer; 203a-first interconnect structure; 203b-second interconnect structure; 204-first capping layer; 205-trench; 206-air gap; 207-second dielectric layer; 210-photoresist layer; B, C-diffusion paths; H-opening.

[0029] Figure 8 In the diagram: 301: First dielectric layer; 302: First diffusion barrier layer; 303a: First interconnect structure; 303b: Second interconnect structure; 303c: Third interconnect structure; 304: First capping layer; 306a: First air gap; 306b: Second air gap; 307: Second dielectric layer; 308: High-layer interconnect structure; 309: Second capping layer.

[0030] Figure 9 In the diagram: 401 - First dielectric layer; 402 - First diffusion barrier layer; 403a - First interconnect structure; 403b - Second interconnect structure; 404 - First cover layer; 406a - First air gap; 406b - Second air gap; 407 - Second dielectric layer.

[0031] Figure 10 S10, S20, S30 - Process steps. Detailed Implementation

[0032] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the present application. Repeated reference numerals may be used in the various embodiments; these repeated reference numerals are for simplicity and clarity only and do not indicate a relationship between the various embodiments.

[0033] Furthermore, in this application, spatial relationship terms such as "below," "under," "above," and "below" can be used to describe the relationship between one element and another in the accompanying drawings. In addition to the orientations shown in the drawings, these spatial relationship terms may also include different orientations of the device / structure during use (e.g., rotation of 90 degrees). The interpretation of the aforementioned spatial relationship terms should be adjusted accordingly for these different orientations.

[0034] In the description of this application, the term "connection" or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. For example, in this application, the formation of a first feature over a second feature can include direct or indirect contact between the first and second features.

[0035] In the embodiments described in this application, the term "about" or a term with an equivalent meaning can refer to a given number of values ​​that vary within, for example, 10% of the value. It is understood that for numerical values ​​not defined by terms such as "about" in this application, the numerical value may also have a certain range of fluctuation, provided that the desired technical effect of the embodiments of this application can be achieved, and the numerical values ​​described in the embodiments are merely exemplary.

[0036] Figure 1 A schematic diagram of an interconnect structure is shown. Multiple trenches are formed within the bottom dielectric layer 11 of the interconnect structure 100, and a barrier layer 12 and a bottom interconnect structure 13 are formed within the trenches. A bottom capping layer 14 is formed on the bottom dielectric layer 11, covering the bottom dielectric layer 11 and the bottom interconnect structure 13. An upper dielectric layer 17 is formed on the bottom capping layer 14, and an upper interconnect structure 18 is formed within the upper dielectric layer 17. An upper capping layer 19 is formed on the upper dielectric layer 17, covering the upper dielectric layer 17 and the upper interconnect structure 18. Both the bottom dielectric layer 11 and the upper dielectric layer 17 are intermetallic dielectric layers. The materials of both the bottom interconnect structure 13 and the upper interconnect structure 18 are metallic copper. The inventors have discovered that the copper damascus process involves etching the intermetallic dielectric layer followed by ECP (Electrochemical Plating) deposition of metallic copper. To facilitate fabrication, the actual trenches after etching the intermetallic dielectric layer are made into an inverted trapezoidal shape, with the bottom trapezoidal angle typically around 86°. Therefore, the top linewidth of the metal will be larger than the designed linewidth. Due to fluctuations in process uniformity, if the critical metal dimension is larger, the intermetallic spacing will further decrease under the same pitch (the distance between the centers of two adjacent cells in integrated circuits). This is because the copper process has no surface barrier layer, only a capping layer made of NDC (SiCN, nitrogen-doped silicon carbide), and copper diffusion under an electric field is mainly surface diffusion, for example, diffusion along diffusion path A. This will cause the intermetallic dielectric layer between the top metals to become a weak point for time-dependent breakdown. As the process shrinks, the risk of time-dependent breakdown of the intermetallic dielectric layer between the top metals becomes increasingly prominent, with the failure point of time-dependent breakdown located on the capping layer between adjacent metal strips. The industry has also conducted extensive research on the effects of the thickness and spacing of the intermetallic dielectric layer. As the spacing between the intermetallic dielectric layers decreases, the degradation of the intermetallic dielectric layer's time-dependent breakdown T63.2 (characteristic time of failure distribution) becomes more pronounced.

[0037] Figure 2 , Figure 3 , Figure 4A and Figure 4B This diagram illustrates a structural schematic of an interconnect structure at an intermediate stage of the manufacturing process according to an embodiment of this application, wherein: Figure 2A schematic diagram showing the formation of a first dielectric layer and a first cover layer of an interconnect structure according to an embodiment of this application is shown. Figure 3 A schematic diagram of the formation of trenches in the interconnect structure according to an embodiment of this application is shown. Figure 4A and Figure 4B A schematic diagram showing the formation of a second dielectric layer and an air gap in an interconnect structure according to an embodiment of this application is shown, wherein... Figure 4B for Figure 4A The interconnection structure in the figure is a cross-sectional view along the AA direction.

[0038] like Figure 2 As shown, this embodiment provides an interconnect structure 200, including a first dielectric layer 201. A first interconnect structure 203a and a second interconnect structure 203b are formed within the first dielectric layer 201. A first diffusion barrier layer 202 is formed between the first interconnect structure 203a and the first dielectric layer 201, and a first diffusion barrier layer 202 is also formed between the second interconnect structure 203b and the first dielectric layer 201. A first capping layer 204 is formed on the first dielectric layer 201, covering the first dielectric layer 201, the first interconnect structure 203a, and the second interconnect structure 203b. The first capping layer 204 is used to block the diffusion of the first interconnect structure 203a and the second interconnect structure 203b. A photoresist layer 210 is formed, with an opening H located between the first interconnect structure 203a and the second interconnect structure 203b, exposing the first capping layer 204.

[0039] Specifically, the first dielectric layer 201 is a low-k dielectric layer, and its dielectric constant is, for example, 1 to 3. The material of the first dielectric layer 201 is, for example, silicon oxide or SiCOH; preferably, in this embodiment, the material of the first dielectric layer 201 is silicon oxide. It can be formed using a chemical vapor deposition process. The first dielectric layer 201 is used to isolate adjacent first interconnect structures 203a and second interconnect structures 203b. The first interconnect structures 203a and second interconnect structures 203b are conductive strips; specifically, the material of the first interconnect structures 203a and second interconnect structures 203b is a metal, more specifically, the material of the first interconnect structures 203a and second interconnect structures 203b is one of tungsten, aluminum, and copper; preferably, in this embodiment, the material of the first interconnect structures 203a and second interconnect structures 203b is copper. It is formed using a physical vapor deposition process. Specifically, a trench is first cut in the first dielectric layer 201, then a diffusion barrier layer 202 is formed, and then the first interconnect structures 203a and second interconnect structures 203b are formed in the trench using a physical vapor deposition process. The first capping layer 204 is a single-layer film or a stacked film. For example, mature planar processes use a single layer, while advanced FinFET processes use a stacked layer. When the first capping layer 204 is a single-layer film, its material is nitrogen-doped silicon carbide (SiCN, NDC) or silicon nitride (SiN). When the first capping layer 204 is a stacked film, its material is an NDC-TEOS (tetraethyl orthosilicate) stacked film or an AlN (aluminum nitride)-ODC (SiCO, O-doped SiC)-Al2O3-TEOS (tetraethyl orthosilicate) stacked film. The first capping layer 204 serves as the cap layer of the first interconnect layer, blocking copper diffusion and also as an etch stop layer for the second dielectric layer 207. Preferably, in this embodiment, the first capping layer 204 is, for example, nitrogen-doped silicon carbide. It can be formed using conventional techniques in the field, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0040] like Figure 3As shown, an etching process is performed, using the photoresist layer 210 forming the opening H as a mask, to sequentially etch the first capping layer 204 and the first dielectric layer 201 to form the trench 205. That is, the trench 205 penetrates the first capping layer 204 and extends into the first dielectric layer 201. The trench 205 is located between the first interconnect structure 203a and the second interconnect structure 203b. The aspect ratio of the trench 205 is 40:1 to 70:1, for example, 50:1 or 60:1. The number of trenches 205 between the first interconnect structure 203a and the second interconnect structure 203b can be one or more, for example, 5, 10, 15, 20, 25, and 30. The depth of the trench 205 can be less than the depth of the first interconnect structure 203a and the second interconnect structure 203b, or the depth of the trench 205 can be greater than or equal to the depth of the first interconnect structure 203a and the second interconnect structure 203b. This embodiment does not limit this, as long as the aspect ratio of the trench 205 is satisfied.

[0041] like Figure 4A and 4BAs shown, a second dielectric layer 207 is formed, which covers the first cover layer 204 and forms an air gap 206 within and on the trench 205. The air gap 206 penetrates the first cover layer 204 and extends upward into the second dielectric layer 207, and downward into the first dielectric layer 201. The air gap 206 can be filled with air or other gases, such as nitrogen or argon. The second dielectric layer 207 is a low-k dielectric layer, and its dielectric constant is, for example, 1 to 3. Specifically, the material of the second dielectric layer 207 is silicon oxide or SiCOH. Preferably, in this embodiment, the material of the second dielectric layer 207 is, for example, silicon oxide. It can be formed using a chemical vapor deposition process. The portion of the air gap 206 located within the first dielectric layer 201 has a first width, the portion located within the first cover layer 204 has a second width, and the portion located within the second dielectric layer 207 has a third width. The second width is greater than the first width, and the first width is greater than the third width. In this embodiment, after adding the air gap 206, metal atoms diffuse around the air gap 206 and diffuse from the first dielectric layer 201 or the second dielectric layer 207, thus increasing the diffusion path of metal atoms. Increasing the diffusion path of metal atoms has the same effect as increasing the spacing between the first interconnect structure 203a and the second interconnect structure 203b, improving the device's IMD TDDB. Since the dielectric constant of low-k is greater than that of air, the capacitance at the air gap 206 is less than the capacitance of the low-k dielectric layer at the same location in the prior art; therefore, the IMD capacitance is reduced in this embodiment. This embodiment extends the copper atom diffusion path by adding the air gap 206 to the metal atom diffusion path, thereby improving the IMD TDDB. An improved IMD TDDB means an increase in metal density, which in turn improves chip integration. Simultaneously, the introduction of the air gap 206 reduces capacitive reactance and signal delay. Furthermore, the process scheme of this embodiment has good compatibility; the formation of the air gap 206 does not affect the subsequent etching of the second dielectric layer 207. In other words, this embodiment takes into account the subsequent etching process of IMD, while bringing about an improvement in IMDTDDB and a reduction in capacitance.

[0042] Figure 5A schematic diagram of the metal atom diffusion path of the interconnect structure according to an embodiment of this application is shown. Because the failure of IMDTDDB is essentially caused by metal atoms diffusing from the anode to the cathode along the diffusion path under electrical and heating stress, the metal atoms typically follow the following diffusion path: Cu Cap Layer / IMD interface (interface layer between the copper cap layer and the intermetallic dielectric layer), IMD inside (inside the intermetallic dielectric layer), and Cap Layer inside (inside the cap layer). In this embodiment, the first interconnect structure 203a and the second interconnect structure 203b are made of, for example, copper. Considering that copper diffusion is mainly surface diffusion, the diffusion path of the interface layer between the copper cap layer and the intermetallic dielectric layer is dominant. Figure 5 As shown, in this embodiment, after adding the air gap 206, copper atoms bypass the air gap 206 and diffuse from the first dielectric layer 201 or the second dielectric layer 207, thus increasing the diffusion path of copper atoms. Increasing the diffusion path of copper atoms has the same effect as increasing the spacing between the first interconnect structure 203a and the second interconnect structure 203b, which improves the device's IMD TDDB.

[0043] The failure model selected by IMD TDDB is as follows:

[0044] T63.2 = A* exp(-γ*E0.5), formula (1)

[0045] Where T63.2 is the characteristic value of the IMD TDDB TTF Weibull distribution, A is a constant, γ is the voltage acceleration factor, and E is the electric field strength (MV / cm).

[0046] The change in the T63.2 eigenvalue caused by the variation in the spacing between adjacent first interconnect structure 203a and second interconnect structure 203b can be characterized by a multiple N of T63.2. The larger N is, the larger the IMD TDDB of the device, the less prone the device is to failure, and the better its performance. The multiple N of T63.2 is:

[0047] N = T63.2' / T63.2 (Equation 2)

[0048] =1 - 0.5 * γ * E0.5 * (E' / E)

[0049] =1-0.5*γ*E0.5*(-Top Space-1*Top Space')

[0050] =1-0.5*γ*U0.5 / (Pitch-Metal CD–Metal THK*Cot(α))1.5*Metal CD'

[0051] Where T63.2 is the characteristic value of the IMD TDDB TTF Weibull distribution, T63.2' is the derivative of T63.2, T63.2 is the reference value, T63.2' is the variable value, γ is the voltage acceleration factor, E is the electric field strength (MV / cm), U is the voltage difference applied across the IMDTDDB test terminals, Top Space is the metal top spacing, Metal CD is the critical dimension of the first interconnect strip, Pitch is the distance between the centers of two adjacent first interconnect strips, α is the angle of the bottom of the Metal inverted trapezoid, Metal THK is the metal thickness, and Pitch, Metal THK, and α are considered constants.

[0052] Figure 6 A schematic diagram showing the relationship between the metal spacing of the interconnect structure and the breakdown of the intermetallic dielectric layer over time according to an embodiment of this application is illustrated. Figure 6 The horizontal axis represents the top space of the metal, in nanometers (nm). The vertical axis represents N, which is the multiple of T63.2 between the original and current spacing of adjacent first interconnect structures 203a and second interconnect structures 203b. For example... Figure 6 As shown, it can be concluded that under the same voltage and temperature, increasing the IMD Top Space will improve the IMD TDDB. Similarly, increasing the metal diffusion distance by adding an air gap 206 between adjacent first interconnect structure 203a and second interconnect structure 203b is also possible. The principle is similar, thus proving that increasing the diffusion path of metal atoms improves the IMD TDDB of the device.

[0053] Figure 7 A schematic diagram of the capacitor configuration of the interconnect structure according to an embodiment of this application is shown. The formula for capacitance is:

[0054] C=εS / 4πkd, Equation (3),

[0055] Where ε is the dielectric constant, S is the area of ​​the two plates facing each other, d is the distance between the two plates of the capacitor, and k is the electrostatic constant.

[0056] The capacitance between adjacent first interconnect structure 203a and second interconnect structure 203b in interconnect structure 200 is:

[0057]

[0058] Since the first dielectric layer 201 is a low-k dielectric layer, the dielectric constant of low-k is greater than that of air. That is, the capacitance of C12 in the equivalent circuit diagram is less than the capacitance of the low-k dielectric layer at the same position in the prior art. Therefore, it can be concluded that the IMD capacitance is reduced in this embodiment.

[0059] In the technical solution of this embodiment, the IMD TDDB of the device is improved and the IMD capacitance is reduced, which means that there is room for further improvement in integration.

[0060] Figure 8 A schematic diagram of another interconnection structure according to an embodiment of this application is shown. For example... Figure 8 As shown, this embodiment provides another interconnect structure 300, which includes a first dielectric layer 301. A first interconnect structure 303a, a second interconnect structure 303b, and a third interconnect structure 303c are formed in the first dielectric layer 301. The first interconnect structure 303a, the second interconnect structure 303b, and the third interconnect structure 303c are separated from each other. A first diffusion barrier layer 302 is formed between the first interconnect structure 303a, the second interconnect structure 303b, and the third interconnect structure 303c and the first dielectric layer 301. A first cover layer 304 is formed on the first dielectric layer 301, covering the upper surface of the first interconnect structure 303a, the upper surface of the second interconnect structure 303b, the upper surface of the third interconnect structure 303c, and the upper surface of the first dielectric layer 301; a second dielectric layer 307 is formed on the first cover layer 304, covering the first cover layer 304; a high-layer interconnect structure 308 is formed within the second dielectric layer 307, and a second cover layer 309 is also formed on the second dielectric layer 307; the interconnect structure 303a... 00 also includes multiple air gaps. The first air gap 306a is located between the first interconnect structure 303a and the second interconnect structure 303b, penetrates the first cover layer 304 and extends upward into the second dielectric layer 307, and extends downward into the first dielectric layer 307. The second air gap 306b is located between the second interconnect structure 303b and the third interconnect structure 303c, penetrates the first cover layer 304 and extends upward into the second dielectric layer 307, and extends downward into the first dielectric layer 301.

[0061] Specifically, the material of the high-layer interconnect structure 308 is a metal, more specifically, the material of the high-layer interconnect structure 308 is one of tungsten, aluminum, and copper. Preferably, the material of the high-layer interconnect structure 308 in this embodiment is copper. It can be formed using a physical vapor deposition process. The second capping layer 309 is a single-layer film or a stacked film. For example, mature planar processes use a single layer, while advanced FinFET processes use a stacked layer. When the second capping layer 309 is a single-layer film, the material of the second capping layer 309 is nitrogen-doped silicon carbide (SiCN, NDC) or silicon nitride (SiN). When the second capping layer 309 is a stacked film, the material of the second capping layer 309 is an NDC-TEOS (tetraethyl orthosilicate) stacked film or an AlN (aluminum nitride)-ODC (SiCO, O-doped SiC)-Al2O3-TEOS (tetraethyl orthosilicate) stacked film. Preferably, in this embodiment, the second capping layer 309 is, for example, nitrogen-doped silicon carbide. The second capping layer 309 serves as the cap layer of the second interconnect layer, preventing copper diffusion. When there is an interconnect layer on the second capping layer 309, it also serves as an etch stop layer for the upper dielectric layer. It can be formed using conventional techniques in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0062] Figure 9 A schematic diagram of another interconnect structure according to an embodiment of this application is shown. This embodiment provides another interconnect structure 400, which includes a first dielectric layer 401. A first interconnect structure 403a and a second interconnect structure 403b are formed in the first dielectric layer 401. The first interconnect structure 403a and the second interconnect structure 403b are separated from each other. A first diffusion barrier layer 402 is formed between the first interconnect structure 403a and the second interconnect structure 403b and the first dielectric layer 401. A first cover layer 404 is formed on the first dielectric layer 401, covering the upper surface of the first interconnect structure 403a, the upper surface of the second interconnect structure 403b, and the upper surface of the first dielectric layer 401; a second dielectric layer 407 is formed on the first cover layer 404, covering the first cover layer 404; the interconnect structure 400 further includes a plurality of air gaps, a first air gap 406a and a second air gap 406b located between the first interconnect structure 403a and the second interconnect structure 403b, penetrating the first cover layer 404 and extending upward into the second dielectric layer 407, and downward into the first dielectric layer 401.

[0063] Figure 10A flowchart illustrating a method for forming an interconnect structure according to an embodiment of this application is shown. This embodiment also provides a method for forming an interconnect structure, including:

[0064] Step S10: A first dielectric layer is provided, in which a first interconnect structure and a second interconnect structure are formed. The first interconnect structure and the second interconnect structure are separated from each other. A first cover layer covers the upper surface of the first interconnect structure, the upper surface of the second interconnect structure, and the upper surface of the first dielectric layer.

[0065] Step S20: Perform an etching process to form a trench between the first interconnect structure and the second interconnect structure, the trench penetrating the first cover layer and extending downward into the first dielectric layer;

[0066] Step S30: A second dielectric layer is formed, which covers the first cover layer and partially fills the trench to form an air gap at the trench. The air gap penetrates the first cover layer and extends upward into the second dielectric layer and downward into the first dielectric layer.

[0067] This embodiment provides an interconnection structure, including:

[0068] A first dielectric layer 201 is formed therein, and a first interconnect structure 203a and a second interconnect structure 203b are formed therein, wherein the first interconnect structure 203a and the second interconnect structure 203b are separated from each other.

[0069] The first cover layer 204 covers the upper surface of the first interconnect structure 203a, the upper surface of the second interconnect structure 203b, and the upper surface of the first dielectric layer 201.

[0070] A second dielectric layer 207 covers the first cover layer 204; and

[0071] Air gap 206 is located between the first interconnect structure 203a and the second interconnect structure 203b, penetrates the first cover layer 204 and extends upward into the second dielectric layer 207, and extends downward into the first dielectric layer 201.

[0072] Optionally, the aspect ratio of the air gap 206 is greater than 40:1.

[0073] Optionally, the number of air gaps 206 is at least two.

[0074] In the interconnect structure 300, a high-level interconnect structure 308 is also formed in the second dielectric layer 307. The high-level interconnect structure 308 penetrates the second dielectric layer 307 and the first cover layer 304. The high-level interconnect structure 308 is in contact with the first interconnect structure 303a. The high-level interconnect structure 308 is separated from the first air gap 306a and the second air gap 306b.

[0075] Optionally, the material of the first capping layer 204 includes at least one of SiCN, SiN, TEOS, AlN, SiCO, and Al2O3.

[0076] Optionally, a diffusion barrier layer 202 is also included, which is located between the first interconnect structure 203a and the first dielectric layer 201.

[0077] This embodiment also provides a method 500 for forming an interconnect structure, including:

[0078] A first dielectric layer 201 is provided, in which a first interconnect structure 203a and a second interconnect structure 203b are formed. The first interconnect structure 203a and the second interconnect structure 203b are separated from each other. A first cover layer 204 covers the upper surface of the first interconnect structure 203a, the upper surface of the second interconnect structure 203b and the upper surface of the first dielectric layer 201.

[0079] An etching process is performed to form a trench 205 between the first interconnect structure 203a and the second interconnect structure 203b, the trench 205 penetrating the first cover layer 204 and extending downward into the first dielectric layer 201;

[0080] A second dielectric layer 207 is formed, which covers the first cover layer 204 and partially fills the trench 205 to form an air gap 206 at the trench 205. The air gap 206 penetrates the first cover layer 204 and extends upward into the second dielectric layer 207, and downward into the first dielectric layer 201.

[0081] Optionally, the depth-to-width ratio of the trench 205 is 40:1 to 70:1.

[0082] Optionally, the etching process includes:

[0083] A photoresist layer 210 is formed, the photoresist layer 210 having an opening H located between the first interconnect structure 203a and the second interconnect structure 203b, and exposing the first cover layer 204.

[0084] An etching process is performed, using the photoresist layer 210 that forms the opening H as a mask, to sequentially etch the first cover layer 204 and the first dielectric layer 201 to form the trench 205.

[0085] In another embodiment, after forming the second dielectric layer 307, the method further includes:

[0086] A high-level interconnect structure 308 is formed in the second dielectric layer 307. The high-level interconnect structure 308 penetrates the second dielectric layer 307 and the first cover layer 304. The high-level interconnect structure 308 is in contact with the first interconnect structure 303a. The high-level interconnect structure 308 is separated from the first air gap 306a and the second air gap 306b.

[0087] This embodiment also provides a chip including an interconnect structure 200, the interconnect structure 200 including: a first dielectric layer 201, in which a first interconnect structure 203a and a second interconnect structure 203b are formed, the first interconnect structure 203a and the second interconnect structure 203b being separated from each other; a first cover layer 204 covering the upper surface of the first interconnect structure 203a, the upper surface of the second interconnect structure 203b and the upper surface of the first dielectric layer 201; a second dielectric layer 207 covering the first cover layer 204; and an air gap 206 located between the first interconnect structure 203a and the second interconnect structure 203b, penetrating the first cover layer 204 and extending upward into the second dielectric layer 207, and downward into the first dielectric layer 201.

[0088] This embodiment also provides an electronic device, including an interconnect structure 200, the interconnect structure 200 including: a first dielectric layer 201, in which a first interconnect structure 203a and a second interconnect structure 203b are formed, the first interconnect structure 203a and the second interconnect structure 203b being separated from each other; a first cover layer 204 covering the upper surface of the first interconnect structure 203a, the upper surface of the second interconnect structure 203b and the upper surface of the first dielectric layer 201; a second dielectric layer 207 covering the first cover layer 204; and an air gap 206 located between the first interconnect structure 203a and the second interconnect structure 203b, penetrating the first cover layer 204 and extending upward into the second dielectric layer 207, and downward into the first dielectric layer 201.

[0089] It is understood that the actions and steps described in the above embodiments and accompanying drawings can be performed in different orders to achieve the technical effects expected in this application, and are not limited to the order described in the above embodiments and accompanying drawings.

[0090] The embodiments of this application have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of this application. The scope of this application is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this application, and all such substitutions and modifications should fall within the scope of this application.

Claims

1. An interconnection structure, characterized in that, include: A first dielectric layer, wherein a first interconnect structure and a second interconnect structure are formed in the first dielectric layer, and the first interconnect structure and the second interconnect structure are separated from each other; A first cover layer covers the upper surface of the first interconnect structure, the upper surface of the second interconnect structure, and the upper surface of the first dielectric layer; A second dielectric layer covers the first cover layer; as well as An air gap is located between the first interconnect structure and the second interconnect structure, extends through the first cover layer and upward into the second dielectric layer, and downward into the first dielectric layer.

2. The interconnection structure according to claim 1, characterized in that, The air gap has a depth-to-width ratio greater than 40:

1.

3. The interconnection structure according to claim 1, characterized in that, The number of air gaps is at least two.

4. The interconnection structure according to claim 1, characterized in that, A high-level interconnect structure is also formed within the second dielectric layer. The high-level interconnect structure penetrates the second dielectric layer and the first cover layer. The high-level interconnect structure is in contact with the first interconnect structure and is separated from the air gap.

5. The interconnection structure according to claim 1, characterized in that, The material of the first capping layer includes at least one of SiCN, SiN, TEOS, AlN, SiCO, and Al2O3.

6. The interconnection structure according to claim 1, characterized in that, It also includes a diffusion barrier layer located between the first interconnect structure and the first dielectric layer.

7. A method for forming an interconnect structure, characterized in that, include: A first dielectric layer is provided, in which a first interconnect structure and a second interconnect structure are formed, the first interconnect structure and the second interconnect structure are separated from each other, and a first cover layer covers the upper surface of the first interconnect structure, the upper surface of the second interconnect structure and the upper surface of the first dielectric layer. An etching process is performed to form a trench between the first interconnect structure and the second interconnect structure, the trench penetrating the first cover layer and extending downward into the first dielectric layer; A second dielectric layer is formed, which covers the first cover layer and partially fills the trench to form an air gap at the trench. The air gap extends through the first cover layer and upward into the second dielectric layer, and downward into the first dielectric layer.

8. The method for forming an interconnect structure according to claim 7, characterized in that, The depth-to-width ratio of the trench is 40:1 to 70:

1.

9. The method for forming an interconnect structure according to claim 7, characterized in that, The etching process includes: A photoresist layer is formed, the photoresist layer having an opening located between the first interconnect structure and the second interconnect structure, and exposing the first cover layer; An etching process is performed, using the photoresist layer that forms the opening as a mask, to sequentially etch the first capping layer and the first dielectric layer to form the trench.

10. The method for forming an interconnect structure according to claim 7, characterized in that, After forming the second dielectric layer, the method further includes: A high-level interconnect structure is formed in the second dielectric layer, the high-level interconnect structure penetrates the second dielectric layer and the first cover layer, the high-level interconnect structure is in contact with the first interconnect structure, and the high-level interconnect structure is separated from the air gap.

11. A chip, characterized in that, The system includes an interconnect structure comprising: a first dielectric layer in which a first interconnect structure and a second interconnect structure are formed, the first interconnect structure and the second interconnect structure being separate from each other; a first cover layer covering the upper surface of the first interconnect structure, the upper surface of the second interconnect structure, and the upper surface of the first dielectric layer; a second dielectric layer covering the first cover layer; and an air gap located between the first interconnect structure and the second interconnect structure, penetrating the first cover layer and extending upward into the second dielectric layer, and downward into the first dielectric layer.

12. An electronic device, characterized in that, The system includes an interconnect structure comprising: a first dielectric layer in which a first interconnect structure and a second interconnect structure are formed, the first interconnect structure and the second interconnect structure being separate from each other; a first cover layer covering the upper surface of the first interconnect structure, the upper surface of the second interconnect structure, and the upper surface of the first dielectric layer; a second dielectric layer covering the first cover layer; and an air gap located between the first interconnect structure and the second interconnect structure, penetrating the first cover layer and extending upward into the second dielectric layer, and downward into the first dielectric layer.

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