Semiconductor structure and manufacturing method thereof, electronic device

Abstract

A semiconductor structure, a manufacturing method thereof and an electronic device, the semiconductor structure comprising: a plurality of signal lines distributed in multiple layers and arranged in a vertical stack on a substrate, and a plurality of connection electrodes arranged on the same side of the plurality of signal lines; the signal lines extend along a direction parallel to the substrate; the connection electrodes comprise horizontal conductive parts extending along a direction parallel to the substrate and vertical conductive parts extending along a direction perpendicular to the substrate and connected to the horizontal conductive parts, the horizontal conductive parts are arranged on the side of the vertical conductive parts facing the signal lines; the horizontal conductive parts of the plurality of connection electrodes are distributed in different layers, and the horizontal conductive parts are connected to one signal line in the same layer; the horizontal conductive parts of the connection electrodes are connected to the connected signal lines to form an integrated structure, and the vertical conductive parts of the same connection electrode are in a non-integrated structure with the horizontal conductive parts. The scheme provided by the embodiment of the present disclosure can reduce the size of the horizontal conductive parts and the size of the semiconductor structure by arranging the horizontal conductive parts on one side of the vertical conductive parts.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, device design and manufacturing in the field of electronic technology, and particularly to a semiconductor structure and its manufacturing method, and electronic equipment. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various structural designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a semiconductor structure and its manufacturing method, as well as an electronic device, which reduces the size of the interconnect structure.

[0006] This application provides a semiconductor structure, including: multiple signal lines stacked on a substrate in a direction perpendicular to the substrate and distributed in multiple layers, and multiple connecting electrodes disposed on the same side of the multiple signal lines; the signal lines extend in a direction parallel to the substrate;

[0007] The connection electrode includes a horizontal conductive portion extending in a direction parallel to the substrate and a vertical conductive portion extending in a direction perpendicular to the substrate connected to the horizontal conductive portion. The horizontal conductive portion is disposed on the side of the vertical conductive portion facing the signal line.

[0008] The multiple horizontal conductive portions of the multiple connecting electrodes are distributed in different layers, and the horizontal conductive portions are connected to a signal line in the same layer; the horizontal conductive portions of the connecting electrodes and the connected signal lines form an integral structure, while the vertical conductive portions of the same connecting electrode and the horizontal conductive portions are not integral structures.

[0009] In some embodiments, the signal lines and the vertical conductive portions are distributed along a first direction parallel to the substrate, the signal lines extend along a second direction parallel to the substrate, and the multiple vertical conductive portions of the plurality of connecting electrodes are spaced apart along the second direction, wherein the first direction and the second direction intersect.

[0010] In some embodiments, the dimension of the horizontal conductive portion along the second direction is greater than the dimension of the vertical conductive portion along the second direction.

[0011] In some embodiments, the plurality of vertical conductive portions have the same size along the direction perpendicular to the substrate, and the plurality of vertical conductive portions are at the same distance from the substrate.

[0012] In some embodiments, the horizontal conductive portions of the different connecting electrodes do not overlap in their orthographic projections onto the substrate.

[0013] In some embodiments, the orthographic projections of the horizontal conductive portions of the different connecting electrodes onto the substrate are arranged sequentially according to the distance between the horizontal conductive portions and the substrate.

[0014] This disclosure provides a method for manufacturing a semiconductor structure, including:

[0015] A stacked structure comprising multiple alternating first insulating layers and sacrificial layers is formed on a substrate;

[0016] A plurality of first holes are formed penetrating the stacked structure along a direction perpendicular to the substrate, and vertical conductive portions are filled in the first holes; the plurality of first holes are spaced apart along a second direction parallel to the substrate;

[0017] A first trench is formed that penetrates the stacked structure along a direction perpendicular to the substrate and extends along a second direction, and a plurality of transverse trenches that are spaced apart along a direction perpendicular to the substrate and extend along a second direction and communicate with the first trench. The transverse trenches are located between adjacent first insulating layers. Each transverse trench exposes one of the vertical conductive portions between a plurality of vertical conductive portions, and different transverse trenches expose different vertical conductive portions.

[0018] A second conductive film is deposited to fill the transverse trench, forming a signal line and a horizontal conductive portion that fill the transverse trench. The signal line extends along a second direction, and the horizontal conductive portion connects the vertical conductive portion and the signal line.

[0019] In some embodiments, the formation of a first trench extending through the stacked structure perpendicular to the substrate direction and extending in a second direction, and the plurality of lateral trenches spaced apart perpendicular to the substrate direction and extending in the second direction communicating with the first trench, include:

[0020] A first trench is formed that penetrates the stacked structure along a direction perpendicular to the substrate and extends along a second direction, and a first dummy layer is formed that fills the first trench;

[0021] A plurality of second holes are formed through the first dummy layer in a direction perpendicular to the substrate, and the sidewalls of the second holes expose a plurality of the first insulating layers and a plurality of the sacrificial layers; the plurality of second holes are spaced apart in a second direction and correspond one-to-one with a plurality of first holes, and the second holes and their corresponding first holes are spaced apart in a first direction;

[0022] A filling layer is formed to fill the second hole; the filling layer is etched such that the distance between the filling layer and the substrate on the side away from the substrate in the plurality of second holes is different, and the distance between the different filling layers and the substrate on the side away from the substrate is the same as the distance between the different sacrificial layers and the substrate on the side away from the substrate; a second dummy layer is formed to cover the sidewall of the second hole;

[0023] The filling layer in each of the second holes is etched so that a sacrificial layer is exposed on the sidewall of the second hole. The exposed sacrificial layer is etched to form a groove that does not expose the vertical conductive portion.

[0024] The first dummy layer, the second dummy layer, and the fill layer are removed by etching;

[0025] Based on the first trench and the groove, the sacrificial layer is etched to expose a vertical conductive portion without exposing the remaining vertical conductive portions, thereby forming the transverse trench.

[0026] In some embodiments, etching the filling layer such that the distance between the filling layer on the side facing away from the substrate and the substrate in the plurality of second holes is different includes:

[0027] A photoresist layer covering multiple second holes is formed. The photoresist layer is etched to expose one second hole. The distance between the etched filling layer in the exposed second hole and the substrate on the side facing away from the substrate is a first preset height. The photoresist layer is etched to expose another second hole. The distance between the etched filling layer in the currently exposed second hole and the substrate on the side facing away from the substrate is a first preset height. The distance between the etched filling layer in the already exposed second hole and the substrate on the side facing away from the substrate is a second preset height. The steps of exposing one second hole and etching the filling layer in all exposed second holes are repeated until all second holes are exposed and the filling layer in all second holes is etched to different heights.

[0028] This disclosure provides an electronic device including any of the semiconductor structures described above, or a semiconductor structure formed according to the manufacturing method of any of the semiconductor structures described above.

[0029] In some embodiments, the method further includes: a multilayer memory cell array disposed on a substrate and stacked in a direction perpendicular to the substrate, the memory cell array comprising a plurality of memory cells, and the signal line connecting at least one of the memory cells.

[0030] This application includes a semiconductor structure, a method for manufacturing the same, and an electronic device. The semiconductor structure includes: multiple signal lines stacked on a substrate in multiple layers and disposed on the same side of the multiple signal lines; the signal lines extend in a direction parallel to the substrate; each connection electrode includes a horizontal conductive portion extending in a direction parallel to the substrate and a vertical conductive portion extending in a direction perpendicular to the substrate connected to the horizontal conductive portion, the horizontal conductive portion being disposed on the side of the vertical conductive portion facing the signal line; the multiple horizontal conductive portions of the multiple connection electrodes are distributed in different layers, and the horizontal conductive portions are connected to a signal line in the same layer; the horizontal conductive portions of the connection electrodes and the connected signal lines form an integral structure, while the vertical conductive portions of the same connection electrode are not integral structures with the horizontal conductive portions. The solution provided by this disclosure, where the horizontal conductive portion is disposed on one side of the vertical conductive portion, can reduce the size of the horizontal conductive portion, reduce the size of the semiconductor structure, and allow the signal lines and the horizontal conductive portion to be manufactured simultaneously, simplifying the process.

[0031] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings.

[0032] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0033] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0034] Figure 1A A three-dimensional schematic diagram of a semiconductor structure is provided for embodiments of this disclosure. Figures 1B to 1G Cross-sectional views are shown along the A5A5', A4A4', A3A3', A2A2', A1A1' and BB' directions, respectively, parallel to the substrate.

[0035] Figure 1H This is a cross-sectional view along the CC' direction perpendicular to the substrate. Figure 1I This is a cross-sectional view along the DD' direction perpendicular to the substrate. Figure 1J This is a cross-sectional view along the EE' direction perpendicular to the substrate;

[0036] Figures 2A to 2D Cross-sectional views along the A4A4' direction, BB' direction, CC' direction, and DD' direction after forming the first hole and the vertical conductive part, respectively, according to some embodiments;

[0037] Figures 3A to 3C Cross-sectional views along the A4A4' direction, BB' direction, and CC' direction after the formation of the first trench and the first dummy layer are provided in some embodiments;

[0038] Figures 4A to 4D These are cross-sectional views along the A4A4' direction, BB' direction, CC' direction, and EE' direction after the second hole is formed, provided in some embodiments.

[0039] Figures 5A to 5E Cross-sectional views along the A4A4', BB', CC', DD', and EE' directions after a step is formed in a semiconductor structure according to some embodiments;

[0040] Figures 6A to 6D These are cross-sectional views along the A4A4' direction, BB' direction, DD' direction, and EE' direction after forming another step of the semiconductor structure according to some embodiments;

[0041] Figures 7A to 7D Cross-sectional views along the A4A4' direction, BB' direction, CC' direction, and EE' direction after the semiconductor structure is formed, provided in some embodiments;

[0042] Figures 8A to 8D These are cross-sectional views along the A4A4' direction, BB' direction, CC' direction, and EE' direction after the formation of the second dummy layer, provided in some embodiments.

[0043] Figures 9A to 9E These are cross-sectional views along the A4A4' direction, BB' direction, CC' direction, DD' direction, and EE' direction after the groove A1 is formed, provided in some embodiments.

[0044] Figures 10A to 10D These are cross-sectional views along the A4A4' direction, BB' direction, CC' direction, and DD' direction after the first groove is exposed, provided in some embodiments.

[0045] Figures 11A to 11D These are cross-sectional views along the A4A4', BB', CC', and DD' directions after the transverse grooves have been formed, provided in some embodiments. Detailed Implementation

[0046] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0047] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0048] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0049] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0050] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0051] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0052] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0053] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0054] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.

[0055] In this embodiment of the disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0056] Figure 1A A three-dimensional schematic diagram of a semiconductor structure is provided for embodiments of this disclosure. Figures 1B to 1G Cross-sectional views are shown along the directions A5A5', A4A4', A3A3', A2A2', A1A1', and BB', which are parallel to substrate 1.

[0057] Figure 1H This is a cross-sectional view along the CC' direction perpendicular to substrate 1. Figure 1I This is a cross-sectional view along the DD' direction perpendicular to substrate 1. Figure 1J This is a cross-sectional view along the EE' direction perpendicular to substrate 1. Signal lines 30 in different layers are represented by directions A5A5', A4A4', A3A3', A2A2', and A1A1'. Direction BB' does not pass through signal line 30. Direction CC' passes through a vertical conductive portion 51. Direction DD' passes through a horizontal conductive portion 52. Direction EE' passes through the isolation film layer separating two sets of connecting electrodes. Figures 1A to 1J As shown, this disclosure provides a semiconductor structure, such as a stepped interconnect structure for use in a three-dimensional memory structure, comprising: multiple signal lines 30 stacked on a substrate 1 in a direction perpendicular to the substrate 1 and multiple connecting electrodes disposed on the same side of the multiple signal lines 30; the signal lines 30 extend in a direction parallel to the substrate 1;

[0058] The connecting electrode includes a horizontal conductive portion 52 extending in a direction parallel to the substrate 1 and a vertical conductive portion 51 extending in a direction perpendicular to the substrate 1 connected to the horizontal conductive portion 52. The horizontal conductive portion 52 is disposed on the side of the vertical conductive portion 51 facing the signal line 30.

[0059] The multiple horizontal conductive portions 52 of the multiple connecting electrodes are distributed in different layers, and the horizontal conductive portions 52 are connected to a signal line 30 in the same layer; the horizontal conductive portions 52 of the connecting electrodes are connected to the signal line 30 to form an integral structure, while the vertical conductive portions 51 and the horizontal conductive portions 52 of the same connecting electrode are not integral structures.

[0060] The solution provided in this disclosure embodiment has a horizontal conductive part disposed on one side of the vertical conductive part, which can reduce the size of the horizontal conductive part and the size of the semiconductor structure. Furthermore, the signal line and the horizontal conductive part can be manufactured simultaneously, simplifying the process.

[0061] In some embodiments, the signal line 30 and the vertical conductive portion 51 are distributed along a first direction X parallel to the substrate 1, the signal line 30 extends along a second direction Y parallel to the substrate 1, and the plurality of vertical conductive portions 51 of the plurality of connecting electrodes are distributed at intervals along the second direction Y, wherein the first direction X and the second direction Y intersect.

[0062] In some embodiments, the first direction X and the second direction Y can be perpendicular.

[0063] In some embodiments, the dimension of the horizontal conductive portion 52 along the second direction Y can be larger than the dimension of the vertical conductive portion 51 along the second direction Y. The solution provided by the embodiments of this disclosure can minimize the dimension of the vertical conductive portion 51 along the second direction Y, reduce the coupling capacitance between different vertical conductive portions 51, and the larger dimension of the horizontal conductive portion 52 can increase the contact area between them and reduce the resistance.

[0064] In some embodiments, the plurality of vertical conductive portions 51 have the same size along the direction perpendicular to the substrate 1, and the plurality of vertical conductive portions 51 are at the same distance from the substrate 1. In this scheme, the vertical conductive portions 51 can be implemented by etching holes of the same depth in one step, which simplifies the process.

[0065] In some embodiments, the horizontal conductive portions 52 of the different connecting electrodes may not overlap in their orthographic projections onto the substrate 1. For example... Figures 1B to 1F As shown, the orthographic projections of different horizontal conductive portions 51 onto the substrate 1 are distributed in different regions and do not overlap. The solution provided in this embodiment, where different horizontal conductive portions 52 do not overlap, can reduce the coupling capacitance between the horizontal conductive portions 52. However, this embodiment is not limited to this; the orthographic projections of the horizontal conductive portions 52 of different connecting electrodes onto the substrate 1 may overlap.

[0066] In some embodiments, the orthographic projections of the horizontal conductive portions 52 of the different connecting electrodes onto the substrate 1 are arranged sequentially according to the distance between the horizontal conductive portions 52 and the substrate 1. For example, the horizontal conductive portions 52 closest to the substrate 1 and the horizontal conductive portions 52 furthest from the substrate 1 are arranged sequentially along the second direction Y in their orthographic projections onto the substrate 1. However, the embodiments of this disclosure are not limited to this, and the arrangement of the orthographic projections of the horizontal conductive portions 52 of the different connecting electrodes onto the substrate 1 can be independent of the distance between the horizontal conductive portions 52 and the substrate 1, and can be arranged in a random order.

[0067] In some embodiments, the dimensions of the horizontal conductive portions 52 connected to the different vertical conductive portions 51 distributed along the second direction Y can be the same.

[0068] In some embodiments, each layer may include multiple signal lines 30 spaced apart along a first direction X, and the semiconductor structure may include multiple columns of vertical conductive portions 51 distributed along a second direction Y. Each column of vertical conductive portions 51 is connected to different signal lines 30 at the same location in the multiple layers.

[0069] In some embodiments, the horizontal conductive portion 52 may be a protrusion on the signal line 30 facing the side of the vertical conductive portion 51. The dimension of the contact surface between the horizontal conductive portion 52 and the signal line 30 along the second direction Y is greater than the dimension of the contact surface between the horizontal conductive portion 52 and the vertical conductive portion 51 along the second direction Y.

[0070] In some embodiments, the signal line 30 can be connected to a memory cell of the memory cell array. The signal line 30 can be a word line or a bit line connecting the memory cell. The word line can be a signal line for reading and writing control of the memory cell, and the bit line can write data to the memory cell or read data from the memory cell.

[0071] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor structure in this embodiment. In this embodiment, a film pattern is formed through a "patterning process" or a "photolithography process." The "patterning process" includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" in this embodiment includes film coating, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning or photolithography process contains at least one "pattern".

[0072] In one exemplary embodiment, the manufacturing process of the semiconductor structure may include:

[0073] 1) Form the first hole K1 and the vertical conductive part 51;

[0074] A first insulating film and a sacrificial layer film are sequentially and alternately deposited on a substrate 1 to form a stacked structure comprising a plurality of alternately arranged first insulating layers 11 and sacrificial layers 10;

[0075] The stacked structure is etched along a direction perpendicular to the substrate 1 to form a plurality of first holes K1 penetrating the stacked structure. The plurality of first holes K1 can be spaced apart along the second direction Y. When multiple semiconductor structures are fabricated, multiple rows of first holes K1 distributed along the second direction Y can be formed. The multiple rows of first holes K1 are spaced apart along the first direction X.

[0076] After depositing the first conductive film, it is smoothed. The first conductive film fills the first hole K1, forming a vertical conductive portion 51. The side of the vertical conductive portion 51 facing away from the substrate 1 is flush with the side of the topmost first insulating layer 11 facing away from the substrate 1. Figures 2A to 2D As shown, Figures 2A to 2D These are cross-sectional views along the A4A4', BB', CC', and DD' directions respectively, provided in some embodiments after the formation of the first hole K1 and the vertical conductive part 51.

[0077] As used herein, the term "substrate" means and includes a base material or structure on which a material such as a vertical field-effect transistor is formed. A substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. A substrate can be a conventional silicon substrate or other bulk substrate that includes layers of semiconductor material.

[0078] In some embodiments, the first insulating film may be a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant K < 3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2). The materials of the subsequent second and third insulating films are similar to those of the first insulating film and will not be described further.

[0079] In some embodiments, the sacrificial layer film may be a film layer that has an etching selectivity ratio with the first insulating film, such as SiN.

[0080] In some embodiments, the first conductive film may be one or more of the following different types of materials:

[0081] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals.

[0082] Alternatively, it can be conductive metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), and indium oxide (InO); or conductive metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0083] Alternatively, it could be polycrystalline silicon, silicon, germanium, silicon-germanium, etc., which become conductive after doping.

[0084] The materials of the second conductive film are similar to those of the first conductive film, and will not be described in detail here.

[0085] In some embodiments, the first hole K1 along a cross section parallel to the substrate 1 can be square, circular, elliptical, etc.

[0086] 2) Form the first trench T1 and the first dummy layer 71;

[0087] The stacked structure is etched along a direction perpendicular to the substrate 1 to form a first trench T1 that penetrates the stacked structure. The first trench T1 extends along a second direction Y, and the first trench T1 and the first hole K1 are distributed at intervals along a first direction X.

[0088] After depositing the first dummy layer film, it is smoothed to form the first dummy layer 71 that fills the first trench T1, as shown below. Figures 3A to 3C As shown, Figures 3A to 3C These are cross-sectional views along the A4A4', BB', and CC' directions respectively, provided in some embodiments, after the formation of the first trench T1 and the first dummy layer 71. A cross-sectional view along the DD' direction is shown in the reference diagram. Figure 2D .

[0089] In some embodiments, the first dummy layer film may be a film layer with an etching selectivity ratio to the first insulating layer film and the sacrificial layer film, such as polysilicon. The subsequent second dummy layer film is made of a similar material to the first dummy layer film and will not be described further.

[0090] 3) Formation of the second hole K2;

[0091] A second insulating film is deposited to form a second insulating layer 12 covering the aforementioned structure. The second insulating layer 12 can protect the vertical conductive part 51.

[0092] The first dummy layer 71 is etched along a direction perpendicular to the substrate 1 to form a plurality of second holes K2. The plurality of second holes K2 are spaced apart along the second direction Y. The sidewalls of the second holes K2 expose a plurality of the first insulating layers 11 and a plurality of the sacrificial layers 10. The dimensions of the second holes K2 along the first direction X and the dimensions of the first dummy layer 71 along the first direction X can be the same, such as... Figures 4A to 4D As shown, Figures 4A to 4D The figures provided are cross-sectional views along the A4A4', BB', CC', and EE' directions after the formation of the second hole K2, as provided in some embodiments. The cross-sectional view along the DD' direction can be found in [reference needed]. Figure 2D The number of first holes K1 in a column of first holes K1 is the same as the number of second holes K2 in a column of second holes K2. The second holes K2 and the first holes K1 are distributed along a first direction X.

[0093] 4) Forming a step in the semiconductor structure;

[0094] After depositing or coating a filler film, the filler layer is ground flat to form a filler layer 41 that fills the second hole K2; the side of the filler layer 41 facing away from the substrate 1 can be flush with the side of the second insulating layer 12 facing away from the substrate 1.

[0095] Photoresist is coated to form a photoresist layer 42 covering the aforementioned structure. The area of ​​the photoresist layer 42 corresponding to one or a row of second holes K2 is removed to expose one or a row of second holes K2 distributed along the first direction X; for example, the first or first row of second holes K2 can be exposed.

[0096] The filling layer 41 in the second hole K2 is etched to the first preset height; as shown. Figures 5A to 5E As shown, Figures 5A to 5EThe images show cross-sectional views along the A4A4', BB', CC', DD', and EE' directions after a step is formed in some embodiments of the semiconductor structure. The first preset height can be determined based on the height of the horizontal conductive portion of the different connecting electrodes in the semiconductor structure to be formed. Taking the first second hole K2 as an example, it can be the height of the film layer where the horizontal conductive portion 52 connected to the vertical conductive portion 51 in the first first hole K1 corresponding to the first second hole K2 is located. In this embodiment, it can be the height of the topmost sacrificial layer 10, that is, the filling layer 41 in the first K2 is etched to be approximately flush with the side of the topmost sacrificial layer 10 away from the substrate 1.

[0097] In some embodiments, the filler layer film may be a film layer with an etching selectivity ratio to the first dummy layer 71, the first insulating layer 11, and the sacrificial layer 10, such as carbon. The filler layer film can be coated by spin coating.

[0098] 5) Forming another step in the semiconductor structure;

[0099] Remove the area of ​​the photoresist layer 42 corresponding to another or another row of second holes K2 to expose another or another row of second holes K2 distributed along the first direction X; for example, the second or second row of second holes K2 can be exposed.

[0100] The filling layer 41 in one or a row of the second holes K2 is etched to the first preset height. At this time, the filling layer 41 in the second holes K2 exposed in the previous step is also etched, and the height decreases to the second preset height; such as Figures 6A to 6D As shown, Figures 6A to 6D These are cross-sectional views along the A4A4', BB', DD', and EE' directions, respectively, after forming another step of the semiconductor structure according to some embodiments. Taking the exposure of the second second hole K2 as an example, the second preset height is, for example, the height of the film layer where the horizontal conductive part 52 connected to the vertical conductive part 51 in the second first hole K1 corresponding to the second second hole K2 is located. In this embodiment, it can be the height of the second-layer sacrificial layer 10, that is, the filling layer 41 in the first second hole K2 is approximately flush with the side of the second-layer sacrificial layer 10 away from the substrate 1; the filling layer 41 in the second second hole K2 is approximately flush with the side of the topmost sacrificial layer 10 away from the substrate 1. A cross-sectional view in the CC' direction is shown in the reference diagram. Figure 5C .

[0101] 6) Forming a semiconductor structure;

[0102] Repeat the aforementioned etching of the photoresist layer 42 to expose one or a row of second holes K2. Repeat the etching process of the filling layer 41 in the exposed second holes K2 multiple times until all the filling layers 41 in the second holes K2 are etched, forming a semiconductor structure. Taking five second holes K2 as an example, expose the third, fourth, and fifth second holes K2 respectively, and etch the filling layers 41 in multiple second holes K2, making the heights of the different filling layers 41 different, forming a semiconductor structure. The sacrificial layer 10 closest to the substrate 1 is called the first sacrificial layer 10. Then, the side of the filling layer 41 in the first second hole K2 facing away from the substrate 1 can be flush with the side of the first sacrificial layer 10 facing away from the substrate 1; the side of the filling layer 41 in the second second hole K2 facing away from the substrate 1 can be flush with the side of the second sacrificial layer 10 facing away from the substrate 1; and so on, until the side of the filling layer 41 in the fifth second hole K2 facing away from the substrate 1 can be flush with the side of the fifth sacrificial layer 10 facing away from the substrate 1. Figures 7A to 7D As shown, Figures 7A to 7D These are cross-sectional views along the A4A4', BB', CC', and EE' directions after the semiconductor structure has been formed, provided in some embodiments.

[0103] The etching sequence in the different second holes K2 described above is merely an example, and the embodiments disclosed herein are not limited thereto. It is possible to achieve a height of the filling layer 41 in the different second holes K2 within the same column that reaches the height of the multiple horizontal conductive portions 52 to be formed. Furthermore... Figure 7D In the arrangement of the second holes K2, the height of the filling layer 41 in the second holes K2 increases sequentially. However, the embodiments disclosed herein are not limited to this. The height order of the filling layer 41 in different second holes K2 may not follow the arrangement order of the second holes K2. For example, the side of the filling layer 41 in the second second hole K2 facing away from the substrate 1 may be flush with the side of the fifth sacrificial layer 10 facing away from the substrate 1.

[0104] 7) Form a second virtual layer 72;

[0105] A second dummy layer film is deposited, covering the bottom wall and sidewalls of the second hole K2 where the filling layer 41 is formed. The second dummy layer film covering the bottom wall of the second hole K2 is etched away, while the second dummy layer film covering the sidewalls of the second hole K2 is retained, forming the second dummy layer 72. Figures 8A to 8D As shown, Figures 8A to 8D The images show cross-sectional views along the A4A4', BB', CC', and EE' directions after the formation of the second dummy layer 72, as provided in some embodiments. The second dummy layer 72 can protect the sacrificial layer 10 exposed on the sidewall of the second hole K2 during subsequent operations.

[0106] 8) Form groove A1;

[0107] Etch the filling layer 41 in each second hole K2 to expose a sacrificial layer 10 on the sidewall of the second hole K2;

[0108] The exposed sacrificial layer 10 is etched along a direction parallel to the substrate 1 to form a groove A1. The bottom wall of the groove A1 (i.e., the side opposite to the opening of the groove A1) does not expose the vertical conductive portion 51. That is, a portion of the sacrificial layer 10 is retained during etching, such as... Figures 9A to 9E As shown, Figures 9A to 9E These are cross-sectional views along the directions A4A4', BB', CC', DD', and EE' after the groove A1 is formed, provided in some embodiments.

[0109] 9) The first groove T1 is exposed;

[0110] Etching removes the second insulating layer 12;

[0111] Etching removes the first dummy layer 71 and the second dummy layer 72;

[0112] Etching removes the filler layer 41. At this point, all the film layers in the first trench T1 have been removed, such as... Figures 10A to 10D As shown, Figures 10A to 10D The following are cross-sectional views along the A4A4', BB', CC', and DD' directions after the first groove T1 is exposed, provided in some embodiments.

[0113] 10) Forming a transverse trench L1;

[0114] Based on the first trench T1 and groove A1, the sacrificial layer 10 is etched until the vertical conductive portions 51 distributed along the first direction X with the groove A1 are exposed, forming multiple transverse trenches L1 located in different layers. The bottom wall of the transverse trench L1 exposes only one vertical conductive portion 51, such as... Figures 11A to 11D As shown, Figures 11A to 11D These are cross-sectional views along the A4A4', BB', CC', and DD' directions after the transverse groove L1 is formed, provided in some embodiments.

[0115] 11) Forming signal line 30 and horizontal conductive part 52;

[0116] A second conductive film is deposited, which fills the transverse trench L1 and covers the bottom and sidewalls of the first trench T1. The second conductive film on the bottom and sidewalls of the first trench T1 is etched away to form a horizontal conductive part 52 and a signal line 30. The horizontal conductive part 52 is connected to a vertical conductive part 51.

[0117] After depositing the third insulating film, it is ground smooth. The third insulating film fills the first trench T1 to form the third insulating layer 13, as shown below. Figures 1A to 1J As shown.

[0118] This disclosure also provides an electronic device, including the semiconductor structure described in any of the foregoing embodiments, or a semiconductor structure formed by the manufacturing method of the semiconductor structure described in any of the foregoing embodiments.

[0119] In some embodiments, the electronic device may further include: a multilayer memory cell array disposed on a substrate and stacked in a direction perpendicular to the substrate, the memory cell array including a plurality of memory cells, and the signal line connecting at least one of the memory cells. The signal line may, for example, connect to a column of memory cells.

[0120] The electronic device may be: a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited here.

[0121] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection for this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Multiple signal lines stacked on a substrate in a direction perpendicular to the substrate and distributed in multiple layers, and multiple connecting electrodes disposed on the same side of the multiple signal lines; the signal lines extend in a direction parallel to the substrate; The connection electrode includes a horizontal conductive portion extending in a direction parallel to the substrate and a vertical conductive portion extending in a direction perpendicular to the substrate connected to the horizontal conductive portion. The horizontal conductive portion is disposed on the side of the vertical conductive portion facing the signal line. The multiple horizontal conductive portions of the multiple connecting electrodes are distributed in different layers, and the horizontal conductive portions are connected to a signal line in the same layer; the horizontal conductive portions of the connecting electrodes and the connected signal lines form an integral structure, while the vertical conductive portions of the same connecting electrode and the horizontal conductive portions are not integral structures.

2. The semiconductor structure according to claim 1, characterized in that, The signal line and the vertical conductive portion are distributed along a first direction parallel to the substrate, the signal line extends along a second direction parallel to the substrate, and the multiple vertical conductive portions of the multiple connecting electrodes are distributed at intervals along the second direction, with the first direction and the second direction intersecting.

3. The semiconductor structure according to claim 2, characterized in that, The dimension of the horizontal conductive part along the second direction is greater than the dimension of the vertical conductive part along the second direction.

4. The semiconductor structure according to claim 1, characterized in that, The plurality of vertical conductive portions have the same size along the direction perpendicular to the substrate, and the plurality of vertical conductive portions are at the same distance from the substrate.

5. The semiconductor structure according to claim 1, characterized in that, The horizontal conductive portions of the different connecting electrodes do not overlap in their orthographic projection onto the substrate.

6. The semiconductor structure according to claim 1, characterized in that, The horizontal conductive portions of the different connecting electrodes are arranged sequentially on the substrate according to the distance between the horizontal conductive portions and the substrate.

7. A method for manufacturing a semiconductor structure, characterized in that, include: A stacked structure comprising multiple alternating first insulating layers and sacrificial layers is formed on a substrate; A plurality of first holes are formed that penetrate the stacked structure along a direction perpendicular to the substrate, and vertical conductive portions are formed that fill the first holes; The plurality of the first holes are spaced apart along a second direction parallel to the substrate; A first trench is formed that penetrates the stacked structure in a direction perpendicular to the substrate and extends in a second direction, and a plurality of transverse trenches that are spaced apart in a direction perpendicular to the substrate and extend in a second direction and communicate with the first trench. The transverse trenches are located between adjacent first insulating layers. Each transverse trench exposes one of the vertical conductive portions between the plurality of vertical conductive portions, and different transverse trenches expose different vertical conductive portions. A second conductive film is deposited to fill the transverse trench, forming a signal line and a horizontal conductive portion that fill the transverse trench. The signal line extends along a second direction, and the horizontal conductive portion connects the vertical conductive portion and the signal line.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, The formation of a first trench extending through the stacked structure perpendicular to the substrate direction and extending in a second direction, and the plurality of lateral trenches communicating with the first trench and spaced apart perpendicular to the substrate direction and extending in the second direction, include: A first trench is formed that penetrates the stacked structure along a direction perpendicular to the substrate and extends along a second direction, and a first dummy layer is formed that fills the first trench; A plurality of second holes are formed through the first dummy layer in a direction perpendicular to the substrate, and the sidewalls of the second holes expose a plurality of the first insulating layers and a plurality of the sacrificial layers; the plurality of second holes are spaced apart in a second direction and correspond one-to-one with a plurality of first holes, and the second holes and their corresponding first holes are spaced apart in a first direction; A filling layer is formed to fill the second hole; the filling layer is etched such that the distance between the filling layer and the substrate on the side away from the substrate in the plurality of second holes is different, and the distance between the different filling layers and the substrate on the side away from the substrate is the same as the distance between the different sacrificial layers and the substrate on the side away from the substrate; a second dummy layer is formed to cover the sidewall of the second hole; The filling layer in each of the second holes is etched so that a sacrificial layer is exposed on the sidewall of the second hole. The exposed sacrificial layer is etched to form a groove that does not expose the vertical conductive portion. The first dummy layer, the second dummy layer, and the fill layer are removed by etching; Based on the first trench and the groove, the sacrificial layer is etched to expose one vertical conductive portion without exposing the remaining vertical conductive portions, thereby forming the transverse trench.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that, The etching of the filling layer such that the distance between the filling layer on the side facing away from the substrate and the substrate in the plurality of second holes is different includes: A photoresist layer covering multiple second holes is formed. The photoresist layer is etched to expose one second hole. The distance between the etched filling layer in the exposed second hole and the substrate on the side facing away from the substrate is a first preset height. The photoresist layer is etched to expose another second hole. The distance between the etched filling layer in the currently exposed second hole and the substrate on the side facing away from the substrate is a first preset height. The distance between the etched filling layer in the already exposed second hole and the substrate on the side facing away from the substrate is a second preset height. The steps of exposing one second hole and etching the filling layer in all exposed second holes are repeated until all second holes are exposed and the filling layer in all second holes is etched to different heights.

10. An electronic device, characterized in that, It includes the semiconductor structure as described in any one of claims 1 to 6, or the semiconductor structure formed by the manufacturing method of the semiconductor structure as described in any one of claims 7 to 9.

11. The electronic device according to claim 10, characterized in that, Also includes: A multilayer memory cell array is disposed on a substrate and stacked in a direction perpendicular to the substrate. The memory cell array includes multiple memory cells, and the signal line is connected to at least one of the memory cells.

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