Double-layer source via structure, silicon carbide mosfet device and chip

Abstract

The application discloses a double-layer source via structure, a silicon carbide MOSFET device and a chip, the double-layer source via structure in the silicon carbide MOSFET device or the chip comprises a semiconductor substrate layer for forming a source region and one or more first interlayer dielectric layers arranged on the semiconductor substrate layer, further comprises a source via penetrating through the first interlayer dielectric layer and extending to the source region, one or more second interlayer dielectric layers wrapped in the first interlayer dielectric layer, wherein the second interlayer dielectric layer is a nitrogen-containing dielectric layer, and a via-filling metal filling the source via. By including the second interlayer dielectric layer in the first interlayer dielectric layer, the second interlayer dielectric layer is prevented from being consumed due to contact with the via-filling metal, thereby avoiding the problem that the insulation integrity of the ILD layer is damaged and the corresponding device gate-source short circuit is failed, and the reliability of subsequent devices and chips is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power device technology, and more specifically, to a dual-layer source via structure, a silicon carbide MOSFET device, and a chip. Background Technology

[0002] Silicon carbide (SiC), as a third-generation semiconductor material, possesses excellent properties such as a wide bandgap, high critical breakdown electric field strength, high electron saturation drift velocity, and high thermal conductivity. Power semiconductor devices based on silicon carbide, especially silicon carbide MOSFETs, exhibit significant performance advantages such as high temperature resistance, high voltage resistance, high frequency, and high efficiency, and have broad application prospects in power electronics systems.

[0003] In the manufacturing process of silicon carbide MOSFETs, the interlayer dielectric (ILD) plays a crucial role in electrical isolation, physical protection, reduction of parasitic capacitance, and surface planarization. Common ILD materials typically include silicon dioxide (SiO2) and silicon nitride (Si3N4). Among them, silicon nitride has superior barrier properties and mechanical strength compared to silicon dioxide, and therefore is widely used in the ILD structure of silicon carbide MOSFETs.

[0004] However, silicon nitride has a serious technical problem in practical applications: during the source via filling metal and subsequent high-temperature heat treatment, silicon nitride reacts chemically with the filling metal at high temperatures to form nickel silicide (Ni3Si). This reaction leads to the local consumption of the ILD layer, destroying the insulation integrity of the ILD layer, and ultimately causing the device to fail due to gate-source short circuit.

[0005] Currently, some solutions exist to address the aforementioned problems. For example, an additional barrier layer is placed between the BPSG insulating film and the source electrode to prevent nickel diffusion; a tilted surface is placed in the interlayer insulating film near the contact holes to prevent nickel residue. However, these solutions either require additional material layers and process steps, resulting in higher costs, or they only partially alleviate the problem and cannot fundamentally eliminate the contact and reaction between silicon nitride and the through-hole metal. Summary of the Invention

[0006] The purpose of this invention is to provide a dual-layer source via structure, a silicon carbide MOSFET device and chip, to solve the problem of the insulation integrity of the interlayer dielectric layer being destroyed due to the consumption of the silicon nitride layer.

[0007] To achieve the above objectives, the present invention provides the following technical solution: To address the aforementioned technical problems, this invention provides a dual-layer source via structure, comprising: Semiconductor substrate layer, used to form the source region; One or more first interlayer dielectric layers disposed on the semiconductor substrate layer; A source via penetrating the first interlayer dielectric layer and extending to the source region; One or more second interlayer dielectric layers are wrapped around the first interlayer dielectric layer; wherein the second interlayer dielectric layer is a nitrogen-containing dielectric layer; The filler metal that fills the source via.

[0008] The aforementioned dual-layer source via structure includes a semiconductor substrate layer for forming the source region and one or more first interlayer dielectric layers disposed on the semiconductor substrate layer. It also includes a source via penetrating the first interlayer dielectric layer and extending to the source region, one or more second interlayer dielectric layers enclosing the first interlayer dielectric layer (where the second interlayer dielectric layer is a nitrogen-containing dielectric layer), and a via-filling metal filling the source via. By including the second interlayer dielectric layer within the first interlayer dielectric layer, contact between the second interlayer dielectric layer and the via-filling metal is avoided, preventing the second interlayer dielectric layer from being consumed. This avoids damage to the insulation integrity of the ILD layer, prevents gate-source short circuits in the corresponding devices from causing failure, and improves the reliability of subsequent devices and chips.

[0009] In one embodiment, the semiconductor substrate includes a GOX layer, a POLY layer, an LPTEOS layer, and a BPSG layer stacked sequentially upwards.

[0010] In one embodiment, it includes: A second interlayer dielectric layer encapsulating the BPSG layer and the LPTEOS layer.

[0011] In one embodiment, the second interlayer dielectric layer is an LPSIN layer.

[0012] In one embodiment, the source via has an upper section and a lower section; the upper section penetrates the BPSG layer, and the lower section penetrates the LPTEOS layer; The upper hole section has a larger cross-sectional dimension in the horizontal direction than the lower hole section.

[0013] In one embodiment, the BPSG layer forms a stepped isolation structure at the junction of the upper and lower aperture segments to cover the end face of the first interlayer dielectric layer located on the sidewall of the lower aperture segment.

[0014] In one embodiment, the horizontal cross-sectional dimension of the lower hole section is 30% to 90% of the horizontal cross-sectional dimension of the upper hole section.

[0015] In one embodiment, the pore-filling metal is a nickel-vanadium alloy.

[0016] This invention also provides a silicon carbide MOSFET device, including the above-described dual-layer source via structure.

[0017] Based on the above-mentioned double-layer source via structure, the substrate and epitaxial structure of silicon carbide MOSFET devices can be formed. The corresponding silicon carbide MOSFET devices are formed on the epitaxial layer, which can avoid the destruction of the insulation integrity of the ILD layer, avoid the problem of gate-source short circuit and failure of the corresponding devices, and improve device reliability.

[0018] This invention also provides a chip including the aforementioned silicon carbide MOSFET device. Based on this silicon carbide MOSFET device, the insulation integrity of the ILD layer can be avoided, preventing the corresponding device from failing due to gate-source short circuits, thus improving chip reliability. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings. Figure 1 This is a schematic diagram of a dual-layer source via structure according to an embodiment of the application; Figure 2 This is a schematic diagram of SIN discoloration for a traditional double-layer source via structure; Figure 3 This is a schematic diagram of a traditional double-layer source via structure with missing SIN. Figure 4 This is a schematic diagram of a preferred embodiment of a dual-layer source via structure; Figure 5 This is an electron microscope image of the double-layer source via structure according to an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] To facilitate understanding of the embodiments of this application, further explanation and description will be provided below with reference to the accompanying drawings and specific embodiments. These embodiments do not constitute a limitation on the embodiments of this application. In the drawings, the dimensions and relative dimensions of components may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a specific process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, the same reference numerals denote the same components.

[0022] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “(the)” are also intended to include the plural forms. Furthermore, when the terms “comprising” and / or “including” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, parts, components, and / or groups thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, parts, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, thus explaining the inherent biases in measurements, calculated values, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0023] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0024] Figure 1 This is a schematic diagram of a dual-layer source via structure according to an embodiment of the application, as shown below. Figure 1 As shown, a dual-layer source via structure according to one embodiment of the application includes: Semiconductor substrate 100 is used to form the source region; One or more first interlayer dielectric layers 101 are disposed on the semiconductor substrate 100; A source via penetrating the first interlayer dielectric layer 101 and extending to the source region; One or more second interlayer dielectric layers 102 are wrapped around the first interlayer dielectric layer 101; wherein the second interlayer dielectric layer is a nitrogen-containing dielectric layer; The filler metal 103 fills the source via.

[0025] The semiconductor substrate layer is the source region of the semiconductor substrate, including a silicon-based substrate and a silicon carbide substrate. Preferably, in this embodiment, the semiconductor substrate layer is a silicon carbide substrate. Based on this embodiment, Figure 2This is a schematic diagram of SIN discoloration for a traditional double-layer source via structure, as shown below. Figure 2 As shown, the SIN layer is in direct contact with the filler metal, which initially causes the SIN layer to be consumed, resulting in defects.

[0026] Furthermore, Figure 3 This is a schematic diagram of a traditional double-layer source via structure with missing SIN, as shown below. Figure 3 As shown, during the Ni removal etching process, the SIN layer is further etched away due to defects already present in the SIN layer. This further consumes the SIN layer, forming voids (missing). The formation of these voids disrupts the insulation integrity of the original interlayer dielectric layer SIN, which can easily cause a gate-source short circuit and device failure.

[0027] In this embodiment, as Figure 1 As shown, the second interlayer dielectric layer of the nitrogen-containing dielectric layer is wrapped by the first interlayer dielectric layer, so that the second interlayer dielectric layer is not directly exposed in the source via and avoids contact with the via-filling metal.

[0028] In one embodiment, the length of the second interlayer dielectric layer in the horizontal direction is less than that of the first interlayer dielectric layer in the horizontal direction. The first interlayer dielectric layer fills the gap in the horizontal length of the second interlayer dielectric layer, and the horizontal dimension of the source via opening meets the requirement of not exposing the second interlayer dielectric layer.

[0029] In one embodiment, Figure 4 This is a schematic diagram of a preferred embodiment of a dual-layer source via structure, as shown below. Figure 4 As shown, a preferred embodiment of the dual-layer source via structure includes a GOX layer (gate oxide layer), a POLY layer (polysilicon layer), an LPTEOS layer (amorphous silicon dioxide dielectric layer), and a BPSG layer (borophosphosilicate glass layer) stacked sequentially upwards from the semiconductor substrate layer.

[0030] The second interlayer dielectric layer is the LPSIN (Low Power Semiconductor Insulator) layer.

[0031] like Figure 4 As shown, the LPTEOS layer is deposited on the surface of the semiconductor layer structure using plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD). As the lower dielectric layer of the LPSIN layer, the LPTEOS layer possesses excellent step coverage and insulation properties, and also serves as an etch stop layer for the subsequent first source via.

[0032] The thickness of the LPTEOS layer ranges from 100nm to 500nm. This thickness range ensures that the LPTEOS layer serves as an effective stop layer during etching, without increasing the aspect ratio of the vias due to excessive thickness.

[0033] like Figure 4 As shown, the LPSIN layer is deposited on the upper surface of the LPTEOS layer using LPCVD or PECVD methods. As the upper dielectric layer of the LPTEOS layer, the LPSIN layer utilizes its excellent barrier properties and mechanical strength to provide good physical protection and impurity blocking capabilities for the device. Preferably, the thickness of the LPSIN layer is between 200 nm and 800 nm. This thickness range ensures that the silicon nitride layer fully utilizes its barrier properties and mechanical strength, while avoiding difficulties in subsequent etching due to excessive thickness.

[0034] like Figure 4 As shown, the BPSG layer is disposed above the interlayer dielectric layer, i.e., on the upper surface of the LPSIN layer. The BPSG layer is deposited using atmospheric pressure chemical vapor deposition (APCVD) or sub-atmospheric pressure chemical vapor deposition (SACVD). The BPSG layer has good fluidity and planarization capabilities, achieving surface planarization in the subsequent high-temperature reflow process, providing a flat surface for subsequent metallization processes. Preferably, the thickness of the BPSG layer is 500 nm to 1500 nm. This thickness range ensures that the BPSG layer can fully exert its planarization and isolation functions, while also providing sufficient material margin for the formation of the stepped isolation structure.

[0035] like Figure 4 As shown, the source via penetrates the BPSG layer, LPSIN layer, LPTEOS layer, POLY layer, and GOX layer, extending to the upper surface of the source region. The source via is a channel through which the filler metal forms an ohmic contact with the source region.

[0036] In one embodiment, the source via has an upper section and a lower section; the upper section penetrates the BPSG layer, and the lower section penetrates the LPTEOS layer; The upper hole section has a larger cross-sectional dimension in the horizontal direction than the lower hole section.

[0037] The upper via penetrates the BPSG layer, with its bottom located on the upper surface of the LPSIN layer. The lower via penetrates both the LPSIN and LPTEOS layers, with its bottom extending to the upper surface of the source region. The horizontal cross-sectional dimension of the lower via is 30% to 90% of the horizontal cross-sectional dimension of the upper via.

[0038] The horizontal cross-sectional dimension of the upper hole section is larger than that of the lower hole section. Specifically, the critical dimension (CD) of the lower hole section is 30% to 90% of that of the upper hole section.

[0039] In this embodiment, the CD of the upper hole section is 2.0 μm, the CD of the lower hole section is 1.4 μm, and the difference in cross-sectional dimensions between the two in the horizontal direction is 0.6 μm.

[0040] Because the cross-sectional dimensions of the upper borehole section are larger than those of the lower borehole section, the BPSG layer forms a stepped isolation structure at the junction of the upper and lower borehole sections. This stepped isolation structure is the portion of the BPSG layer that protrudes inward from the sidewall of the through-hole, completely covering the end face of the LPSIN layer located on the sidewall of the lower borehole section, thus enveloping the end face of the LPSIN layer beneath the BPSG layer.

[0041] In one embodiment, such as Figure 4 As shown, the filler metal is used to fill the source via. The filler metal is a nickel-vanadium alloy (Ni-V), which is deposited in the source via using physical vapor deposition (PVD). Nickel silicide is then formed on the surface of the source region through high-temperature annealing to achieve low-resistance ohmic contact with the source region.

[0042] like Figure 4 As shown, after the via filler metal fills the source via, the sidewalls of the via filler metal contact the BPSG layer (upper via segment) and the LPTEOS layer (lower via segment). At the stepped isolation structure, the via filler metal contacts the BPSG layer, while the end face of the LPSIN layer is completely covered by the stepped isolation structure. Therefore, there is no direct contact between the via filler metal and the LPSIN layer; they are physically isolated by the BPSG layer. The LPSIN layer remains intact, the insulation integrity of the ILD layer is guaranteed, and the device will not experience a gate-source short circuit due to ILD layer failure.

[0043] In the manufacturing process of silicon carbide MOSFETs, after the source via is formed, filler metal is deposited and filled into the source via. Subsequently, the device undergoes high-temperature heat treatment to form an ohmic contact between the filler metal and the source region.

[0044] Figure 5 Here is an electron microscope image of the double-layer source via structure according to an embodiment of this application, as shown. Figure 5 As shown, the double-layer source via structure of this application does not exhibit SIN discoloration or further SIN missing issues, and there are no voids on the inner wall of the source via, thus effectively ensuring its insulation integrity.

[0045] The dual-layer source via structure of any of the above embodiments includes a semiconductor substrate layer for forming the source region and one or more first interlayer dielectric layers disposed on the semiconductor substrate layer. It also includes a source via penetrating the first interlayer dielectric layer and extending to the source region, one or more second interlayer dielectric layers enclosing the first interlayer dielectric layer, wherein the second interlayer dielectric layer is a nitrogen-containing dielectric layer, and a via-filling metal filling the source via. By including the second interlayer dielectric layer within the first interlayer dielectric layer, contact between the second interlayer dielectric layer and the via-filling metal is avoided, preventing the second interlayer dielectric layer from being consumed. This avoids damage to the insulation integrity of the ILD layer, prevents the corresponding device from failing due to gate-source short circuits, and improves the reliability of subsequent devices and chips.

[0046] This application also provides a silicon carbide MOSFET device, including the above-described dual-layer source via structure.

[0047] The aforementioned silicon carbide MOSFET device fundamentally eliminates the reaction between silicon nitride and the via metal. By setting a double-layer source via with an upper aperture larger than the lower aperture, the BPSG layer naturally forms a stepped isolation structure within the via, completely covering the end face of the silicon nitride layer. After filling, the via metal only contacts the BPSG and TEOS layers, and is physically isolated from the silicon nitride layer by the BPSG layer, with no direct contact. Therefore, it will not chemically react at high temperatures, the ILD layer will not be consumed, and the insulation integrity is guaranteed. Because the end face of the silicon nitride layer is completely covered by the BPSG layer, the insulation integrity of the ILD layer is guaranteed, and the silicon nitride layer will not be consumed or damaged. Therefore, short circuits between the gate and source will not occur due to ILD layer insulation failure, significantly improving device reliability and yield.

[0048] Compared to traditional silicon carbide MOSFET devices, no additional material layer is required. Isolation is achieved by optimizing the source via aperture design (two openings with different CD values), without adding any extra material layers or complex process steps, resulting in low manufacturing costs and good process compatibility. Furthermore, the absence of direct contact between the silicon nitride layer and the via-filling metal avoids delamination and cracking issues caused by the difference in thermal expansion coefficients between the two materials, improving the device's mechanical strength and long-term reliability.

[0049] Furthermore, since the reaction between silicon nitride and the pore-filling metal at high temperatures is completely eliminated, the high-temperature heat treatment process in device manufacturing is no longer constrained by this reaction, the high-temperature process window is expanded, and each process step can be optimized independently.

[0050] Based on the aforementioned silicon carbide MOSFET device, this application also provides a chip including the aforementioned silicon carbide MOSFET device. Based on this silicon carbide MOSFET device, the insulation integrity of the ILD layer can be avoided, preventing the corresponding device from failing due to gate-source short circuit, thus improving chip reliability.

[0051] The following points should be noted regarding this application: (1) The accompanying drawings of the embodiments of this application only involve the structures involved in the embodiments of this application. Other structures can be referred to the general design.

[0052] (2) For clarity, the thickness and dimensions of layers or structures are enlarged in the accompanying drawings used to describe embodiments of the invention. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be intermediate elements present.

[0053] (3) Where there is no conflict, the embodiments and features in the embodiments of this application can be combined with each other to obtain new embodiments. The above are only specific implementations of this application, but the protection scope of this application is not limited thereto, and the protection scope of this application shall be determined by the protection scope of the claims.

[0054] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0055] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

[0056] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above description is only a specific embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A double-layer source via structure, characterized in that, include: Semiconductor substrate layer, used to form the source region; One or more first interlayer dielectric layers disposed on the semiconductor substrate layer; A source via penetrating the first interlayer dielectric layer and extending to the source region; One or more second interlayer dielectric layers are wrapped around the first interlayer dielectric layer; wherein the second interlayer dielectric layer is a nitrogen-containing dielectric layer; The filler metal that fills the source via.

2. The dual-layer source via structure according to claim 1, characterized in that, It includes the GOX layer, POLY layer, LPTEOS layer and BPSG layer stacked sequentially upwards from the semiconductor substrate layer.

3. The dual-layer source via structure according to claim 2, characterized in that, include: A second interlayer dielectric layer encapsulating the BPSG layer and the LPTEOS layer.

4. The dual-layer source via structure according to claim 1 or 3, characterized in that, The second interlayer dielectric layer is an LPSIN layer.

5. The dual-layer source via structure according to claim 2 or 3, characterized in that, The source via has an upper section and a lower section; the upper section penetrates the BPSG layer, and the lower section penetrates the LPTEOS layer; The upper hole section has a larger cross-sectional dimension in the horizontal direction than the lower hole section.

6. The dual-layer source via structure according to claim 5, characterized in that, The BPSG layer forms a stepped isolation structure at the junction of the upper and lower hole sections to cover the end face of the first interlayer dielectric layer located on the sidewall of the lower hole section.

7. The dual-layer source via structure according to claim 1, characterized in that, The horizontal cross-sectional dimension of the lower hole section is 30% to 90% of the horizontal cross-sectional dimension of the upper hole section.

8. The dual-layer source via structure according to claim 1, characterized in that, The filling metal is a nickel-vanadium alloy.

9. A silicon carbide MOSFET device, characterized in that, Includes the dual-layer source via structure as described in any one of claims 1 to 8.

10. A chip, characterized in that, Including the silicon carbide MOSFET device as described in claim 9.

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