Semiconductor chip, chip stack structure, and semiconductor package including the same

Abstract

According to some embodiments of the present disclosure, a semiconductor chip includes a device layer having a first surface and a second surface opposite to the first surface, and a first wiring structure on the first surface of the device layer. The first wiring structure includes a first via layer having a first via, a first metal layer having a first wiring, the first metal layer being stacked on the first via layer in a first direction perpendicular to the first surface of the device layer, and a first heat dissipation structure including a first heat dissipation film having a first portion of a bottom surface and side surfaces surrounding the first via. The first heat dissipation structure includes a 2D material, and an upper surface of the first portion of the first heat dissipation film contacts a lower surface of the first wiring.

Description

Technical Field

[0001] This disclosure relates to semiconductor chips, chip stacking structures, and semiconductor packages including the thereof. Background Technology

[0002] As electronic devices become lighter and more powerful, there is a growing need for smaller and higher-performance semiconductor packages in the semiconductor packaging field. To achieve miniaturization, weight reduction, high performance, and high reliability in semiconductor packages, research and development have been ongoing on semiconductor packages with multiple vertically stacked semiconductor chips.

[0003] When multiple semiconductor chips are stacked, power density increases, and heat can be generated as power and signals are exchanged between the stacked chips. Because the generated heat can raise the temperature of multiple semiconductor chips or semiconductor packages, this heat needs to be dissipated to the outside.

[0004] The purpose of this disclosure is to provide semiconductor chips, chip stack structures, and semiconductor packages including thereof with improved thermal performance.

[0005] Another object of this disclosure is to provide semiconductor chips, chip stacking structures, and semiconductor packages including thereof with improved electrical performance and electrical reliability. Summary of the Invention

[0006] According to some embodiments of this disclosure, a semiconductor chip includes: a device layer having a first surface and a second surface opposite to the first surface; and a first wiring structure on the first surface of the device layer. The first wiring structure includes: a first via layer including a first via; a first metal layer including a first wiring, the first metal layer being stacked on the first via layer in a first direction perpendicular to the first surface of the device layer; and a first heat dissipation structure including a first heat dissipation film, the first heat dissipation film including a first portion surrounding a bottom surface and a side surface of the first via, the first heat dissipation structure being formed of a two-dimensional (2D) material. The upper surface of the first portion of the first heat dissipation film is contacting the lower surface of the first wiring.

[0007] According to some embodiments of this disclosure, a chip stacking structure includes: a first semiconductor chip including a first substrate, a first device layer on the first substrate, and a first front-side wiring structure on the front surface of the first device layer; a second semiconductor chip including a second substrate, a second device layer on the second substrate, and a second front-side wiring structure on the front surface of the second device layer, the second semiconductor chip being stacked on the first semiconductor chip; a through electrode penetrating at least a portion of the first semiconductor chip; and a through heat dissipation film surrounding at least a portion of the through electrode. The first front-side wiring structure includes: a first front-side via layer including a first front-side via, the first front-side via layer being disposed on the first device layer; a first front-side metal layer including the first front-side wiring, the first front-side metal layer being disposed on the first front-side via layer; and a first front-side heat dissipation structure including a first portion surrounding the bottom surface and side surface of the first front-side via. The second front-side wiring structure includes: a second front-side via layer, including a second front-side via, the second front-side via layer being disposed on the second device layer; a second front-side metal layer, including second front-side wiring, the second front-side metal layer being disposed on the second front-side via layer; and a second front-side heat dissipation structure, including a first portion surrounding the bottom surface and side surface of the second front-side via.

[0008] According to some embodiments of this disclosure, a semiconductor package includes: a package substrate; and a chip stack structure disposed on the package substrate. The chip stack structure includes: a first semiconductor chip including a first device layer and a first front-side wiring structure on the first device layer; a second semiconductor chip including a second device layer and a second front-side wiring structure on the second device layer, and stacked on the first semiconductor chip; a through electrode penetrating at least a portion of the first semiconductor chip; and a through heat dissipation film surrounding at least a portion of the through electrode. The first front-side wiring structure includes: a first front-side via layer including a first front-side via; a first front-side metal layer including a first front-side wiring, the first front-side metal layer being disposed on the first front-side via layer; and a first front-side heat dissipation structure including a first portion surrounding a bottom surface and a side surface of the first front-side via. The second front-side wiring structure includes: a second front-side via layer including a second front-side via; a second front-side metal layer including a second front-side wiring, the second front-side metal layer being disposed on the second front-side via layer; and a second front-side heat dissipation structure including a first portion surrounding a bottom surface and a side surface of the second front-side via. The heat dissipation film, the first front heat dissipation structure, and the second front heat dissipation structure all contain 2D materials.

[0009] According to some embodiments of this disclosure, a method of manufacturing a semiconductor chip includes: forming a device layer on a substrate; and forming a front-side wiring structure on the device layer. The step of forming the front-side wiring structure may include: forming a first front-side via layer; forming a first front-side metal layer on the first front-side via layer; and forming a first front-side heat dissipation film in the first front-side via layer and the first front-side metal layer.

[0010] According to the above manufacturing method, the step of forming the first front via layer may include: forming a first interlayer insulating film on the device layer; forming a first via in the first interlayer insulating film; and filling the first via with conductive material to form the first via.

[0011] The above manufacturing method may further include: forming a heat-dissipating insulating film on a portion of the first front heat dissipation film.

[0012] According to the above manufacturing method, the first front heat dissipation film may include graphene, and the heat dissipation insulating film may include graphene oxide.

[0013] Based on the manufacturing method described above, the step of forming a heat-dissipating insulating film can be performed through an oxidation process.

[0014] The above manufacturing method may further include: forming a back-side wiring structure after forming a front-side wiring structure. The step of forming the back-side wiring structure may include: attaching a support substrate to the front-side wiring structure; removing the substrate; forming a first back-side via layer on the device layer; forming a first back-side metal layer on the first back-side via layer; and forming a first back-side heat dissipation film in the first back-side via layer and the first back-side metal layer.

[0015] The above manufacturing method may further include: forming a through electrode after forming the back-side wiring structure. The step of forming the through electrode may include: forming a trench that penetrates the support substrate, the front-side wiring structure, and the device layer; forming a through heat dissipation film in the trench; and filling the through heat dissipation film with a conductive material.

[0016] The above manufacturing methods may also include: forming a surface heat dissipation film on a supporting substrate.

[0017] According to some embodiments of this disclosure, the heat dissipation performance of semiconductor chips, chip stack structures, and semiconductor packages including them can be improved.

[0018] According to some embodiments of this disclosure, the electrical performance and electrical reliability of semiconductor chips, chip stack structures, and semiconductor packages including the semiconductor chips can be improved. Attached Figure Description

[0019] Figure 1 This is a cross-sectional view showing a semiconductor package according to some example embodiments of the present disclosure.

[0020] Figure 2 This is a cross-sectional view showing some components of a semiconductor chip according to some example embodiments of the present disclosure.

[0021] Figure 3 This is a cross-sectional view showing some components of a semiconductor chip according to some example embodiments of the present disclosure.

[0022] Figure 4 This is a cross-sectional view showing some components of a semiconductor chip according to some example embodiments of the present disclosure.

[0023] Figure 5 This is a cross-sectional view showing some components of a semiconductor chip according to some example embodiments of the present disclosure.

[0024] Figure 6 This is a cross-sectional view showing some components of a semiconductor chip according to some example embodiments of the present disclosure.

[0025] Figure 7 This is a cross-sectional view showing some components of a semiconductor chip according to some example embodiments of the present disclosure.

[0026] Figures 8 to 11 This is a cross-sectional view showing a chip stack structure according to some example embodiments of the present disclosure.

[0027] Figures 12 to 21 This is a cross-sectional view illustrating a method of manufacturing a semiconductor chip and a chip stack structure according to some example embodiments of the present disclosure. Detailed Implementation

[0028] Referring to the accompanying drawings, a semiconductor chip, a chip stack structure, and a semiconductor package including the semiconductor chip according to some embodiments of the present disclosure are described in detail below. The same reference numerals always refer to the same elements.

[0029] It will be understood that when an element is referred to as being “connected” or “bonded” to another element or “on” another element, the element may be directly connected to or bonded to said other element or directly on said other element, or there may be an intermediate element present. Conversely, when an element is referred to as being “directly connected” or “directly bonded” to another element, or referred to as being “in contact” with another element or “in contact” with another element (or using any form of the word “in contact”), there is no intermediate element at the point of contact.

[0030] It will be understood that although the terms first and / or primary, second and / or secondary, third and / or tertiary, etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. Such terms may include, for example, but not limited to, "first," "primary first," "secondary first," "second," "primary second," "secondary second," etc. Unless the context otherwise indicates, such terms are used only to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion, for example, as a naming convention. Therefore, without departing from the teachings of the invention, the first and / or primary elements, components, regions, layers, or portions discussed below in one part of the specification may be referred to as second and / or secondary elements, components, regions, layers, or portions in another part of the specification or in the claims. Furthermore, in certain cases, even if the terms are not described in the specification as first and / or primary, second and / or secondary, the terms may still be referred to as first and / or primary, second and / or secondary in the claims in order to distinguish the different claimed elements from each other.

[0031] Terms such as “identical,” “equal,” “planar,” or “coplanar” used herein when referring to orientation, layout, location, shape, size, quantity, or other measurement do not necessarily mean precisely identical orientation, layout, location, shape, size, quantity, or other measurement, but are intended to cover substantially identical orientation, layout, location, shape, size, quantity, or other measurement within acceptable variations that may occur, for example, due to manufacturing processes. Unless otherwise indicated by context or other statements, the term “substantially” may be used herein to emphasize this meaning. For example, items described as “substantially identical,” “substantially equal,” or “substantially planar” may be precisely identical, equal, or planar, or may be identical, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.

[0032] For ease of description, spatial relative terms (such as "below," "under," "lower," "above," "upper," etc.) are used herein to describe the relationship of one element or feature as shown in the figure to another element(s) or feature(s). It will be understood that, in addition to the orientation depicted in the figure, spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, an element described as "below" or "under" other elements or features would be oriented as "above" other elements or features. Thus, the term "below" can cover both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein are interpreted accordingly.

[0033] Figure 1 This is a cross-sectional view showing a semiconductor package according to some example embodiments of the present disclosure.

[0034] Reference Figure 1 According to some embodiments of the present disclosure, the semiconductor package 1 may include a package substrate 10, a first semiconductor chip 100, a second semiconductor chip 200, a first connection terminal 191, a second connection terminal 192, a lower terminal 193, and a molding layer 50.

[0035] The packaging substrate 10 may be a printed circuit board (PCB), a ceramic substrate, a packaging manufacturing wafer, an interposer (or interposer layer), or a redistribution layer. In some embodiments, the printed circuit board may be a multilayer printed circuit board having a substrate substrate in which multiple substrate layers are stacked. In some embodiments, each of the multiple substrate layers constituting the substrate substrate may be formed of at least one material selected from phenolic resin, epoxy resin, and polyimide. For example, each of the multiple matrix layers constituting the substrate may be formed from at least one material selected from flame retardant 4 (FR-4), tetrafunctional epoxy, polyphenylene ether, epoxy / polyphenylene oxide, BT (bismaleimide triazine) resin, thermount (or polyamide fiber nonwoven fabric), cyanate ester, polyimide, and liquid crystal polymer, or may include at least one material selected from flame retardant 4 (FR-4), tetrafunctional epoxy, polyphenylene ether, epoxy / polyphenylene oxide, BT (bismaleimide triazine) resin, thermount (or polyamide fiber nonwoven fabric), cyanate ester, polyimide, and liquid crystal polymer.

[0036] The packaging substrate 10 may include a wiring pattern 11, an upper pad 12, and a lower pad 13. The wiring pattern 11 may be disposed on the upper and lower surfaces of each of a plurality of substrate layers. The wiring pattern 11 may be formed, for example, from electrolytically deposited copper foil, rolled annealed copper foil, stainless steel foil, aluminum foil, ultrathin copper foil, sputtered copper, copper alloy, etc. In some embodiments, conductive vias (not shown) connecting the wiring patterns 11 to each other may electrically connect the wiring patterns 11 to each other. For example, each of the conductive vias may contact a corresponding upper and lower surface of the wiring pattern 11 at a different layer. The conductive vias may be formed to penetrate at least one of the plurality of substrate layers. In some embodiments, each conductive via may be formed of copper, nickel, stainless steel, or beryllium copper.

[0037] An upper pad 12 may be disposed on the upper surface of the package substrate 10, and a lower pad 13 may be disposed on the lower surface of the package substrate 10. For example, the upper surface of the upper pad 12 may be coplanar with the upper surface of the package substrate 10, and the lower surface of the lower pad 13 may be coplanar with the lower surface of the package substrate 10. Multiple upper pads 12 and lower pads 13 may be provided. A lower terminal 193 may be disposed on the upper pad 12. For example, each lower terminal 193 may contact the upper surface of a corresponding upper pad 12. The first semiconductor chip 100 and the package substrate 10 may be electrically connected via the upper pads 12 and the lower terminals 193.

[0038] Multiple external terminals 14 may be disposed on multiple lower pads 13. For example, each external terminal 14 may contact the lower surface of a corresponding one of the multiple lower pads 13. The semiconductor package 1 may be mounted on a system board via the multiple external terminals 14 and the multiple lower pads 13. For example, the multiple external terminals 14 may be electrically connected to pads of the system board.

[0039] A first semiconductor chip 100 may be mounted on a package substrate 10. The upper surface of the first semiconductor chip 100 represents the surface facing the second semiconductor chip 200, and the lower surface of the first semiconductor chip 100 represents the surface facing the package substrate 10. In some embodiments, the upper surface of the first semiconductor chip 100 may be a back surface on which a back-side wiring layer is formed. In another embodiment, the upper surface of the first semiconductor chip 100 may be a front surface on which a device layer and a front-side wiring layer are formed.

[0040] The first semiconductor chip 100 may include a first substrate 110, an upper pad 180, a lower pad 185, and a through electrode 155.

[0041] The first substrate 110 may include semiconductor elements (such as silicon or germanium), or may include compound semiconductors (such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP)). The first substrate 110 may have a silicon-on-insulator (SOI) structure. The first substrate 110 may include conductive regions (e.g., impurity-doped wells or impurity-doped structures). The first substrate 110 may include various device isolation structures (such as shallow trench isolation (STI)).

[0042] The upper pad 180 may be disposed on the upper surface of the first semiconductor chip 100. For example, the upper pad 180 may contact the upper surface of the first semiconductor chip 100 and the upper surface of the through electrode 155. Multiple upper pads 180 may be provided. Each upper pad 180 may be formed of at least one selected from aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au), or may include at least one selected from aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au).

[0043] A lower pad 185 may be disposed on the lower surface of the first semiconductor chip 100. For example, the lower pad 185 may contact the lower surface of the first semiconductor chip 100 and the lower surface of the through electrode 155. Multiple lower pads 185 may be provided. Each lower pad 185 may be formed of at least one selected from aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au), or may include at least one selected from aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au).

[0044] The first connection terminal 191 and the second connection terminal 192 may be disposed on the upper pad 180 of the first semiconductor chip 100. The second semiconductor chip 200 and the first semiconductor chip 100 may be electrically connected via the upper pad 180, the first connection terminal 191, the second connection terminal 192, and the lower pad 195 disposed on the lower surface of the second semiconductor chip 200. The lower terminal 193 may be disposed on the lower pad 185 on the lower surface of the first semiconductor chip 100. For example, each lower terminal 193 may contact a corresponding one of the lower pads 185 of the first semiconductor chip 100. Each of the first connection terminal 191, the second connection terminal 192, and the lower terminal 193 may be formed of tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and / or alloys thereof, or may include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and / or alloys thereof. The alloy may be formed from, for example, Sn-Pb, Sn-Ag, Sn-Au, Sn-Cu, Sn-Bi, Sn-Zn, Sn-Ag-Cu, Sn-Ag-Bi, Sn-Ag-Zn, Sn-Cu-Bi, Sn-Cu-Zn and Sn-Bi-Zn, or may include, for example, Sn-Pb, Sn-Ag, Sn-Au, Sn-Cu, Sn-Bi, Sn-Bi, Sn-Zn, Sn-Ag-Cu, Sn-Ag-Bi, Sn-Ag-Zn, Sn-Cu-Bi, Sn-Cu-Zn and Sn-Bi-Zn.

[0045] The through electrode 155 may extend in a first direction D1 perpendicular to the upper surface of the first semiconductor chip 100. The first direction D1 may correspond to a vertical direction. The through electrode 155 may be located inside the first semiconductor chip 100 and may be arranged in a second direction D2 and a third direction D3, which are horizontal directions perpendicular to the first direction D1. The through electrode 155 may penetrate the first substrate 110 in the first direction D1, penetrating between the upper and lower surfaces of the first substrate 110. The through electrode 155 may provide an electrical path connecting the upper pad 180 and the lower pad 185.

[0046] Each through electrode 155 may include a core metal layer and a barrier film surrounding the core metal layer. The core metal layer may be formed of or may include a metallic material (such as tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu)) and may be formed by plating, physical vapor deposition (PVD), or chemical vapor deposition (CVD). The barrier film may be formed of or include a 2D material and may be formed of or include titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), and may be formed by plating, PVD, or CVD. In some embodiments, a side-surface insulating film including an insulating material (such as silicon oxide, silicon nitride, or silicon oxynitride) may be formed between the side surface of the through electrode 155 and the first substrate 110.

[0047] The first semiconductor chip 100 may be, for example, a buffer chip that includes multiple logic devices and / or memory devices in a device layer. The first semiconductor chip 100 may transmit signals received from a second semiconductor chip 200 stacked on top of the first semiconductor chip 100 to the outside, and may transmit signals and power received from the outside to the second semiconductor chip 200. Although the first semiconductor chip 100 may perform both logic functions and memory functions through logic devices and memory devices, the first semiconductor chip 100 may include only logic devices. In some embodiments, the first semiconductor chip 100 may include volatile memory devices (such as dynamic random access memory (DRAM) and static random access memory (SRAM)) or non-volatile memory devices (such as flash memory).

[0048] The second semiconductor chip 200 may be disposed on the upper surface of the first semiconductor chip 100 and may be stacked in a first direction D1, which is a direction perpendicular to the upper surface of the first semiconductor chip 100. In some embodiments, additional semiconductor chips may be further stacked on the second semiconductor chip 200 in the first direction D1.

[0049] The second semiconductor chip 200 may be configured as a memory chip or memory device to store and / or output data based on received address commands and control commands. For example, the second semiconductor chip 200 may include volatile memory devices (such as DRAM and SRAM) or non-volatile memory devices (such as phase-change random access memory (PRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM)). In some embodiments, the second semiconductor chip 200 may be configured as a plurality of second semiconductor chips stacked on the first semiconductor chip 100 in a first direction D1.

[0050] A molding layer 50 may surround the first semiconductor chip 100 and the second semiconductor chip 200 on the package substrate 10. For example, the molding layer 50 may cover the front surface, side surface, and back surface of the first semiconductor chip 100 and the second semiconductor chip 200. In some embodiments, the molding layer 50 may cover a portion of the lower surface of the first semiconductor chip 100 and the second semiconductor chip 200. The molding layer 50 may include an insulating material (such as a thermosetting resin (e.g., epoxy resin) or a thermoplastic resin (e.g., polyimide)). The molding layer 50 may include a resin containing a reinforcing material (e.g., inorganic filler) (e.g., ABF, FR-4, or BT resin). Furthermore, the molding layer 50 may include a molding material (such as EMC) or a photosensitive material (such as PIE (photoimageable encapsulant)).

[0051] The molding layer 50 may surround the first connection terminal 191 and the second connection terminal 192 disposed between the first semiconductor chip 100 and the second semiconductor chip 200. The molding layer 50 may surround the lower terminal 193 disposed on the lower surface of the first semiconductor chip 100.

[0052] Figure 2 This is a cross-sectional view illustrating some components of a semiconductor chip according to some exemplary embodiments of the present disclosure. In the exemplary embodiments, Figure 2 Semiconductor chip 100 can be used with Figure 1 This corresponds to a portion of the semiconductor chip 100.

[0053] Reference Figure 2 According to some embodiments of the present disclosure, a semiconductor chip 100 may include a substrate 110, a device layer 120, and a wiring structure WS.

[0054] Device layer 120 may be formed on substrate 110. Device layer 120 may be disposed on a first surface 110_1 of substrate 110, the first surface 110_1 may be referred to as the front surface of substrate 110.

[0055] Device layer 120 may include various types of devices. For example, device layer 120 may include field-effect transistors (FETs) (such as planar FETs, FinFETs, or gate all-around FETs (GAAFETs)), memory devices (such as flash memory, DRAM, SRAM, electrically erasable programmable read-only memory (EEPROM), PRAM, MRAM, FeRAM, and RRAM), logic devices (such as AND gates, OR gates, and NOT gates), system-level large-scale integration (LSI), complementary metal-oxide-semiconductor (CMOS) image sensors (CIS), microelectromechanical systems (MEMS), and other active and / or passive devices.

[0056] In some embodiments, the device layer 120 may further include contact structures disposed on the device. The contact structures can connect the device to the wiring structure WS.

[0057] The wiring structure WS can be disposed on the device layer 120 and can be connected to the contact structure of the device layer 120. The wiring structure WS can be electrically connected to the device layer 120. The wiring structure WS can provide at least one of signal lines and / or power lines for various devices in the device layer 120.

[0058] The wiring structure WS may include a first via layer V1, a first metal layer M1, a second via layer V2, a second metal layer M2, and a heat dissipation structure 300. The first via layer V1, the first metal layer M1, the second via layer V2, and the second metal layer M2 may be sequentially stacked on the device layer 120, with the first via layer V1 positioned at the bottommost part of the wiring structure WS. For example, the first via layer V1 may be positioned closest to the substrate 110 among the first via layer V1, the first metal layer M1, the second via layer V2, and the second metal layer M2. The number and arrangement of the layers in the wiring structure WS are merely illustrative, and the wiring structure WS may include more layers than shown or may consist of only a single via layer and a single metal layer.

[0059] The first via layer V1 may include a first-first via V11, a first-second via V12, and a first interlayer insulating film 131. This is merely illustrative, and the first via layer V1 may include three or more vias. The vias disposed in the first via layer V1 may be collectively referred to as the first vias V11 and V12.

[0060] First-first vias V11 and first-second vias V12 may be disposed in the first interlayer insulating film 131. For example, first-first vias V11 and first-second vias V12 may be disposed on the contact structure of the device layer 120. First-first vias V11 and first-second vias V12 may be electrically connected to the first metal layer M1. Although depicted as a single-layer structure, first-first vias V11 and first-second vias V12 may have a multilayer structure.

[0061] The widths of the first-first via V11 and the first-second via V12 may decrease toward the device layer 120. That is, the widths of the first-first via V11 and the first-second via V12 may increase further away from the substrate 110. For example, the widths of the first-first via V11 and the first-second via V12 may be defined with reference to the second direction D2.

[0062] A first portion 311 of the first heat dissipation film 310 may surround the side surface of the first-first via V11 and the side surface of the first-second via V12. For example, the first portion 311 of the first heat dissipation film 310 may contact the side surface of the first-first via V11 and the side surface of the first-second via V12. In an example embodiment, the upper surface of the first-first via V11, the upper surface of the first-second via V12, and the upper surface of the first portion 311 of the first heat dissipation film 310 may be coplanar with each other. In some embodiments, the upper surface of the first-first via V11, the upper surface of the first-second via V12, and the upper surface of the first portion 311 of the first heat dissipation film 310 may be coplanar with the upper surface of the first interlayer insulating film 131. The lower surface of the first portion 311 of the first heat dissipation film 310 may be coplanar with the lower surface of the first interlayer insulating film 131. The lower surface of the first portion 311 of the first heat dissipation film 310 may contact the upper top surface of the device layer 120.

[0063] The first metal layer M1 may include a first-first wiring M11, a first-second wiring M12, a first-third wiring M13, and a second interlayer insulating film 132. This is merely illustrative, and the first metal layer M1 may include four or more wirings. The wirings disposed in the first metal layer M1 may be collectively referred to as the first wirings M11, M12, and M13.

[0064] First-first wiring M11, first-second wiring M12, and first-third wiring M13 may be disposed in the second interlayer insulating film 132. For example, first-first wiring M11 may be disposed on the first portion 311 surrounding the first-first via V11 and the first heat dissipation film 310, and first-third wiring M13 may be disposed on the first portion 311 surrounding the first-second via V12 and the first heat dissipation film 310. First-first wiring M11, first-second wiring M12, and first-third wiring M13 may be electrically connected to the first via layer V1. For example, first-first wiring M11, first-second wiring M12, and first-third wiring M13 (e.g., the lower surfaces of first wiring M11, M12, and M13) may contact the upper surface of the first via layer V1 and the upper surface of the first portion 311 of the first heat dissipation film 310. The upper surfaces of the first-first wiring M11, the first-second wiring M12, and the first-third wiring M13 may be coplanar with the upper surface of the second interlayer insulating film 132, and the lower surfaces of the first-first wiring M11, the first-second wiring M12, and the first-third wiring M13 may be coplanar with the lower surface of the second interlayer insulating film 132. Although depicted as a single-layer structure, the first-first wiring M11, the first-second wiring M12, and the first-third wiring M13 may have a multi-layer structure.

[0065] The width of each of the first-first wiring M11, the first-second wiring M12, and the first-third wiring M13 may decrease towards the first via layer V1. That is, the width of each of the first-first wiring M11, the first-second wiring M12, and the first-third wiring M13 may increase as it moves further away from the substrate 110. For example, the width of each of the first-first wiring M11, the first-second wiring M12, and the first-third wiring M13 may be defined with reference to the second direction D2.

[0066] The first vias V11 and V12 in the first via layer V1 and the first wirings M11, M12 and M13 in the first metal layer M1 can be formed by a damascene process. In some embodiments, at least a portion of the first vias V11 and V12 and the first wirings M11, M12 and M13 can be formed by a subtractive process.

[0067] The second via layer V2 may include a second-first via V21, a second-second via V22, a second-third via V23, and a third interlayer insulating film 133. This is merely illustrative, and the second via layer V2 may include four or more vias. The vias disposed in the second via layer V2 may be collectively referred to as second vias V21, V22, and V23.

[0068] The second-first via V21, the second-second via V22, and the second-third via V23 may be disposed in the third interlayer insulating film 133. For example, the second-first via V21, the second-second via V22, and the second-third via V23 may be disposed on the wirings M11, M12, and M13 of the first metal layer M1, respectively, and may electrically connect the first metal layer M1 and the second metal layer M2. Although depicted as a single-layer structure, the second-first via V21, the second-second via V22, and the second-third via V23 may have a multilayer structure.

[0069] The widths of the second-first via V21, the second-second via V22, and the second-third via V23 may decrease towards the first metal layer M1. That is, the widths of the second-first via V21, the second-second via V22, and the second-third via V23 may increase as they move further away from the substrate 110. For example, the widths of the second-first via V21, the second-second via V22, and the second-third via V23 may be defined with reference to the second direction D2.

[0070] The first portion 321 of the second heat dissipation film 320 may surround the side surface of the second-first via V21, the side surface of the second-second via V22, and the side surface of the second-third via V23. For example, the first portion 321 of the second heat dissipation film 320 may contact the side surfaces of the second-first via V21, the second-second via V22, and the second-third via V23. In an example embodiment, the upper surfaces of the second-first via V21, the second-second via V22, the second-third via V23, and the first portion 321 of the second heat dissipation film 320 may be coplanar with each other. In some embodiments, the upper surfaces of the second-first via V21, the second-second via V22, the second-third via V23, and the first portion 321 of the second heat dissipation film 320 may be coplanar with the upper surface of the third interlayer insulating film 133. The lower surface of the first portion 321 of the second heat dissipation film 320 may be coplanar with the lower surface of the third interlayer insulating film 133. The lower surface of the first portion 321 of the second heat dissipation film 320 may contact the upper surface of the first-first wiring M11, the upper surface of the first-second wiring M12, and the upper surface of the first-third wiring M13.

[0071] Metal layer M2 may include a second-to-first wiring M21, a second-to-second wiring M22, and a fourth interlayer insulating film 134. This is merely illustrative, and the second metal layer M2 may include three or more wirings. The wirings disposed in the second metal layer M2 may be collectively referred to as the second wirings M21 and M22.

[0072] The second-first wiring M21 and the second-second wiring M22 may be disposed within the fourth interlayer insulating film 134. In an example embodiment, the upper surfaces of the second-first wiring M21, the second-second wiring M22, and the fourth interlayer insulating film 134 may be coplanar with each other, and the lower surfaces of the second-first wiring M21, the second-second wiring M22, and the fourth interlayer insulating film 134 may also be coplanar with each other. For example, the second-first wiring M21 may be disposed on the first portion 321 surrounding the second-first via V21 and the second heat dissipation film 320, and on the first portion 321 surrounding the second-second via V22 and the second heat dissipation film 320. For example, the second-first wiring M21 may contact the upper surface of the second-first via V21 and the upper surface of the first portion 321 of the second heat dissipation film 320 surrounding the second-first via V21, as well as the upper surface of the second-second via V22 and the upper surface of the first portion 321 of the second heat dissipation film 320 surrounding the second-second via V22. The second-second wiring M22 may be electrically connected to the second-third via V23. For example, the second-second wiring M22 may be disposed on the second-third via V23 and the first portion 321 of the second heat dissipation film 320 surrounding the second-third via V23. For example, the second-second wiring M22 may contact the upper surface of the second-third via V23 and the upper surface of the first portion 321 of the second heat dissipation film 320 surrounding the second-third via V23. Although depicted as a single-layer structure, the second-first wiring M21 and the second-second wiring M22 may have a multi-layer structure.

[0073] The widths of the second-first wiring M21 and the second-second wiring M22 may decrease toward the second via layer V2. That is, the width of each of the second-first wiring M21 and the second-second wiring M22 may increase as it moves further away from the substrate 110. For example, the widths of the second-first wiring M21 and the second-second wiring M22 may be defined with reference to the second direction D2.

[0074] The second vias V21, V22, and V23 in the second via layer V2 and the second wirings M21 and M22 in the second metal layer M2 can be formed by a single damascene process. In some embodiments, at least a portion of the second vias V21, V22, and V23 and the second wirings M21 and M22 can be formed by a subtractive process or a semi-damascene process.

[0075] The heat dissipation structure 300 may include a first heat dissipation film 310 and a second heat dissipation film 320. The heat dissipation structure 300 may be disposed in a first via layer V1 and a second via layer V2.

[0076] A first heat dissipation film 310 may be disposed in a first via layer V1, and a second heat dissipation film 320 may be disposed in a second via layer V2. The first heat dissipation film 310 may include a first portion 311 surrounding at least one of the bottom surface and side surface of at least one of the first vias V11 and V12. For example, the first portion 311 of the first heat dissipation film 310 may contact the lower surface and side surface of the first vias V11 and V12. The second heat dissipation film 320 may include a first portion 321 surrounding at least one of the bottom surface and side surface of at least one of the second vias V21, V22, and V23. For example, the first portion 321 of the second heat dissipation film 320 may contact the lower surface and side surface of the second vias V21, V22, and V23. For ease of description, the first portion 311 of the first heat dissipation film 310 is described as surrounding the bottom and side surfaces of each of the first vias V11 and V12, and the first portion 321 of the second heat dissipation film 320 is described as surrounding the bottom and side surfaces of each of the second vias V21, V22, and V23. For example, in Figure 2 In one embodiment, a first portion 311 of the first heat dissipation film 310 contacts the bottom and side surfaces of each of the first vias V11 and V12, and a first portion 321 of the second heat dissipation film 320 contacts the bottom and side surfaces of each of the second vias V21, V22 and V23.

[0077] The first portion 311 of the first heat dissipation film 310 may have a cup shape surrounding the bottom and side surfaces of each of the first-first via V11 and the first-second via V12. In some embodiments, the first portion 311 of the first heat dissipation film 310 may not be disposed on the bottom surfaces of the first-first via V11 and the first-second via V12. In such an embodiment, the lower surfaces of the first-first via V11 and the first-second via V12 may be coplanar with the lower surface of the first interlayer insulating film 131.

[0078] The first portion 321 of the second heat dissipation film 320 may have a cup shape surrounding the bottom and side surfaces of each of the second-first via V21, the second-second via V22, and the second-third via V23. In some embodiments, the first portion 321 of the second heat dissipation film 320 may not be disposed on the bottom surfaces of the second-first via V21, the second-second via V22, and the second-third via V23.

[0079] The heat dissipation structure 300 may include a material with high thermal conductivity. For example, the heat dissipation structure 300 (i.e., the first heat dissipation film 310 and the second heat dissipation film 320) may be formed of or include 2D materials (such as graphene, diamond-like carbon (DLC), hexagonal boron nitride (hBN), or transition metal dichalcogenides (TMD)). For example, the TMD may include at least one of MoS2, WS2, MoSe2, WSe2, HfS2, and ZrS2.

[0080] A first portion 311 of the first heat dissipation film 310 may be part of a path for dissipating heat generated inside the semiconductor chip 100. For example, the first portion 311 of the first heat dissipation film 310 may be part of a path for dissipating heat generated in the first vias V11 and V12 and the first wirings M11, M12 and M13. Similarly, a first portion 321 of the second heat dissipation film 320 may be part of a path for dissipating heat generated inside the semiconductor chip 100. For example, the first portion 321 of the second heat dissipation film 320 may be part of a path for dissipating heat generated in the second vias V21, V22 and V23 and the second wirings M21 and M22.

[0081] The heat dissipation structure 300 may include a material with high electrical conductivity. For example, a first portion 311 of the first heat dissipation film 310 may be formed of or include a 2D material (such as graphene) and may electrically connect the device layer 120 and the first via layer V1. Similarly, a first portion 321 of the second heat dissipation film 320 may electrically connect the device layer 120 and the second via layer V2. The heat dissipation structure 300 may include a material with both high thermal conductivity and high electrical conductivity.

[0082] The first portion 311 of the first heat dissipation film 310 prevents the diffusion of the metallic material constituting the first-first via V11 and the first-second via V12. For example, the first portion 311 of the first heat dissipation film 310 prevents the diffusion of copper ions constituting the first-first via V11 and the first-second via V12. The first portion 321 of the second heat dissipation film 320 prevents the diffusion of the metallic material constituting the second-first via V21, the second-second via V22, and the second-third via V23. For example, the first portion 321 of the second heat dissipation film 320 prevents the diffusion of copper ions constituting the second-first via V21, the second-second via V22, and the second-third via V23.

[0083] In the following text, the description and Figure 2 Different embodiments are described. The same reference numerals denote the same elements, and their detailed descriptions are not repeated; only the differences are discussed.

[0084] Figure 3 This is a cross-sectional view illustrating some components of a semiconductor chip according to some exemplary embodiments of the present disclosure. In the exemplary embodiments, Figure 3 Semiconductor chip 101 can be used with Figure 1 This corresponds to a portion of the semiconductor chip 100.

[0085] Reference Figure 3 In the semiconductor chip 101 according to some embodiments of the present disclosure, the first heat dissipation film 310 may further include a second portion 312, and the second heat dissipation film 320 may further include a second portion 322.

[0086] The second portion 312 of the first heat dissipation film 310 may extend along the lower surface of the first metal layer M1. For example, the second portion 312 of the first heat dissipation film 310 may extend along the lower surface of at least one of the first wirings M11, M12, and M13. For example, the lower surface of at least one of the first wirings M11, M12, and M13 may contact the upper surface of the second portion 312 of the first heat dissipation film 310. The second portion 312 of the first heat dissipation film 310 may be disposed between the lower surface of at least one of the first wirings M11, M12, and M13 and the first interlayer insulating film 131. The second portion 322 of the second heat dissipation film 320 may extend along the lower surface of the second metal layer M2. For example, the second portion 322 of the second heat dissipation film 320 may extend along the lower surface of at least one of the second wirings M21 and M22. For example, the lower surface of at least one of the second wirings M21 and M22 may contact the upper surface of the second portion 322 of the second heat dissipation film 320. A second portion 322 of the second heat dissipation film 320 may be formed between the lower surface of at least one of the second wirings M21 and M22 and the third interlayer insulating film 133. For ease of description, the second portion 312 of the first heat dissipation film 310 is described as extending along the lower surface of each of the first wirings M11, M12 and M13, and the second portion 322 of the second heat dissipation film 320 is described as extending along the lower surface of each of the second wirings M21 and M22.

[0087] The second portion 312 of the first heat dissipation film 310 may extend from the first portion 311 of the first heat dissipation film 310. The second portion 312 of the first heat dissipation film 310 may extend in the second direction D2 and / or the third direction D3, and may extend along the lower surface of the first metal layer M1. The second portion 312 of the first heat dissipation film 310 may be bent from the upper end of the first portion 311 of the first heat dissipation film 310. The second portion 312 of the first heat dissipation film 310 and the first portion 311 of the first heat dissipation film 310 may have a predetermined angle between them.

[0088] The second portion 312 of the first heat dissipation film 310 may be a portion of a path for dissipating heat generated inside the semiconductor chip 101. For example, the second portion 312 of the first heat dissipation film 310 may be a portion of a path for dissipating heat generated in the first vias V11 and V12 and the first wirings M11, M12 and M13. For example, the second portion 312 of the first heat dissipation film 310 may provide a path for heat dissipation for the first heat dissipation film 310.

[0089] The second portion 312 of the first heat dissipation film 310 can prevent the diffusion of the metallic material constituting the first-first wiring M11, the first-second wiring M12, and the first-third wiring M13. For example, the second portion 312 of the first heat dissipation film 310 can prevent the diffusion of copper ions constituting the first-first wiring M11, the first-second wiring M12, and the first-third wiring M13.

[0090] The second portion 322 of the second heat dissipation film 320 may extend from the first portion 321 of the second heat dissipation film 320. The second portion 322 of the second heat dissipation film 320 may extend in the second direction D2 and / or the third direction D3, and may extend along the lower surface of the second metal layer M2. The second portion 322 of the second heat dissipation film 320 may be bent from the upper end of the first portion 321 of the second heat dissipation film 320, and the second portion 322 of the second heat dissipation film 320 and the first portion 321 of the second heat dissipation film 320 may have a predetermined angle between them.

[0091] The second portion 322 of the second heat dissipation film 320 may be part of a path for dissipating heat generated inside the semiconductor chip 101. For example, the second portion 322 of the second heat dissipation film 320 may be part of a path for dissipating heat generated in the second vias V21, V22 and V23 and the second wirings M21 and M22, thereby providing a heat dissipation path for the second heat dissipation film 320.

[0092] The second portion 322 of the second heat dissipation film 320 can prevent the diffusion of the metallic material constituting the second-first wiring M21 and the second-second wiring M22. For example, the second portion 322 of the second heat dissipation film 320 can prevent the diffusion of copper ions constituting the second-first wiring M21 and the second-second wiring M22.

[0093] In some embodiments, the first portions 311 and 321 and the second portions 312 and 322 may be formed of different materials. Both the first portions 311 and 321 and the second portions 312 and 322 may comprise materials having high thermal conductivity. For example, the first portions 311 and 321 may be formed of an insulating material, and the second portions 312 and 322 may be formed of a conductive material. Specifically, the first portions 311 and 321 may be formed of hBN, and the second portions 312 and 322 may be formed of graphene.

[0094] The heat dissipation structure 300 may also include a heat dissipation insulation structure 330. The heat dissipation insulation structure 330 may include a first heat dissipation insulation film 331 and a second heat dissipation insulation film 332.

[0095] A first heat-dissipating insulating film 331 may be disposed between the second portions 312 of the first heat-dissipating film 310. The first heat-dissipating insulating film 331 may overlap the second portions 312 of the first heat-dissipating film 310 in the second direction D2. The first heat-dissipating insulating film 331 may have the same thickness as the second portions 312 of the first heat-dissipating film 310 in the first direction D1. For example, the upper surface of the first heat-dissipating insulating film 331 and the upper surface of the second portions 312 of the first heat-dissipating film 310 may be coplanar with each other, and the lower surface of the first heat-dissipating insulating film 331 and the lower surface of the second portions 312 of the first heat-dissipating film 310 may be coplanar with each other. The first heat-dissipating insulating film 331 may be formed by oxidizing a portion of the first heat-dissipating film 310. The first heat-dissipating insulating film 331 may be disposed between the first wirings M11, M12, and M13. The first heat-dissipating insulating film 331 may be disposed on the lower surface of the second interlayer insulating film 132. The first heat-dissipating insulating film 331 may extend along the lower surface of the second interlayer insulating film 132. The first heat-dissipating insulating film 331 can contact the lower surface of the second interlayer insulating film 132 and the upper surface of the first interlayer insulating film 131.

[0096] A second heat-dissipating insulating film 332 may be disposed between the second portions 322 of the second heat-dissipating film 320. The second heat-dissipating insulating film 332 may overlap with the second portions 322 in the second direction D2. The second heat-dissipating insulating film 332 may have the same thickness as the second portions 322 of the second heat-dissipating film 320 in the first direction D1. For example, the upper surface of the second heat-dissipating insulating film 332 and the upper surface of the second portion 322 of the second heat-dissipating film 320 may be coplanar with each other, and the lower surface of the second heat-dissipating insulating film 332 and the lower surface of the second portion 322 of the second heat-dissipating film 320 may be coplanar with each other. The second heat-dissipating insulating film 332 may be formed by oxidizing a portion of the second heat-dissipating film 320. The second heat-dissipating insulating film 332 may be disposed between the second wirings M21 and M22. The second heat-dissipating insulating film 332 may be disposed on the lower surface of the fourth interlayer insulating film 134. The second heat-dissipating insulating film 332 may extend along the lower surface of the fourth interlayer insulating film 134. The second heat dissipation insulating film 332 can contact the lower surface of the fourth interlayer insulating film 134 and the upper surface of the third interlayer insulating film 133.

[0097] The heat-dissipating insulating structure 330 may include an insulating material. The heat-dissipating insulating structure 330 may include an oxide obtained by oxidizing a conductive material. For example, the heat-dissipating insulating structure 330 may be formed of or include graphene oxide. In some embodiments, the heat-dissipating insulating structure 330 may be formed of or include silicon oxide, silicon nitride, or silicon oxynitride.

[0098] Figure 4 This is a cross-sectional view illustrating some components of a semiconductor chip according to some exemplary embodiments of the present disclosure. In the exemplary embodiments, Figure 4 Semiconductor chip 102 and Figure 1 This corresponds to a portion of the semiconductor chip 100.

[0099] Reference Figure 4 In the semiconductor chip 102 according to some embodiments of the present disclosure, for example, the first vias V11 and V12 of the first via layer V1 and the first wirings M11 and M13 of the first metal layer M1 may have an integrated structure and may be formed by a dual-damascene process. For example, each of the first vias V11 and V12 of the first via layer V1 may be a single structure, and each of the first wirings M11 and M13 of the first metal layer M1 may be a single structure.

[0100] The first heat dissipation film 310 may further include a third part 313, and the second heat dissipation film 320 may further include a third part 323.

[0101] The third portion 313 of the first heat dissipation film 310 may extend along the side surface of the first metal layer M1. For example, the third portion 313 of the first heat dissipation film 310 may extend along the side surface of at least one of the first wirings M11, M12, and M13. The third portion 313 of the first heat dissipation film 310 may contact the side surface of at least one of the first wirings M11, M12, and M13. The upper surface of the third portion 313 of the first heat dissipation film 310 may be coplanar with the upper surfaces of the first wirings M11, M12, and M13. The third portion 323 of the second heat dissipation film 320 may extend along the side surface of the second metal layer M2. For example, the third portion 323 of the second heat dissipation film 320 may extend along the side surface of at least one of the second wirings M21 and M22. The third portion 323 of the second heat dissipation film 320 may contact the side surface of at least one of the second wirings M21 and M22. The upper surface of the third portion 323 of the second heat dissipation film 320 may be coplanar with the upper surfaces of the second wirings M21 and M22. For ease of description, the third portion 313 of the first heat dissipation film 310 is described as extending along the side surface of each of the first wirings M11, M12, and M13, and the third portion 323 of the second heat dissipation film 320 is described as extending along the side surface of each of the second wirings M21 and M22. For example, in these exemplary embodiments, the third portion 313 of the first heat dissipation film 310 contacts the side surface of each of the first wirings M11, M12, and M13, and the third portion 323 of the second heat dissipation film 320 contacts the side surface of each of the second wirings M21 and M22.

[0102] The third portion 313 of the first heat dissipation film 310 may extend from the second portion 312 of the first heat dissipation film 310. The third portion 313 of the first heat dissipation film 310 may be bent from the end of the second portion 312 of the first heat dissipation film 310, and the third portion 313 and the second portion 312 of the first heat dissipation film 310 may have a predetermined angle between them. Similarly, the third portion 323 of the second heat dissipation film 320 may extend from the second portion 322 of the second heat dissipation film 320, and may be bent from the end of the second portion 322 of the second heat dissipation film 320, and the third portion 323 and the second portion 322 of the second heat dissipation film 320 may have a predetermined angle between them.

[0103] The third portion 313 of the first heat dissipation film 310 may be part of a path for dissipating heat generated inside the semiconductor chip 102. For example, the third portion 313 of the first heat dissipation film 310 may be part of a path for dissipating heat generated in the first wirings M11, M12 and M13, thereby providing a heat dissipation path for the first heat dissipation film 310.

[0104] The third portion 323 of the second heat dissipation film 320 may be part of a path for dissipating heat generated inside the semiconductor chip 102. For example, the third portion 323 of the second heat dissipation film 320 may be part of a path for dissipating heat generated in the second wirings M21 and M22, thereby providing a heat dissipation path for the second heat dissipation film 320.

[0105] The third portion 313 of the first heat dissipation film 310 can prevent the diffusion of the metallic material constituting the first-first wiring M11, the first-second wiring M12, and the first-third wiring M13. For example, the third portion 313 of the first heat dissipation film 310 can prevent the diffusion of copper ions constituting the first-first wiring M11, the first-second wiring M12, and the first-third wiring M13. The third portion 323 of the second heat dissipation film 320 can prevent the diffusion of the metallic material constituting the second-first wiring M21 and the second-second wiring M22. For example, the third portion 323 of the second heat dissipation film 320 can prevent the diffusion of copper ions constituting the second-first wiring M21 and the second-second wiring M22.

[0106] Figure 5 This is a cross-sectional view illustrating some components of a semiconductor chip according to some exemplary embodiments of the present disclosure. In the exemplary embodiments, Figure 5 Semiconductor chip 103 can be used with Figure 1 This corresponds to a portion of the semiconductor chip 100.

[0107] Reference Figure 5 In the semiconductor chip 103 according to some embodiments of the present disclosure, and Figure 3 Compared to the previous embodiment, the first heat dissipation film 310 may further include a fourth portion 314, and the second heat dissipation film 320 may further include a fourth portion 324.

[0108] The fourth portion 314 of the first heat dissipation film 310 may extend along the upper surfaces of the first wirings M11, M12, and M13. The fourth portion 314 of the first heat dissipation film 310 may be disposed on the upper surfaces of the first wirings M11, M12, and M13. The fourth portion 314 of the first heat dissipation film 310 may be positioned between the first wirings M11, M12, and M13 and the first portion 321 of the second heat dissipation film 320. The fourth portion 314 of the first heat dissipation film 310 may contact the upper surfaces of the first wirings M11, M12, and M13 and the lower surface of the first portion 321 of the second heat dissipation film 320.

[0109] The fourth portion 314 of the first heat dissipation film 310 may be part of a path for dissipating heat generated inside the semiconductor chip 103. For example, the fourth portion 314 of the first heat dissipation film 310 may be part of a path for dissipating heat generated in the first wirings M11, M12 and M13, thereby providing a heat dissipation path for the first heat dissipation film 310.

[0110] The fourth portion 324 of the second heat dissipation film 320 may extend along the upper surfaces of the second wirings M21 and M22. The fourth portion 324 of the second heat dissipation film 320 may be disposed on the upper surfaces of the second wirings M21 and M22. The fourth portion 324 of the second heat dissipation film 320 may contact the upper surfaces of the second wirings M21 and M22.

[0111] The fourth portion 324 of the second heat dissipation film 320 may be part of a path for dissipating heat generated inside the semiconductor chip 103. For example, the fourth portion 324 of the second heat dissipation film 320 may be part of a path for dissipating heat generated in the second wirings M21 and M22, thereby providing a heat dissipation path for the second heat dissipation film 320.

[0112] The heat dissipation insulation structure 330 may further include a third heat dissipation insulation film 333 and a fourth heat dissipation insulation film 334. The third heat dissipation insulation film 333 may be disposed between the second via layer V2 and the first metal layer M1. The fourth heat dissipation insulation film 334 may be disposed on the second metal layer M2.

[0113] A third heat-dissipating insulating film 333 may be disposed between the fourth portion 314 of the first heat-dissipating film 310. The third heat-dissipating insulating film 333 may overlap with the fourth portion 314 of the first heat-dissipating film 310 in the second direction D2. For example, the upper surface of the third heat-dissipating insulating film 333 may be coplanar with the upper surface of the fourth portion 314 of the first heat-dissipating film 310, and the lower surface of the third heat-dissipating insulating film 333 may be coplanar with the lower surface of the fourth portion 314 of the first heat-dissipating film 310. The third heat-dissipating insulating film 333 may be disposed on the upper surface of the second interlayer insulating film 132. The third heat-dissipating insulating film 333 may extend along the upper surface of the second interlayer insulating film 132. For example, the third heat-dissipating insulating film 333 may contact the upper surface and the lower surface of the second interlayer insulating film 132.

[0114] A fourth heat-dissipating insulating film 334 may be disposed between the fourth portions 324 of the second heat-dissipating film 320. The fourth heat-dissipating insulating film 334 may overlap with the fourth portions 324 of the second heat-dissipating film 320 in the second direction D2. For example, the upper surface of the fourth heat-dissipating insulating film 334 may be coplanar with the upper surface of the fourth portion 324 of the second heat-dissipating film 320, and the lower surface of the fourth heat-dissipating insulating film 334 may be coplanar with the lower surface of the fourth portion 324 of the second heat-dissipating film 320. The fourth heat-dissipating insulating film 334 may be disposed on the upper surface of the fourth interlayer insulating film 134. The fourth heat-dissipating insulating film 334 may extend along the upper surface of the fourth interlayer insulating film 134. For example, the fourth heat-dissipating insulating film 334 may contact the upper surface of the fourth interlayer insulating film 134.

[0115] Figure 6 This is a cross-sectional view illustrating some components of a semiconductor chip according to some exemplary embodiments of the present disclosure. In the exemplary embodiments, Figure 6 Semiconductor chip 104 can be used with Figure 1 This corresponds to a portion of the semiconductor chip 100.

[0116] Reference Figure 6 According to some embodiments of this disclosure, a semiconductor chip 104 may include a first wiring structure WS1, a second wiring structure WS2, and a support substrate 115. The first wiring structure WS1 may be disposed on one surface of the device layer 120, and the second wiring structure WS2 may be disposed on the other surface of the device layer 120. For example, the first wiring structure WS1 may be disposed on the front surface of the device layer 120, and the second wiring structure WS2 may be disposed on the back surface of the device layer 120. Hereinafter, the first wiring structure WS1 may be referred to as the front-side wiring structure, and the second wiring structure WS2 may be referred to as the back-side wiring structure. The number of layers, vias, and wirings in the first wiring structure WS1 and the second wiring structure WS2, and their arrangement in the via layers and metal layers, are merely illustrative and are not limited to those shown.

[0117] The first wiring structure WS1 may include a first via layer V1, a first metal layer M1, a second via layer V2, a second metal layer M2, and a first heat dissipation structure 300. In an example embodiment, in the first wiring structure WS1, the first via layer V1 may also be referred to as the front-side first via layer V1, the first metal layer M1 may also be referred to as the front-side first metal layer M1, the second via layer V2 may also be referred to as the front-side second via layer V2, and the second metal layer M2 may also be referred to as the front-side second metal layer M2. The second wiring structure WS2 may include a first via layer V1, a first metal layer M1, a second via layer V2, and a second heat dissipation structure 400. In an example embodiment, in the second wiring structure WS2, the first via layer V1 may also be referred to as the back-side first via layer V1, the first metal layer M1 may also be referred to as the back-side first metal layer M1, and the second via layer V2 may also be referred to as the back-side second via layer V2. The descriptions of the corresponding components of the first wiring structure WS1 and the second wiring structure WS2 are consistent with those described above. Figure 3 The descriptions are basically the same.

[0118] The first heat dissipation structure 300 may include a first heat dissipation film 310 and a second heat dissipation film 320. The first heat dissipation film 310 of the first heat dissipation structure 300 may be disposed in the first via layer V1 and the first metal layer M1 of the first wiring structure WS1, and the second heat dissipation film 320 of the first heat dissipation structure 300 may be disposed in the second via layer V2 and the second metal layer M2 of the first wiring structure WS1.

[0119] The second heat dissipation structure 400 may include a first heat dissipation film 410 and a second heat dissipation film 420. The first heat dissipation film 410 of the second heat dissipation structure 400 may be disposed in the first via layer V1 and the first metal layer M1 of the second wiring structure WS2. The second heat dissipation film 420 of the second heat dissipation structure 400 may be disposed in the second via layer V2 of the second wiring structure WS2. The first heat dissipation film 410 of the second heat dissipation structure 400 may be disposed in the second via layer V2 of the second wiring structure WS2. Figure 3 The first heat dissipation film 310 of the heat dissipation structure 300 is basically the same, and the second heat dissipation film 420 of the second heat dissipation structure 400 can be the same as... Figure 3 The second heat dissipation film 320 of the heat dissipation structure 300 is basically the same.

[0120] A first wiring structure WS1 is electrically connected to device layer 120. The first wiring structure WS1 provides at least one of signal lines and power lines for various devices in device layer 120. A second wiring structure WS2 is electrically connected to device layer 120. The second wiring structure WS2 provides at least one of power lines and signal lines for various devices in device layer 120. For example, a semiconductor chip according to this disclosure can employ a back-side power delivery network (BSPDN) scheme in which power wiring is disposed on the back surface of the semiconductor chip.

[0121] A support substrate 115 may be disposed on the first wiring structure WS1. A second surface 115_2 of the support substrate 115 may be configured to contact the first wiring structure WS1. A first surface 115_1 of the support substrate 115 may be referred to as the upper surface of the semiconductor chip 104. The support substrate 115 may be located on the side of the device layer 120 opposite to the second wiring structure WS2. The support substrate 115 may be bulk silicon or silicon-on-insulator (SOI). Optionally, the support substrate 115 may be formed of SiGe, SGOI, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, or may include, but is not limited to, SiGe, SGOI, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0122] Figure 7 This is a cross-sectional view illustrating some components of a semiconductor chip according to some exemplary embodiments of the present disclosure. In the exemplary embodiments, Figure 7 Semiconductor chip 105 can be used with Figure 1 A portion of the semiconductor chip 100 corresponds to this. In the example embodiment, instead of Figure 1 One or more of the through electrodes 155 or except Figure 1 In addition to one or more of the through electrodes 155 Figure 7 A through electrode 150 may be provided.

[0123] Reference Figure 7 The semiconductor chip 105 according to some embodiments of the present disclosure may also include a through electrode 150.

[0124] The through electrode 150 can penetrate at least a portion of the semiconductor chip 105. The through electrode 150 can penetrate the semiconductor chip 105 in a first direction D1. For example, the through electrode 150 can penetrate the support substrate 115 in the first direction D1. The through electrode 150 can penetrate the first surface 115_1 of the support substrate 115 in the first direction D1. The through electrode 150 can penetrate the first wiring structure WS1 and the device layer 120 in the first direction D1, and can be stacked with the first wiring structure WS1 and the device layer 120 in a second direction D2. For example, a portion of the device layer 120 may include a penetration region in which the through electrode 150 is formed. In some embodiments, the through electrode 150 can also penetrate a portion of the second wiring structure WS2 and can be connected to the second wiring structure WS2. For example, the through electrode 150 can contact at least one of the via layer and the metal layer constituting the second wiring structure WS2.

[0125] The heat dissipation film 161 may contact the through electrode 150. The heat dissipation film 161 may extend along the side and bottom surfaces of the through electrode 150. The heat dissipation film 161 may contact the side and bottom surfaces of the through electrode 150. For example, the heat dissipation film 161 may have a cup shape surrounding the through electrode 150. In some embodiments, the heat dissipation film 161 may not be disposed on the bottom surface of the through electrode 150. For example, the bottom surface of the through electrode 150 may contact the second wiring structure WS2.

[0126] A heat dissipation film 161 may be disposed between the through electrode 150 and the support substrate 115. The heat dissipation film 161 may penetrate the first surface 115_1 of the support substrate 115 in a first direction D1. The heat dissipation film 161 may be stacked with the device layer 120 in a second direction D2; for example, the heat dissipation film 161 may penetrate the penetration region of the device layer 120 in the first direction D1. The bottom surface of the heat dissipation film 161 may contact the second wiring structure WS2.

[0127] The heat dissipation film 161 can prevent the diffusion of the metallic material constituting the through electrode 150. For example, the heat dissipation film 161 can prevent copper ions constituting the through electrode 150 from diffusing into the support substrate 115.

[0128] A surface heat dissipation film 162 may be disposed on the semiconductor chip 105. The surface heat dissipation film 162 may be disposed on the first surface 115_1 of the supporting substrate 115. The surface heat dissipation film 162 may contact the first surface 115_1 of the supporting substrate 115. For example, the surface heat dissipation film 162 may be disposed on the upper surface of the semiconductor chip 105. The surface heat dissipation film 162 may be connected to a through heat dissipation film 161 and may extend in a second direction D2.

[0129] The surface heat dissipation film 162 may be stacked with the through electrode 150 in the second direction D2. At least a portion of the through electrode 150 may be located at a vertical height higher than the vertical height of the first surface 115_1 of the supporting substrate 115. The through electrode 150 may be stacked with the surface heat dissipation film 162 in the second direction D2. For example, the upper portion of the through electrode 150 may be stacked with the surface heat dissipation film 162 in the second direction D2. In some embodiments, the upper surface of the surface heat dissipation film 162 may be coplanar with the upper surface of the through electrode 150.

[0130] The heat dissipation film 161 and the surface heat dissipation film 162 provide pathways for dissipating heat generated from the semiconductor chip 105. For example, heat generated in the semiconductor chip 105 can be dissipated along the through electrode 150, the through heat dissipation film 161 and / or the surface heat dissipation film 162.

[0131] The through-hole heat dissipation film 161 and the surface heat dissipation film 162 may include materials with high electrical conductivity. The through-hole heat dissipation film 161 and the surface heat dissipation film 162 may be electrically connected to the through-hole electrode 150. The through-hole heat dissipation film 161 and the surface heat dissipation film 162 may include conductive materials. The through-hole heat dissipation film 161 and the surface heat dissipation film 162 may also include materials with high thermal conductivity. For example, the through-hole heat dissipation film 161 and the surface heat dissipation film 162 may be formed of or include graphene. In some embodiments, the through-hole heat dissipation film 161 and the surface heat dissipation film 162 may include 2D materials, including at least one selected from diamond-like carbon (DLC), hexagonal boron nitride (hBN), and transition metal dichalcogenides (TMD).

[0132] Figures 8 to 11 This is a cross-sectional view illustrating a chip stacking structure according to some example embodiments of the present disclosure. In the example embodiments, Figures 8 to 11 Each chip stack structure shown may include Figure 2 Semiconductor chips 100 Figure 3 Semiconductor chip 101, Figure 4 Semiconductor chip 102, Figure 5 Semiconductor chip 103, Figure 6 Semiconductor chip 104 and Figure 7 One or more of the semiconductor chips 105.

[0133] Reference Figure 8 According to some embodiments of this disclosure, a chip stack structure CS1 may include a first semiconductor chip 100, a second semiconductor chip 200, a first connection terminal 191, a second connection terminal 192, and a lower terminal 193. The second semiconductor chip 200 may be stacked on the first semiconductor chip 100. The first connection terminal 191 and the second connection terminal 192 may be disposed between the first semiconductor chip 100 and the second semiconductor chip 200, and may connect the first semiconductor chip 100 and the second semiconductor chip 200. The lower terminal 193 may be disposed on the lower surface of the first semiconductor chip 100. Each of the lower terminals 193 may be disposed on a lower pad 185. The chip stack structure CS1 can be mounted on a package substrate or a motherboard via the lower terminals 193.

[0134] and Figure 7 Compared to the semiconductor chip 105, the first semiconductor chip 100 may further include an upper pad 180, a first surface insulating film 181a, and a second surface insulating film 181b.

[0135] The first semiconductor chip 100 may include a first substrate 110, a first device layer 120, a first front-side wiring structure FWS1, an upper pad 180, a through electrode 150, a through heat dissipation film 161, and a surface heat dissipation film 162. The description of the first substrate 110, the first device layer 120, and the first front-side wiring structure FWS1 is consistent with reference to [reference needed]. Figures 2 to 4 The descriptions of the substrate 110, device layer 120, and wiring structure WS are substantially the same. For example, the heat dissipation structure of the first front wiring structure FWS1 can be referred to as the first front heat dissipation structure. Furthermore, the first via layer and the first metal layer of the first front wiring structure FWS1 can be referred to as the first front via layer and the first front metal layer, respectively. That is, the first front wiring structure FWS1 may include a first front via layer, a first front metal layer, and a first front heat dissipation structure. The first front via layer includes a first front via disposed on the first device layer 120, the first front metal layer includes first front wiring disposed on the first front via layer, and the first front heat dissipation structure includes a first portion surrounding the bottom surface and side surface of the first front via.

[0136] The upper pad 180 may be disposed on the first substrate 110. For example, the upper pad 180 may be disposed on the first surface 110_1 of the first substrate 110. The upper pad 180 may be disposed in the surface heat dissipation film 162. The upper pad 180 may be surrounded by the surface heat dissipation film 162. Multiple upper pads 180 may be provided. The upper pad 180 may include at least one of Al, Cu, Ni, W, Pt and Au, but the material constituting the upper pad 180 is not limited to this.

[0137] The first connection terminal 191 may be disposed on the upper pad 180 of the first semiconductor chip 100. The second semiconductor chip 200 and the first semiconductor chip 100 may be electrically connected through the upper pad 180 and the first connection terminal 191.

[0138] The second connection terminal 192 may be disposed on the through electrode 150 and electrically connected to the through electrode 150. In some embodiments, a pad for attaching the second connection terminal 192 may be formed on the through electrode 150. In other embodiments, the second connection terminal 192 may be formed to directly contact the through electrode 150. The second connection terminal 192 may be connected to the first device layer 120 and the first front side wiring structure FSW1 of the first semiconductor chip 100 via the through electrode 150.

[0139] The first connection terminal 191 and the second connection terminal 192 can be connected to the second device layer 220 and the second front side wiring structure FSW2 of the second semiconductor chip 200 via the lower pad 195 disposed on the lower surface of the second semiconductor chip 200.

[0140] A first surface insulating film 181a and a second surface insulating film 181b may be disposed on a first surface 110_1 of a first substrate 110. The first surface insulating film 181a and the second surface insulating film 181b may contact the first surface 110_1 of the first substrate 110.

[0141] A first surface insulating film 181a may be disposed around the upper pad 180. The first surface insulating film 181a prevents electrical conduction between the upper pad 180 and the surface heat dissipation film 162. The first surface insulating film 181a may be configured such that the upper pad 180 and the surface heat dissipation film 162 are spaced apart from each other in the second direction D2. The first surface insulating film 181a may surround the upper pad 180. For example, the first surface insulating film 181a may contact the side surface of the upper pad 180. The upper surface of the first surface insulating film 181a, the upper surface of the upper pad 180, and the upper surface of the surface heat dissipation film 162 may be coplanar, and the lower surface of the first surface insulating film 181a, the lower surface of the upper pad 180, and the lower surface of the surface heat dissipation film 162 may be coplanar. For example, the first surface insulating film 181a may overlap with the upper pad 180 and the surface heat dissipation film 162 in the second direction D2.

[0142] A second surface insulating film 181b may be disposed around the through electrode 150 and between the through heat dissipation film 161 and the surface heat dissipation film 162. The second surface insulating film 181b prevents electrical conduction between the through electrode 150 and / or between the through heat dissipation film 161 and the surface heat dissipation film 162. For example, the second surface insulating film 181b may be configured such that the through heat dissipation film 161 and the surface heat dissipation film 162 are spaced apart from each other in the second direction D2. The second surface insulating film 181b may surround the through heat dissipation film 161. The second surface insulating film 181b may contact a portion of the side surface of the through heat dissipation film 161. The upper surface of the second surface insulating film 181b may be coplanar with the upper surface of the surface heat dissipation film 162, the upper surface of the through heat dissipation film 161, and the upper surface of the through electrode 150. For example, the second surface insulating film 181b may overlap with the through electrode 150 and the surface heat dissipation film 162 in the second direction D2.

[0143] The first surface insulating film 181a and the second surface insulating film 181b may include an insulating material. The first surface insulating film 181a and the second surface insulating film 181b may include oxides obtained by oxidizing a conductive material. For example, the first surface insulating film 181a and the second surface insulating film 181b may be formed of or include graphene oxide. In some embodiments, the first surface insulating film 181a and the second surface insulating film 181b may be formed of, or include, silicon oxide, silicon nitride, or silicon oxynitride.

[0144] The second semiconductor chip 200 may include a second substrate 210, a second device layer 220, and a second front-side wiring structure (FSW2). The description of the second front-side wiring structure (FSW2) is consistent with that of the reference. Figures 2 to 4 The descriptions of the wiring structures WS are essentially the same. For example, the heat dissipation structure of the second front wiring structure FSW2 can be referred to as the second front heat dissipation structure. Furthermore, the first via layer and the first metal layer of the second front wiring structure FSW2 can be referred to as the second front via layer and the second front metal layer, respectively. For example, the second front wiring structure FSW2 may include a second front via layer, a second front metal layer, and a second front heat dissipation structure. The second front via layer includes a second front via disposed on the second device layer 220, the second front metal layer includes second front wiring disposed on the second front via layer, and the second front heat dissipation structure includes a first portion surrounding the bottom surface and side surface of the second front via.

[0145] As described above, in the chip stacking structure CS1 according to some embodiments of the present disclosure, the first front wiring structure FWS1 and the second front wiring structure FSW2 of the corresponding first semiconductor chip 100 and second semiconductor chip 200 can perform signal transmission and / or power supply.

[0146] Reference Figure 9 ,according to Figure 9 The chip stacking structure CS2 of the embodiment and Figure 8 The difference between the embodiments may lie in the structure of the first semiconductor chip 100A and... Figure 8 The structure of the first semiconductor chip 100 is different.

[0147] The first semiconductor chip 100A may include a first substrate 110, a first front-side wiring structure FWS1, and a first back-side wiring structure BWS1. The heat dissipation structure of the first front-side wiring structure FWS1 may be referred to as the first front-side heat dissipation structure, and the heat dissipation structure of the first back-side wiring structure BWS1 may be referred to as the first back-side heat dissipation structure.

[0148] The first substrate 110 may be a support substrate for forming the first back-side wiring structure BWS1, and may be disposed on the first front-side wiring structure FWS1. The first substrate 110 may be disposed on the upper surface of the first front-side wiring structure FWS1.

[0149] The first front wiring structure FWS1 and the first back wiring structure BWS1 may be positioned relative to each other with respect to the first device layer 120. For example, the first front wiring structure FWS1 may be disposed on the front surface of the first device layer 120, and the first back wiring structure BWS1 may be disposed on the back surface of the first device layer 120.

[0150] The first front-side wiring structure FWS1 provides signal lines for various devices in the first device layer 120. The first back-side wiring structure BWS1 provides power lines for various devices in the first device layer 120. That is, the first semiconductor chip 100A can adopt a BSPDN scheme in which power lines are arranged on the back surface of the semiconductor chip.

[0151] Reference Figure 10 ,according to Figure 10 The chip stacking structure CS3 of the embodiment and Figure 8 The difference in the embodiments may be that the structure of the second semiconductor chip 200A is different.

[0152] The second semiconductor chip 200A may include a second substrate 210, a second front-side wiring structure FSW2, and a second back-side wiring structure BWS2. The heat dissipation structure of the second front-side wiring structure FSW2 may be referred to as the second front-side heat dissipation structure, and the heat dissipation structure of the second back-side wiring structure BWS2 may be referred to as the second back-side heat dissipation structure.

[0153] The second substrate 210 may be a support substrate for forming the second back-side wiring structure BWS2, and may be disposed on the second front-side wiring structure FSW2. The second substrate 210 may be disposed on the upper surface of the second front-side wiring structure FSW2.

[0154] The second front-side wiring structure FSW2 and the second back-side wiring structure BWS2 can be positioned relative to each other with respect to the second device layer 220. For example, the second front-side wiring structure FSW2 can be disposed on the front surface of the second device layer 220, and the second back-side wiring structure BWS2 can be disposed on the back surface of the second device layer 220.

[0155] The second front-side wiring structure FSW2 provides signal lines for various devices in the second device layer 220. The second back-side wiring structure BWS2 provides power lines for various devices in the second device layer 220. For example, the second semiconductor chip 200A may employ a BSPDN scheme in which power lines are disposed on the back surface of the semiconductor chip.

[0156] Reference Figure 11 ,according to Figure 11 The chip stacking structure CS4 of the embodiment and Figure 8 The difference between the embodiments may be that the first semiconductor chip 100A and the second semiconductor chip 200A have different structures.

[0157] The first semiconductor chip 100A may include a first substrate 110, a first front-side wiring structure FWS1, and a first back-side wiring structure BWS1. The heat dissipation structure of the first front-side wiring structure FWS1 may be referred to as the first front-side heat dissipation structure, and the heat dissipation structure of the first back-side wiring structure BWS1 may be referred to as the first back-side heat dissipation structure.

[0158] The first substrate 110 may be a support substrate for forming the first back-side wiring structure BWS1, and may be disposed on the first front-side wiring structure FWS1. The first substrate 110 may be disposed on the upper surface of the first front-side wiring structure FWS1.

[0159] The first front wiring structure FWS1 and the first back wiring structure BWS1 may be positioned relative to each other with respect to the first device layer 120. For example, the first front wiring structure FWS1 may be disposed on the front surface of the first device layer 120, and the first back wiring structure BWS1 may be disposed on the back surface of the first device layer 120.

[0160] The first front-side wiring structure FWS1 provides signal lines for various devices in the first device layer 120. The first back-side wiring structure BWS1 provides power lines for various devices in the first device layer 120. That is, the first semiconductor chip 100A can adopt a BSPDN scheme in which power lines are arranged on the back surface of the semiconductor chip.

[0161] The second semiconductor chip 200A may include a second substrate 210, a second front-side wiring structure FSW2, and a second back-side wiring structure BWS2. The heat dissipation structure of the second front-side wiring structure FSW2 may be referred to as the second front-side heat dissipation structure, and the heat dissipation structure of the second back-side wiring structure BWS2 may be referred to as the second back-side heat dissipation structure.

[0162] The second substrate 210 may be a support substrate for forming the second back-side wiring structure BWS2, and may be disposed on the second front-side wiring structure FSW2. The second substrate 210 may be disposed on the upper surface of the second front-side wiring structure FSW2.

[0163] The second front-side wiring structure FSW2 and the second back-side wiring structure BWS2 can be positioned relative to each other with respect to the second device layer 220. For example, the second front-side wiring structure FSW2 can be disposed on the front surface of the second device layer 220, and the second back-side wiring structure BWS2 can be disposed on the back surface of the second device layer 220.

[0164] The second front-side wiring structure FSW2 provides signal lines for various devices in the second device layer 220. The second back-side wiring structure BWS2 provides power lines for various devices in the second device layer 220. That is, the second semiconductor chip 200A can adopt a BSPDN scheme in which the power wiring is arranged on the back surface of the semiconductor chip.

[0165] Figures 12 to 21 This is a cross-sectional view illustrating a method of manufacturing a semiconductor chip and a chip stack structure according to some example embodiments of the present disclosure.

[0166] Reference Figure 12 The device layer 120 may be formed on the substrate 110. For example, the device layer 120 may be formed on the first surface 110_1 of the substrate 110. The device layer 120 may contact the first surface 110_1 of the substrate 110.

[0167] Next, a first via layer V1 can be formed on the device layer 120. For example, the first via layer V1 can be formed by a mosaic process.

[0168] In some embodiments, a first interlayer insulating film 131 may be formed on the device layer 120. The first interlayer insulating film 131 may contact the upper surface of the device layer 120. Subsequently, a portion of the first interlayer insulating film 131 may be removed. For example, a mask pattern may be formed on the upper surface of the first interlayer insulating film 131, and the portion exposed through the mask pattern may be removed. Thus, a portion of the first interlayer insulating film 131 may be removed to form a first via hole. For example, the first via hole may include a first-first via hole VH11 and a first-second via hole VH12. The number and location of the first via holes are merely illustrative and may be provided in a larger number.

[0169] A first heat dissipation film 310 may be formed in the first via layer V1. The first heat dissipation film 310 may be conformally formed by a process such as CVD or PVD. Specifically, the first heat dissipation film 310 may be formed on the side surfaces of the first-first via VH11 and the first-second via VH12 and on the upper surface of the first interlayer insulating film 131. The first heat dissipation film 310 may contact the inner surface and the upper surface of the first interlayer insulating film 131. The portion formed along the side surfaces of the first-first via VH11 and the first-second via VH12 forms the first portion 311 of the first heat dissipation film 310, and the portion formed along the upper surface of the first interlayer insulating film 131 forms the second portion 312 of the first heat dissipation film 310. In some embodiments, the portion of the first heat dissipation film 310 on the first interlayer insulating film 131 may be removed. For example, a CMP process may remove the portion of the first heat dissipation film 310 on the first interlayer insulating film 131, leaving only the first portion 311 of the first heat dissipation film 310.

[0170] The first heat dissipation film 310 may be formed of a 2D material, or may include a 2D material. The first heat dissipation film 310 may be formed of a conductive material, or may include a conductive material. For example, the first heat dissipation film 310 may be formed of graphene. In some embodiments, the first heat dissipation film 310 may be formed of at least one of diamond-like carbon (DLC), hBN, and TMD.

[0171] Reference Figure 13 First vias V11 and V12 can be formed. Specifically, the first-first via V11 can be formed in the first-first through-hole VH11, and the first-second via V12 can be formed in the first-second through-hole VH12. A seed layer can be conformally disposed in the first-first through-hole VH11 and the first-second through-hole VH12, and a plating process using the seed layer as an electrode can form the first-first via V11 and the first-second via V12. For example, the first vias V11 and V12 may include Cu. In some embodiments, the first vias V11 and V12 may include W or Co, and can be formed by CVD.

[0172] Next, a planarization process can be performed on the upper surface of the first via layer V1. For example, a CMP process can be performed on the upper surface of the first via layer V1. In the example embodiment, the upper surfaces of the first-first via V11, the first-second via V12, and the upper surface of the first heat dissipation film 310 may be coplanar.

[0173] Next, a first heat-dissipating insulating film 331 may be formed on the portion of the first heat-dissipating film 310 excluding the portion where wiring will be formed. The first heat-dissipating insulating film 331 may include an insulating material. For example, a mask pattern may be provided on the first heat-dissipating film 310 at the location where wiring will be formed, and an oxidation process may be performed on the portion exposed through the mask pattern. For example, an oxide obtained by oxidizing the conductive material constituting the first heat-dissipating film 310 may be formed by using a chemical oxidation process that supplies an oxidant to induce oxidation, irradiating a surface with a laser or electron beam, plasma treatment, or the application of voltage.

[0174] In some embodiments, a portion of the first heat dissipation film 310 may be removed and filled with insulating material to form a first heat dissipation insulating film 331. The upper surface of the first heat dissipation insulating film 331 may be coplanar with the upper surface of the remaining portion of the first heat dissipation film 310.

[0175] For example, the first heat-dissipating insulating film 331 may be formed of graphene oxide, or may include graphene oxide. In some embodiments, the first heat-dissipating insulating film 331 may include an insulating material having high thermal conductivity.

[0176] Reference Figure 14A first metal layer M1 can be formed on the first via layer V1.

[0177] A second interlayer insulating film 132 can be formed on the first via layer V1. Then, a portion of the second interlayer insulating film 132 can be removed to form wiring trenches. Wiring trenches can be formed on the first heat dissipation film 310 and the first vias V11 and V12. The second interlayer insulating film 132 can remain on the first heat dissipation insulating film 331. That is, the portion of the second interlayer insulating film 132 on the first heat dissipation insulating film 331 may not be removed, while the portion on the first heat dissipation film 310 and the first vias V11 and V12 may be removed. For example, the second interlayer insulating film 132 may contact the entire upper surface of the first heat dissipation insulating film 331.

[0178] First wirings M11, M12, and M13 can be formed in wiring trenches. First-first wiring M11 and first-third wiring M13 can respectively contact the entire upper surface of first-first via V11 and first-second via V12. The first-first wiring M11, first-second wiring M12, and first-third wiring M13 can be formed by conformally setting a seed layer and using the seed layer as an electrode to perform a plating process. For example, the first-first wiring M11, first-second wiring M12, and first-third wiring M13 may include Cu. In some embodiments, the first wirings M11, M12, and M13 may include W or Co and can be formed by CVD.

[0179] Next, a planarization process can be performed on the upper surface of the first metal layer M1. For example, a CMP process can be performed on the upper surface of the first metal layer M1. The upper surfaces of the first-first wiring M11, the first-second wiring M12, and the first-third wiring M13 can be coplanar with the remaining portion of the second interlayer insulating film 132 (e.g., the upper surface of the remaining portion).

[0180] Reference Figure 15 This allows the formation of second vias V21, V22, and V23. The method for forming the second vias V21, V22, and V23 is the same as described in the reference. Figure 12 and Figure 13 The methods for forming the first vias V11 and V12 are essentially the same. For example, a third interlayer insulating film 133 may be formed on the first metal layer M1. The third interlayer insulating film 133 may contact the upper surface of the first metal layer M1 and the upper surface of the second interlayer insulating film 132.

[0181] A mask pattern can be formed on the upper surface of the third interlayer insulating film 133, and thus a portion of the third interlayer insulating film 133 can be removed to form a second via. A second heat dissipation film 320 can be formed on the side surface of the second via and on the upper surface of the third interlayer insulating film 133. The second heat dissipation film 320 can contact the inner surface and the upper surface of the third interlayer insulating film 133.

[0182] In some embodiments, the portion of the second heat dissipation film 320 on the third interlayer insulating film 133 may be removed. For example, a CMP process may remove the portion of the second heat dissipation film 320 on the third interlayer insulating film 133, leaving only the first portion 321 of the second heat dissipation film 320.

[0183] Next, second vias V21, V22, and V23 can be formed. For example, a seed layer can be conformally disposed in the second vias, and a plating process using the seed layer as an electrode can form the second vias V21, V22, and V23.

[0184] Next, a planarization process can be performed on the upper surface of the second via layer V2. For example, a CMP process can be performed on the upper surface of the second via layer V2. In the example embodiment, the upper surfaces of the second vias V21, V22, and V23 and the upper surface of the second heat dissipation film 320 may be coplanar.

[0185] Next, a second heat-dissipating insulating film 332 can be formed on the portion of the second heat-dissipating film 320 other than the portion where the second wiring will be formed. The method for forming the second heat-dissipating insulating film 332 can be the same as described in the reference. Figure 13 The method for forming the first heat-dissipating insulating film 331 is basically the same as described. The upper surface of the second heat-dissipating insulating film 332 may be coplanar with the upper surface of the remaining portion of the second heat-dissipating film 320.

[0186] As described above, an oxide can be formed by oxidizing the conductive material constituting the second heat dissipation film 320. For example, the second heat dissipation insulating film 332 may be formed of graphene oxide, or may include graphene oxide. In some embodiments, the second heat dissipation insulating film 332 may include an insulating material having high thermal conductivity.

[0187] Reference Figure 16 A second metal layer M2 can be formed on the second via layer V2. The method for forming the second metal layer M2 is similar to that described in the reference. Figure 14 The method for forming the first metal layer M1 is basically the same as described. The upper surfaces of the second wirings M21 and M22 may be coplanar with the upper surface of the fourth interlayer insulating film 134.

[0188] Next, a support substrate 115 can be formed on the wiring structure WS. The first surface 115_1 of the support substrate 115 may face the same direction as the first surface 110_1 of the substrate 110. The second surface 115_2 of the support substrate 115 may face the wiring structure WS. The second surface 115_2 of the support substrate 115 may contact the upper surfaces of the second wirings M21 and M22 and the upper surface of the fourth interlayer insulating film 134. An oxide film for bonding can be formed between the support substrate 115 and the wiring structure WS. For example, a silicon oxide film may be placed between the support substrate 115 and the wiring structure WS to attach the support substrate 115.

[0189] Reference Figure 17 A second wiring structure WS2 can be formed on the back surface of the device layer 120. In the following text, the wiring structure disposed on the front surface of the device layer 120 may be referred to as the first wiring structure WS1 or the front wiring structure WS1.

[0190] The substrate 110 disposed on the back surface of the device layer 120 can be removed. For example, the substrate 110 can be removed by a CMP process. Subsequently, a first via layer V1, a first metal layer M1, and a second via layer V2 can be sequentially formed on the back surface of the device layer 120. The method for forming the first via layer V1, the first metal layer M1, and the second via layer V2 of the second wiring structure WS2 can be the same as described in the reference. Figures 12 to 14 The methods described are basically the same. In this way, a second wiring structure WS2 can be formed.

[0191] Reference Figure 18 Trench TRs can be formed in a semiconductor chip. Such trench TRs can be used to form through electrodes or through heat dissipation films. The trench TRs can penetrate the support substrate 115 and can be formed by an etching process. For example, the trench TRs can be formed by a wet etching process or a dry etching process. The etching process removes a portion of the support substrate 115.

[0192] A trench TR may be formed until the trench TR reaches the upper surface of the second wiring structure WS2 or penetrates a portion of the second wiring structure WS2. A portion of the second wiring structure WS2 may be exposed by the trench TR. In some embodiments, the trench TR may be formed such that the trench TR penetrates at least one of a plurality of wiring patterns constituting the second wiring structure WS2.

[0193] Reference Figure 19A surface heat dissipation film 162 can be formed on the first surface 115_1 of the support substrate 115, and a through heat dissipation film 161 can be formed inside the trench TR. The through heat dissipation film 161 can contact the surface of the first via layer V1 of the first wiring structure WS1, the surface of the first metal layer M1, the surface of the second via layer V2 and the second metal layer M2, the side surface of the device layer 120 between the first wiring structure WS1 and the second wiring structure WS2, the side surface of the first via layer V1 of the second wiring structure WS2, and the upper surface of the second portion 312 of the first heat dissipation film 310 of the first via layer V1 of the second wiring structure WS2.

[0194] For example, the heat dissipation film 161 can contact the side surfaces of one or more of the first vias V11 and V12, the first interlayer insulating film 131, the first heat dissipation film 310, and the first heat dissipation insulating film 331 of the first wiring structure WS1. Furthermore, the heat dissipation film 161 can contact the side surfaces of one or more of the first wirings M11, M12, and M13 of the first wiring structure WS1 and the second interlayer insulating film 132. Furthermore, the heat dissipation film 161 can contact the side surfaces of one or more of the second vias V21, V22, and V23, the third interlayer insulating film 133, the second heat dissipation film 320, and the second heat dissipation insulating film 332 of the first wiring structure WS1. Furthermore, the heat dissipation film 161 can contact the side surfaces of one or more of the second wirings M21 and M22 of the first wiring structure WS1 and the fourth interlayer insulating film 134. The heat dissipation film 161 can contact the side surfaces of the supporting substrate 115, and the surface heat dissipation film 162 can contact the first surface 115_1 of the supporting substrate 115.

[0195] The surface heat dissipation film 162 and the through heat dissipation film 161 can be integrally formed. The surface heat dissipation film 162 and the through heat dissipation film 161 may include conductive materials. For example, the surface heat dissipation film 162 and the through heat dissipation film 161 may be formed from graphene in a single layer or multiple layers. The surface heat dissipation film 162 and the through heat dissipation film 161 may be formed by conformal CVD or by sputtering or PVD. In some embodiments, although formed from the same material, the surface heat dissipation film 162 and the through heat dissipation film 161 may be formed by different processes.

[0196] Conductive material can be filled inside the trench TR to form a through electrode 150. The conductive material may include Cu, W, polycrystalline silicon, or Al, etc. For example, a seed layer may be formed inside the trench TR, and an electroplating process using the seed layer as an electrode can fill the conductive material. The conductive material may cover the seed layer inside the trench TR. In some embodiments, a planarization process may be performed on the upper surface of the conductive material.

[0197] In some embodiments, the surface heat dissipation film 162 and the through heat dissipation film 161 may be formed from different materials. Both the surface heat dissipation film 162 and the through heat dissipation film 161 may comprise materials having high thermal conductivity. In some embodiments, the through heat dissipation film 161 may be formed from an insulating material, and the surface heat dissipation film 162 may be formed from a conductive material. For example, the through heat dissipation film 161 may be formed from hBN, and the surface heat dissipation film 162 may be formed from graphene.

[0198] Reference Figure 20 An upper pad 180, a first surface insulating film 181a, and a second surface insulating film 181b can be formed on the surface heat dissipation film 162.

[0199] Mask patterns can be formed on the surface heat dissipation film 162 and the through heat dissipation film 161. For example, the mask pattern can cover a portion of the surface heat dissipation film 162 while covering the entire through heat dissipation film 161. The mask pattern can expose the areas where the first surface insulating film 181a and the second surface insulating film 181b will be formed.

[0200] An oxidation process can be performed on the portion of the surface heat dissipation film 162 that is exposed by the mask pattern. For example, a chemical oxidation process that supplies an oxidant, irradiating the surface with a laser or electron beam, plasma treatment, or applying a voltage to the surface heat dissipation film 162 can oxidize the exposed portion, thereby forming an oxide obtained by oxidizing the conductive material constituting the surface heat dissipation film 162.

[0201] As described above, a first surface insulating film 181a and a second surface insulating film 181b can be formed by partially oxidizing the surface heat dissipation film 162. The first surface insulating film 181a and the second surface insulating film 181b may comprise oxides obtained by oxidizing a conductive material. Therefore, the oxides constituting the first surface insulating film 181a and the second surface insulating film 181b may have insulating properties.

[0202] Optionally, a portion of the surface heat dissipation film 162 may be removed and filled with insulating material to form a first surface insulating film 181a and a second surface insulating film 181b.

[0203] For example, the first surface insulating film 181a and the second surface insulating film 181b may be formed of graphene oxide obtained by oxidizing graphene, or may include graphene oxide obtained by oxidizing graphene.

[0204] A first surface insulating film 181a and a second surface insulating film 181b may be formed on a first surface 115_1 of the supporting substrate 115. For example, the first surface insulating film 181a and the second surface insulating film 181b may be formed in a portion of the surface heat dissipation film 162. Specifically, the first surface insulating film 181a may be formed around the location where the upper pad 180 will be formed, and the second surface insulating film 181b may be formed around the location where the through electrode 150 will be formed.

[0205] Upper pads 180 may be formed on the first surface insulating film 181a. Upper pads 180 may be formed by depositing a metallic material onto the first surface insulating film 181a. The lower surface of each upper pad 180 may contact the upper surface of the first surface insulating film 181a. In some embodiments, a pad for attaching the second connection terminal 192 may be formed on the through electrode 150.

[0206] In some embodiments, during the deposition of the upper pad 180, a portion of the first surface insulating film 181a may be melted and combined with the upper pad 180. While the first surface insulating film 181a melts, the upper pad 180 may become substantially coplanar with the first surface insulating film 181a. In some embodiments, a seed layer may be conformally disposed beneath the upper pad 180, and the upper pad 180 may be formed using a plating process employing the seed layer as an electrode.

[0207] In this way, a first semiconductor chip 100 can be manufactured. Hereinafter, a method for manufacturing a chip stack structure CS by stacking a second semiconductor chip 200 on the first semiconductor chip 100 is described.

[0208] Reference Figure 21 The first semiconductor chip 100 may include a first front-side wiring structure FWS1 and a first back-side wiring structure BWS1, and the second semiconductor chip 200 may include a second front-side wiring structure FWS2 and a second back-side wiring structure BWS2.

[0209] A first connection terminal 191 can be attached to the upper pad 180 of the first semiconductor chip 100, and a second connection terminal 192 can be attached to the through electrode 150 of the first semiconductor chip 100. A second semiconductor chip 200 can be stacked on the first semiconductor chip 100. When the second semiconductor chip 200 is stacked on the first semiconductor chip 100, a reflow process can fuse the first connection terminal 191 and the second connection terminal 192 to the connection terminals (e.g., solder balls) attached to the second semiconductor chip 200.

[0210] In the manufacturing method for semiconductor chips and chip stack structures according to the present disclosure, although the first semiconductor chip 100 and the second semiconductor chip 200 are shown as employing a BSPDN scheme in which power supply wiring is disposed on the back surface of the semiconductor chip, the present disclosure is not limited thereto.

[0211] Although the present disclosure has been described above with reference to limited embodiments and drawings, the present disclosure is not limited thereto, and various modifications and alterations can be made by those skilled in the art within the scope of the technical concept of the present disclosure and the equivalents defined by the appended claims.

Claims

1. A semiconductor chip, comprising: The device layer has a first surface and a second surface opposite to the first surface; as well as The first wiring structure is located on the first surface of the device layer. The first wiring structure includes: The first via layer includes the first via; A first metal layer, including a first wiring, is stacked on a first via layer in a first direction perpendicular to a first surface of the device layer; and A first heat dissipation structure includes a first heat dissipation film, the first heat dissipation film including a first portion surrounding a bottom surface and a side surface of a first through-hole, the first heat dissipation structure comprising a two-dimensional material, and In this process, the upper surface of the first portion of the first heat dissipation film contacts the lower surface of the first wiring.

2. The semiconductor chip according to claim 1, wherein, The first heat dissipation film also includes a second portion extending along the lower surface of the first wiring of the first metal layer.

3. The semiconductor chip according to claim 2, in, The first heat dissipation film also includes a third portion extending from the second portion along the side surface of the first wiring of the first metal layer, and The upper surface of the third part is coplanar with the upper surface of the first wiring of the first metal layer.

4. The semiconductor chip according to claim 3, wherein, The first via and the first wiring have an integrated structure.

5. The semiconductor chip according to claim 2, in, The first heat dissipation film also includes a fourth portion extending along the upper surface of the first wiring, and The semiconductor chip further includes: A heat-dissipating insulating film is stacked with a fourth portion in a second direction perpendicular to the first direction.

6. The semiconductor chip according to claim 2, wherein, The first heat dissipation structure also includes a heat dissipation insulating film superimposed on the second portion in a second direction perpendicular to the first direction.

7. The semiconductor chip according to claim 6, wherein, The thickness of the second part in the first direction is the same as the thickness of the heat dissipation insulating film in the first direction.

8. The semiconductor chip according to claim 6, in, The first wiring structure also includes a second wiring spaced apart from the first wiring in a second direction, and The heat dissipation insulating film is located between the first wiring and the second wiring.

9. The semiconductor chip according to claim 6, in, The two-dimensional materials constituting the first heat dissipation structure include graphene, and The heat dissipation insulating film includes graphene oxide.

10. The semiconductor chip according to claim 1, further comprising: The second wiring structure is on the second surface of the device layer; as well as Supporting substrate, on the first wiring structure, The second wiring structure includes: The second via layer includes the second via; The second metal layer includes a second wiring, and the second metal layer is disposed on the second via layer; and The second heat dissipation structure is located on at least a portion of the second via and the second wiring.

11. The semiconductor chip according to any one of claims 1 to 10, wherein the semiconductor chip further comprises: The through electrode extends in a first direction and is stacked with the device in a second direction perpendicular to the first direction; It penetrates the heat dissipation film and extends along the bottom and side surfaces of the electrode. as well as A surface heat dissipation film is connected to a through-heat dissipation film and extends in a second direction.

12. The semiconductor chip according to claim 11, wherein, It penetrates the heat dissipation film and contacts the first wiring structure.

13. A chip stacking structure, comprising: The first semiconductor chip includes a first substrate, a first device layer on the first substrate, and a first front-side wiring structure on the front surface of the first device layer. The second semiconductor chip includes a second substrate, a second device layer on the second substrate, and a second front-side wiring structure on the front surface of the second device layer. The second semiconductor chip is stacked on the first semiconductor chip. Penetrating electrodes, penetrating at least a portion of the first semiconductor chip; as well as Penetrating the heat dissipation film, surrounding at least a portion of the penetrating electrode, The first front wiring structure includes: A first front via layer, including a first front via, is disposed on a first device layer; A first front metal layer, including a first front wiring, wherein the first front metal layer is disposed on a first front via layer; and The first front heat dissipation structure includes a first portion of the bottom surface and the side surface surrounding the first front through-hole, and The second front wiring structure includes: The second front via layer includes a second front via, and the second front via layer is disposed on the second device layer; A second front metal layer, including second front wiring, wherein the second front metal layer is disposed on a second front via layer; and The second front heat dissipation structure includes a first portion of the bottom surface and the side surface surrounding the second front through-hole.

14. The chip stacking structure according to claim 13, in, The first semiconductor chip also includes a first back-side wiring structure and a first support substrate. The first back-side wiring structure is located on the back surface of the first device layer, and the first support substrate is located on the first front-side wiring structure. Among them, the through electrode penetrates the first supporting substrate, and Among them, the heat dissipation film contacts the first back-side wiring structure.

15. The chip stacking structure according to claim 14, wherein, The first back-side wiring structure includes: A first back-side via layer, including a first back-side via, is disposed on a first device layer; A first back-side metal layer, including a first back-side wiring, wherein the first back-side metal layer is disposed on a first back-side via layer; and The first back-side heat dissipation structure includes a first portion of the bottom surface and the side surface surrounding the first back-side via.

16. The chip stacking structure according to claim 15, in, The second semiconductor chip also includes a second back-side wiring structure and a second support substrate. The second back-side wiring structure is located on the back surface of the second device layer, and the second support substrate is located on the second front-side wiring structure. The second back-side wiring structure includes: The second back-side via layer includes a second back-side via, and the second back-side via layer is disposed on the second device layer; A second back-side wiring layer, including second back-side wiring, wherein the second back-side wiring layer is disposed on a second back-side via layer; and The second rear-side heat dissipation structure includes a first portion of the bottom surface and the side surface surrounding the second rear-side via.

17. The chip stacking structure according to any one of claims 13 to 16, wherein, The first semiconductor chip also includes a surface heat dissipation film disposed on the first substrate.

18. The chip stacking structure according to claim 17, further comprising: A first surface insulating film is disposed between the penetrating heat dissipation film and the surface heat dissipation film; A pad is disposed in a surface heat dissipation film on a first substrate; A second surface insulating film is disposed in a surface heat dissipation film on the first substrate and surrounds the pad; A first connection terminal is disposed on the pad and connects the first semiconductor chip and the second semiconductor chip. as well as The second connection terminal is disposed on the through electrode and connects the first semiconductor chip and the second semiconductor chip.

19. The chip stacking structure according to claim 18, wherein, The first and second surface insulating films include graphene oxide.

20. A semiconductor package, comprising: Packaging substrate; as well as The chip stacking structure is set on the packaging substrate. The chip stacking structure includes: A first semiconductor chip includes a first device layer and a first front-side wiring structure on the front surface of the first device layer; The second semiconductor chip includes a second device layer and a second front-side wiring structure on the front surface of the second device layer, and the second semiconductor chip is stacked on the first semiconductor chip. Penetrating electrodes, penetrating at least a portion of the first semiconductor chip; and Penetrating the heat dissipation film, surrounding at least a portion of the penetrating electrode, The first front wiring structure includes: The first front via layer includes a first front via; A first front metal layer, including a first front wiring, wherein the first front metal layer is disposed on a first front via layer; and The first front heat dissipation structure includes a first portion of the bottom surface and the side surface surrounding the first front through-hole, and The second front wiring structure includes: The second front via layer includes a second front via; A second front metal layer, including second front wiring, wherein the second front metal layer is disposed on a second front via layer; and The second front heat dissipation structure includes a first portion of the bottom surface and the side surface surrounding the second front through-hole, and Each of the heat dissipation film, the first front heat dissipation structure, and the second front heat dissipation structure comprises a two-dimensional material.

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