Seal ring structure

Abstract

The present disclosure relates to semiconductor structures, and more particularly to a seal ring structure and method of manufacture. The structure includes a trench structure located in a GaN material stack, an ohmic metal contacting an upper surface of the GaN material stack on one side of the trench structure, and a seal ring structure extending vertically from and in contact with the ohmic metal on one side of the trench structure.

Description

Technical Field

[0001] This disclosure relates to semiconductor structures, and more specifically to sealing ring structures and manufacturing methods. Background Technology

[0002] MOSFET devices are used for power switching in power applications and others. MOSFET devices continue to improve in key parameters such as on-resistance, rated voltage, and switching speed. However, the performance of MOSFET devices may be approaching their physical limits.

[0003] To continue its improvement, GaN devices are becoming increasingly attractive in many applications. GaN devices are high electron mobility transistors (HEMTs). GaN devices can have higher electric field strengths than traditional MOSFETs, providing further performance improvements in areas such as on-resistance and breakdown voltage, while also offering fast switching speeds and other important parameters. However, GaN devices are susceptible to moisture penetration, which can affect device performance and integrity. Summary of the Invention

[0004] In one aspect of this disclosure, a structure includes: a trench structure located in a GaN material stack; an ohmic metal contacting an upper surface of the GaN material stack on one side of the trench structure; and a sealing ring structure extending vertically from and in contact with the ohmic metal on one side of the trench structure.

[0005] In one aspect of this disclosure, a structure includes: a trench structure located in a GaN material stack extending to an underlying semiconductor material; an ohmic metal contacting an upper surface of the GaN material stack and surrounding the trench structure; an active region adjacent to the inner side of the trench structure; and a sealing ring structure extending vertically from the ohmic metal and encapsulated by the ohmic metal.

[0006] In one aspect of this disclosure, a method includes: forming a trench structure in a GaN material stack; forming an ohmic metal on one side of the trench structure that contacts an upper surface of the GaN material stack; and forming a sealing ring structure that extends vertically from and contacts the ohmic metal on one side of the trench structure. Attached Figure Description

[0007] In the following detailed description, the present disclosure is described with reference to the various accompanying drawings, using non-limiting examples of exemplary embodiments of the present disclosure.

[0008] Figure 1 The sealing ring structure and corresponding manufacturing process according to aspects of this disclosure are shown.

[0009] Figure 2 A top view of the structure according to an aspect of this disclosure is shown.

[0010] Figure 3 The present disclosure illustrates a method for manufacturing... Figure 1 The manufacturing process of the structure. Detailed Implementation

[0011] This disclosure relates to semiconductor structures, and more specifically to sealing ring structures and manufacturing methods. More specifically, this disclosure relates to sealing ring structures for GaN devices. Advantageously, this sealing ring structure prevents moisture from entering the GaN layer and active region of a high electron mobility transistor (HEMT).

[0012] In a more specific embodiment, a III-V device includes a semiconductor substrate, a channel layer (e.g., GaN) above the semiconductor substrate, and a moisture barrier layer located within a trench in the channel layer. In one embodiment, the trench may be a sealing ring trench. The trench may extend completely through the channel layer at the edge of the active region. In other embodiments, the ohmic metal contact may be a continuous ohmic metal contact connected to the GaN layer on the opposite side of the trench. A sealing ring structure may be disposed above and in direct contact with an ohmic metal contact adjacent to the trench, thereby preventing moisture from entering the active region. In one embodiment, the ohmic metal covers the trench and contacts the GaN on either side of the trench, so that moisture does not "jump the gap" through the interlayer dielectric layer.

[0013] The sealing ring structures of this disclosure can be fabricated using a variety of different tools and in a variety of ways. However, generally, methods and tools are used to form structures with micron and nanometer-scale dimensions. Methods (i.e., techniques) for fabricating the sealing ring structures of this disclosure have been adopted according to integrated circuit (IC) technology. For example, these structures are built on a wafer and realized in a material film patterned by photolithography on top of the wafer. Specifically, the fabrication of the sealing ring structure uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithographic imaging; and (iii) selectively etching the film onto the mask. Furthermore, as is known in the art, a pre-cleaning process can be used to clean any contaminants from the etched surface. Additionally, as is known in the art, a rapid thermal annealing process can be used, where necessary, to drive in dopants or material layers.

[0014] Figure 1 The sealing ring structure and corresponding manufacturing process according to aspects of this disclosure are shown, among other features. More specifically, Figure 1Structure 10 includes GaN material 14 disposed on a semiconductor substrate 12, for example, a GaN material stack. In embodiments, the semiconductor substrate 12 can be any suitable substrate material used in III-V devices, including but not limited to Si, SiC, or sapphire as examples.

[0015] GaN stack 14 may include a channel layer for HEMT or metal-insulator-silicon HEMT (MISHEMT) and may be defined by different layers, including but not limited to a buffer layer (e.g., AlN) on the semiconductor substrate 12, a GaN layer on top of the buffer layer, and an AlGaN top layer. Those skilled in the art will understand that other materials may be used in the material stack, and the examples above are merely illustrative and non-limiting. For example, the GaN layer may contain different percentage concentrations of Ga as it transitions from the upper surface to the lower surface. Furthermore, in a preferred embodiment, the semiconductor substrate 12 and GaN stack 14 may include different band gaps. Patterning of GaN stack 14 may result in a slight stepped structure 14a at the edges of trench 16. Those skilled in the art will recognize that this disclosure is not limited to GaN stack 14, and in embodiments, other transistors may be included containing different III-V materials (e.g., GaAs and AlGaAs as alternatives to GaN and AlGaN).

[0016] Still referencing Figure 1 A barrier layer 22, such as aluminum oxide, can be formed on top of the GaN stack 14. In an embodiment, a trench 16 can be formed across the GaN stack 14 and the barrier layer 22 at the outer edge of the active region 15. In an embodiment, the trench 16 can extend to the semiconductor substrate 12. In an embodiment, it is also possible to deposit the Al2O3 after the trench is formed. The PGAN gate material (if any) can be patterned before the Al2O3 is deposited. All sides and the bottom surface of the trench 16 can be lined with a moisture barrier layer 18. The moisture barrier layer 18 can be SiN or another non-conductive material. The trench 16 can be filled with an insulating material 20, such as an oxide material or other low-k dielectric material 20. In an embodiment, the insulating material 20 can be an interlayer dielectric material.

[0017] An optional moisture barrier layer 18a may be disposed above the insulating material 20 (and below the metallic material 26 (e.g., ohmic contact)). The optional moisture barrier layer 18a may be a single layer or a stack of layers, such as nitrides and oxides, and may be patterned above the insulating material 20 and extend to the GaN stack 14, barrier layer 22, or extend to barrier layer 18. As will be understood by those skilled in the art, the moisture barrier layers 18, 18a prevent moisture from entering the active region 15 of the GaN stack 14 from the upper surface and outer edges. In embodiments, barrier layer 18a may be used to protect seams (if any) from any subsequent dielectric material etching or wet cleaning.

[0018] Still referencing Figure 1 A metallic material 26 can be formed to contact the GaN material 14 (e.g., a GaN material stack). In other embodiments, the metallic material 26 covers the trench and contacts the GaN stack 14 on either side of the trench 16, so that moisture does not “skip the gap” through the interlayer dielectric layer. The metallic material can contact the upper surface of an optional moisture barrier layer 18a and can surround the trench 16 itself. In embodiments, the metallic material 26 can be an ohmic contact. The metallic material 26 can be formed directly on the upper surface of the GaN stack 14 (e.g., contacting the upper surface), extending through an opening in the barrier layer 22. In embodiments, the metallic material 26 can extend over the trench 16 and contact the GaN stack 14 on either side of the trench 16, preferably on the side opposite the active region 15. In embodiments, the metallic material 26 does not need to contact the active region of the device because the guarding is grounded preferentially independent of the device elements. The metallic material 26 can be aluminum, an aluminum substrate, WN, TiN or TaN, tungsten, or combinations thereof. Several layers of insulating material 24 may be disposed above the metal material 26 and the barrier material 22. The insulating material 24 may include, for example, alternating layers of oxides and nitrides.

[0019] Figure 1 A sealing ring structure 28 is also shown, extending to the metal material 26 located on one side of the trench 16 and on the opposite side of the active region 15. In an embodiment, the sealing ring structure 28 directly contacts the metal material 26 and extends to the upper surface of the top insulating layer 24 (e.g., an interlayer dielectric material). In a more specific embodiment, the sealing ring structure 28 is a vertical structure having continuous metal all the way to the last metal wiring layer. Those skilled in the art will understand that the sealing ring structure 28 is a continuous ring around the chip (e.g., the active region 15).

[0020] For example, the sealing ring structure 28 may include a combination of an interconnect structure 28a and a wiring structure 28b (these two structures are joined together to form a monolithic vertical structure extending from the metallic material 26 to the upper surface of the insulating material 24). The interconnect structure 28a may be tungsten; however, other materials, such as copper or cobalt, are also contemplated herein. As a non-limiting example, the wiring structure 28b may comprise copper or aluminum.

[0021] Figure 2 A top view of the structure according to an aspect of this disclosure is shown. In an embodiment, the sealing ring structure 28 completely surrounds the active region 15 of the device. In an embodiment, the active region 15 may include gate structures and associated channel regions known in the art; therefore, no further explanation is required to fully understand this disclosure.

[0022] Figure 3 The present disclosure illustrates a method for manufacturing... Figure 1 The fabrication process for the structure. In step 300, a GaN stack (including a barrier layer) can be deposited on a semiconductor substrate. In embodiments, the GaN stack can be ensured (more or less) as a single-crystal GaN / AlGaN by epitaxial growth (MOCVD or MBE). The initial AlN deposition can be performed in the same process or by CVD / PVD.

[0023] In step 305, trenches can be formed through the GaN stack to the underlying semiconductor substrate using conventional photolithography and etching processes. For example, a resist formed over the GaN stack and barrier layer is exposed to energy (light) and developed using a conventional resist developer to form a pattern (opening). Using an etching process with selective chemical action, such as reactive ion etching (RIE), the pattern is transferred from the photoresist layer to form one or more trenches in the GaN stack and barrier layer through the openings in the resist.

[0024] After the resist is removed by a conventional oxygen ashing process or other known stripping agents, the trench can be filled in step 310. For example, a nitride layer can be deposited to line the trench, followed by the deposition of an oxide material to fill the trench. The nitride and oxide layers can be deposited using any conventional deposition process, such as CVD. An optional nitride layer can be formed over the oxide layer. The deposition process can be a conventional CVD process. Any residual material on the surfaces of the GaN stack and barrier layer can be removed using a conventional chemical mechanical polishing (CMP) process.

[0025] In step 315, a metallic material may be deposited on the trench and GaN stack 14. In this embodiment, the metallic material may be any suitable conductive material for ohmic contacts. In step 320, the metallic material is patterned using conventional photolithography and etching processes to form contacts on and above the opposite sides of the trench.

[0026] In step 320, a sealing ring structure is formed using a back-end process. In an embodiment, the sealing ring structure is formed using a conventional back-end process. For example, an interlayer dielectric material can be deposited over a metallic material (e.g., an ohmic contact), followed by photolithography and etching processes to form trenches (outside the active region) exposing the metallic material. In an embodiment, the photolithography and etching processes can be a single-damascene process or a dual-damascene process. In any case, as is known to those skilled in the art, interconnect metals and wiring metals are formed within trenches in successive wiring layers, and therefore no further explanation is required to fully understand this disclosure. Those skilled in the art will understand that after the deposition process of each wiring layer, the material can be planarized (e.g., a chemical mechanical process) to prepare a surface for depositing additional material in the next wiring layer.

[0027] Sealed ring structures can be used in System-on-Chip (SoC) technology. An SoC is an integrated circuit (also called a "chip") that integrates all the components of an electronic system onto a single chip or substrate. Because the components are integrated on a single substrate, an SoC consumes significantly less power and occupies a much smaller area compared to a multi-chip design with equivalent functionality. Therefore, SoCs are becoming a dominant force in the mobile computing (e.g., in smartphones) and edge computing markets. SoCs are also used in embedded systems and the Internet of Things (IoT).

[0028] The methods described above are used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with one or both surface-mount or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0029] Descriptions of various embodiments of this disclosure have been given for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: The trench structure is located within a GaN material stack; Ohmic metal, which contacts the upper surface of the GaN material stack on one side of the trench structure; as well as A sealing ring structure that extends vertically from the ohmic metal on one side of the groove structure and contacts the ohmic metal.

2. The structure according to claim 1, wherein, The trench structure extends through the GaN material stack to the underlying semiconductor substrate.

3. The structure of claim 1, further comprising a barrier material located above the GaN material stack, wherein, The ohmic metal extends through the barrier material and contacts the GaN material stack.

4. The structure according to claim 1, wherein, The trench structure includes a lining of a first insulating material and a second insulating material that fills the remainder of the trench structure.

5. The structure according to claim 4, wherein, The first insulating material comprises a nitride, and the second insulating material comprises an interlayer dielectric material.

6. The structure according to claim 4 further includes a third insulating material, which lines the surface of the second insulating material and is located below the ohmic metal.

7. The structure according to claim 4, wherein, The ohmic metal is a continuous ohmic metal extending above the trench structure and on the opposite side of the trench structure.

8. The structure according to claim 1, wherein, The sealing ring structure is connected to the ohmic metal located on the outer edge of the groove structure and opposite to the active region.

9. The structure according to claim 8, wherein, The sealing ring structure completely surrounds the active region.

10. The structure according to claim 8, wherein, The sealing ring structure contains a metallic material.

11. The structure according to claim 8, wherein, The sealing ring structure includes via interconnects and wiring structures.

12. A structure comprising: A trench structure located in a GaN material stack that extends into the underlying semiconductor material; Ohmic metal, which contacts the upper surface of the GaN material stack and surrounds the trench structure; The active region is adjacent to the inner side of the trench structure; as well as A sealing ring structure that extends vertically from the ohmic metal on the outside of the groove structure and is surrounded by the ohmic metal.

13. The structure of claim 12, further comprising a barrier material located above the GaN material stack, wherein, The ohmic metal extends through the barrier material and contacts the GaN material stack.

14. The structure according to claim 12, wherein, The trench structure includes a lining of a first insulating material and a second insulating material that fills the remainder of the trench structure.

15. The structure of claim 14 further includes a third insulating material, which lines the surface of the second insulating material.

16. The structure according to claim 14, wherein, The sealing ring structure is connected to the ohmic metal located on the outside of the groove structure and opposite to the active region.

17. The structure according to claim 12, wherein, The sealing ring structure completely surrounds the active region.

18. The structure according to claim 17, wherein, The sealing ring structure contains a conductive material.

19. The structure according to claim 12, wherein, The sealing ring structure includes via interconnects and wiring structures extending through the interlayer dielectric material.

20. A method comprising: Trench structures are formed in GaN material stacks; An ohmic metal is formed on one side of the trench structure in contact with the upper surface of the GaN material stack; as well as A sealing ring structure is formed on one side of the groove structure, extending vertically from the ohmic metal and in contact with the ohmic metal.

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