Method for manufacturing a redistribution layer

Abstract

A method of manufacturing a redistribution layer, including: a first exposure step of exposing a negative photosensitive material layer on a first main surface of a support substrate in a predetermined pattern; a second exposure step of exposing the negative photosensitive material layer on its entire surface from a second main surface side of the support substrate; a development step of developing the exposed negative photosensitive material layer to form a first insulating layer having a recess pattern on the second main surface; a first wiring layer formation step of forming a first wiring layer on the second main surface of the first insulating layer; and a separation step of irradiating light to the first insulating layer from the second main surface side of the support substrate to separate the first insulating layer from the support substrate.

Description

Cross-reference to related applications

[0001] This application claims priority to Japanese Patent Application No. 2025-063690, filed on April 8, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a method for manufacturing a redistribution layer. Background Technology

[0003] As packaging technologies for semiconductor chips that address the need for thinner wiring substrates and higher integration of mounted semiconductor chips, technologies such as fan-out wafer-level packaging (FOWLP) and fan-out panel-level packaging (FOPLP) are known. As an example of FOWLP technology, a manufacturing method is known that involves forming a redistribution layer by stacking insulating layers and wiring layers on a support substrate, and then separating the redistribution layer from the support substrate (e.g., Japanese Patent No. 5042297 and Japanese Patent No. 7208011).

[0004] In manufacturing methods that separate the redistribution layer from the support substrate, a release layer is provided between the support substrate and the redistribution layer to facilitate easy separation. For example, in Japanese Patent No. 7208011, a multilayer laminate comprising a substrate, a release layer, and a metal layer is prepared. A first wiring layer is formed on the surface of the metal layer, and an insulating layer and an nth wiring layer are alternately formed on the surface where the first wiring layer has been formed, to obtain a multilayer laminate. In Japanese Patent No. 7208011, a reinforcing sheet is provided on the multilayer laminate, and then the substrate is separated from the metal layer at the release layer.

[0005] In the manufacturing methods disclosed in Japanese Patent No. 5042297 and Japanese Patent No. 7208011, a release layer is provided in addition to the insulating layer and the wiring layer, which increases the material cost of the release layer and the number of manufacturing steps. Therefore, there is a risk of increased manufacturing costs in the manufacturing methods disclosed in Japanese Patent No. 5042297 and Japanese Patent No. 7208011.

[0006] This disclosure was made in consideration of the above circumstances, and the purpose of this disclosure is to provide a method for manufacturing a redistribution layer that can easily manufacture the redistribution layer while reducing manufacturing costs. Summary of the Invention

[0007] The method for manufacturing the redistribution layer disclosed herein includes: In the photosensitive layer formation step, a negative photosensitive material layer is formed on the first main surface of the light-transmitting support substrate; The first exposure step involves exposing a negative photosensitive material layer formed on the first main surface of the support substrate in a predetermined pattern. In the second exposure step, the negative photosensitive material layer formed on the first main surface of the support substrate is exposed to the entire surface of the negative photosensitive material layer from the second main surface side opposite to the first main surface of the support substrate. The developing step develops the negative photosensitive material layer exposed in the first exposure step and the second exposure step, thereby forming a first insulating layer on the first main surface of the support substrate. The first insulating layer has a recessed pattern corresponding to the predetermined pattern on the second main surface of the first insulating layer. The second main surface of the first insulating layer is opposite to the first main surface of the first insulating layer that is opposite to the first main surface of the support substrate. The first wiring layer forming step involves forming a first wiring layer on the second main surface of the first insulating layer based on the recessed pattern; and In the separation step, light to be absorbed by the first insulating layer is irradiated from the second main surface side of the support substrate onto the first insulating layer, thereby separating the first insulating layer, on which the first wiring layer is formed, from the support substrate. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and not intended to limit this disclosure.

[0008] This disclosure allows for the fabrication of a redistribution layer by separating a first insulating layer, on which a first wiring layer is formed, from a support substrate. This eliminates the need for a release layer on the support substrate and allows for easy fabrication of the redistribution layer while reducing manufacturing costs. Attached Figure Description

[0009] A more complete understanding of this application can be obtained by considering the following detailed description in conjunction with the accompanying drawings, wherein: Figure 1 This is a cross-sectional view showing the redistribution layer according to Embodiment 1; Figure 2 This is a cross-sectional view showing a semiconductor device according to Embodiment 1; Figure 3 This is a flowchart illustrating a method for manufacturing a redistribution layer according to Example 1; Figure 4 This is a cross-sectional view showing the support substrate and the negative photosensitive material layer according to Embodiment 1; Figure 5 This is a schematic diagram illustrating the first exposure step according to Example 1; Figure 6 This is a graph showing the exposure sensitivity curve of the negative photosensitive material according to Example 1; Figure 7 This is a schematic diagram illustrating the second exposure step according to Example 1; Figure 8 This is a cross-sectional view showing the support substrate and the first insulating layer according to Embodiment 1; Figure 9 This is a graph showing the relationship between the exposure amount in the second exposure step according to Example 1 and the thickness of the first insulating layer at the location where the recess is formed; Figure 10 This is a cross-sectional view showing the support substrate, the first insulating layer, and the first wiring layer according to Embodiment 1; Figure 11 This is a diagram illustrating the steps of forming the first wiring layer according to Embodiment 1; Figure 12 This is a diagram illustrating the steps of forming the first wiring layer according to Embodiment 1; Figure 13 This is a diagram illustrating the steps of forming the first wiring layer according to Embodiment 1; Figure 14 This is a diagram illustrating the upper layer formation steps according to Example 1; Figure 15 This is a diagram illustrating the steps for forming the terminal protective layer according to Embodiment 1; Figure 16 This is a diagram illustrating the molding process according to Example 1; Figure 17 This is a diagram illustrating the separation steps according to Example 1; Figure 18 This is a diagram illustrating the separation steps according to Example 1; Figure 19 This is a cross-sectional view showing the support substrate, the first insulating layer, and the first wiring layer according to a comparative example; Figure 20 This is a diagram illustrating the steps for forming the external connection terminal according to Embodiment 1; Figure 21 This is a diagram illustrating the first exposure step according to Example 2; Figure 22 This is a cross-sectional view showing the redistribution layer according to Embodiment 3; Figure 23 This is a flowchart illustrating a method for manufacturing the redistribution layer according to Example 3; Figure 24 This is a schematic diagram used for the second exposure step based on the modified example; and Figure 25 This is a cross-sectional view showing the redistribution layer according to the modified example. Detailed Implementation

[0010] Hereinafter, a method for manufacturing a redistribution layer and a semiconductor device including a redistribution layer according to an embodiment will be described with reference to the accompanying drawings.

[0011] Example 1 Reference Figures 1 to 20 The manufacturing method of the redistribution layer 100 according to this embodiment, and the semiconductor device 300 including the redistribution layer 100, will be described. The redistribution layer 100 is used, for example, for packaging a semiconductor chip 200. The semiconductor device 300 is a fan-out semiconductor device.

[0012] First, the structure of the redistribution layer 100 and the semiconductor device 300 will be explained.

[0013] like Figure 1 As shown, the redistribution layer 100 includes a first insulating layer 20, a first wiring layer 30, upper insulating layers 42 and 44, an upper wiring layer 52, and a terminal protection layer 54. The redistribution layer 100 includes chip connection terminals 60 and external connection terminals 70.

[0014] An upper wiring layer 52 is disposed on the first wiring layer 30. The first wiring layer 30 is electrically connected to the upper wiring layer 52. One end of each of the first wiring layers 30 is electrically connected to each of the external connection terminals 70. The external connection terminals 70 are electrically connected to an external circuit (not shown). Each of the terminal protection layers 54 covers the portion of the upper wiring layer 52 exposed from the upper insulating layer 44. Each of the terminal protection layers 54 is electrically connected to each of the upper wiring layers 52. One end of each of the terminal protection layers 54 is electrically connected to each of the chip connection terminals 60. Each of the chip connection terminals 60 is electrically connected to each of the terminals 202 of the semiconductor chip 200, described later.

[0015] The first insulating layer 20 and the upper insulating layers 42 and 44 are stacked in sequence to fill the space between the wiring layers (the space between the first wiring layers 30, the space between the first wiring layer 30 and the upper wiring layer 52, etc.) and to make the wiring layers insulated from each other.

[0016] In this embodiment, a first wiring layer 30, an upper wiring layer 52, and a terminal protection layer 54 connected by a predetermined wiring pattern are formed inside the stacked first insulating layer 20 and upper insulating layers 42 and 44. The redistribution layer 100 does not necessarily need to include the terminal protection layer 54, the chip connection terminal 60, and the external connection terminal 70.

[0017] like Figure 2As shown, the semiconductor device 300 includes a redistribution layer 100, a semiconductor chip 200, and a molding resin layer 210. The semiconductor chip 200 is mounted on the redistribution layer 100. Each of the terminals 202 of the semiconductor chip 200 is electrically connected to each of the chip connection terminals 60 of the redistribution layer 100. The molding resin layer 210 covers the semiconductor chip 200 and the upper insulating layer 44, and seals the semiconductor chip 200.

[0018] Next, the manufacturing method of the redistribution layer 100 will be described. Figure 3 This is a flowchart illustrating a method for manufacturing the redistribution layer 100. The method for manufacturing the redistribution layer 100 includes: a photosensitive layer forming step (step S110) of forming a negative photosensitive material layer 22 on a first main surface 10a of a support substrate 10; a first exposure step (step S120) of exposing the negative photosensitive material layer 22 to a predetermined pattern; a second exposure step (step S130) of exposing the negative photosensitive material layer 22 to its entire surface from the second main surface 10b side of the support substrate 10; a development step (step S140) of developing the exposed negative photosensitive material layer 22 to form a first insulating layer 20 having a recessed pattern 26; and a first wiring layer forming step (step S150) of forming a first wiring layer 30 based on the recessed pattern 26.

[0019] The manufacturing method of the redistribution layer 100 further includes: an upper layer forming step (step S160) to form upper insulating layers 42 and 44 and upper wiring layer 52; a terminal protection layer forming step (step S170) to form terminal protection layer 54; a chip connection terminal forming step (step S180) to form chip connection terminal 60; a mounting step (step S190) to mount semiconductor chip 200; a molding forming step (step S210) to form molding resin layer 210; a separation step (step S220) to separate the first insulating layer 20 from the support substrate 10; and an external connection terminal forming step (step S230) to form external connection terminal 70.

[0020] In the photosensitive layer formation step (step S110), as Figure 4 As shown, a negative photosensitive material layer 22 is formed on the first main surface 10a of the light-transmitting support substrate 10. In one example, the support substrate 10 is implemented as a glass substrate. The negative photosensitive material layer 22 is formed of an insulating negative photosensitive material (e.g., a photosensitive polyimide-based material). The negative photosensitive material can be a liquid or a dry film. When the negative photosensitive material is a liquid, the negative photosensitive material layer 22 is formed on the first main surface 10a of the support substrate 10 by spin coating or slot coating, etc. The negative photosensitive material layer 22 formed on the first main surface 10a of the support substrate 10 can also be pre-baked.

[0021] In the first exposure step (step S120), as Figure 5 As shown, the negative photosensitive material layer 22 formed on the first main surface 10a of the support substrate 10 is exposed with a predetermined pattern using an exposure ExL1 from the negative photosensitive material layer 22 side using a mask M.

[0022] Here, the exposure amount used to expose the negative photosensitive material layer 22 is explained. Figure 6 The exposure sensitivity curves representing the residual film rate after development relative to the exposure amount of the negative photosensitive material are shown. The residual film rate of the negative photosensitive material after development refers to the ratio of the film thickness of the negative photosensitive material after development to the film thickness of the negative photosensitive material before development. For negative photosensitive materials, the residual film rate increases from zero when the exposure amount exceeds the exposure amount Ith, and saturates when the exposure amount reaches the exposure amount Isat. In other words, when the negative photosensitive material is exposed at an exposure amount exceeding Ith, the solubility of the negative photosensitive material in the developer gradually decreases. When the negative photosensitive material is exposed at an exposure amount exceeding Isat, the negative photosensitive material becomes insoluble in the developer. In this paper, the exposure amount Ith is referred to as the threshold exposure amount Ith, and the exposure amount Isat is referred to as the saturation exposure amount Isat.

[0023] In the first exposure step (step S120), the negative photosensitive material layer 22 is preferably exposed with an exposure amount I1 that is greater than or equal to the saturation exposure amount Isat (i.e., the exposure amount that saturates the residual film rate).

[0024] In the second exposure step (step S130), as Figure 7 As shown, from the second main surface 10b side of the support substrate 10 opposite to the first main surface 10a, the negative photosensitive material layer 22 exposed in the first exposure step (step S120) is exposed over its entire surface with exposure light ExL2. In the second exposure step, the negative photosensitive material layer 22 is exposed with an exposure amount I2 that is greater than or equal to the threshold exposure amount Ith and less than the saturation exposure amount Isat.

[0025] In the developing step (step S140), as Figure 8 As shown, the negative photosensitive material layer 22 exposed in the first exposure step (step S120) and the second exposure step (step S130) is developed using a developer to form a first insulating layer 20 on the first main surface 10a of the support substrate 10. The first insulating layer 20 has a recessed pattern 26 on a second main surface 20b opposite to the first main surface 20a of the support substrate 10. The recessed pattern 26 corresponds to a predetermined pattern of the negative photosensitive material layer 22 that has been exposed in the first exposure step (step S120). The recessed pattern 26 includes a recess 26a.

[0026] In this embodiment, the exposure amount I1 in the first exposure step (step S120) is greater than or equal to the exposure amount Isat, and the exposure amount I2 in the second exposure step (step S130) is greater than or equal to the threshold exposure amount Ith and less than the saturation exposure amount Isat. Therefore, the first main surface 20a of the first insulating layer 20 is in contact with the first main surface 10a of the support substrate 10 over its entire surface, and the recessed pattern 26 is formed on the second main surface 20b of the first insulating layer 20.

[0027] The thickness D1 of the first insulating layer 20 at the location where the recess 26a is not formed is, for example, 10 mm. Up to 20 To facilitate the removal of the portion of the first insulating layer 20 located below the recess 26a in the external connection terminal forming step (step S230) described later, it is preferable that the thickness D2 of the first insulating layer 20 at each location where the recess 26a is formed satisfies .

[0028] like Figure 9 As shown, in the second exposure step, the thickness D2 can be controlled by changing the exposure amount I2 (step S130). Figure 9 This shows that the thickness of the negative photosensitive material layer 22 is set to 13.7 mm. The exposure amount I1 in the first exposure step (step S120) is set to The relationship between exposure amount I2 and thickness D2 in the second exposure step (step S130) when the development step (step S140) is performed.

[0029] Meanwhile, when the first insulating layer 20 having a recessed pattern 26 on the second main surface 20b is formed of a positive photosensitive material, the thickness is 10. Up to 20 The positive photosensitive material has been exposed, therefore, the exposure amount of the light irradiating the positive photosensitive material is increased. To make the thickness D2 set to meet the requirements... Therefore, it is necessary to precisely control the exposure over a large exposure range. That is, when using positive photosensitive materials, controlling the residual film rate is difficult. As a result, it is difficult to form a first insulating layer 20 with a recessed pattern 26 on the second main surface 20b using a positive photosensitive material with high reproducibility.

[0030] In the first wiring layer formation step (step S150), as Figure 10 As shown, a first wiring layer 30 is formed on the second main surface 20b of the first insulating layer 20 based on the recessed pattern 26. The first wiring layer 30 is formed of copper (Cu), nickel (Ni), titanium (Ti), etc.

[0031] For example, the first wiring layer 30 is formed by electroplating. Specifically, such as... Figure 11 As shown, a seed layer 32 is first formed on the second main surface 20b of the first insulating layer 20 (step S151). The seed layer 32 is formed by sputtering copper, nickel, titanium, etc. Figure 11 In subsequent figures, the shaded lines of seed layer 32 have been omitted for ease of understanding.

[0032] Next, as Figure 12 As shown, a resist layer 34 having a pattern corresponding to the first wiring layer 30 is formed on the seed layer 32 (step S152). The resist layer 34 is formed by applying, exposing, and developing a known resist. Figure 13 As shown, an electroplated layer 36 is formed on the seed layer 32 by a known electroplating process. Then, the resist layer 34 is removed, and excess portions of the seed layer 32 exposed in the portion where the resist layer 34 has been removed are removed from the second main surface 20b of the first insulating layer 20 by etching (step S153). Thus, the first wiring layer 30 can be formed.

[0033] In the upper layer formation step (step S160), an upper insulating layer 42, an upper wiring layer 52, and an upper insulating layer 44 are sequentially formed on the first insulating layer 20 and the first wiring layer 30. For example... Figure 14 As shown, the upper insulating layer 42 is first formed (step S161). Specifically, a photosensitive insulating material layer (not shown) is formed on the first insulating layer 20 and the first wiring layer 30, then the photosensitive insulating material layer is exposed and developed to form the upper insulating layer 42. The material used to form the upper insulating layer 42 (photosensitive insulating material layer) can be the same as the material used to form the first insulating layer 20.

[0034] Next, the upper wiring layer 52 is formed through the same steps as steps S151 to S153 (step S162), and then the upper insulating layer 44 is further formed (step S163). Similar to the upper insulating layer 42, a photosensitive insulating material layer is formed, then exposed to the photosensitive insulating material layer, and developed to form the upper insulating layer 44. Therefore, the upper insulating layers 42 and 44, as well as the upper wiring layer 52, can be formed on the first insulating layer 20 and the first wiring layer 30. The material used to form the upper insulating layer 44 (photosensitive insulating material layer) can be the same as the material used to form the first insulating layer 20 or the upper insulating layer 42.

[0035] In the terminal protective layer forming step (step S170), as Figure 15As shown, a terminal protection layer 54 is formed that is connected to the upper wiring layer 52. Specifically, the terminal protection layer 54 is formed by electroless Ni immersion gold (ENIG) treatment, electroless Ni electroless palladium immersion gold (ENEPIG) treatment, etc.

[0036] In the chip connection terminal forming step (step S180), a chip connection terminal 60 is formed to be connected to the terminal protection layer 54. The chip connection terminal 60 is formed by solder using known methods.

[0037] In the mounting step (step S190), each of the terminals 202 of the semiconductor chip 200 is connected to each of the chip connection terminals 60, thereby mounting the semiconductor chip 200 onto the upper insulating layer 44. Specifically, the semiconductor chip 200 is positioned on the upper insulating layer 44, and then the terminals 202 of the semiconductor chip 200 are soldered to the chip connection terminals 60, for example, by reflow soldering, to mount the semiconductor chip 200 onto the upper insulating layer 44.

[0038] In the molding step (step S210), as Figure 16 As shown, a molding resin layer 210 is formed covering the main surface 44a of the semiconductor chip 200 and the upper insulating layer 44. In one example, the molding resin layer 210 is formed of epoxy resin.

[0039] In the separation step (step S220), light L1, which is to be absorbed by the first insulating layer 20, is irradiated from the second main surface 10b side of the support substrate 10 towards the first insulating layer 20, so as to separate the first insulating layer 20 from the support substrate 10. Figure 17 Specifically, such as Figure 18 As shown, while scanning with laser L1, the first insulating layer 20 is separated from the support substrate 10 by laser ablation, in which laser L1 (e.g., wavelength 355 nm) to be absorbed by the first insulating layer 20 is irradiated onto the first insulating layer 20 from the second main surface 10b side of the support substrate 10. During laser ablation, the interface between the support substrate 10 (first main surface 10a) and the first insulating layer 20 (first main surface 20a) is ablated by laser L1, thereby separating the first insulating layer 20 from the support substrate 10.

[0040] In this embodiment, the first main surface 20a of the first insulating layer 20 is in contact with the first main surface 10a of the support substrate 10 over its entire surface. Since the first insulating layer 20 undergoes ablation at low laser energy, it can be easily separated from the support substrate 10. Furthermore, since a release layer for separating the first insulating layer 20 from the support substrate 10 is not required, manufacturing costs can be reduced.

[0041] On the other hand, such as Figure 19 As shown, in the structure where the first main surface 10a of the support substrate 10 contacts the first insulating layer 20 and the first wiring layer 30 (hereinafter referred to as the comparative example), interfaces exist between the support substrate 10 and the first insulating layer 20, and between the support substrate 10 and the first wiring layer 30. At the interface where the first wiring layer 30 is directly formed on the support substrate 10, the first wiring layer 30 and the support substrate 10 are firmly adhered to each other. As described above, the interface between the support substrate 10 and the first insulating layer 20 can be separated by low laser energy, while the interface between the support substrate 10 and the first wiring layer 30 is difficult to separate by low laser energy. High laser energy is required to separate the first wiring layer 30 from the support substrate 10. When the interface between the support substrate 10 and the first insulating layer 20 and the interface between the support substrate 10 and the first wiring layer 30 are separated by high laser energy, significant damage occurs at the interface between the support substrate 10 and the first insulating layer 20. Therefore, it is difficult to separate the first insulating layer 20 and the first wiring layer 30 from the support substrate 10 by laser peeling. Note that in Figure 19 The layer above the upper insulating layer 42 is omitted.

[0042] In the external connection terminal forming step (step S230), at least a portion of each of the first wiring layers 30 is exposed from the first insulating layer 20 to form an external connection terminal 70 to be connected to the exposed first wiring layer 30. Specifically, as Figure 20 As shown, for example, a portion of the first insulating layer 20 is removed from the first main surface 20a side by oxygen ashing, exposing the first wiring layer 30 (step S231). Then, an external connection terminal 70 to be connected to the first wiring layer 30 is formed (step S232). The external connection terminal 70 is formed by solder using known methods.

[0043] The redistribution layer 100 can be manufactured as described above. The manufacturing method of the redistribution layer 100 in this embodiment corresponds to the manufacturing method of the semiconductor device 300.

[0044] As described above, a first insulating layer 20 having a recessed pattern 26 on the second main surface 20b is formed such that the first main surface 20a contacts the first main surface 10a of the support substrate 10 over its entire surface. Therefore, the manufacturing method of the redistribution layer 100 allows for easy manufacturing of the redistribution layer 100 while reducing manufacturing costs.

[0045] Example 2 In the first exposure step (step S120) of Embodiment 1, the negative photosensitive material layer 22 is exposed from the negative photosensitive material layer 22 side using a mask M. The negative photosensitive material layer 22 can be exposed from the second main surface 10b side of the support substrate 10 using a mask M.

[0046] Except for the first exposure step (step S120), the manufacturing method of the redistribution layer 100 in this embodiment is the same as the manufacturing method of the redistribution layer 100 in Embodiment 1. Here, the first exposure step (step S120) of this embodiment will be described.

[0047] In the first exposure step (step S120) of this embodiment, as follows Figure 21 As shown, the negative photosensitive material layer 22 formed on the first main surface 10a of the support substrate 10 is exposed to the exposure light ExL1 from the second main surface 10b side of the support substrate 10 using a mask M in a predetermined pattern. Similar to Example 1, the exposure amount I1 is preferably greater than or equal to the saturation exposure amount Isat (the exposure amount that saturates the residual film rate).

[0048] In this embodiment, a first insulating layer 20 having a recessed pattern 26 on the second main surface 20b is formed such that the first main surface 20a contacts the first main surface 10a of the support substrate 10 over its entire surface. Therefore, the method of manufacturing the redistribution layer 100 allows for easy manufacturing of the redistribution layer 100 while reducing manufacturing costs.

[0049] Example 3 In Embodiment 1, the redistribution layer 100 is manufactured with a semiconductor chip 200 mounted thereon. The redistribution layer 100 includes a terminal protection layer 54, chip connection terminals 60, and external connection terminals 70.

[0050] The redistribution layer 100 does not necessarily need to be manufactured with a semiconductor chip 200 mounted on it. In addition, the redistribution layer 100 does not necessarily need to include a terminal protection layer 54, a chip connection terminal 60, and an external connection terminal 70.

[0051] like Figure 22As shown, the redistribution layer 100 of this embodiment does not include the terminal protection layer 54, the chip connection terminal 60, and the external connection terminal 70. Except that the redistribution layer 100 does not include the terminal protection layer 54, the chip connection terminal 60, and the external connection terminal 70, and the first wiring layer 30 is not exposed from the first insulating layer 20, the structure of the redistribution layer 100 of this embodiment is the same as that of the redistribution layer 100 of Embodiment 1.

[0052] Next, the manufacturing method of the redistribution layer 100 in this embodiment will be described. Figure 23 This is a flowchart illustrating a method for manufacturing the redistribution layer 100 of this embodiment. The method for manufacturing the redistribution layer 100 of this embodiment includes a photosensitive layer formation step (step S110), a first exposure step (step S120), a second exposure step (step S130), a development step (step S140), a first wiring layer formation step (step S150), an upper layer formation step (step S160), and a separation step (step S220). Each step in this embodiment is the same as in Embodiment 1.

[0053] In this embodiment, a first insulating layer 20 having a recessed pattern 26 on the second main surface 20b is formed such that the first main surface 20a contacts the first main surface 10a of the support substrate 10 over its entire surface. Therefore, the method of manufacturing the redistribution layer 100 allows for easy manufacturing of the redistribution layer 100 while reducing manufacturing costs.

[0054] In the redistribution layer 100 of this embodiment, at least a portion of each of the first wiring layers 30 may be exposed from the first insulating layer 20 by removing a portion of the first insulating layer 20 from the first main surface 20a side.

[0055] Modify Example The above embodiments can be modified in various ways within the spirit of this disclosure.

[0056] For example, the seed layer 32 formed in the first wiring layer formation step (step S150) can be formed by a single layer or by multiple layers.

[0057] In this embodiment, after the photosensitive layer formation step (step S110), the negative photosensitive material layer 22 is exposed in the order of a first exposure step (step S120) and a second exposure step (step S130). In the method for manufacturing the redistribution layer 100, the negative photosensitive material layer 22 can be exposed in the order of a second exposure step (step S130) and a first exposure step (step S120) after the photosensitive layer formation step (step S110).

[0058] In the second exposure step (step S130) of the embodiment, the support substrate 10 is oriented upward on the paper so that the negative photosensitive material layer 22 is exposed to the entire surface of the second main surface 10b of the support substrate 10 using exposure light ExL2. Figure 7 In the second exposure step (step S130), as follows: Figure 24 As shown, the support substrate 10 can also be oriented downwards on the paper so that the negative photosensitive material layer 22 can be exposed to the entire surface of the support substrate 10 from the second main surface 10b side using exposure light ExL2.

[0059] In the second exposure step (step S130) of the embodiment, the exposure amount I2 used to expose the negative photosensitive material layer 22 is preferably a smaller exposure amount (close to the threshold exposure amount Ith) within the range of being greater than or equal to the threshold exposure amount Ith and less than the saturation exposure amount Isat. This reduces the exposure intensity, thus allowing the residual film rate to be easily controlled by changing the exposure time, thereby improving time controllability.

[0060] The redistribution layer 100 in this embodiment includes an upper wiring layer 52 and a terminal protection layer 54. For example... Figure 25 As shown, the redistribution layer 100 can be formed from a first insulating layer 20, a first wiring layer 30, and an upper insulating layer 42. In this case, the manufacturing method of the redistribution layer 100 includes a photosensitive layer formation step (step S110), a first exposure step (step S120), a second exposure step (step S130), a development step (step S140), a first wiring layer formation step (step S150), a step of forming the upper insulating layer 42 (step S161), and a separation step (step S220).

[0061] The redistribution layer 100 may include two or more upper wiring layers.

[0062] Furthermore, the redistribution layer 100 may be formed of a first insulating layer 20 and a first wiring layer 30.

[0063] For illustrative purposes, some exemplary embodiments have been described above. While specific embodiments have been given in the preceding discussion, those skilled in the art will recognize that changes in form and detail may be made without departing from the broader spirit and scope of the invention. Therefore, the specification and drawings are to be considered illustrative rather than restrictive. Consequently, this detailed description is not limiting, and the scope of the invention is defined only by the appended claims and all their equivalents.

Claims

1. A method for manufacturing a redistribution layer, comprising: In the photosensitive layer formation step, a negative photosensitive material layer is formed on the first main surface of the light-transmitting support substrate; The first exposure step involves exposing a negative photosensitive material layer formed on the first main surface of the support substrate in a predetermined pattern. In the second exposure step, the negative photosensitive material layer formed on the first main surface of the support substrate is exposed to the entire surface of the negative photosensitive material layer from the second main surface side opposite to the first main surface of the support substrate. The developing step develops the negative photosensitive material layer exposed in the first exposure step and the second exposure step to form a first insulating layer on the first main surface of the support substrate. The first insulating layer has a recessed pattern on the second main surface of the first insulating layer that corresponds to the predetermined pattern. The second main surface of the first insulating layer is opposite to the first main surface of the first insulating layer that is opposite to the first main surface of the support substrate. The first wiring layer forming step involves forming a first wiring layer on the second main surface of the first insulating layer based on the recessed pattern. as well as In the separation step, light to be absorbed by the first insulating layer is irradiated from the second main surface side of the support substrate onto the first insulating layer, thereby separating the first insulating layer on which the first wiring layer is formed from the support substrate.

2. The method for manufacturing the redistribution layer according to claim 1, wherein... In the first exposure step, the negative photosensitive material layer formed on the first main surface of the support substrate is exposed to an exposure amount greater than or equal to the exposure amount that saturates the residual film rate, according to the exposure sensitivity curve representing the residual film rate after development relative to the exposure amount of the negative photosensitive material layer. In the second exposure step, the negative photosensitive material layer formed on the first main surface of the support substrate is exposed to an exposure amount greater than that which makes the residual film rate greater than zero and less than that which saturates the residual film rate, according to the exposure sensitivity curve.

3. The method for manufacturing the redistribution layer according to claim 1, wherein... In the first exposure step, the negative photosensitive material layer formed on the first main surface of the support substrate is exposed in the predetermined pattern from the negative photosensitive material layer side.

4. The method for manufacturing the redistribution layer according to claim 1, wherein... In the first exposure step, the negative photosensitive material layer formed on the first main surface of the support substrate is exposed in the predetermined pattern from the second main surface side of the support substrate.

5. The method for manufacturing the redistribution layer according to claim 1, further comprising: In the upper layer formation step, an upper insulating layer and an upper wiring layer are sequentially formed on the first wiring layer, and the upper wiring layer is connected to the first wiring layer.

6. The method for manufacturing the redistribution layer according to claim 5, further comprising: Installation steps: Install the semiconductor chip connected to the upper wiring layer.

7. The method for manufacturing the redistribution layer according to any one of claims 1 to 6, further comprising: The external connection terminal forming step involves exposing at least a portion of the first wiring layer from the first insulating layer separated from the support substrate, and forming an external connection terminal to be connected to the exposed portion of the first wiring layer.

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