An embedded MCS structure semiconductor and a preparation method thereof

Abstract

The application discloses an embedded MCS structure semiconductor and a preparation method thereof, and comprises the following steps: S1. adopting silicon nitride ceramic as a substrate, preparing an upper copper layer and a bottom copper layer through an AMB process, and forming a standard ceramic copper-clad plate; S2. performing pattern etching on the upper copper layer to form a chip pad and a stepped copper boss; S3. performing laser etching on a groove in the periphery of the stepped copper boss, filling the groove with silicon nitride ceramic slurry, and forming a local ceramic reinforcing layer after degassing and sintering; S4. performing planarization treatment on the substrate of the standard ceramic copper-clad plate to ensure the flatness of the stepped copper boss; S5. printing sintering solder on the surface of the stepped copper boss, mounting an SiC chip, and performing low-temperature pressure sintering; and S6. preparing a passivation layer and a solder resist layer, completing wire bonding and packaging, and obtaining a final device. The application improves the overall heat dissipation capacity of the device, greatly improves the reliability of the solder layer and the substrate interface, and is suitable for mass production.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor packaging technology, and specifically relates to an embedded MCS structure semiconductor and its fabrication method. Background Technology

[0002] The conventional AMB substrate used in existing technology is a planar copper-ceramic-copper three-layer structure, such as... Figure 1 As shown, the chip is directly mounted on the surface of the planar copper layer, resulting in a long heat flow path and high interface thermal resistance. At the same time, the thermal expansion coefficients of the copper layer and ceramic are significantly different. Under long-term high and low temperature cycling and power cycling, stress concentration is obvious, which can easily lead to solder layer fatigue, interface debonding, and even device failure. This results in defects such as long non-heat dissipation paths, high thermal resistance, insufficient thermal cycling reliability, large structural stress, complex processes, or high costs, making it difficult to meet the long-term reliable operation requirements of the new generation of SiC power devices under high temperature, high frequency, and high power density.

[0003] The existing technology 2 uses a mature and low-cost DBC substrate process, and commonly uses alumina or aluminum nitride ceramics. The structure mostly only thickens or etches the copper layer, without specifically reinforcing stress concentration areas. Although some solutions introduce ceramic auxiliary structures, the auxiliary structures often have thermal expansion mismatch with the main substrate, which exacerbates local stress. Moreover, it relies heavily on empirical design and lacks systematic simulation optimization of the thermo-mechanical coupling field, which makes it easy for microcracks to propagate and interface delamination to occur in actual service. It has limited thermal conductivity and low bending strength. Under high temperature and temperature cycling conditions, it is prone to problems such as ceramic cracking, copper layer warping, and interface delamination. It has complex processes, high sintering temperatures, poor compatibility with conventional AMB / DBC production lines, difficulty in controlling flatness, and low mass production yield. It cannot simultaneously achieve low thermal resistance, high reliability, and low cost for industrial applications. Summary of the Invention

[0004] Purpose of the invention: The purpose of this invention is to address the shortcomings of the prior art by providing an embedded MCS structure semiconductor and its fabrication method, which solves the problems of insufficient heat dissipation efficiency, high interface thermal resistance, large thermal cycling stress, easy delamination and cracking, poor process compatibility, and high cost of existing DBC, AMB, and conventional MCS substrates.

[0005] Technical solution: A method for fabricating an embedded MCS structure semiconductor, the fabrication steps are as follows: S1. Using silicon nitride ceramic as a substrate, an upper copper layer and a lower copper layer are prepared by the AMB process to form a standard ceramic copper-clad laminate; S2. Perform pattern etching on the upper copper layer to form chip pads and stepped copper bumps; S3. Laser-etch grooves around the stepped copper bosses, fill the grooves with silicon nitride ceramic slurry, and form a local ceramic reinforcement layer after debinding and sintering; S4. Planarize the substrate of the standard ceramic copper-clad laminate to ensure the flatness of the stepped copper bosses; S5. Print sintering solder on the surface of the stepped copper boss, mount the SiC chip and perform low-temperature pressure sintering; S6. Prepare passivation layer and solder mask layer, complete wire bonding and packaging to obtain the final device.

[0006] A further improvement of the present invention is that, in step S3, the temperature of the adhesive discharge is 200–500°C.

[0007] A further improvement of the present invention is that, in step S3, the sintering temperature is 700–1000°C.

[0008] A further improvement of the present invention is that, in step S2, the height of the stepped copper boss is 50-100 μm.

[0009] A further improvement of the present invention is that, in step S3, the local ceramic reinforcement layer and the silicon nitride ceramic form an integrated structure.

[0010] A further improvement of the present invention is that, in step S5, the SiC chip is mounted on the surface of the stepped copper boss by sintering nano-silver or nano-copper solder.

[0011] A further improvement of the present invention is that the solder layer thickness of the sintered nano-silver or nano-copper solder is 10–30 μm.

[0012] An embedded MCS structure semiconductor is disclosed using a method for fabricating an embedded MCS structure semiconductor, wherein an upper copper layer and stepped copper bumps are disposed on the top side of a silicon nitride ceramic, and a lower copper layer is disposed on the bottom side of the silicon nitride ceramic.

[0013] Compared with the prior art, the embedded MCS structure semiconductor and its fabrication method provided by the present invention achieve at least the following beneficial effects: 1. Compared to traditional planar DBC / AMB substrates, stepped copper bumps shorten the heat conduction path, reduce interface thermal resistance, improve the overall heat dissipation capacity of the device, and are more suitable for high power density SiC devices. 2. By locally enhancing the structure with ceramic reinforcement and optimizing thermal expansion matching, the locally enhanced ceramic layer can effectively buffer thermal stress, significantly improve the reliability of the interface between the solder layer and the substrate, maintain a high interface bonding strength, and extend the device life. 3. The process is compatible with existing AMB / DBC production lines, is simple to control, has a high yield, reduces production costs, and is suitable for large-scale industrial production; 4. The local ceramic reinforcement layer improves the rigidity of the substrate and reduces warping and deformation; the stepped copper boss structure shortens the interconnect distance, reduces parasitic inductance, and is more suitable for high-frequency and high-voltage switching conditions of SiC devices. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a traditional planar structure. Figure 2 A schematic diagram of the MCS structure of this invention.

[0015] Explanation of reference numerals in the attached figures: 1- Bottom copper layer; 2- Silicon nitride ceramic layer; 3- Top copper layer; 4- Stepped copper bumps; 5- Local ceramic reinforcement layer; 6- SiC chip. Detailed Implementation

[0016] Various exemplary embodiments of the present invention will now be described in detail. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0017] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0018] See Figure 2 A method for fabricating an embedded MCS structure semiconductor, comprising the following steps: S1. Using silicon nitride ceramic 2 as a substrate, an upper copper layer 3 and a lower copper layer 1 are prepared by AMB process to form a standard ceramic copper-clad laminate; S2. Perform pattern etching on the upper copper layer 3 to form chip pads and stepped copper bumps 4; S3. Laser-etched grooves are formed around the stepped copper boss 4. The grooves are filled with silicon nitride ceramic slurry, and after debinding and sintering, a local ceramic reinforcement layer 5 is formed. S4. The substrate of the standard ceramic copper-clad laminate is planarized to ensure the flatness of the stepped copper boss 4. S5. Print sintering solder on the surface of the stepped copper boss 4, mount the SiC chip 6 and perform low-temperature pressure sintering; S6. Prepare passivation layer and solder mask layer, complete wire bonding and packaging to obtain the final device.

[0019] In step S3, the temperature for debinding is 200–500°C, and the temperature for sintering is 700–1000°C.

[0020] In step S2, the height of the stepped copper boss 4 is 50-100 μm.

[0021] In step S3, the local ceramic reinforcement layer 5 and the silicon nitride ceramic 2 form an integrated structure.

[0022] In step S5, the SiC chip 6 is mounted on the surface of the stepped copper boss 4 by sintering nano-silver or nano-copper solder, and the overall structure has both low thermal resistance and high stress buffering capacity; the solder layer thickness of the sintered nano-silver or nano-copper solder is 10-30μm.

[0023] An embedded MCS structure semiconductor is disclosed using a method for fabricating an embedded MCS structure semiconductor. The upper copper layer 3 and the stepped copper protrusions 4 are disposed on the top side of the silicon nitride ceramic 2, and the bottom copper layer 1 is disposed on the bottom side of the silicon nitride ceramic 2. The heat flow path is sequentially SiC chip 6, stepped copper protrusions 4, silicon nitride ceramic 2, and bottom copper layer 1. The stepped copper protrusions 4 shorten the vertical heat flow path, thereby improving the overall heat dissipation capability of the device.

[0024] Compared to traditional planar DBC / AMB substrates, the stepped copper bumps 4 shorten the heat conduction path, reduce interface thermal resistance by more than 30%, and lower the chip junction temperature by 15-25°C under the same operating conditions, making it more suitable for high power density SiC devices. Thermal cycling reliability is significantly improved; the local ceramic reinforcement layer effectively buffers thermal stress, exhibiting no delamination or cracking after 1000 high and low temperature cycles at -40°C to 125°C, with an interface adhesion retention rate of ≥90%, and device lifespan more than double that of traditional structures. Mass production and cost advantages are significant; the process is fully compatible with existing AMB / DBC production lines, requiring no additional large equipment, and the overall cost is 10-15% lower than conventional AMB substrates, with a yield rate exceeding 95%, making it suitable for industrial mass production. Structural stability and high-frequency adaptability are good; the local ceramic reinforcement layer improves substrate rigidity, reducing warpage and deformation.

[0025] The specific embodiments described herein are merely illustrative of the spirit of the invention. Those skilled in the art to which this invention pertains may make various modifications or additions to the described specific embodiments or use similar methods to substitute them, without departing from the spirit of the invention or exceeding the scope defined by the appended claims.

Claims

1. A method for fabricating an embedded MCS structure semiconductor, characterized in that, The preparation steps are as follows: S1. Using silicon nitride ceramic (2) as the substrate, an upper copper layer (3) and a lower copper layer (1) are prepared by AMB process to form a standard ceramic copper-clad laminate; S2. The upper copper layer (3) is patterned by etching to form chip pads and stepped copper bumps (4). S3. Laser etching grooves are made around the stepped copper boss (4), the grooves are filled with silicon nitride ceramic slurry, and after debinding and sintering, a local ceramic reinforcement layer (5) is formed. S4. The substrate of the standard ceramic copper-clad laminate is planarized to ensure the flatness of the stepped copper boss (4); S5. Print sintered solder on the surface of the stepped copper boss (4), mount the SiC chip (6) and perform low-temperature pressure sintering; S6. Prepare passivation layer and solder mask layer, complete wire bonding and packaging to obtain the final device.

2. The method for fabricating an embedded MCS structure semiconductor according to claim 1, characterized in that, In step S3, the temperature for discharging the adhesive is 200–500°C.

3. The method for fabricating an embedded MCS structure semiconductor according to claim 1, characterized in that, In step S3, the sintering temperature is 700–1000°C.

4. The method for fabricating an embedded MCS structure semiconductor according to claim 1, characterized in that, In step S2, the height of the stepped copper boss (4) is 50-100 μm.

5. The method for fabricating an embedded MCS structure semiconductor according to claim 1, characterized in that, In step S3, the local ceramic reinforcement layer (5) and the silicon nitride ceramic (2) form an integrated structure.

6. The method for fabricating an embedded MCS structure semiconductor according to claim 1, characterized in that, In step S5, the SiC chip (6) is mounted on the surface of the stepped copper boss (4) by sintering nano-silver or nano-copper solder.

7. The method for fabricating an embedded MCS structure semiconductor according to claim 6, characterized in that, The solder layer thickness of the sintered nano-silver or nano-copper solder is 10–30 μm.

8. An embedded MCS structure semiconductor, characterized in that, The method for fabricating an embedded MCS structure semiconductor as described in claim 1 is used, wherein the upper copper layer (3) and the stepped copper protrusions (4) are disposed on the top side of the silicon nitride ceramic (2), and the lower copper layer (1) is disposed on the bottom side of the silicon nitride ceramic (2).

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