Semiconductor package structure and preparation method thereof, composite substrate

Abstract

The application provides a semiconductor packaging structure and a preparation method thereof, and a composite substrate. The preparation method of the semiconductor packaging structure comprises the following steps: providing a packaging substrate, forming a plurality of first conductive columns on one side of the packaging substrate; cutting the packaging substrate to form a plurality of substrate units; screening qualified substrate units and arranging the qualified substrate units on a temporary carrier; manufacturing a molding layer to cover the substrate units and fill the intervals between the first conductive columns, thereby forming a reconfigured substrate; and performing a planarization treatment to remove part of the molding layer, thereby exposing the first conductive columns and forming a composite substrate. By means of the screening and reconfiguration, unqualified substrate units are intercepted at the front end of the process, and the overall packaging yield is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging structure and its preparation method, and a composite substrate. Background Technology

[0002] Multi-chip 2.5D packaging is a key advanced packaging technology that breaks through the physical limits of single-chip packaging in the post-Moore's Law era, and it has been widely used in computing power chips such as AI accelerators, high-end GPUs, and network chips. Reducing the interposer layer and directly realizing multi-chip packaging through substrate technology can simplify the structure, save costs, and has advantages in signal conduction and reliability.

[0003] However, the overall packaging yield of current semiconductor packaging structures needs to be improved. Summary of the Invention

[0004] Based on this, this application provides a semiconductor packaging structure and its preparation method, as well as a composite substrate, which can improve the packaging yield.

[0005] In a first aspect, this application provides a method for fabricating a semiconductor package structure, comprising: providing a package substrate and forming a plurality of first conductive pillars on one side of the package substrate; cutting the package substrate to form a plurality of substrate units; screening the plurality of substrate units and selecting qualified substrate units; placing the selected plurality of substrate units on a temporary carrier; fabricating a molding layer that covers the plurality of substrate units and fills the gaps between the first conductive pillars to form a reconstructed substrate; planarizing the surface of the reconstructed substrate, removing at least a portion of the molding layer, exposing the first conductive pillars, and forming a composite substrate.

[0006] Optionally, the method further includes: A conductive connection structure is formed on the side of the composite substrate away from the temporary carrier, so that the conductive connection structure is electrically connected to the first conductive post.

[0007] Multiple functional chips are arranged on the side of the conductive connection structure away from the first conductive post.

[0008] A molding compound is formed, which encapsulates the functional chip.

[0009] Optionally, the selected substrate units are placed on a temporary carrier, including: On the temporary carrier, gaps are formed between adjacent substrate units.

[0010] Optionally, after forming the molding compound, the method further includes: The composite substrate is cut along the dicing lines to obtain multiple semiconductor package structures. The dicing lines correspond to the gaps, and the width of the dicing lines is smaller than the width of the gaps.

[0011] Remove the temporary carrier board.

[0012] Optionally, multiple substrate units may be screened, including: electrical performance testing of the substrate units.

[0013] Secondly, this application provides a composite substrate, including multiple substrate units, multiple first conductive pillars, and a molding layer. Adjacent substrate units have gaps between them, and the multiple first conductive pillars are located on one side of each substrate unit. The molding layer fills the gaps and covers the multiple substrate units, and also fills the spaces between the first conductive pillars, thus connecting the multiple substrate units into one unit. The end face of the first conductive pillar on the side away from the substrate unit is flush with the surface of the molding layer on the side away from the substrate unit.

[0014] Thirdly, this application provides a semiconductor packaging structure, including a substrate unit, a plurality of first conductive pillars, a molding portion, a conductive connection structure, and a functional chip. The plurality of first conductive pillars are located on one side of the substrate unit. The molding portion at least covers the sidewall of the substrate unit. The conductive connection structure is placed on the side of the substrate unit near the first conductive pillars and is electrically connected to the first conductive pillars. The functional chip is connected to the substrate unit through the conductive connection structure.

[0015] The end face of the first conductive post on the side away from the substrate unit is flush with the surface of the molding part on the side away from the substrate unit.

[0016] Optionally, the conductive connection structure includes a plurality of second conductive pillars, a bridging chip, and a second insulating layer. The second conductive pillars are at least partially located within the second insulating layer, and the bridging chip is at least partially located within the second insulating layer. The bridging chip electrically connects at least two functional chips.

[0017] Optionally, the diameter of the first conductive post is larger than the diameter of the second conductive post.

[0018] Optionally, at least two of the first conductive posts have different axial dimensions.

[0019] The semiconductor packaging structure fabrication method provided in this application first cuts and screens qualified substrate units, then molds, reconstructs, and planarizes them to form a composite substrate. This intercepts unqualified substrate units at the front end of the process, improving the overall packaging yield while retaining the high efficiency advantage of board-level packaging. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1This is a flowchart of the method for fabricating the semiconductor packaging structure in the embodiments of this application; Figure 2 This is a cross-sectional view of the packaging substrate in the embodiments of this application; Figure 3 This is a cross-sectional view of the semiconductor packaging structure during the fabrication process in the embodiments of this application; Figure 4 This is a cross-sectional view of the structure of the reconstructed substrate formed during the fabrication process of the semiconductor packaging structure in the embodiments of this application; Figure 5 This is a cross-sectional view of the composite substrate formed during the fabrication process of the semiconductor packaging structure in the embodiments of this application; Figure 6 This is a cross-sectional view of the semiconductor packaging structure during the fabrication process in the embodiments of this application; Figure 7 This is a cross-sectional view of the semiconductor packaging structure during the fabrication process in the embodiments of this application; Figure 8 This is a cross-sectional view of the semiconductor packaging structure during the fabrication process in the embodiments of this application; Figure 9 This is a cross-sectional view of the semiconductor packaging structure during the fabrication process in the embodiments of this application; Figure 10 This is a cross-sectional view of the semiconductor packaging structure in the embodiments of this application.

[0022] Marker explanation: 100. Semiconductor packaging structure; 10. Packaging substrate; 101. Substrate unit; 102. Gap; 103. Cutting channel; 11. Glass core board; 12. Conductive connection post; 13. Redundancy layer; 21. First conductive pillar; 22. Photoresist; 201. Seed layer; 30. Conductive connection structure; 31. Bridge chip; 32. Second conductive post; 33. Second insulating layer; 40. Molding layer; 41. Molding part; 50. Reconstructed substrate; 51. Composite substrate; 60. Functional chips; 70. Plastic sealant layer; 80. Conductive bumps; 90. Temporary carrier plate; 91. Temporary connecting layer. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0024] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0025] With the rapid development of high-performance computing, artificial intelligence, and other fields, higher demands are being placed on chip integration, interconnect bandwidth, and energy efficiency. 2.5D multi-chip packaging technology has become one of the key paths to overcome the physical limits of single-chip solutions. Among these, direct-to-board (DTSB) packaging simplifies the packaging structure, reduces material costs, and improves signal integrity and long-term reliability by eliminating the need for a large silicon interposer, thus attracting widespread attention from the industry. One related DTSB solution employs board-level packaging technology to achieve high throughput and incorporates warpage absorption structures on the substrate surface to improve flatness, thereby meeting the mounting requirements of high-density interconnect bridges and high-precision chips.

[0026] However, the inventors discovered that the relevant technical solutions suffer from low overall yield and high investment costs per unit capacity. The root cause lies in the fact that the entire packaging substrate is directly input into the subsequent processes, resulting in a limited yield of the substrate itself. Defective cells undergo the subsequent processes along with qualified cells, only to be rejected in the final testing, causing significant losses in process investment. Furthermore, when using glass substrates, their brittleness, low thermal conductivity, easy softening at high temperatures, and high resistivity further exacerbate the process difficulty and yield losses.

[0027] In view of this, embodiments of the first aspect of this application provide a method for fabricating a semiconductor packaging structure. (See reference...) Figure 1 The method for preparing the semiconductor package structure 100 includes steps S10 to S60.

[0028] Step S10 includes: providing a packaging substrate 10 and forming a plurality of first conductive pillars 21 on one side of the packaging substrate 10.

[0029] Specifically, refer to Figure 2 First, a packaging substrate 10 to be processed is provided. The packaging substrate 10 can be an ABF organic substrate or a glass substrate. Taking a glass substrate as an example, refer to... Figure 2 The packaging substrate 10 includes a glass core plate 11, conductive connecting posts 12 penetrating the glass core plate 11, and redistribution layers 13 located on the upper and lower surfaces of the glass core plate 11. The thickness of the glass core plate 11 can be selected according to the requirements of the packaging product. The conductive connecting posts 12 can be made of copper or tungsten and are formed by first laser drilling holes in the glass core plate 11 and then electroplating them.

[0030] Then, refer to Figure 3 Multiple first conductive pillars 21 are prepared on the upper surface of the packaging substrate 10.

[0031] First, a first sublayer and a second sublayer are sequentially deposited on the surface of the packaging substrate 10 using a physical vapor deposition process to form a seed layer 201. The first sublayer can be a titanium layer, serving as an adhesion layer to enhance the bonding between the seed layer 201 and the surface of the packaging substrate 10; the second sublayer can be a copper layer, serving as a conductive layer to provide a conductive path for subsequent electroplating to form the first conductive pillars 21. Next, photoresist 22 is spin-coated onto the seed layer 201, and an opening pattern is formed through exposure and development. The openings correspond to the areas where the first conductive pillars 21 will be formed. Then, copper material is filled into the openings through an electroplating process to form the first conductive pillars 21, with a height ranging from 15 micrometers to 50 micrometers. Finally, the photoresist 22 is removed using a wet stripper, and excess seed layer 201 is removed by wet etching. This results in multiple independent first conductive pillars 21 protruding from the surface of the packaging substrate 10, with gaps between adjacent first conductive pillars 21.

[0032] Step S20 includes cutting the packaging substrate 10 to form a plurality of substrate units 101.

[0033] After the first conductive post 21 is fabricated, the packaging substrate 10 is cut along a preset cutting path using a diamond blade cutter or a laser cutter, separating it into multiple independent substrate units 101. The size of each substrate unit 101 is determined according to the requirements of the final packaged product.

[0034] Step S30 includes: screening multiple substrate units 101 and selecting qualified substrate units 101.

[0035] Specifically, after cutting, each substrate unit 101 is subjected to electrical performance tests using automated testing equipment and a probe station to screen out qualified substrate units 101 that pass the tests. The electrical performance tests include: continuity testing of the conductive path formed by the first conductive post 21 and the bottom pad of the substrate, resistance measurement, and insulation testing between adjacent paths. Substrate units 101 that pass all tests are retained and proceed to the next process; substrate units 101 with defects such as short circuits, open circuits, or poor insulation are directly rejected. This step intercepts unqualified substrate units at the beginning of the process, avoiding waste of subsequent input.

[0036] Step S40 includes: setting the selected multiple substrate units 101 on a temporary carrier board 90.

[0037] Specifically, a temporary carrier plate 90 is provided, which can be made of glass, silicon, or stainless steel, to provide rigid support for subsequent processes. A temporary bonding layer 91 can be disposed on the surface of the temporary carrier plate 90, which can be made of thermal separation tape or optical separation tape to facilitate subsequent separation.

[0038] Multiple qualified substrate units 101 selected in step S30 are precisely mounted one by one onto the temporary carrier board 90 with the first conductive post 21 facing upwards through the temporary connection layer 91. During mounting, a certain distance is maintained between adjacent substrate units 101, forming a gap 102. The width of the gap 102 is greater than the width of the cutting track 103 used for subsequent finished product cutting.

[0039] Step S50 includes: fabricating a molding layer 40, which covers multiple substrate units 101 to form a reconstructed substrate 50.

[0040] Specifically, refer to Figure 4 Above the multiple substrate units 101 supported on the temporary carrier plate 90, a molding material is filled using compression molding or transfer molding processes. The molding material can be an epoxy molding compound, in which silica filler can be added to adjust the coefficient of thermal expansion and thermal conductivity. The molding material melts and flows under appropriate molding temperature conditions, filling the gaps 102 between the substrate units 101 and covering the upper surface and sidewalls of the substrate units 101, while also filling all the gaps between the first conductive pillars 21. After curing, a continuous molding layer 40 is formed. This molding layer 40 encapsulates and connects the dispersed multiple substrate units 101 into a single plate-like structure, forming the reconstructed substrate 50.

[0041] Step S60 includes: planarizing the surface of the reconstructed substrate 50, removing at least a portion of the molding layer 40, exposing the first conductive pillar 21, and forming a composite substrate 51.

[0042] Specifically, refer to Figure 5 The surface of the reconstructed substrate 50 away from the temporary carrier 90 is planarized. The planarization process can employ physical grinding or chemical mechanical polishing. By precisely controlling the grinding thickness, the surface molding layer 40 material is gradually removed until the top faces of all the first conductive pillars 21 are cleanly and completely exposed. After grinding, the exposed faces of the first conductive pillars 21 are substantially flush with the surface of the molding layer 40, forming a highly flat plane. This forms the composite substrate 51.

[0043] This application provides a method for fabricating a semiconductor package structure 100. By first cutting and screening substrate units 101, unqualified substrate units are excluded from subsequent processes, thus avoiding waste of materials and time in later stages. Simultaneously, the selected qualified substrate units 101 are rearranged, and a molding layer 40 is used to cover the substrate units 101 and directly fill the gaps between the first conductive pillars 21. Planarization processing makes the end faces of the first conductive pillars 21 flush with the surface of the molding layer 40, providing a flat surface for subsequent interconnect structure fabrication. The method for fabricating the semiconductor package structure 100 of this application can solve the problem of low substrate yield dragging down the overall package yield from the source, while retaining the high efficiency advantages of board-level packaging.

[0044] In some embodiments, the method for fabricating the semiconductor package structure 100 further includes steps S70 to S90.

[0045] Step S70 includes: forming a conductive connection structure 30 on the side of the composite substrate 51 away from the temporary carrier plate 90, so that the conductive connection structure 30 is electrically connected to the first conductive post 21.

[0046] Specifically, refer to Figure 6 , Figure 7 A conductive connection structure 30 is fabricated on the flat upper surface of the composite substrate 51. The conductive connection structure 30 is used to realize the electrical connection between the first conductive post 21 and the subsequently mounted functional chip 60, as well as the high-density interconnection between the functional chips 60. The fabrication of the conductive connection structure 30 includes fabricating a second conductive post 32, mounting a bridging chip 31, and forming a second insulating layer 33.

[0047] The fabrication process of the conductive connection structure 30 can be as follows: First, a titanium adhesion layer and a copper seed layer are deposited on the surface of the composite substrate 51 by sputtering; then, photoresist is coated and the opening pattern of the second conductive pillar 32 is formed by exposure and development, and copper is filled into the opening by electroplating; then, the photoresist and excess seed layer are removed; then, the bridging chip 31 is mounted to the corresponding pad by flip-chip bonding; subsequently, a second insulating layer 33 is formed by vacuum lamination or spin coating to cover the second conductive pillar 32 and the bridging chip 31; finally, planarization is performed by chemical mechanical polishing or physical grinding to expose the top end face of the second conductive pillar 32 and the connection end face of the bridging chip 31.

[0048] Step S80 includes: setting a plurality of functional chips 60 on the side of the conductive connection structure 30 away from the first conductive post 21.

[0049] Specifically, refer to Figure 8 Multiple functional chips 60 are disposed on the surface of the conductive connection structure 30. The functional chips 60 may be one or more of a graphics processor, a central processing unit, high-bandwidth memory, etc. The functional chips 60 are aligned with the exposed connection end faces of the conductive connection structure 30 through connection bumps on their surfaces, and can be electrically connected and mechanically fixed by a reflow soldering process.

[0050] Step S90 includes: forming a molding compound 70, which encapsulates the functional chip 60.

[0051] Specifically, after the functional chip 60 is mounted, a molding layer 70 is formed on the surface of the conductive connection structure 30 through a molding process. The molding layer 70 covers the functional chip 60 and can also fill the gaps at the bottom of the functional chip 60, providing physical protection for the functional chip 60.

[0052] The process involves fabricating conductive interconnect structures, mounting multiple chips, and finally packaging, all based on the composite substrate 51. Because the composite substrate 51 is reconstructed from selected qualified substrate units 101 and has a highly flat surface, the mounting yield of the conductive connection structure 30 and the functional chips 60 is significantly improved. The bridging chip 31 provides high-density interconnection between multiple functional chips 60, meeting the requirements for high-bandwidth inter-chip communication. The molding compound 70 provides complete protection for the entire packaging structure.

[0053] For ease of distinction, in this application, the packaging material covering the substrate unit 101 and constituting the composite substrate 51 is referred to as the "molding layer," and the packaging material that finally covers the functional chip 60 is referred to as the "molding layer." The molding layer 70 and the molding layer 40 may be made of the same or different materials.

[0054] In some embodiments, step S40, which involves setting the selected substrate units 101 on a temporary carrier plate 90, further includes forming gaps 102 between adjacent substrate units 101 on the temporary carrier plate 90.

[0055] Specifically, when multiple qualified substrate units 101 are selected and placed on the temporary carrier board 90, the placement position of the mounting equipment is controlled to maintain a preset spacing between adjacent substrate units 101, forming a gap 102. For example, the width of the gap 102 can be set to 1.5 to 5 times the width of the cutting path 103 to ensure that the cutting tool does not touch the sidewall of the substrate unit 101 during cutting. In step S50, the material of the molding layer 40 fills the gap 102, and after curing, adjacent substrate units 101 are separated by the molding material.

[0056] By pre-setting a gap 102 between adjacent substrate units 101 and limiting the cutting path 103 within the range of the gap 102, the cutting tool only cuts the molding material of the molding layer 40 during final cutting and separation, without contacting the body of the substrate unit 101. For glass substrate units, this avoids problems such as edge chipping and breakage caused by the tool directly cutting the glass, thus improving the cutting yield. The molding material is easier to cut than the substrate material, which reduces the wear of the cutting tool and extends the tool life.

[0057] In addition, the temporary carrier plate 90 can provide rigid support for subsequent molding and planarization processes, preventing warping during processing.

[0058] In some embodiments, after forming the molding layer 70 in step S90, the method for preparing the semiconductor package structure 100 further includes step S100.

[0059] Step S100 includes: cutting the composite substrate 51 along the dicing groove 103 to obtain multiple semiconductor package structures 100. The dicing groove 103 corresponds to the gap 102, and the width of the dicing groove 103 is smaller than the width of the gap 102. Finally, the temporary carrier board 90 is removed.

[0060] Specifically, refer to Figure 9After the formation of the plastic encapsulation layer 70 is completed, the entire panel is cut and separated along the pre-planned dicing streets 103. Before dicing, the alignment marks on the composite substrate 51 can be identified by an image recognition system to determine the precise position of the dicing streets 103. The position of the dicing street 103 spatially corresponds to the gap 102 between adjacent substrate units 101 during reconfiguration, that is, the dicing street 103 is located directly above or directly below the gap 102. The width of the gap 102 is a first width W1. The width of the dicing street 103 is a second width W2, where W2<W1. During dicing, for example, a diamond blade dicing saw is used, and the blade thickness matches the width of the dicing street 103. The blade travels along the dicing street 103, and its dicing area is always limited within the range of the gap 102, without touching the substrate unit 101 on both sides. After the dicing is completed, a plurality of independent semiconductor packaging structures 100 are obtained. After that, the temporary connection layer 91 is debonded by means of heating, illumination or the like, and the temporary carrier 90 is removed.

[0061] Herein, through the positional correspondence and dimensional relationship between the dicing streets 103 and the gaps 102, it is ensured that the cutter only acts on the molding material of the molding layer 40 during the dicing process, without cutting the substrate units 101, thereby reducing the risk of chipping during the dicing process of the glass substrate. In each diced semiconductor packaging structure 100, the four side surfaces of the substrate unit 101 each retain a molding portion 41 with a certain thickness as a protective layer, which improves the mechanical shock resistance of the product during subsequent transportation, testing and surface mounting processes.

[0062] In some embodiments, the step of screening the plurality of substrate units 101 in step S30 specifically includes: performing an electrical performance test on the substrate units 101.

[0063] Exemplarily, the specific manner of screening the substrate units 101 is to perform an electrical performance test. The test equipment may adopt an automatic probe station combined with a semiconductor parameter analyzer. The items of the electrical performance test may include: first, a continuity test, which detects whether each electrical path is conductive; second, a resistance test, which accurately measures the resistance value of each path through a four-wire method, and if the resistance value exceeds a preset qualified range, the substrate unit is determined to be unqualified; third, an insulation test, which applies a DC voltage between two adjacent electrical paths to measure the leakage current, and if the leakage current exceeds a preset threshold, the substrate unit is determined to be unqualified. Substrate units 101 that pass all test items enter the subsequent reconfiguration process; substrate units 101 that fail any test item are rejected.

[0064] By employing electrical performance testing to screen the substrate units 101, defective units with various electrical defects can be accurately and efficiently identified. This testing method directly reflects the functional status of the substrate units 101, and compared to indirect methods such as visual inspection, its screening accuracy is higher, effectively avoiding missed detections. Furthermore, the electrical testing is fast, completing the testing of a single unit within seconds, suitable for the cycle time requirements of mass production.

[0065] An embodiment of the second aspect of this application provides a composite substrate 51. (See reference...) Figure 5 The composite substrate 51 includes a plurality of substrate units 101 and a plurality of first conductive pillars 21, and also includes a molding layer 40. The first conductive pillars 21 are located on one side of the substrate units 101. The molding layer 40 at least covers the plurality of substrate units 101 and fills the gaps between the first conductive pillars 21, thereby connecting the plurality of substrate units 101 into one unit. The end face of the first conductive pillar 21 on the side away from the substrate units 101 is flush with the surface of the molding layer 40 on the side away from the substrate units 101.

[0066] Specifically, the composite substrate 51 includes multiple substrate units 101 as core components. All of these substrate units 101 are qualified units that have passed electrical performance testing (i.e., qualified substrate units 101), and they are free from defects such as short circuits and open circuits. Each substrate unit 101 has multiple protruding first conductive pillars 21 on one side surface. The bottom of each first conductive pillar 21 is electrically connected to a conductive connection pillar 12 or a redistribution layer 13 inside the substrate unit 101. The original air gaps between the first conductive pillars 21 have been filled with the material of the molding layer 40.

[0067] A molding layer 40 is disposed around each substrate unit 101. The molding layer 40 may be made of epoxy molding compound. The molding layer 40 at least fills the gap 102 between adjacent substrate units 101, covers the sidewalls of each substrate unit 101, and fills the gaps between all the first conductive posts 21 on each substrate unit 101. The molding layer 40 encapsulates all substrate units 101 and mechanically connects them into a single plate-like structure.

[0068] The surface of the composite substrate 51 is highly flat. The end face of the first conductive post 21 away from the substrate unit 101 is substantially flush with the surface of the molding layer 40 away from the substrate unit 101, forming a highly flat plane. This coplanarity is achieved through the aforementioned planarization process. The molding layer 40 serves as both the covering material and adhesive material for the substrate unit 101, as well as the electrical isolation medium and planarization reference medium between the first conductive posts 21.

[0069] The composite substrate 51 provided in this embodiment, being reconstructed from selected qualified substrate units 101, improves the overall functional yield and solves the problem of low overall yield caused by low substrate material yield in current direct-packing solutions. Simultaneously, the molding layer 40 serves multiple purposes, achieving both board-level reconstruction of the substrate units 101 and directly filling the gaps between the first conductive pillars 21 to form a flat surface. This eliminates the need for a separate insulating layer fabrication step in traditional solutions, simplifying the process. The flat surface provides an excellent foundation for the subsequent high-density interconnect bridges and high-precision mounting of functional chips.

[0070] An embodiment of a third aspect of this application provides a semiconductor package structure 100. (See reference...) Figure 10 The semiconductor packaging structure 100 includes a substrate unit 101, a plurality of first conductive pillars 21, a molding part 41, a conductive connection structure 30, and a functional chip 60.

[0071] The first conductive post 21 is located on one side of the substrate unit 101. The molding portion 41 at least covers the sidewall of the substrate unit 101. A conductive connection structure 30 is disposed on the side of the substrate unit 101 near the first conductive post 21 and is electrically connected to the first conductive post 21. The functional chip 60 is connected to the substrate unit 101 through the conductive connection structure 30. The end face of the first conductive post 21 away from the substrate unit 101 is flush with the surface of the molding portion 41 away from the substrate unit 101.

[0072] Specifically, the substrate unit 101 is a single packaged substrate unit that has passed electrical testing, and it contains conductive connection pillars 12 for signal transmission and a redistribution layer 13. The substrate unit 101 can be made of ABF organic substrate or glass substrate.

[0073] The first conductive pillars 21 are disposed on the upper surface of the substrate unit 101 and are multiple independent protruding metal pillars, mainly made of copper. Adjacent first conductive pillars 21 are filled and separated by the molding material of the molding part 41.

[0074] At least two of the first conductive pillars 21 have different axial dimensions. Here, "axial dimension" refers to the height of the first conductive pillar 21 in the direction perpendicular to the surface of the substrate unit 101. For example, the height of the first conductive pillar 21 located in the central region of the substrate unit 101 can be set to 20 micrometers, while the height of the first conductive pillar 21 located in the edge region can be set to 25 micrometers. Alternatively, depending on the function, the first conductive pillar 21 used for transmitting high-speed signals may have a smaller height, while the first conductive pillar 21 used for providing power or grounding loops may have a larger height. The first conductive pillars 21 with different heights can be formed through two photolithography and electroplating processes: first, electroplating of the first set of conductive pillars is completed to achieve the first height; then, photoresist is applied again, and only the openings in the areas requiring increased height are subjected to a second electroplating process, thereby achieving the height difference.

[0075] The molding portion 41 is the part of the aforementioned molding layer 40 that remains in each semiconductor package structure 100 after cutting and separation. The molding portion 41 at least covers all sidewalls of the substrate unit 101 and fills all gaps between the first conductive pillars 21. The upper surface of the molding portion 41 is flush with the end faces of the first conductive pillars 21. When the substrate unit 101 is made of glass, the covering layer formed by the molding portion 41 on the sidewalls can effectively prevent crack propagation and breakage at the glass edges.

[0076] The conductive connection structure 30 is disposed above the substrate unit 101, located above the exposed end face of the first conductive post 21. The conductive connection structure 30 internally includes a second conductive post 32, a bridging chip 31, and a second insulating layer 33. The bottom surface of the conductive connection structure 30 is in direct contact with and electrically connected to the end face of the first conductive post 21, and its upper surface provides pads for connection with the functional chip 60.

[0077] The functional chip 60 is electrically connected to the substrate unit 101 through the conductive connection structure 30. The functional chip 60 may be a graphics processor, a central processing unit, high-bandwidth memory, or other application-specific integrated circuit.

[0078] The semiconductor package structure 100 also includes a molding compound 70, which is disposed on the side of the conductive connection structure 30 away from the substrate unit 101. The molding compound 70 encapsulates all the functional chips 60.

[0079] The semiconductor packaging structure 100 provided in this application embodiment has a sidewall of the substrate unit 101 covered by a molding portion 41, providing effective edge protection. The end face of the first conductive post 21 is flush with the surface of the molding portion 41, providing a highly flat reference surface for the fabrication of the conductive connection structure 30.

[0080] Furthermore, by setting first conductive pillars 21 with different axial dimensions, the total thickness variation (TTV) during the planarization process can be balanced. During the grinding process of the board-level reconstruction substrate 50, due to differences in the arrangement density of the substrate units 101 or the flow characteristics of the molding layer 40, the grinding rate of different areas of the substrate may be inconsistent, which may easily lead to over-grinding or failure to expose the first conductive pillars 21 in some areas. By presetting first conductive pillars 21 with different heights in different areas, the difference in grinding rate can be compensated, so that the first conductive pillars 21 in each area can be reliably exposed after planarization and the end face height tends to be consistent, thereby achieving uniform surface flatness over a larger area, which is beneficial to improving the mounting yield of subsequent high-density interconnects.

[0081] Furthermore, the semiconductor packaging structure 100 provided in this application embodiment also has the following effects: the molding portion 41 covers the sidewall of the substrate unit 101 and forms a molding material layer of a certain thickness above the substrate unit 101. This structure provides effective mechanical buffer protection for the glass substrate unit, reducing the risk of glass breakage due to external impact during subsequent assembly and use; at the same time, by adding high thermal conductivity filler to the molding material, an auxiliary heat dissipation path can be constructed around the glass substrate unit, improving the heat dissipation problem caused by the low thermal conductivity of the glass. The molding layer 70 encapsulates the functional chip 60 and the conductive connection structure 30 as a whole, further enhancing the mechanical strength and reliability of the packaging structure.

[0082] In some embodiments, reference Figure 7 , Figure 10 The conductive connection structure 30 includes a plurality of second conductive pillars 32, a bridging chip 31, and a second insulating layer 33. The second conductive pillars 32 are at least partially located within the second insulating layer 33, and the bridging chip 31 is at least partially located within the second insulating layer 33. The bridging chip 31 is electrically connected to at least two functional chips 60.

[0083] Specifically, the conductive connection structure 30 is an interconnect layer disposed between the substrate unit 101 and the functional chip 60. Multiple second conductive pillars 32 are distributed within the conductive connection structure 30. The bottom of each second conductive pillar 32 is in direct contact and electrically connected to the exposed end face of the first conductive pillar 21 below it, while the top of each second conductive pillar 32 is exposed on the upper surface of the conductive connection structure 30, providing connection pads for mounting the functional chip 60. The bridging chip 31 is a small-sized, high-density interconnect chip with finely fabricated multilayer metal interconnect lines inside, and its surface has multiple high-density arranged micro-connection terminals. The bridging chip 31 is disposed within the conductive connection structure 30, with its upper surface exposed on the upper surface of the conductive connection structure 30. The bridging chip 31 provides a high-density, high-bandwidth interconnect channel between two or more functional chips 60. A second insulating layer 33 is disposed within the conductive connection structure 30, covering the second conductive pillars 32 and the bridging chip 31, to provide electrical isolation and mechanical support.

[0084] The combination of the second conductive post 32 in the conductive connection structure 30 and the bridging chip 31 simultaneously achieves both vertical interconnection and horizontal high-density interconnection. The bridging chip 31 builds a local high-density interconnect bridge between adjacent functional chips 60, solving the problem that the wiring capability of traditional substrates is insufficient to support a large amount of data exchange between multiple chips, shortening the signal transmission distance between chips, and reducing transmission delay and power consumption.

[0085] In some embodiments, the diameter of the first conductive post 21 is larger than the diameter of the second conductive post 32.

[0086] Specifically, the diameter of the first conductive post 21 is designed to be larger than the diameter of the second conductive post 32. The first conductive post 21 is located on the upper surface of the substrate unit 101, and its bottom is electrically connected to the redistribution layer 13 inside the substrate unit 101. It requires a larger contact area to ensure connection reliability and carry a larger current, hence its relatively large diameter. The second conductive post 32 is located within the conductive connection structure 30 and is connected to the functional chip 60. Because the interconnection spacing of the functional chip 60 is more compact, the second conductive post 32 is required to have a smaller diameter to achieve high-density wiring.

[0087] The diameter of the first conductive post 21 is larger than that of the second conductive post 32, achieving functional division and performance optimization. The thicker first conductive post 21 forms a reliable electrical connection with the internal circuitry of the substrate unit 101, providing lower contact resistance and better current carrying capacity. The thinner second conductive post 32 matches the high-density interconnect spacing of the functional chip 60, which is beneficial for realizing more interconnect ports within a limited chip area, meeting the needs of high-density multi-chip integration.

[0088] In some embodiments, the bridging chip 31 includes a silicon bridge or a glass bridge.

[0089] Specifically, the bridging chip 31 can be either a silicon bridge or a glass bridge. A silicon bridge is a chip formed by fabricating multiple layers of fine copper interconnects on a single-crystal silicon wafer as a substrate through a front-end process, and can integrate passive devices such as decoupling capacitors. A glass bridge is a chip formed by fabricating fine copper interconnects on a glass substrate through a semi-additive process, and has a lower dielectric constant and dielectric loss, making it suitable for high-frequency signal transmission.

[0090] The semiconductor package structure 100 also includes a plurality of conductive bumps 80. The conductive bumps 80 are disposed on the side of the substrate unit 101 away from the first conductive post 21 and are electrically connected to the redistribution layer 13 inside the substrate unit 101 to realize the electrical connection between the semiconductor package structure 100 and the external circuit.

[0091] The semiconductor packaging structure 100 and its fabrication method provided in this application can be widely used in various electronic devices. For example, it can be used in AI accelerator cards and high-performance servers, utilizing the high-density interconnect channels provided by the bridge chip 31 to meet the massive data exchange needs between the graphics processor and high-bandwidth memory, shortening the signal transmission path to reduce power consumption; it can also be used in large-scale antenna arrays of 5G / 6G communication base stations, where the electrical insulation and low dielectric constant of the glass substrate can reduce high-frequency signal transmission loss; it can also be used in the packaging of MEMS devices, providing stable mechanical support and electrical insulation for microelectromechanical structures, reducing parasitic capacitance to improve device sensitivity and response speed.

[0092] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0093] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the technical concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor packaging structure, characterized in that, The method includes: A packaging substrate is provided, and a plurality of first conductive pillars are formed on one side of the packaging substrate; The packaging substrate is cut to form multiple substrate units; The multiple substrate units are screened to select qualified substrate units; The selected substrate units are placed on a temporary carrier plate; A molding layer is fabricated, which covers multiple substrate units and fills the gaps between the first conductive pillars to form a reconstructed substrate; The surface of the reconstructed substrate is planarized to remove at least a portion of the molding layer, exposing the first conductive pillar to form a composite substrate.

2. The method for fabricating a semiconductor packaging structure according to claim 1, characterized in that, The method further includes: A conductive connection structure is formed on the side of the composite substrate away from the temporary carrier plate, so that the conductive connection structure is electrically connected to the first conductive pillar; Multiple functional chips are disposed on the side of the conductive connection structure away from the first conductive post; A molding compound is formed, which encapsulates the functional chip.

3. The method for preparing a semiconductor packaging structure according to claim 2, characterized in that, The step of setting the selected substrate units on a temporary carrier plate includes: On the temporary carrier plate, gaps are formed between adjacent substrate units.

4. The method for preparing a semiconductor packaging structure according to claim 3, characterized in that, After forming the molding layer, the method further includes: The composite substrate is cut along the dicing groove to obtain multiple semiconductor package structures; wherein the dicing groove corresponds to the gap, and the width of the dicing groove is smaller than the width of the gap; Remove the temporary carrier plate.

5. The method for fabricating a semiconductor packaging structure according to claim 1, characterized in that, The screening of the plurality of substrate units includes: performing electrical performance tests on the substrate units.

6. A composite substrate, characterized in that, include: Multiple substrate units, with gaps between adjacent substrate units; Multiple first conductive pillars are located on one side of the substrate unit; A molding layer fills the gaps and covers the plurality of substrate units, and fills the gaps between the first conductive pillars, thereby connecting the plurality of substrate units into one unit; Wherein, the end face of the first conductive post on the side away from the substrate unit is flush with the surface of the molding layer on the side away from the substrate unit.

7. A semiconductor packaging structure, characterized in that, include: Substrate unit; Multiple first conductive pillars are located on one side of the substrate unit; The molding portion at least covers the sidewalls of the substrate unit; A conductive connection structure is disposed on the side of the substrate unit near the first conductive post and is electrically connected to the first conductive post; The functional chip is connected to the substrate unit through the conductive connection structure; Wherein, the end face of the first conductive post on the side away from the substrate unit is flush with the surface of the molded part on the side away from the substrate unit.

8. The semiconductor packaging structure according to claim 7, characterized in that, The conductive connection structure includes a plurality of second conductive pillars, a bridging chip, and a second insulating layer. The second conductive pillars are at least partially located within the second insulating layer, and the bridging chip is at least partially located within the second insulating layer. The bridging chip is electrically connected to at least two of the functional chips.

9. The semiconductor packaging structure according to claim 8, characterized in that, The diameter of the first conductive post is larger than the diameter of the second conductive post.

10. The semiconductor packaging structure according to claim 7, characterized in that, At least two of the first conductive posts have different axial dimensions.

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