Manufacturing method of packaging structure, packaging structure and electronic device

Abstract

The application provides a packaging structure manufacturing method, a packaging structure and an electronic device, and relates to the technical field of semiconductors. The method comprises the following steps: providing a first substrate and a second substrate, wherein the first substrate comprises a first surface and a second surface arranged oppositely, and the second substrate comprises a third surface and a fourth surface arranged oppositely; forming a plurality of first blind holes arranged at intervals on the first surface of the first substrate, and forming a plurality of second blind holes arranged at intervals on the third surface of the second substrate; forming a first conductive column in the first blind hole; forming a second conductive column in the second blind hole; polishing the second surface of the first substrate to expose the first conductive column; polishing the fourth surface of the second substrate to expose the second conductive column; and bonding the first substrate and the second substrate to electrically connect the first conductive column and the second conductive column. In this way, the filling difficulty of the conductive column can be reduced, the filling defects can be reduced, and the reliability of the packaging structure can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a method for manufacturing a packaging structure, a packaging structure, and an electronic device. Background Technology

[0002] Currently, in the fabrication of packaging structures, through-glass via (TGV) technology is typically used to create vias on the substrate, followed by double-sided electroplating to form conductive pillars within the vias. However, this double-sided electroplating process makes it difficult to fill the conductive pillars, easily leading to voids or gaps within the vias. This, in turn, reduces the conductivity of the conductive pillars and affects the overall reliability of the packaging structure. Summary of the Invention

[0003] In order to at least overcome the above-mentioned deficiencies in the prior art, the purpose of this application is to provide a method for manufacturing a packaging structure, a packaging structure, and an electronic device.

[0004] In a first aspect, embodiments of this application provide a method for manufacturing a packaging structure, the method comprising: A first substrate and a second substrate are provided, wherein the first substrate includes a first surface and a second surface disposed opposite to each other, and the second substrate includes a third surface and a fourth surface disposed opposite to each other; A plurality of spaced-apart first blind holes are formed on the first surface of the first substrate, and a plurality of spaced-apart second blind holes are formed on the third surface of the second substrate; A first conductive post is formed in the first blind hole; a second conductive post is formed in the second blind hole; The second surface of the first substrate is polished to expose the first conductive pillar; the fourth surface of the second substrate is polished to expose the second conductive pillar. The first substrate and the second substrate are bonded together to electrically connect the first conductive post and the second conductive post.

[0005] In one possible implementation, before the step of forming a first conductive post in the first blind hole and forming a second conductive post in the second blind hole, the method further includes: A first buffer layer is formed on the first surface of the first substrate and the sidewall of the first blind hole, and a second buffer layer is formed on the third surface of the second substrate and the sidewall of the second blind hole. A first seed layer is formed on the side of the first buffer layer away from the first substrate, and a second seed layer is formed on the side of the second buffer layer away from the second substrate.

[0006] In one possible implementation, the step of forming a first conductive post within the first blind hole and forming a second conductive post within the second blind hole includes: A first conductive layer is formed on the side of the first seed layer away from the first substrate, and a second conductive layer is formed on the side of the second seed layer away from the second substrate; the first conductive layer covers the first seed layer and fills the first blind via, and the second conductive layer covers the second seed layer and fills the second blind via. The first conductive layer and the first seed layer are etched to remove the first conductive layer located on the first surface, while retaining the first conductive layer located in the first blind hole, to form a first conductive pillar; the second conductive layer and the second seed layer are etched to remove the second conductive layer located on the third surface, while retaining the second conductive layer located in the second blind hole, to form a second conductive pillar.

[0007] In one possible implementation, the step of forming a first conductive layer on the side of the first seed layer away from the first substrate and forming a second conductive layer on the side of the second seed layer away from the second substrate includes: An electric current is applied to the first surface of the first substrate to perform electroplating, thereby forming a first conductive layer on the side of the first seed layer away from the first substrate. An electric current is applied to the third surface of the second substrate to perform electroplating, thereby forming a second conductive layer on the side of the second seed layer away from the second substrate.

[0008] In one possible implementation, the step of bonding the first substrate and the second substrate includes: The second surface of the first substrate is bonded to the fourth surface of the second substrate; After the step of bonding the first substrate and the second substrate, the method further includes: A first circuit layer is formed on the first surface of the first substrate, and the first circuit layer is electrically connected to the first conductive pillar. A second circuit layer is formed on the fourth surface of the second substrate, and the second circuit layer is electrically connected to the second conductive pillar.

[0009] In one possible implementation, the first line layer and the second line layer have the same type of line layer structure, or the first line layer and the second line layer have different types of line layer structures. Among them, the types of line layer structures include redistribution line layer structures and ABF line layer structures.

[0010] In one possible implementation, the first line layer includes a plurality of stacked first trace layers and an insulating layer located between adjacent first trace layers, with adjacent first trace layers connected by through-holes in the insulating layer. The second wiring layer includes multiple stacked second wiring layers and an insulating layer located between adjacent second wiring layers, with adjacent second wiring layers connected by through-holes in the insulating layer.

[0011] In one possible implementation, the step of forming a plurality of spaced-apart first blind vias on the first surface of the first substrate and a plurality of spaced-apart second blind vias on the third surface of the second substrate includes: A first blind hole is formed on the first surface of the first substrate using a laser-induced etching process, and a second blind hole is formed on the third surface of the second substrate using a laser-induced etching process.

[0012] Secondly, embodiments of this application also provide a packaging structure, which is manufactured using the packaging structure manufacturing method described in any of the above aspects.

[0013] Thirdly, embodiments of this application also provide an electronic device, which includes the packaging structure described in any of the above aspects.

[0014] Based on any of the above aspects, the packaging structure manufacturing method, packaging structure, and electronic device provided in the embodiments of this application, by fabricating a first blind hole and a second blind hole on a first substrate and a second substrate respectively, filling the blind holes with conductive material to form a first conductive pillar and a second conductive pillar, and then bonding the two substrates to electrically connect the first conductive pillar and the second conductive pillar, thereby achieving vertical interconnection, can reduce filling difficulty and reduce filling defects. At the same time, it has a wider range of adaptability to the aspect ratio of the conductive pillars, can adapt to higher density packaging interconnection requirements, and improve the overall reliability of the packaging structure. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is one of the flowcharts illustrating the method for fabricating the packaging structure provided in this embodiment; Figure 2 This is one of the schematic diagrams illustrating the manufacturing process of the packaging structure provided in this embodiment; Figure 3This is the second flowchart illustrating the method for fabricating the packaging structure provided in this embodiment; Figure 4 This is the second schematic diagram of the manufacturing process of the packaging structure provided in this embodiment; Figure 5 This is a schematic diagram of the sub-steps of step S130 provided in this embodiment; Figure 6 This is the third schematic diagram of the manufacturing process of the packaging structure provided in this embodiment; Figure 7 This is a schematic diagram of the sub-steps of step S131 provided in this embodiment; Figure 8 This is the third flowchart illustrating the method for fabricating the packaging structure provided in this embodiment; Figure 9 This is a schematic diagram of the packaging structure provided in this embodiment.

[0017] Icons: 100 - First substrate; 110 - First surface; 120 - Second surface; 101 - First blind via; 200 - Second substrate; 210 - Third surface; 220 - Fourth surface; 201 - Second blind via; 301 - First conductive layer; 302 - Second conductive layer; 310 - First conductive pillar; 320 - Second conductive pillar; 410 - First buffer layer; 420 - Second buffer layer; 510 - First seed layer; 520 - Second seed layer; 610 - First circuit layer; 620 - Second circuit layer. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0021] In the description of this application, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In addition, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0023] This embodiment provides a solution to the above problems. The specific implementation of this application will be described in detail below with reference to the accompanying drawings.

[0024] Please refer to Figure 1 , Figure 1 This embodiment provides a flowchart illustrating the method for fabricating a packaging structure, which may include the following steps.

[0025] Step S110: A first substrate 100 and a second substrate 200 are provided. The first substrate 100 includes a first surface 110 and a second surface 120 disposed opposite to each other. The second substrate 200 includes a third surface 210 and a fourth surface 220 disposed opposite to each other.

[0026] In this embodiment, the first substrate 100 may include a first surface 110 and a second surface 120 disposed opposite to each other, and the second substrate 200 may include a third surface 210 and a fourth surface 220 disposed opposite to each other. Both the first substrate 100 and the second substrate 200 may be glass substrates. Compared to substrates made of silicon or organic materials, glass substrates have superior high-frequency electrical performance and extremely high surface flatness, facilitating the fabrication of fine metal traces. They also possess superior mechanical and thermal stability, which helps improve the reliability of the packaging structure and reduce costs.

[0027] Furthermore, the cross-sectional area of ​​the first substrate 100 can be equal to the cross-sectional area of ​​the second substrate 200, and the cross-sectional shape of the first substrate 100 is also the same as that of the second substrate 200, which facilitates subsequent bonding processes. For example, the cross-sectional shapes of the first substrate 100 and the second substrate 200 can both be rectangular.

[0028] The thickness of the first substrate 100 may be equal to or different from the thickness of the second substrate 200. It can be adjusted according to actual needs, and no specific limitation is made here.

[0029] In step S120, a plurality of spaced first blind holes 101 are formed on the first surface 110 of the first substrate 100, and a plurality of spaced second blind holes 201 are formed on the third surface 210 of the second substrate 200.

[0030] In this embodiment, please refer to Figure 2 The locations of the holes to be drilled on the first substrate 100 and the second substrate 200 can be determined according to actual needs. Then, multiple first blind holes 101 and second blind holes 201 are respectively formed on the first surface 110 of the first substrate 100 and the third surface 210 of the second substrate 200, spaced apart. The number of first blind holes 101 and second blind holes 201 is the same and they correspond one-to-one. The depth of the first blind hole 101 is less than the depth of the first substrate 100, that is, the first blind hole 101 does not penetrate the first substrate 100; the depth of the second blind hole 201 is less than the thickness of the second substrate 200, that is, the second blind hole 201 does not penetrate the second substrate 200. The depth of the first blind hole 101 can be the same as or different from the depth of the second blind hole 201.

[0031] In some examples, the first blind hole 101 may be circular in the direction parallel to the first substrate 100, and the diameter of the first blind hole 101 may be equal at all locations in the direction perpendicular to the first substrate 100. The second blind hole 201 may be circular in the direction parallel to the second substrate 200, and the diameter of the second blind hole 201 may be equal to the diameter of the first blind hole 101 in the direction perpendicular to the second substrate 200.

[0032] When both the first blind hole 101 and the second blind hole 201 are circular, the ratio of the sum of the heights of the first blind hole 101 and the second blind hole 201 to the diameters of the first blind hole 101 and the second blind hole 201 can be 10:1 or 15:1.

[0033] In other examples, in the direction perpendicular to the first substrate 100, the shape of the first blind hole 101 can be funnel-shaped, and the diameter of the first blind hole 101 gradually decreases from the first surface 110 toward the direction closer to the second surface 120. In the direction perpendicular to the second substrate 200, the shape of the second blind hole 201 can also be funnel-shaped, and the diameter of the second blind hole 201 gradually decreases from the third surface 210 toward the direction closer to the fourth surface 220. Furthermore, the diameter of the second blind hole 201 at the third surface 210 is smaller than the diameter of the first blind hole 101 at the second surface 120.

[0034] It should be noted that the aperture and depth of the first blind via 101 and the second blind via 201, as well as the spacing between two adjacent first blind vias 101 and two adjacent second blind vias 201, can be adjusted according to actual packaging requirements, and are not specifically limited here.

[0035] In step S130, a first conductive post 310 is formed in the first blind hole 101; and a second conductive post 320 is formed in the second blind hole 201.

[0036] In this embodiment, please refer again. Figure 2 A first conductive pillar 310 can be formed in the first blind hole 101 of the first substrate 100, and a second conductive pillar 320 can be formed in the second blind hole 201 of the second substrate 200. Since the first blind hole 101 and the second blind hole 201 are not through holes in the prior art, the conductive material will grow from the bottom of the blind hole. Only single-sided electroplating is required to complete the filling, which reduces the difficulty of filling the conductive pillar and can effectively avoid filling defects such as holes and gaps that are easy to occur in the traditional double-sided electroplating process.

[0037] In step S140, the second surface 120 of the first substrate 100 is polished to expose the first conductive pillar 310; the fourth surface 220 of the second substrate 200 is polished to expose the second conductive pillar 320.

[0038] In this embodiment, please refer again. Figure 2 Chemical mechanical polishing (CMP) can be used to polish the second surface 120 of the first substrate 100 and the fourth surface 220 of the second substrate 200, respectively, to thin the first substrate 100 and the second substrate 200, remove excess substrate material from the second surface 120 of the first substrate 100 and the fourth surface 220 of the second substrate 200, expose one end of the first conductive post 310 facing the second surface 120 and the other end of the second conductive post 320 facing the fourth surface 220, and make the surface of the first conductive post 310 facing the second surface 120 flush with the polished second surface 120, and make the surface of the second conductive post 320 facing the fourth surface 220 flush with the polished fourth surface 220.

[0039] In the above design, by polishing the second surface 120 of the first substrate 100 and the fourth surface 220 of the second substrate 200, not only can the first conductive post 310 and the second conductive post 320 be exposed, but the flatness of the second surface 120 of the first substrate 100 and the fourth surface 220 of the second substrate 200 can also be improved, which is beneficial to the subsequent bonding of the first substrate 100 and the second substrate 200, and improves the reliability and stability of the bonding.

[0040] In step S150, the first substrate 100 and the second substrate 200 are bonded together, so that the first conductive post 310 and the second conductive post 320 are electrically connected.

[0041] In this embodiment, please refer again. Figure 2 The first substrate 100 after grinding can be bonded to the second substrate 200, so that each first conductive post 310 and each second conductive post 320 make contact with each other to achieve electrical connection.

[0042] In some examples, direct bonding can be used to bond the first substrate 100 and the second substrate 200. Utilizing the surface flatness of the glass substrate, bonding can be achieved under high temperature and pressure conditions, eliminating the need for an additional adhesive layer, thus simplifying the bonding process and reducing costs. In other examples, anodic bonding, plasma-activated bonding, or other methods can be used to bond the first substrate 100 and the second substrate 200. The appropriate bonding process can be selected based on actual needs, and no specific limitations are made here.

[0043] In addition, during the fabrication of the packaging structure, at least one third substrate can be provided. The third substrate includes a third blind via and a third conductive post located within the third blind via. The fabrication method of the third blind via is the same as that of the first blind via 101 and the second blind via 201. The formation method of the third conductive post is also the same as that of the first conductive post 310 and the second conductive post 320. After polishing the third substrate, the third substrate can be bonded to the first substrate 100 and the second substrate 200 to increase the aspect ratio of the conductive post, meet the requirements of higher density vertical interconnection, and improve the reliability of the packaging structure.

[0044] It should be noted that the number of the third substrate can be adjusted according to actual needs, and no specific limit is made here.

[0045] Based on the above design, in the packaging structure manufacturing method provided in this embodiment, a first blind via 101 and a second blind via 201 are respectively fabricated on the first substrate 100 and the second substrate 200. Conductive material is filled into the blind vias to form a first conductive post 310 and a second conductive post 320. The two substrates are then bonded to electrically connect the first conductive post 310 and the second conductive post 320, thereby achieving vertical interconnection. This reduces the difficulty of filling the conductive posts and reduces filling defects. At the same time, it has a wider range of adaptability to the aspect ratio of the conductive posts, which can adapt to higher density packaging interconnection requirements and improve the overall reliability of the packaging structure.

[0046] In one possible implementation, please refer to Figure 3 Before forming the first conductive post 310 in the first blind hole 101 and the second conductive post 320 in the second blind hole 201, the method of fabricating the package structure may further include the following steps.

[0047] In step S210, a first buffer layer 410 is formed on the first surface 110 of the first substrate 100 and the sidewall of the first blind hole 101, and a second buffer layer 420 is formed on the third surface 210 of the second substrate 200 and the sidewall of the second blind hole 201.

[0048] In this embodiment, please refer to Figure 4 A very thin first buffer layer 410 can be deposited on the first surface 110 of the first substrate 100, and a very thin second buffer layer 420 can be deposited on the third surface 210 of the second substrate 200. The first buffer layer 410 covers the first surface 110 of the first substrate 100 and the entire sidewall and bottom surface of the first blind via 201, and the second buffer layer 420 covers the third surface 210 of the second substrate 200 and the entire sidewall and bottom surface of the second blind via 201. The first buffer layer 410 and the second buffer layer 420 can be used to improve the bonding stability between the conductive pillar and the substrate, while blocking unnecessary electrical interactions between the conductive pillar and the substrate, ensuring stable conductivity.

[0049] In some examples, the first buffer layer 410 and the second buffer layer 420 may be made of insulating materials. In other examples, the first buffer layer 410 and the second buffer layer 420 may be made of metallic materials, such as titanium (Ti).

[0050] It should be noted that the materials of the first buffer layer 410 and the second buffer layer 420 can be adjusted according to actual needs, and no specific limitations are made again.

[0051] In step S220, a first seed layer 510 is formed on the side of the first buffer layer 410 away from the first substrate 100, and a second seed layer 520 is formed on the side of the second buffer layer 420 away from the second substrate 200.

[0052] In this embodiment, please refer again. Figure 4A first seed layer 510 can be formed on the side of the first buffer layer 410 away from the first substrate 100 using chemical plating or physical vapor deposition (PVD) processes. Similarly, a second seed layer 520 can be formed on the side of the second buffer layer 420 away from the second substrate 200 using the same process. The first seed layer 510 uniformly covers the entire surface of the first buffer layer 410, including portions on the sidewalls and bottom surface of the first blind via 101. The second seed layer 520 uniformly covers the entire surface of the second buffer layer 420, including portions on the sidewalls and bottom surface of the second blind via 201. The first and second seed layers 510 and 520 serve as conductive substrates for subsequent electroplating processes, ensuring uniform deposition of the electroplated conductive layer and preventing uneven filling.

[0053] The materials of the first seed layer 510 and the second seed layer 520 can be metallic materials, such as copper (Cu).

[0054] In the above design, since the first blind hole 101 and the second blind hole 201 are not through holes in the prior art, the seed layer can be uniformly attached to the sidewall and bottom surface of the blind hole when preparing the seed layer, which reduces the process complexity and improves the continuity of the seed layer.

[0055] In one possible implementation, please refer to Figure 5 Step S130 may include the following sub-steps.

[0056] In step S131, a first conductive layer 301 is formed on the side of the first seed layer 510 away from the first substrate 100, and a second conductive layer 302 is formed on the side of the second seed layer 520 away from the second substrate 200; the first conductive layer 301 covers the first seed layer 510 and fills the first blind via 101, and the second conductive layer 302 covers the second seed layer 520 and fills the second blind via 201.

[0057] Step S132: Etch the first conductive layer 301 and the first seed layer 510 to remove the first conductive layer 301 located on the first surface 110, and retain the first conductive layer 301 located in the first blind hole 101 to form a first conductive pillar 310; etch the second conductive layer 302 and the second seed layer 520 to remove the second conductive layer 302 located on the third surface 210, and retain the second conductive layer 302 located in the second blind hole 201 to form a second conductive pillar 320.

[0058] In this embodiment, please refer to Figure 6 A first conductive layer 301 and a second conductive layer 302 can be formed on the surfaces of the first seed layer 510 and the second seed layer 520, respectively, so that the first conductive layer 301 completely fills the first blind via 101 and the second conductive layer 302 completely fills the second blind via 201. Then, the first conductive layer 301 on the first surface 110 and the second conductive layer 302 on the third surface 210 are removed by etching or physical vapor deposition. Only the first conductive layer 301 inside the first blind via 101 is retained to form the first conductive pillar 310, and the second conductive layer 302 inside the second blind via 201 is retained to form the second conductive pillar 320. The surface of the first conductive pillar 310 away from the second surface 120 is flush with the first surface 110 of the first substrate 100, and the surface of the second conductive pillar 320 away from the fourth surface 220 is flush with the third surface 210 of the second substrate 200, which facilitates subsequent manufacturing processes.

[0059] In addition, when removing the first conductive layer 301 of the first surface 110, the first seed layer 510 and the first buffer layer 410 of the first surface 110 can also be removed at the same time. When removing the second conductive layer 302 of the third surface 210, the second seed layer 520 and the second buffer layer 420 of the third surface 210 can also be removed at the same time.

[0060] In one possible implementation, please refer to Figure 7 Step S131 may include the following sub-steps.

[0061] In step S131a, an electric current is applied to the first surface 110 of the first substrate 100 to perform electroplating, and a first conductive layer 301 is formed on the side of the first seed layer 510 away from the first substrate 100.

[0062] In step S131b, an electric current is applied to the third surface 210 of the second substrate 200 to perform electroplating, and a second conductive layer 302 is formed on the side of the second seed layer 520 away from the second substrate 200.

[0063] In this embodiment, electroplating is completed by applying current to the first surface 110 of the first substrate 100 and the third surface 210 of the second substrate 200. Compared with the traditional through-hole filling process that requires double-sided electroplating, this embodiment only requires single-sided electroplating, making the process simpler. It also avoids defects such as voids inside blind holes due to insufficient electroplating, effectively improving the structural reliability of the first conductive pillar 310 and the second conductive pillar 320 and ensuring conductivity. After electroplating, the first conductive layer 301 completely covers the first seed layer 510 and fills the first blind hole 101, and the second conductive layer 302 completely covers the second seed layer 520 and fills the second blind hole 201.

[0064] In one possible implementation, when bonding the first substrate 100 and the second substrate 200, the second surface 120 of the first substrate 100 and the fourth surface 220 of the second substrate 200 can be bonded together.

[0065] Please refer to Figure 8 After bonding the first substrate 100 and the second substrate 200, the method for fabricating the package structure may further include the following steps.

[0066] In step S310, a first circuit layer 610 is formed on the first surface 110 of the first substrate 100, and the first circuit layer 610 is electrically connected to the first conductive post 310.

[0067] In step S320, a second circuit layer 620 is formed on the fourth surface 220 of the second substrate 200, and the second circuit layer 620 is electrically connected to the second conductive pillar 320.

[0068] In this embodiment, please refer to Figure 9 First, the second surface 120 of the first substrate 100 and the fourth surface 220 of the second substrate 200 can be bonded together. Then, a first circuit layer 610 for realizing electrical connection is formed on the first surface 110 of the first substrate 100, and a second circuit layer 620 for realizing electrical connection is formed on the fourth surface 220 of the second substrate 200. The first circuit layer 610 can realize the electrical connection between the chip to be packaged and the first conductive post 310, and the second circuit layer 620 can realize the electrical connection between the package structure and the external circuit. The first circuit layer 610 and the second circuit layer 620 realize signal transmission through the electrical connection of the first conductive post 310 and the second conductive post 320, thereby completing high-density vertical interconnection.

[0069] In one possible implementation, the first line layer 610 and the second line layer 620 have the same type of line layer structure, wherein the type of line layer structure includes redistribution layer structure (RDL) and ABF line layer structure.

[0070] For example, the first circuit layer 610 and the second circuit layer 620 can be both multilayer RDLs or multilayer ABFs. RDLs are mainly composed of dielectric materials such as polyimide and copper metal, while ABFs are made of a composite material mainly composed of epoxy resin, silica powder and curing agent.

[0071] In another possible implementation, the first line layer 610 and the second line layer 620 have different types of line layer structures. For example, the first line layer 610 can be a multi-layer RDL, and the second line layer 620 can be a multi-layer ABF; or, the first line layer 610 can be a multi-layer ABF, and the second line layer 620 can be a multi-layer RDL.

[0072] In one possible implementation, the first wiring layer 610 may include a plurality of stacked first wiring layers and an insulating layer located between adjacent first wiring layers, with adjacent first wiring layers connected through insulating layer vias. The second wiring layer 620 may include a plurality of stacked second wiring layers and an insulating layer located between adjacent second wiring layers, with adjacent second wiring layers connected through insulating layer vias.

[0073] In this embodiment, the first routing layer and the second routing layer can be of type RDL or ABF at the same time. That is, the first routing layer 610 and the second routing layer 620 can be of type RDL or ABF at the same time.

[0074] Alternatively, the first routing layer can be of type RDL, and the second routing layer can be of type ABF. In this case, the first routing layer 610 is a multi-layer RDL, and the second routing layer 620 is a multi-layer ABF. Or, the first routing layer can be of type ABF, and the second routing layer can be of type RDL. In this case, the first routing layer 610 is a multi-layer ABF, and the second routing layer 620 is a multi-layer RDL.

[0075] In one possible implementation, when a plurality of spaced-apart first blind holes 101 are formed on the first surface 110 of the first substrate 100 and a plurality of spaced-apart second blind holes 201 are formed on the third surface 210 of the second substrate 200, a laser-induced etching process can be used to form the first blind holes 101 on the first surface 110 of the first substrate 100 and the second blind holes 201 on the third surface 210 of the second substrate 200.

[0076] In this embodiment, the positions of the holes to be opened in the first substrate 100 and the second substrate 200 can be determined firstly, and then a first blind hole 101 can be formed on the first surface 110 of the first substrate 100 and a second blind hole 201 can be formed on the third surface 210 of the second substrate 200 using laser-induced and wet etching processes. In this way, the processing accuracy is higher, blind holes with a larger aspect ratio can be produced, and the process cost is reduced.

[0077] This application also provides a packaging structure, which can be manufactured using the packaging structure manufacturing method provided in this embodiment.

[0078] This application also provides an electronic device, which may include the packaging structure provided in this embodiment.

[0079] In summary, this embodiment provides a method for manufacturing a packaging structure, a packaging structure, and an electronic device. By fabricating a first blind via and a second blind via on a first substrate and a second substrate respectively, filling the blind vias with conductive material to form a first conductive pillar and a second conductive pillar, and then bonding the two substrates to electrically connect the first conductive pillar and the second conductive pillar, vertical interconnection is achieved. This reduces the difficulty of filling and reduces filling defects. At the same time, it has a wider range of adaptability to the aspect ratio of the conductive pillars, can adapt to higher density packaging interconnection requirements, and improves the overall reliability of the packaging structure.

[0080] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0081] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for manufacturing an encapsulation structure, characterized in that, The method includes: A first substrate and a second substrate are provided, wherein the first substrate includes a first surface and a second surface disposed opposite to each other, and the second substrate includes a third surface and a fourth surface disposed opposite to each other; A plurality of spaced-apart first blind holes are formed on the first surface of the first substrate, and a plurality of spaced-apart second blind holes are formed on the third surface of the second substrate; A first conductive post is formed in the first blind hole; a second conductive post is formed in the second blind hole; The second surface of the first substrate is polished to expose the first conductive pillar; the fourth surface of the second substrate is polished to expose the second conductive pillar. The first substrate and the second substrate are bonded together to electrically connect the first conductive post and the second conductive post.

2. The method for manufacturing the packaging structure according to claim 1, characterized in that, A first conductive post is formed within the first blind hole; Prior to the step of forming the second conductive post within the second blind hole, the method further includes: A first buffer layer is formed on the first surface of the first substrate and the sidewall of the first blind hole, and a second buffer layer is formed on the third surface of the second substrate and the sidewall of the second blind hole. A first seed layer is formed on the side of the first buffer layer away from the first substrate, and a second seed layer is formed on the side of the second buffer layer away from the second substrate.

3. The method for manufacturing the packaging structure according to claim 2, characterized in that, A first conductive post is formed within the first blind hole; The step of forming a second conductive post within the second blind hole includes: A first conductive layer is formed on the side of the first seed layer away from the first substrate, and a second conductive layer is formed on the side of the second seed layer away from the second substrate; the first conductive layer covers the first seed layer and fills the first blind via, and the second conductive layer covers the second seed layer and fills the second blind via. The first conductive layer and the first seed layer are etched to remove the first conductive layer located on the first surface, while retaining the first conductive layer located in the first blind hole, to form a first conductive pillar; the second conductive layer and the second seed layer are etched to remove the second conductive layer located on the third surface, while retaining the second conductive layer located in the second blind hole, to form a second conductive pillar.

4. The method for manufacturing the packaging structure according to claim 3, characterized in that, The step of forming a first conductive layer on the side of the first seed layer away from the first substrate and forming a second conductive layer on the side of the second seed layer away from the second substrate includes: An electric current is applied to the first surface of the first substrate to perform electroplating, thereby forming a first conductive layer on the side of the first seed layer away from the first substrate. An electric current is applied to the third surface of the second substrate to perform electroplating, thereby forming a second conductive layer on the side of the second seed layer away from the second substrate.

5. The method for manufacturing the packaging structure according to claim 1, characterized in that, The step of bonding the first substrate and the second substrate includes: The second surface of the first substrate is bonded to the fourth surface of the second substrate; After the step of bonding the first substrate and the second substrate, the method further includes: A first circuit layer is formed on the first surface of the first substrate, and the first circuit layer is electrically connected to the first conductive pillar. A second circuit layer is formed on the fourth surface of the second substrate, and the second circuit layer is electrically connected to the second conductive pillar.

6. The method for manufacturing the packaging structure according to claim 5, characterized in that, The first line layer and the second line layer have the same type of line layer structure, or the first line layer and the second line layer have different types of line layer structures; Among them, the types of line layer structures include redistribution line layer structures and ABF line layer structures.

7. The method for manufacturing the packaging structure according to claim 5, characterized in that, The first line layer includes a plurality of stacked first trace layers and an insulating layer located between adjacent first trace layers, with adjacent first trace layers connected by through-holes in the insulating layer; The second wiring layer includes multiple stacked second wiring layers and an insulating layer located between adjacent second wiring layers, with adjacent second wiring layers connected by through-holes in the insulating layer.

8. The method for manufacturing the packaging structure according to claim 1, characterized in that, The step of forming a plurality of spaced-apart first blind vias on the first surface of the first substrate and a plurality of spaced-apart second blind vias on the third surface of the second substrate includes: A first blind hole is formed on the first surface of the first substrate using a laser-induced etching process, and a second blind hole is formed on the third surface of the second substrate using a laser-induced etching process.

9. A packaging structure, characterized in that, The encapsulation structure is manufactured using the method for manufacturing the encapsulation structure according to any one of claims 1-8.

10. An electronic device, characterized in that, The electronic device includes the packaging structure of claim 9.

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