Semiconductor device and method of manufacture using a die and a pre-column

Abstract

Semiconductor devices and methods of manufacture using a die and first pillar approach. A semiconductor device has a semiconductor die and a conductive pillar disposed adjacent the semiconductor die. An encapsulant is deposited over the semiconductor die and the conductive pillar. A first conductive layer is formed directly on the encapsulant, the conductive pillar, and the semiconductor die. A second conductive layer is formed directly on the encapsulant, the conductive pillar, and the semiconductor die opposite the first conductive layer.

Description

Technical Field

[0001] This invention relates generally to semiconductor devices, and more specifically to semiconductor devices and manufacturing methods using a die-first approach. Background Technology

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide variety of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electricity, and creating visual images for television displays. Semiconductor devices are found in communications, power conversion, networking, computers, entertainment, and consumer products. They are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0003] Building semiconductor packages on a substrate typically involves creating a reconstructed wafer, where a semiconductor die is molded together with pre-molded copper pillar modules, e-bars, or PCB cells into a panel. However, existing technologies suffer from die shift, leading to defective cells. The risk of die shift means that line spacing and pitch cannot be technically as precise as possible based on the manufacturing method employed. Wider pitches must be used to ensure accommodation for potential die shift. Therefore, there is a need for a new die and pillar method. Attached Figure Description

[0004] Figures 1a-1c The illustration shows a semiconductor wafer with multiple semiconductor dies separated by saw marks; Figure 2a-2m The illustration shows the formation of a semiconductor package using a die and post-cone method; Figure 3 An embodiment with through-silicon vias is illustrated; Figure 4 An embodiment with preformed columns is illustrated; Figures 5a-5h An embodiment with conductive blocks is illustrated; and Figure 6a and 6b The illustration shows an electronic device with a semiconductor package. Detailed Implementation

[0005] In the following description with reference to the figures, the invention is described in one or more embodiments, wherein the same numerals denote the same or similar elements. While the invention has been described in terms of the best mode for carrying out its objectives, those skilled in the art will appreciate that the invention is intended to cover substitutions, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents, supported by the following disclosure and the accompanying drawings. Features shown in the figures are not necessarily drawn to scale. Elements given the same reference numerals in the figures have similar functions and descriptions to each other. The term “semiconductor die” as used herein refers to both the singular and plural forms of the word, and therefore can refer to both a single semiconductor device and multiple semiconductor devices.

[0006] Semiconductor devices are typically manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, create a relationship between the voltage and current necessary to perform the circuit's function.

[0007] Back-end manufacturing refers to the process of dicing or isomerizing a finished wafer into individual semiconductor dies and packaging those dies for structural support, electrical interconnection, and environmental isolation. To isomerize a semiconductor die, the wafer is scribed and broken along non-functional regions (called serrations or cuts). This is done using a laser cutting tool or saw blade. After isomerization, the individual semiconductor dies are placed on a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. Electrical connections can be achieved using conductive layers, bumps, column bumps, conductive paste, or wire bonding. A sealant or other molding material is deposited over the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system, making the semiconductor device functional and available to other system components.

[0008] Figure 1aA semiconductor wafer 100 with a base substrate material 102 is shown, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, silicon nitride, lithium niobate (LiNbO3), or other bulk materials used for structural support. Multiple semiconductor dies or electrical components 104 are formed on the wafer 100, separated by non-active inter-die wafer regions or saw tracks 106. The saw tracks 106 provide dicing areas to individualize the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0009] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or non-active surface 108 and an active surface 110, the active surface 110 containing analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers, formed above or inside the die, and electrically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuitry, such as digital signal processors (DSPs), application-specific integrated circuits (ASICs), memory, power devices, or other signal processing circuitry. The semiconductor die 104 may also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0010] A conductive layer 112 is formed over the active surface 110 using physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, electroless plating, or other suitable metal deposition processes. The conductive layer 112 may be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 operates as contact pads for electrical connections to circuitry on the active surface 110. The semiconductor wafer 100 will typically have several interleaved insulating and conductive layers to achieve desired circuit design and signal routing, with the conductive layer 112 being the top conductive layer. Any other conductive layers mentioned above or below may be formed using the same materials and methods described for the conductive layer 112.

[0011] exist Figure 1c In this process, a saw blade or laser cutting tool 118 is used to monomerize a semiconductor wafer 100 into individual semiconductor dies 104 through a saw path 106. Individual semiconductor dies 104 can be inspected and electrically tested to identify known good dies (KGD) or known good cells (KGU) after monomerization.

[0012] Figure 2a-2mThe illustration shows the die and post method for forming a semiconductor package using semiconductor die 104. Figure 2a A carrier 120 is shown, wherein an optional interface layer, release adhesive layer, or double-sided tape 122 is formed or disposed over the carrier 120 as a temporary adhesive film, etch stop layer, heat release layer, or UV release layer. The carrier 120 comprises a sacrificial substrate material, such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost rigid material for structural support. The term carrier may refer only to carrier 120 or a combination of carrier 120 and interface layer 122.

[0013] Semiconductor die 104 is picked up and placed onto carrier 120, with back face 108 on interface layer 122. Alternatively, semiconductor die 104 is mounted onto carrier 120 with an adhesive layer disposed on back face 108, without interface layer 122. A semiconductor die 104 is disposed on carrier 120 according to the package being manufactured, separated by saw marks 126. Although carrier 120 sufficient to form two packages at a time is shown, hundreds or thousands of packages are typically formed together on a common carrier using the same steps disclosed herein, but performed together. Any other electrical components packaged with semiconductor die 104 are also expected to be disposed on carrier 120 at this stage, such as additional semiconductor dies, sub-packages, chiplets, or discrete active or passive electrical components.

[0014] exist Figure 2b In this process, a photoresist layer 130 is formed on a carrier 120 to encapsulate a semiconductor die 104, while exposing the active surface 110 and making it coplanar with the top surface of the photoresist layer 130. The photoresist layer 130 can be formed using spin coating, spraying, lamination, thin-film assisted molding, or any other suitable method. The material of the photoresist layer 130 includes photosensitive polyimide (PSPI), epoxy-based photoresist, acrylic-based photoresist, or any other suitable material. The thickness of the photoresist layer 130 can vary depending on the desired conductive pillar dimension and subsequent process requirements.

[0015] Figure 2c A via opening 132 is shown that extends completely through the photoresist layer 130, thereby exposing the carrier 120 or interface layer 122. The via opening 132 is formed using photolithography by applying a patterned mask to the photoresist layer 130, exposing selected areas to light, and developing the exposed or unexposed areas to form an opening. In other embodiments, the via opening 132 is formed using laser ablation, plasma etching, or any other suitable method. The size and placement of the via opening 132 are tailored based on the specific application and desired electrical properties.

[0016] exist Figure 2dIn this embodiment, conductive pillars 134 are formed by filling openings 132 with a conductive material. The conductive pillars 134 can be formed from any material described above for conductive layer 112 and deposited using any of the methods mentioned above. The conductive material is typically deposited to overfill openings 132 and then covered with the top surface of the photoresist layer 130 before being back-side ground or planarized to give the conductive pillars 134 a top surface coplanar with both the photoresist layer 130 and the semiconductor die 104. In other embodiments, a bottom-up technique is used to deposit the conductive material, stopping the technique when the conductive material completely fills openings 132, so that the conductive pillars 134 are formed without a separate back-side grinding step.

[0017] Figure 2e The illustration shows the removal of the photoresist layer 130, leaving conductive pillars 134 and a semiconductor die 104 on the carrier 120. The photoresist layer 130 can be removed by wet stripping, plasma ashing, thermal decomposition, or any other suitable method. During removal, the conductive pillars 134 remain on the carrier 120, with their top surfaces coplanar with the active surface 110 of the semiconductor die 104.

[0018] exist Figure 2f In this process, a sealant or molding compound 140 is deposited on and around the semiconductor die 104 and conductive pillars 134 using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable applicators to form a reconstructed wafer 142. The sealant 140 can be a liquid or particulate polymer composite, such as epoxy resin, epoxy acrylate, or another suitable polymer, with or without fillers. The sealant 140 is non-conductive, provides structural support, and protects the semiconductor device from external factors and contaminants in the environment.

[0019] The sealant 140 is deposited using a method that employs thin-film assisted molding or another method that exposes the sealed components, wherein the top surface is coplanar with the top surfaces of the conductive pillar 134 and the semiconductor die 104. In other embodiments, the sealant 140 is deposited to completely cover the conductive pillar 134 and the semiconductor die 104, and then back-side-polished to expose the sealed components.

[0020] The reconstructed wafer 142 is named this way because the semiconductor die 104 is repositioned and reassembled from the wafer 100 into a new structure. The term "reconstructed" reflects that the original wafer 100 has been decomposed and then reassembled into a new wafer. After sealing and planarization, the surface of the reconstructed wafer 142 resembles the surface of a standard semiconductor wafer. This allows for further processing similar to conventional wafer-level processes, such as redistribution layer (RDL) formation. The reconstructed wafer 142 functions similarly to a conventional wafer, but consists of multiple individual dies that have been sealed.

[0021] exist Figure 2gIn this configuration, a conductive layer 150 is formed on the coplanar surfaces of the semiconductor die 104, the sealant 140, and the conductive pillars 134. The conductive layer 150 is a redistribution layer (RDL) with conductive traces that interconnect or fan-out the contact pads of the conductive layer 112 to the conductive pillars 134. Each of the traces may have a contact pad at each end, one above the contact pads of the conductive layer 112 and one above the conductive pillar 134, to ensure electrical connections for given relevant manufacturing tolerances. The conductive layer 150 is formed directly on the semiconductor die 104, which will typically have an insulating layer exposed between the contact pads of the conductive layer 112 to prevent electrical short circuits with the underlying conductive paths of the semiconductor die. The conductive layer 150 is also formed directly on the conductive pillars 134 and the sealant 140. The sealant 140, the conductive pillars 134, and the semiconductor die 104 have coplanar surfaces such that the conductive layer 150 is formed planar across all three.

[0022] exist Figure 2h In this configuration, an insulating layer 152 is formed over the reconstructed wafer 142 having a conductive layer 150. The insulating layer 152 comprises one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide (PI), photosensitive polyimide (PSPI), benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials having similar insulating and structural properties. The insulating layer 152 can be formed using PVD, CVD, printing, lamination, spin coating, spraying, sintering, or thermal oxidation. Any insulating, passivating, or dielectric layers mentioned above or below can be formed using any of the materials or methods described for the insulating layer 152.

[0023] In other embodiments, the insulating layer 152 is a sealant formed in a molding process. In those embodiments, the insulating layer 152 can be formed from any material and using any of the processes described above for the sealant 140. In one embodiment, both the sealant 140 and the insulating layer 152 are formed using the same material selected from any of those mentioned. A first molding process is used to deposit the sealant 140 around the semiconductor die 104 and the conductive pillar 134, while a second molding process is used to form the insulating layer 152. The insulating layer 152 completely covers the reconstructed wafer 142 and the conductive layer 150, thereby electrically isolating the conductive layer and physically protecting both.

[0024] exist Figure 2iIn this process, the reconstructed wafer 142 is flipped so that the back side 108 of the semiconductor die 104 is oriented upwards. The reconstructed wafer 142 is mounted onto a back polishing tape 153 or another suitable carrier, and the carrier 120 is removed by back polishing with a polisher 155. In other embodiments, other processes suitable for removing specific types of carrier 120 and interface layer 122 are used, such as UV or thermal release. As an alternative to the back polishing tape 153, another carrier may be attached over the insulating layer 152 before flipping the reconstructed wafer 142 and removing the carrier 120.

[0025] exist Figure 2j In this configuration, a conductive layer 154 is formed over the back surface of the semiconductor die 104, sealant 140, and conductive pillar 134, opposite to the conductive layer 150. The conductive layer 154 is another RDL layer fan-in or fan-out electrically connected from the conductive pillar 134. Like the conductive layer 150, the conductive layer 154 is formed directly on the coplanar surfaces of the semiconductor die 104, sealant 140, and conductive pillar 134 to maintain complete flatness.

[0026] exist Figure 2k In this process, an insulating layer 156 is formed over the reconstructed wafer 142 and the conductive layer 154, as described above for the insulating layer 152. As mentioned above, the insulating layer 156 can be formed in the third molding step using the same type of molding process and the same materials as both the sealant 140 and the insulating layer 152. The insulating layer 156 is deposited to completely cover the reconstructed wafer 142 and the conductive layer 154.

[0027] An opening is formed through the insulating layer 156 to expose the contact pads of the conductive layer 154 for external interconnection. The opening can be formed by laser ablation, mechanical drilling, chemical etching, or another suitable process. Solder bumps 158 are formed on the conductive layer 154 within the opening in the insulating layer 156. Conductive bump material is deposited over the conductive layer 154 using evaporation, electrolytic plating, electroless plating, droplet coating, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, or combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder.

[0028] Bump material is bonded to conductive layer 154 using a suitable adhesion or bonding process. Optionally, bump 158 is formed by reflowing the bump material after heating it above its melting point. In one embodiment, bump 158 is formed over under-bump metallization (UBM) having a wetting layer, a barrier layer, and an adhesion layer. UBM can be formed over insulating layer 156 and conductive layer 154 after an opening is formed in the insulating layer. Bump 158 can also be compression bonded or thermocompressed to conductive layer 154. In some embodiments, bump 158 is formed prior to insulating layer 156. Solder bumps are electrically connected to conductive layer 112 of semiconductor die 104 through conductive layer 154, conductive pillar 134, and conductive layer 150.

[0029] exist Figure 2l In this process, the reconstructed wafer 142 is monolithized into individual semiconductor packages 160 using a laser cutting tool 162 or another suitable means. Figure 2m The monolithized package 160 is shown. The monolithized package 160 is removed from the back-side polishing tape 153 and placed into a tape-and-real, JEDEC tray, or other suitable storage medium.

[0030] Semiconductor package 160 is a small package in which the sealant 140 is the same thickness as the embedded semiconductor die 104, and a single planar conductive layer 150 or 154 and a single insulating layer 152 or 156 are formed only over the sealant and each top and bottom surface of the semiconductor die. Depositing the sealant 140 over the carrier 120 (where the semiconductor die 104 and exposed conductive pillars 134 are formed or set only on the carrier) improves the design to reduce die displacement without prior and separate molding. Furthermore, this process eliminates the need for temporary bonding and stripping (TBDB) during manufacturing, thereby reducing cost and complexity. Eliminating TBDB by removing the carrier 120 through back-grinding and limiting subsequent processing allows the back-grinding tape 153 to adequately support the reconstructed wafer 142 for the remainder of the manufacturing process.

[0031] Figure 3 An alternative embodiment is illustrated, wherein the semiconductor package 170 has a semiconductor die 104 having a conductive via 174 for perpendicular interconnection with a conductive layer 112 on an active surface 110 and a back contact pad 172. The semiconductor die 104 is fabricated as described above, and then the conductive via 174 and the contact pad 172 are formed. The contact pad 172 can be formed as described above for the conductive layer 112. The conductive via 174 is formed by creating an opening through the semiconductor die 104 using mechanical drilling, chemical etching, deep reactive ion etching (DRIE), or another suitable means, and then depositing a conductive material into the opening.

[0032] Using the back contact pad 172, the conductive layer 150 can be reconfigured to fan out interconnects from the back contact pad to the solder bumps 158, thereby reducing some of the load on the conductive layer 154 and relaxing routing design constraints. Some solder bumps 158 are electrically coupled to the conductive layer 112 via the conductive layer 154, conductive pillars 134, and conductive layer 150, while other solder bumps 158 are electrically coupled to the conductive layer 112 via the conductive layer 154, contact pad 172, and conductive via 174. In other embodiments, the back contact pad 172 is used without the conductive via 174 or without connection to the conductive layer 112.

[0033] Figure 4 An alternative embodiment is illustrated, in which the conductive pillars 178 are pre-formed and picked up and placed onto the carrier 120, instead of forming the conductive pillars 134 directly on the carrier. The pillars 178 are formed on a separate carrier using a photolithographic mask or any other suitable means, and then picked up and placed onto the carrier 120 or into an intermediate storage medium, such as tape-and-reel. Semiconductor package fabrication is as described above. Figure 2f-2m It should be done in a public manner.

[0034] Figures 5a-5h An embodiment of the conductive block is illustrated. From Figure 2a Continuing, after the semiconductor die 104 is placed on the carrier 120. Figure 5a The diagram illustrates the placement of a conductive block 180 onto a carrier 120 around a semiconductor die 104. The conductive block is formed by cutting a sheet of conductive material to the desired size and shape, or by any other suitable means, using a photolithographic mask on a separate carrier, and then picking it up and placing it onto the carrier 120.

[0035] Alternatively, the conductive block 180 can be formed directly on the carrier 120, as described above for... Figures 2b-2e The conductive pillar 134 is shown and described in the diagram. Alternatively, any of the methods and materials generally described above for conductive layers can be used to form the conductive block 180 on the carrier 120. The conductive block 180 can be any desired size and shape, but is generally a flat planar block suitable for shaping, reflecting, or amplifying electromagnetic signals. The conductive block 180 is typically formed of copper, but in other embodiments any other suitable conductive material is used. In other embodiments, the conductive block 180 is formed or disposed on the carrier 120 prior to the placement of the semiconductor die 104 on the carrier.

[0036] Figure 5b As described above and Figure 2fThe image shows a sealant 140 deposited in such a manner that it is coplanar with the semiconductor die 104, for example, by using thin-film assisted molding. Figure 5c In the middle, the conductive layer 154, the insulating layer 156, and the solder bumps 158 are as described above and in Figure 2j-2k As shown, it is formed in that manner. A conductive layer 154 extends over the conductive block 180, and its operation is to shape or amplify radio signals emitted by the conductive layer. Figure 5d In this process, the carrier 120 is removed by back-side grinding or another suitable process to expose the conductive block 180 and the back side 108 of the semiconductor die 104. Figure 5e The panel of the device with the carrier 120 removed is shown.

[0037] exist Figure 5f In this configuration, a back protective layer 181 is formed over the sealant 140, the conductive block 180, and the semiconductor die 104. The back protective layer 181 is typically formed using any of the methods and materials described above for the insulating layer. In other embodiments, the back protective layer 181 is molded similarly to the sealant 140. The back protective layer 181 physically isolates and protects the conductive block 180 and the semiconductor die 104. Figure 5g In this process, a saw blade or laser cutting tool 162 is used to isolate multiple semiconductor packages 182 from each other.

[0038] Figure 5h The completed semiconductor package 182 is shown. Semiconductor package 182 is formed using processes that provide the same benefits as semiconductor package 160, such as eliminating the need for TBDB processes, allowing for reductions in line pitch and pitch width shifting issues, while utilizing existing established embedded wafer-level ball grid array processes and tooling. Semiconductor package 182 has conductive blocks 180 that help amplify or guide electromagnetic waves. In some embodiments, both conductive blocks 180 and conductive posts 134 or 178 are used together by forming or setting them on carrier 120 prior to depositing sealant 140.

[0039] Figure 6a and 6b The illustration shows the integration of the semiconductor package described above (e.g., semiconductor package 182) into a larger electronic device 300. Figure 6aThe illustration shows a partial cross-section of a semiconductor package 182 mounted as part of an electronic device 300 onto a printed circuit board (PCB) or other substrate 302. Solder bumps 158 are reflowed onto the conductive layer 304 of the PCB 302 to physically attach and electrically connect the semiconductor package to the PCB. In other embodiments, thermoforming or another suitable attachment and connection method is used. In some embodiments, an adhesive or underfill layer is used between the semiconductor package 182 and the PCB 302. The semiconductor die 104 is electrically coupled to the conductive layer 304 via bumps 158 and conductive layer 154, and in some embodiments, also via conductive pillars 134 and conductive layer 150.

[0040] Figure 6b The illustration shows an electronic device 300 having a chip carrier substrate or PCB 302, wherein multiple semiconductor packages are disposed on the surface of the PCB 302, including semiconductor package 182. Depending on the application, the electronic device 300 may have one type of semiconductor package or multiple types of semiconductor packages.

[0041] Electronic device 300 may be a standalone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, electronic device 300 may be a sub-component of a larger system. For example, electronic device 300 may be part of a tablet computer, cellular phone, digital camera, communication system, or other electronic device. Alternatively, electronic device 300 may be a graphics card, network interface card, or other signal processing card that can be plugged into a computer. Semiconductor packages may include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor dies or electrical components. Miniaturization and weight reduction are essential for product market acceptance. The distance between semiconductor devices can be reduced to achieve higher density. PCB 302 may have a more irregular shape to facilitate fitting into more ergonomic and smaller device housings.

[0042] exist Figure 6b In this PCB 302, a general-purpose substrate is provided for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 304 are formed on or within the surface of the PCB 302 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition processes. The signal traces 304 provide electrical communication between each semiconductor package, mounted components, and other external system components. The traces 304 also provide power and ground connections to each semiconductor package.

[0043] In some embodiments, the semiconductor device has two packaging levels. The first-level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second-level packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only a first-level package, where the die is mechanically and electrically disposed directly on the PCB.

[0044] For illustrative purposes, several types of first-level packages, including wire bond packages 346 and flip chips 348, are shown on PCB 302. Additionally, several types of second-level packages, including ball grid arrays (BGAs) 350, bump chip carriers (BCCs) 352, pad gate arrays (LGAs) 356, multi-chip modules (MCMs) or SIP modules 358, square flat no-lead packages (QFNs) 360, square flat packages 362, and embedded wafer-level ball grid arrays (eWLBs) 364, are shown disposed on PCB 302. In one embodiment, eWLB 364 is a fan-out wafer-level package (Fo-WLP) or a fan-in wafer-level package (Fi-WLP).

[0045] Depending on system requirements, any combination of semiconductor packages configured with first and second level package styles, along with other electrical components, can be connected to PCB 302. In some embodiments, electronics 300 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can integrate prefabricated components into electronics and systems. Because semiconductor packages include complex functions, electronics can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less likely to fail and less expensive to manufacture, leading to lower costs for consumers.

[0046] Although one or more embodiments of the invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: Provide semiconductor dies; Conductive pillars are placed near the semiconductor die; Deposit a sealant over the semiconductor die and conductive pillars; The first conductive layer is formed directly on the sealant, conductive pillars, and semiconductor die; and A second conductive layer is formed directly on the sealant, conductive pillars, and semiconductor die opposite to the first conductive layer.

2. The method of claim 1 further comprises forming a conductive via through the semiconductor die.

3. The method according to claim 1, further comprising: The sealant is molded in the first molding step; and In the second molding step, an insulating material is molded over the first conductive layer.

4. The method according to claim 3 further includes providing solder bumps on the second conductive layer.

5. The method of claim 4, further comprising forming an insulating layer over a second conductive layer surrounding the solder bumps.

6. The method of claim 1, further comprising: The semiconductor die and conductive pillars are mounted on a silicon substrate; The first conductive layer is formed, while the semiconductor die and conductive pillars remain on the silicon carrier; and The silicon carrier is removed by back-side grinding.

7. A method for manufacturing a semiconductor device, comprising: Provide semiconductor dies; Conductive elements are placed near the semiconductor die; Deposit a sealant over the semiconductor die and conductive components; and The first conductive layer is formed directly on the sealant and the semiconductor die.

8. The method of claim 7 further comprises forming a conductive via through the semiconductor die.

9. The method of claim 7, further comprising: The sealant is molded in the first molding step; and In the second molding step, an insulating material is molded over the sealant and semiconductor die opposite to the first conductive layer.

10. The method according to claim 9, further comprising providing solder bumps on the first conductive layer.

11. A semiconductor device, comprising: Semiconductor die; Conductive elements located adjacent to the semiconductor die; A sealant deposited on top of semiconductor dies and conductive components; and The first conductive layer is formed directly on the sealant and the semiconductor die.

12. The semiconductor device of claim 11 further includes a conductive via formed through the semiconductor die.

13. The semiconductor device of claim 11, further comprising an insulating material molded over a sealant and a semiconductor die opposite to the first conductive layer.

14. The semiconductor device according to claim 11, wherein, The conductive element is a conductive block or a conductive column.

15. The semiconductor device according to claim 11, wherein, The semiconductor die and conductive elements are disposed on a silicon carrier.

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