A method of embedding a double-sided bump photonics integrated circuit into a glass substrate

Abstract

The application discloses a method for embedding a double-sided bump photonic integrated circuit into a glass substrate, comprising the following steps: firstly, a glass substrate with at least two glass cavities and a glass through hole is prepared; secondly, a first flavor of a laminated film is attached to the back of the glass substrate; thirdly, a photonic integrated circuit with double-sided bumps and a bridge chip are respectively embedded into the two glass cavities; fourthly, an optical waveguide is prepared and coupled between the side of the glass substrate and the side of the photonic integrated circuit; fifthly, a second flavor of a laminated film is attached to the front of the glass substrate, and holes are drilled on both sides of the glass substrate to expose the double-sided bumps of the photonic integrated circuit and the bridge chip and the glass through hole. The application embeds the double-sided bump PIC into the glass cavity, connects the optical waveguide on the side, and realizes signal interconnection through RDL and EIC and ASIC, so that the electric signal loss is small, the space is saved, the interconnection distance is shortened, and the signal exchange speed is improved.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more particularly to a method for embedding a double-sided bumped photonic integrated circuit into a glass substrate. Background Technology

[0002] like Figure 1 As shown, Broadcom currently embeds single-sided bump electronic integrated circuits (EICs) into glass vias (TGVs) and achieves signal interconnection between the optical engine (OE) and application-specific integrated circuits (ASICs) through a redistribution layer (RDL), thereby achieving higher signal density.

[0003] High signal transmission loss limits high-speed signal performance: Existing single-sided bump chip embedding architecture can only extract electrical signals from one side of the chip. The signal needs to be transmitted through multiple layers of RDL and substrate vias on one side. The high redundancy of the interconnect path leads to a significant increase in insertion loss, crosstalk and transmission delay of high-speed signals.

[0004] Insufficient packaging space utilization limits miniaturization: Existing technologies only support single-sided bump EIC embedding inside the glass substrate. Photonic integrated circuits (PICs) and other optical functional chips can only be externally mounted on the substrate surface and cannot be embedded inside the substrate to achieve three-dimensional integration. This results in a large overall thickness and planar area occupied by the packaging structure, low space utilization efficiency, and an inability to meet the increasingly stringent miniaturization and thinning design requirements of high-end optoelectronic modules.

[0005] The long interconnection path of the chips has led to a bottleneck in improving the signal exchange speed: In the current architecture, PIC3, EIC2 and ASIC are placed on different surfaces or different layers of the substrate. The signal interaction between chips needs to go through multiple transfers through the substrate surface wiring, vias and redistribution layers. The interconnection physical path is long and the signal round-trip delay is high, which directly limits the signal exchange speed and data interaction bandwidth between chips, making it difficult to support the performance requirements of the next generation of ultra-high-speed optoelectronic co-processing.

[0006] Existing embedding solutions only support the embedding of a single type of chip. They cannot embed double-sided bump PICs and bridge chips together inside the glass substrate to achieve close-to-close interconnection. Signal interaction between multiple chips still relies on surface wiring on the substrate, and the improvement in interconnection density is limited, failing to fully tap the high-density integration performance potential under a multi-chip collaborative architecture.

[0007] Therefore, it is necessary to develop a method for embedding double-sided bump photonic integrated circuits into glass substrates to solve the above problems. Summary of the Invention

[0008] The purpose of this invention is to design a method for embedding a double-sided bumped photonic integrated circuit into a glass substrate in order to solve the above-mentioned problems.

[0009] The present invention achieves the above objectives through the following technical solutions: A method for embedding a double-sided bump photonic integrated circuit into a glass substrate includes the following steps: S1. First, fabricate a glass substrate with at least two glass cavities and glass through holes. S2. Lay a first-aji-based multilayer film on the back of the glass substrate; S3. The photonic integrated circuit with double-sided bumps and the bridging chip are respectively embedded in two glass cavities; S4. Fabricate an optical waveguide coupled between the side of the glass substrate and the side of the photonic integrated circuit. S5. A second amizoline multilayer film is bonded to the front side of the glass substrate, and holes are drilled on both sides of the glass substrate to expose the double-sided bumps of the photonic integrated circuit and the bridging chip, as well as the glass through-holes.

[0010] Preferably, in step S3, the photonic integrated circuit and the bridging chip are embedded in the glass cavity through a pre-packaging process.

[0011] Preferably, in step S4, the optical waveguide is fabricated by laser induction or ion exchange.

[0012] Preferably, in step S5, the drilling is laser drilling.

[0013] The beneficial effects of this invention are as follows: This invention embeds a double-sided bumped PIC (photonic integrated circuit) within a glass cavity, connects it to an optical waveguide on the side, and then achieves signal interconnection with EIC (electronic integrated circuit) and ASIC (application-specific integrated circuit) through RDL (rewiring layer). The electrical signal loss through the glass substrate is small, and it saves space, shortens the interconnection distance, and improves the signal exchange speed. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the existing technology; Figure 2 This is a schematic diagram of the structure of step S1 of the present invention; Figure 3 This is a schematic diagram of the structure of step S2 of the present invention; Figure 4 This is a schematic diagram of the structure of step S3 of the present invention; Figure 5 This is a schematic diagram of the structure of step S4 of the present invention; Figure 6 This is a schematic diagram of the structure of step S5 of the present invention.

[0015] In the figure: 1-glass substrate; 2-electronic integrated circuit; 3-photonic integrated circuit; 4-glass cavity; 5-first Amitoxin multilayer film; 6-bridging chip; 7-glass via; 8-optical waveguide; 9-second Amitoxin multilayer film. Detailed Implementation

[0016] The specific embodiments of the present invention will be described in detail below.

[0017] A method for embedding a double-sided bump photonic integrated circuit into a glass substrate includes the following steps: S1, such as Figure 2 As shown, a glass substrate 1 with at least two glass cavities 4 and glass through holes 7 is first fabricated. S2, such as Figure 3 As shown, a first ajinomoto multilayer film 5 (ABF) is bonded to the back of the glass substrate 1. S3, such as Figure 4 As shown, the photonic integrated circuit 3 (PIC) with double-sided bumps and the bridge die 6 are respectively embedded in two glass cavities 4 using a pre-packaging process (PNP). S4, such as Figure 5 As shown, an optical waveguide 8 coupled to the side of the PIC (photonic integrated circuit) is fabricated using laser-induced technology or ion exchange technology. S5, such as Figure 6 As shown, a second anazone multilayer film 9 (ABF) is bonded to the front side of the glass substrate 1, and laser drilling is performed on both sides of the glass substrate 1 to expose the double-sided bumps and glass vias 7 (TGV) of the photonic integrated circuit 3 and the bridging chip 6, thereby facilitating the subsequent redistribution layer (RDL) process.

[0018] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for embedding a double-sided bumped photonic integrated circuit into a glass substrate, characterized in that, Including the following steps: S1. First, fabricate a glass substrate with at least two glass cavities and glass through holes. S2. Lay a first-aji-based multilayer film on the back of the glass substrate; S3. The photonic integrated circuit with double-sided bumps and the bridging chip are respectively embedded in two glass cavities; S4. Fabricate an optical waveguide coupled between the side of the glass substrate and the side of the photonic integrated circuit. S5. A second amizoline multilayer film is bonded to the front side of the glass substrate, and holes are drilled on both sides of the glass substrate to expose the double-sided bumps of the photonic integrated circuit and the bridging chip, as well as the glass through-holes.

2. The method for embedding a double-sided bumped photonic integrated circuit into a glass substrate according to claim 1, characterized in that, In step S3, the photonic integrated circuit and the bridging chip are embedded in the glass cavity through a pre-packaging process.

3. The method for embedding a double-sided bumped photonic integrated circuit into a glass substrate according to claim 1, characterized in that, In step S4, the optical waveguide is fabricated by laser induction or ion exchange.

4. The method for embedding a double-sided bumped photonic integrated circuit into a glass substrate according to claim 1, characterized in that, In step S5, the drilling is laser drilling.

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