An electronic integrated circuit based on double-sided bump and a manufacturing method thereof

Abstract

The application discloses a kind of electronic integrated circuit based on double-face bump and preparation method thereof, it is related to semiconductor packaging technical field, including: rewire layer, TMV copper column is equipped on rewire layer, TMV copper column bottom and rewire layer electric connection;Chip group, chip group includes electric chip, optical chip, the positive and negative of electric chip are equipped with bump, electric chip is embedded in TMV copper column, the bump of electric chip positive and rewire layer electric connection, electric chip, TMV copper column is formed after plastic package plastic package structure, optical chip is externally located in the top surface of plastic package structure and is located above electric chip, optical chip is electrically connected with the bump of electric chip negative by hybrid bonding process.The application improves signal transmission quality, saves space, shortens interconnection distance, and improves signal exchange speed.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to an electronic integrated circuit based on double-sided bumps and its fabrication method. Background Technology

[0002] In existing technologies, companies like Broadcom employ a single-sided bump EIC (Electronic Integrated Circuit) embedding TMV (Transmission Video Module) solution, which achieves higher signal density through redistribution layers compared to traditional substrate solutions. However, the single-sided bump EIC solution has the following drawbacks: First, the single-sided bump structure concentrates all power signals and high-speed signals on the same side of the EIC. The lack of effective physical isolation between the power and high-speed signals leads to serious signal crosstalk problems and affects the signal transmission quality. Second, the fan-out density of single-sided bumps is limited by the area of ​​one side of the EIC, making it difficult to meet the needs of high-density interconnects. Third, in the existing solution, the interconnection between EIC and PIC still needs to be achieved through an intermediary layer or an additional wiring layer. The interconnection path is long and the signal transmission delay is large, which limits the improvement of signal exchange speed.

[0003] Therefore, there is an urgent need for a novel EIC packaging structure and its manufacturing method that can effectively solve the signal crosstalk problem, improve fan-out density, and shorten interconnect distance. Thus, an electronic integrated circuit based on double-sided bumps and its fabrication method were developed to address these issues. Summary of the Invention

[0004] This invention proposes an electronic integrated circuit based on double-sided bumps and its fabrication method to solve the problems of poor signal transmission quality, large space occupation, and limited signal exchange speed in the existing single-sided bump EIC embedding TMV scheme.

[0005] The present invention achieves the above objectives through the following technical solutions: This invention discloses an electronic integrated circuit based on double-sided bumps, comprising: A redistribution layer is provided, and TMV copper pillars are provided on the redistribution layer. The bottom of the TMV copper pillars is electrically connected to the redistribution layer. The chipset includes an electrical chip and an optical chip. The electrical chip has bumps on both the front and back sides and is embedded in a TMV copper pillar. The bumps on the front side of the electrical chip are electrically connected to the redistribution layer. The electrical chip and the TMV copper pillar are encapsulated to form a plastic encapsulation structure. The optical chip is placed on the top surface of the plastic encapsulation structure and above the electrical chip. The optical chip is electrically connected to the bumps on the back side of the electrical chip through a hybrid bonding process.

[0006] Furthermore, the chipset also includes a bridge chip embedded in a TMV copper pillar. The bridge chip, along with the electrical chip and the TMV copper pillar, are molded together to form a molded structure.

[0007] Furthermore, the bridging chip and electrical chip are laid flat within the plastic package structure.

[0008] Furthermore, the chipset also includes a high-bandwidth memory, which is externally located on the top surface of the plastic package and above the bridge chip. The high-bandwidth memory is electrically connected to the bridge chip via a flip-chip bonding process.

[0009] Furthermore, the chipset also includes a system-on-a-chip (SoC), which is externally mounted on the top surface of the plastic package and located above the bridge chip. The SoC is electrically connected to the bridge chip via flip-chip bonding.

[0010] Furthermore, an optical fiber array unit is provided on the top surface of the optical chip. The light-emitting end of the optical fiber core of the optical fiber array unit is aligned with the grating coupler array on the surface of the optical chip. The light is coupled into the on-chip optical waveguide through grating diffraction to realize the mutual transmission of optical signals.

[0011] Furthermore, BGA solder balls are provided at the bottom of the redistribution layer.

[0012] This invention discloses a method for fabricating an electronic integrated circuit based on double-sided bumps, comprising the following steps: S1: Prepare a redistribution layer on a temporary carrier board; S2: Fabricate TMV copper pillars on the redistribution layer, with the bottom of the TMV copper pillars electrically connected to the redistribution layer; S3: Embedding electrical chips in TMV copper pillars; S4: The electrical chip and TMV copper pillars are encapsulated to form a plastic encapsulation structure; S5: Grind the top surface of the encapsulated structure to expose the TMV copper pillars; S5: An external optical chip is placed on the top surface of the plastic-encapsulated structure. The optical chip is located above the electrical chip and is electrically connected to the back bumps of the electrical chip through hybrid bonding.

[0013] Furthermore, step S3 also includes embedding a bridging chip in the TMV copper pillar, and in step S4, the bridging chip, the electrical chip, and the TMV copper pillar are encapsulated together to form a plastic-encapsulated structure.

[0014] Furthermore, it also includes placing a high-bandwidth memory and / or system-on-a-chip externally on the top surface of the plastic-encapsulated structure, and electrically connecting the high-bandwidth memory and / or system-on-a-chip to the bridge chip through a flip-chip bonding process.

[0015] The beneficial effects of this invention are as follows: This invention proposes an electronic integrated circuit based on double-sided bumps and its fabrication method. The double-sided bumped electronic chip is embedded in a TMV and then directly connected to an optical chip. Signal interconnection is achieved through a redistribution layer and functional chips such as SOC and HBM. Compared with single-sided bumps, power supply and high-speed signals are physically isolated in layers, resulting in extremely low crosstalk and doubled fan-out density. Compared with traditional structures, this improves signal transmission quality, saves space, shortens interconnection distance, and increases signal exchange speed. Attached Figure Description

[0016] Figure 1 This is a structural diagram of an electronic integrated circuit based on double-sided bumps in an embodiment of this application; Figure 2 This is a flowchart illustrating the fabrication method of a double-sided bump-based electronic integrated circuit in this application.

[0017] In the diagram: 1-Rewiring layer; 2-TMV copper pillar; 3-Electrical chip; 4-Plastic encapsulation structure; 5-Optical chip; 6-Bridge chip; 7-High bandwidth memory; 8-System-on-a-chip; 9-Fiber optic array unit. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0020] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0021] In the description of this invention, it should be understood that the terms "upper," "lower," "inner," "outer," "left," "right," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are only used to facilitate the description of this invention and to simplify the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0022] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, terms such as "set" and "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0023] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0024] like Figure 1 As shown, in one embodiment, an electronic integrated circuit based on double-sided bumps includes: Redundancy layer 1 (RDL) is provided with TMV copper pillars 2, and the bottom of the TMV copper pillars 2 is electrically connected to the redundancy layer 1. The chipset includes an electrical chip 3 (EIC) and an optical chip 5 (PIC). The electrical chip 3 has bumps on both its front and back sides. The electrical chip 3 is embedded in the TMV copper pillar 2. The bumps on the front side of the electrical chip 3 are electrically connected to the redistribution layer 1. The electrical chip 3 and the TMV copper pillar 2 are encapsulated to form a plastic encapsulation structure 4. The optical chip 5 is placed on the top surface of the plastic encapsulation structure 4 and is located above the electrical chip 3. The optical chip 5 is electrically connected to the bumps on the back side of the electrical chip 3 through a hybrid bonding process.

[0025] In one embodiment, the chipset further includes a bridging chip 6, which is embedded in the TMV copper pillar 2. The bridging chip 6, together with the electrical chip 3 and the TMV copper pillar 2, is encapsulated to form a plastic encapsulation structure 4.

[0026] In one embodiment, the bridge die 6 and the electrical chip 3 are laid flat within the plastic encapsulation structure 4.

[0027] In one embodiment, the chipset further includes a high-bandwidth memory 7 (HBM), which is externally located on the top surface of the plastic package structure 4 and above the bridge chip 6. The high-bandwidth memory 7 is electrically connected to the bridge chip 6 via a flip-chip bonding process.

[0028] In one embodiment, the chipset further includes a system-on-a-chip (SOC) 8, which is externally disposed on the top surface of the plastic package structure 4 and located above the bridge chip 6. The system-on-a-chip 8 is electrically connected to the bridge chip 6 via a flip-chip bonding process.

[0029] In one embodiment, an optical fiber array unit (FAU) is disposed on the top surface of the optical chip 5, and the light-emitting end of the optical fiber core of the optical fiber array unit is aligned with the grating coupler array on the surface of the optical chip 5.

[0030] In one embodiment, BGA solder balls are provided at the bottom of the redistribution layer 1.

[0031] In one embodiment, a method for fabricating an electronic integrated circuit based on double-sided bumps includes the following steps: S1: Prepare redistribution layer 1 on a temporary substrate; S2: Fabricate TMV copper pillars 2 on redistribution layer 1, with the bottom of TMV copper pillars 2 electrically connected to redistribution layer 1; S3: Embed the electrical chip 3 in the TMV copper pillar 2; S4: After encapsulating the electrical chip 3 and the TMV copper pillar 2, a plastic encapsulation structure 4 is formed; S5: Grind the top surface of the encapsulated structure 4 to expose the TMV copper pillar 2; S5: An external optical chip 5 is placed on the top surface of the plastic encapsulation structure 4. The optical chip 5 is located above the electrical chip 3. The optical chip 5 is electrically connected to the back bump of the electrical chip 3 through hybrid bonding.

[0032] In one embodiment, step S3 further includes embedding a bridging chip 6 in the TMV copper pillar 2, and in step S4, the bridging chip 6, the electrical chip 3, and the TMV copper pillar 2 are encapsulated together to form a plastic encapsulation structure 4.

[0033] In one embodiment, a high-bandwidth memory 7 and / or a system-on-a-chip 8 are externally mounted on the top surface of the plastic-encapsulated structure 4, and the high-bandwidth memory 7 and / or system-on-a-chip 8 are electrically connected to the bridge chip 6 by a flip-chip bonding process.

[0034] This invention proposes an electronic integrated circuit based on double-sided bumps and its fabrication method. The double-sided bumped electronic chip is embedded in a TMV and then directly connected to an optical chip. Signal interconnection is achieved through a redistribution layer and functional chips such as SOC and HBM. Compared with single-sided bumps, power supply and high-speed signals are physically isolated in layers, resulting in extremely low crosstalk and doubled fan-out density. Compared with traditional structures, this improves signal transmission quality, saves space, shortens interconnection distance, and increases signal exchange speed.

[0035] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An electronic integrated circuit based on double-sided bumps, characterized in that, include: A redistribution layer is provided, and TMV copper pillars are provided on the redistribution layer. The bottom of the TMV copper pillars is electrically connected to the redistribution layer. The chipset includes an electrical chip and an optical chip. The electrical chip has bumps on both the front and back sides and is embedded in a TMV copper pillar. The bumps on the front side of the electrical chip are electrically connected to the redistribution layer. The electrical chip and the TMV copper pillar are encapsulated to form a plastic encapsulation structure. The optical chip is placed on the top surface of the plastic encapsulation structure and above the electrical chip. The optical chip is electrically connected to the bumps on the back side of the electrical chip through a hybrid bonding process.

2. The electronic integrated circuit based on double-sided bumps according to claim 1, characterized in that, The chipset also includes a bridge chip, which is embedded in the TMV copper pillars. The bridge chip, along with the electrical chip and the TMV copper pillars, are molded together to form a molded structure.

3. The electronic integrated circuit based on double-sided bumps according to claim 1, characterized in that, The bridging chip and electrical chip are laid flat within the plastic package structure.

4. An electronic integrated circuit based on double-sided bumps according to claim 1, characterized in that, The chipset also includes a high-bandwidth memory, which is externally located on the top surface of the plastic package and above the bridge chip. The high-bandwidth memory is electrically connected to the bridge chip via a flip-chip bonding process.

5. An electronic integrated circuit based on double-sided bumps according to claim 4, characterized in that, The chipset also includes a system-on-a-chip (SoC), which is externally mounted on the top surface of the plastic package and located above the bridge chip. The SoC is electrically connected to the bridge chip via flip-chip bonding.

6. An electronic integrated circuit based on double-sided bumps according to claim 4, characterized in that, The top surface of the optical chip is provided with an optical fiber array unit, and the light-emitting end of the optical fiber core of the optical fiber array unit is aligned with the grating coupler array on the surface of the optical chip.

7. An electronic integrated circuit based on double-sided bumps according to claim 1, characterized in that, BGA solder balls are located at the bottom of the redistribution layer.

8. A method for fabricating an electronic integrated circuit based on double-sided bumps as described in any one of claims 1-7, characterized in that, Includes the following steps: S1: Prepare a redistribution layer on a temporary carrier board; S2: Fabricate TMV copper pillars on the redistribution layer, with the bottom of the TMV copper pillars electrically connected to the redistribution layer; S3: Embedding electrical chips in TMV copper pillars; S4: The electrical chip and TMV copper pillars are encapsulated to form a plastic encapsulation structure; S5: Grind the top surface of the encapsulated structure to expose the TMV copper pillars; S5: An external optical chip is placed on the top surface of the plastic-encapsulated structure. The optical chip is located above the electrical chip and is electrically connected to the back bumps of the electrical chip through hybrid bonding.

9. The method for fabricating an electronic integrated circuit based on double-sided bumps according to claim 8, characterized in that, Step S3 also includes embedding a bridging chip in the TMV copper pillar, and in step S4, the bridging chip, the electrical chip, and the TMV copper pillar are encapsulated together to form a plastic encapsulation structure.

10. The method for fabricating an electronic integrated circuit based on double-sided bumps according to claim 8, characterized in that, It also includes placing high-bandwidth memory and / or system-on-a-chip externally on the top surface of the plastic-encapsulated structure, and electrically connecting the high-bandwidth memory and / or system-on-a-chip to the bridge chip through a flip-chip bonding process.

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