Substrate structure of electronic device and manufacturing method of electronic device

Abstract

The present disclosure provides a substrate structure of an electronic device and a manufacturing method of an electronic device. The substrate structure of the electronic device includes a substrate, a plurality of through holes, and a conductive member. The plurality of through holes penetrate the substrate, wherein a spacing between two adjacent ones of the plurality of through holes is less than or equal to 200 μm. The conductive member is disposed in at least one of the plurality of through holes. In a cross-sectional view of the substrate structure, the conductive member has, in sequence along a normal direction of the substrate, a bridge, a first portion, a second portion, and a third portion, the bridge is adjacent to a sidewall of the at least one of the plurality of through holes, the first portion is adjacent to a sidewall of the bridge, and the first portion has an average grain size less than or equal to 5 μm.

Description

Technical Field

[0001] This disclosure relates to an electronic device, and more particularly to the design and manufacturing method of an electronic device having a substrate structure. Background Technology

[0002] In the process of forming electronic devices, electroplating is used to form conductive elements in the vias of a substrate to create the substrate structure. However, the conductive elements formed using existing electroplating processes have relatively large grain sizes and / or different crystallinity. During the later stages of electronic device fabrication, the substrate structure is prone to cracking after thermal processing. This can lead to abnormal signal transmission in the formed electronic device, resulting in a decrease in the reliability of the electronic device. Summary of the Invention

[0003] This disclosure relates to a substrate structure for an electronic device, which can have relatively high reliability.

[0004] According to some embodiments disclosed herein, the substrate structure of an electronic device includes a substrate, a plurality of through-holes, and a conductive element. The plurality of through-holes penetrate the substrate, wherein the spacing between adjacent through-holes is less than or equal to 200 μm. The conductive element is disposed in at least one of the plurality of through-holes. In a cross-sectional view of the substrate structure, the conductive element has a bridge, a first portion, a second portion, and a third portion sequentially disposed along the normal direction of the substrate. The bridge is adjacent to the sidewall of at least one of the plurality of through-holes, the first portion is adjacent to the sidewall of the bridge, and the first portion has an average grain size less than or equal to 5 μm.

[0005] This disclosure relates to a method for manufacturing an electronic device that can produce an electronic device with relatively high reliability.

[0006] According to some embodiments of this disclosure, a method for manufacturing an electronic device includes the following steps: Providing a substrate structure, which includes the following steps: Providing a substrate having a plurality of through-holes; Performing an electroplating process to form a conductive element, including: performing a first electroplating process to form a bridging sidewall adjacent to at least one of the plurality of through-holes, followed by a second electroplating process to form other portions of the conductive element connecting the bridging in at least one of the plurality of through-holes. In a cross-sectional view of the substrate structure, the other portions of the conductive element have a first portion, a second portion, and a third portion sequentially disposed along the normal direction of the substrate, the first portion being adjacent to the sidewall of the bridging, and the first portion having an average grain size less than or equal to 5 μm. The spacing between adjacent through-holes is less than or equal to 200 μm. Performing at least one process to form an electronic device. The current density and electroplating time used in the first electroplating process are greater than the current density and electroplating time used in the second electroplating process. Attached Figure Description

[0007] Figure 1 This is a schematic flowchart of a method for manufacturing an electronic device according to an embodiment of the present disclosure;

[0008] Figure 2 This is a schematic cross-sectional view of a substrate structure in an electronic device according to an embodiment of the present disclosure;

[0009] Figure 3A Based on Figure 2 A scanning electron microscope photograph of an embodiment of region R1 in the image;

[0010] Figure 3B Based on Figure 2 A scanning electron microscope photograph of an embodiment of region R2 in the image;

[0011] Figure 4 This is a partial top view of a substrate structure in an electronic device according to an embodiment of the present disclosure;

[0012] Figure 5 This is a cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0013] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0014] This disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and for the sake of brevity, many of the drawings in this disclosure depict only a portion of the electronic device, and certain components in the drawings are not drawn to scale. Furthermore, the number and dimensions of the components in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0015] Throughout this disclosure and in the appended claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names. In the following description and claims, words such as “comprising,” “containing,” and “having” are open-ended terms and should therefore be interpreted as “containing but not limited to…”. Thus, when the terms “comprising,” “containing,” and / or “having” are used in the description of this disclosure, they specify the presence of the corresponding feature, area, step, operation, and / or component, but do not exclude the presence of one or more of the corresponding feature, area, step, operation, and / or component.

[0016] The directional terms used herein, such as "up," "down," "front," "back," "left," and "right," are for illustrative purposes only and are not intended to limit this disclosure. The accompanying drawings illustrate general features of the methods, structures, and / or materials used in specific embodiments. However, these drawings should not be construed as defining or limiting the scope or nature covered by these embodiments.

[0017] When a component (e.g., a membrane or region) is referred to as "on another component," it can be directly on that component, or there may be other components between them. Conversely, when a component is referred to as "directly on another component," there are no components between them. Furthermore, when a component is referred to as "on another component," the two components are vertically related in the planar view, and this component can be above or below the other component, depending on the orientation of the device.

[0018] The terms "equal to" or "same as", "substantially" or "approximately" are generally interpreted as being within 20% of a given value or range, or within 10%, 5% or 0.5% of a given value or range.

[0019] The ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify elements, do not in themselves imply or represent any prior ordinal number of that element (or those elements), nor do they represent the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another element with the same name. The claims and specification may not use the same terminology; therefore, a first element in the specification may be a second element in the claims.

[0020] It should be understood that the features in the following embodiments can be replaced to complete other embodiments without departing from the spirit of this disclosure. Features between the embodiments can be arbitrarily mixed and matched as long as they do not violate the spirit of the invention or conflict with it.

[0021] The electrical connections or couplings described in this disclosure can refer to direct or indirect connections. In the case of a direct connection, the endpoints of the two circuit components are directly connected or connected to each other by a conductor segment. In the case of an indirect connection, there are other suitable components between the endpoints of the two circuit components.

[0022] In this disclosure, the definitions of thickness, length, width, area, and roughness can be obtained through observation using optical microscopes, scanning electron microscopes, or transmission electron microscopes. On an uneven surface, the distance difference between the peaks and valleys of the surface undulations can be defined as the roughness of that surface. The surface undulations are observed under appropriate magnification, and the roughness range is determined by comparing the undulations using a sample of unit length (e.g., 10 micrometers). Here, "appropriate magnification" means a surface roughness (Rz) or average roughness (Ra) where at least 10 undulation peaks can be observed under this magnification.

[0023] The process of the electronic device disclosed herein can be provided, for example, through a wafer-level package (WLP) or panel-level package (PLP) process, which can be a chip-first or chip-last (RDL first) process.

[0024] The electronic devices disclosed herein can be applied to power modules, semiconductor packaging devices, display devices, light-emitting devices, backlight devices, antenna devices, sensing devices, or splicing devices, but are not limited thereto. The electronic devices may have peripheral systems such as drive systems, control systems, and light source systems to support display devices, antenna devices, wearable devices, automotive devices, or splicing devices. The electronic devices may include packaging devices such as High Bandwidth Memory (HBM) packages, Chip on Wafer on Substrate (CoWoS) packaging structures, System on a Chip (SoC), System in a Package (SiP), Antenna in Package (AiP), Co-packaged Optics (CPO), or various combinations of the above devices, but are not limited thereto.

[0025] Please refer to the following at the same time Figure 1 and Figure 2 In this embodiment, the electronic device 10c and the substrate structure of the electronic device 10c can be formed by performing the following steps, but this disclosure is not limited thereto.

[0026] Step (1): Form multiple through holes VH through the substrate 10.

[0027] The substrate 10 may be made of a suitable ceramic material, for example. For instance, the substrate 10 may be made of transparent materials, glass, alkali-free glass, or quartz glass. In this embodiment, the substrate 10 is a glass substrate and has surfaces 10s1 and 10s2 that are opposite each other in the Z direction (the normal direction of the substrate 10). A plurality of through-holes VH can be formed through the substrate 10 by performing appropriate etching and / or laser processes.

[0028] Step (2): Form a seed layer 20 in multiple vias VH of the substrate 10.

[0029] The seed layer 20 can be formed by chemical plating, electroplating, atomic deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or a combination thereof. In this embodiment, the seed layer 20 may include a stacked multilayer structure. It is worth noting that the seed layer 20 may also be formed on surfaces 10s1 and 10s2 of the substrate 10.

[0030] Step (3): Pre-treatment process of seed layer 20.

[0031] In some embodiments, the pretreatment process for the seed layer 20 may include a cleaning process and / or a micro-etching process and / or a heat treatment. For example, a first cleaning process may be performed to remove gaps and / or holes that appear when adjacent seed layers 20 are joined in the via VH. Subsequently, a micro-etching process may be performed on the seed layer 20 to give it a rough surface, which may improve the adhesion to subsequently formed film layers. A second cleaning process is then performed to remove impurities formed in the micro-etching process described above. After the pretreatment process of the seed layer 20, step (2) may be selectively repeated to form another seed layer, which may improve seed layer continuity.

[0032] Step (4): Perform the first electroplating process to form the bridge 20B of the conductive part 30.

[0033] In this embodiment, the first electroplating process is a pulse periodic reverse electroplating process (PPR). Specifically, the current flow time, the current stop time (electroplating time), and / or the current density can be independently adjusted to form a bridge 20B between adjacent seed layers 20 located in the via VH. After the first electroplating process, step (4-1), i.e., an annealing process, can be optionally performed.

[0034] Step (5): Perform the first inspection process.

[0035] In this embodiment, the first inspection process includes: (a) checking whether the bridge 20B is formed; and (b) checking the formation location of the bridge 20B. In step (a), if it is observed that the bridge 20B is not formed, the process returns to step (3). If it is observed that the bridge 20B is formed, step (b) is performed to check whether the bridge 20B is located in a region extending in the direction Z from the surface 10s1 of the substrate 10 for 0.25 times the thickness t of the substrate 10 to 0.75 times the thickness t of the substrate 10. If it is observed that the bridge 20B is not formed in the aforementioned region, the process returns to step (3).

[0036] In some embodiments, the condition of the bridging 20B can be confirmed by an optical inspection system or a scanning electron microscope, but this disclosure is not limited to these inspection methods. A cleaning process may be performed before the first inspection process.

[0037] Step (6): Perform a second electroplating process to form the other parts of the conductive component 30 connecting bridge 20B, which has now been completed.

[0038] The second electroplating process is, for example, a multi-stage DC electroplating process. Specifically, a conductive element 30 comprising a first portion 30a, a second portion 30b, and a third portion 30c can be formed by performing a three-stage DC electroplating process, wherein the first portion 30a, the second portion 30b, and the third portion 30c are arranged sequentially. Here, "arranged sequentially" means that the first portion 30a, the second portion 30b, and the third portion 30c are arranged sequentially along a direction perpendicular to the normal direction (direction Z) of the substrate (direction X or direction Y), and the first portion 30a is adjacent to the sidewall of the bridge 20B. In this embodiment, the first portion 30a and the second portion 30b are conformally formed in the through-hole VH, and the third portion 30c is filled into the through-hole VH. In other words, the conductive element 30 is fabricated by filling the through-hole VH using the bridge 20B as a foundation. The current density and electroplating time used in the first and second electroplating processes are different from each other. In this embodiment, the current density and plating time of the first electroplating process are each greater than the current density and plating time of the second electroplating process. In some embodiments, the average particle size of the third portion 30c is greater than or equal to the average particle size of the bridging 20B. The technical solution regarding particle size is detailed in the following embodiments.

[0039] In this embodiment, the current density increases sequentially in the three stages of the DC electroplating process, and the plating time decreases sequentially in the three stages of the DC electroplating process. Specifically, the current density in the DC electroplating process forming the first portion 30a is less than the current density in the DC electroplating process forming the second portion 30b, and the current density in the DC electroplating process forming the second portion 30b is less than the current density in the DC electroplating process forming the third portion 30c. Furthermore, the plating time in the DC electroplating process forming the first portion 30a is greater than the plating time in the DC electroplating process forming the second portion 30b, and the plating time in the DC electroplating process forming the second portion 30b is greater than the plating time in the DC electroplating process forming the third portion 30c.

[0040] By changing the current density and plating time in the three stages of the DC electroplating process, the crystallization state in the first part 30a, the second part 30b, and the third part 30c can be adjusted respectively. This can reduce the stress caused by the different thermal expansion coefficients between layers in subsequent processes, thereby reducing the possibility of cracks appearing in the conductive component 30 formed in the through-hole VH. After the second electroplating process, step (6-1), i.e., annealing, can be selectively performed to reduce the internal stress of the conductive component 30 and / or change the microstructure of the conductive component 30.

[0041] In some embodiments, the materials of the bridge 20B and the conductive element 30 may include copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tungsten (W), platinum (Pt), nickel (Ni), gold (Au), silver (Ag), or combinations thereof.

[0042] After the second electroplating process, a surface planarization step can be performed to make the surface of the conductive element 30 almost coplanar with the surface of the substrate 10. That is, in the Z direction, the distance between the surface of the conductive element 30 and the surface of the substrate 10 is less than or equal to 10 micrometers. Please refer to... Figure 3A After the planarization step, in a cross-sectional region extending 50 μm from the surface 30s1 of the conductive element 30 in the Z direction, the average grain size of the conductive element 30 is less than or equal to 5 μm, and the maximum grain size of the conductive element 30 is less than 20 μm. The conductive element 30 is formed by using a suitable instrument... Figure 3A The area of ​​the profile region circled in the center (its surface area is the product of the pore size W and 50 μm) was calculated. Please refer to [reference needed]. Figure 4 In the top-view surface region of surface 30s1 of conductive element 30 in direction Z and in the top-view surface region of surface 30s2 of conductive element 30 in direction Z (not shown in the figure), the average grain size of conductive element 30 is less than or equal to 6 μm. Please refer to... Figure 3BIt shows a cross-sectional area near the center of the conductive element 30. According to some embodiments, the maximum particle size in the cross-sectional area and the top surface area is no greater than 20 micrometers or no greater than 15 micrometers.

[0043] This completes the fabrication of substrate structure 100.

[0044] Step (7): Perform the second inspection process.

[0045] In this embodiment, the second inspection process includes: (c) inspecting a cross-sectional region extending 50 micrometers from the surface 30s1 of the conductive element 30 in the Z direction, to determine whether the average grain size of the conductive element 30 is less than or equal to 5 micrometers; and (d) inspecting the top-view surface regions of the surfaces 30s1 and 30s2 of the conductive element 30 in the Z direction, to determine whether the average grain size of the conductive element 30 is less than or equal to 6 micrometers. If the parameters defined in at least one of steps (c) and (d) are not met, it may be considered to return to step (6-1) or discard this substrate structure.

[0046] In some embodiments, multiple holes VH may be confirmed to meet the parameters defined in steps (c) and (d) by an optical inspection system or a scanning electron microscope, but this disclosure is not limited to these inspection methods.

[0047] After the second inspection process, the substrate structure 100 can be applied to subsequent processes to form a corresponding electronic device. According to some embodiments, a separate step may be included to cut the substrate structure 100 into multiple sub-substrates. For example, step (8) may be performed: at least one process is applied to the substrate structure 100 to form such a... Figure 5 The electronic device 10c shown is shown.

[0048] In this embodiment, at least one corresponding process may be performed on the substrate structure 100 to form an electronic device 10c, which may include performing processes for forming a circuit structure ES and forming electronic components 2 on the substrate structure 100, but this disclosure is not limited thereto.

[0049] Please refer to Figure 5 In this embodiment, the circuit structure ES is disposed on the surface 10s1 of the substrate 10 and at least partially overlaps a plurality of vias VH. In some embodiments, the circuit structure ES includes at least one insulating layer IL and at least one conductive layer M. The material of the insulating layer IL may include an Ajinomoto build-up film (ABF), photosensitive polyimide (PSPI), polyimide (PI), epoxy resin, or other suitable insulating materials. The conductive layer M may include a suitable conductive material similar to the conductive element 30.

[0050] The thickness t of substrate 10 is 0.6 mm to 2 mm, and the coefficient of thermal expansion of substrate 10 is 1 ppm / K to 10 ppm / K. The minimum aperture d of the plurality of vias VH is 90 μm to 110 μm, and the aspect ratio (AR) of the plurality of vias VH is 8 to 20. The spacing p between two adjacent vias VH is less than or equal to 200 μm. In this disclosure, "adjacent" or "nearby" means that two of the plurality of elements (e.g., multiple vias VH) are arranged along one direction and have a minimum distance or minimum spacing.

[0051] Please refer to Figure 2 Before the annealing process, in a cross-sectional region extending 50 micrometers from the surface 30s1 of the conductive element 30 in direction Z (or from the surface 30s2 in the opposite direction to Z), the average grain size of the conductive element 30 is less than or equal to 5 μm. Specifically, the average grain size of the bridge 20B and the first portion 30a is less than or equal to 5 μm, the average grain size of the second portion 30b is greater than or equal to the average grain size of the first portion 30a, and the average grain size of the third portion 30c is greater than or equal to the average grain size of the first portion 30a. In some embodiments, after the annealing process or after forming the circuit structure ES, the average grain size of the third portion 30c of the conductive element 30 is greater than or equal to 2 μm and less than or equal to one-fifth of the minimum aperture d of the plurality of vias VH, which can reduce the risk of substrate 10 cracking. The bridge 20B referred to in this disclosure is a conductive element 30 with a continuous structure adjacent to the sidewall of the through hole VH and at the center of the through hole VH (where the width of the through hole VH is the smallest). The first part 30a is within 10 micrometers from the sidewall of the bridge 20B, the second part 30b is within 15 micrometers from the sidewall of the first part 30a, and the rest is the third part 30c.

[0052] In this embodiment, the multilayer conductive layer M in the circuit structure ES includes pads PAD1 and PAD2. Pad PAD1 is located, for example, on one side of surface 10s1 of the substrate 10, and is a portion of the multilayer conductive layer M furthest from surface 10s1 of the substrate 10, and is exposed by the multilayer insulating layer IL. Pad PAD2 is located, for example, on one side of surface 10s2 of the substrate 10. In this embodiment, at least a portion of the multilayer conductive layer M is disposed in a plurality of vias VH to establish an electrical connection path between pads PAD1 and pads PAD2.

[0053] In this embodiment, the circuit structure ES includes a redistribution structure, which can be used to redistribute lines and / or further increase the fan-out area of ​​the lines. The purpose of the redistribution structure is to extend the connections to a wider spacing or to redistribute the connections to another connection with a different spacing. Based on this, identical or different electronic components 2 can be disposed on and electrically connected to the circuit structure ES. External components CB can be disposed on the surface 10s2 of the substrate 10 and electrically connected to the circuit structure ES via vias VH, allowing electronic components 2 to be electrically connected to external components CB through the circuit structure ES. External components CB may include circuit boards, IC carriers, or other suitable components. Methods for forming the circuit structure ES include electroplating, chemical plating, etching, laser processing, photolithography, annealing, or other suitable methods.

[0054] In this embodiment, the electronic device 10c further includes a buffer layer BF. The material of the buffer layer BF may include suitable organic and / or inorganic materials. The material of the buffer layer BF may include polyimide, parylene, benzocyclobutene (BCB), epoxy resin, benzocyclobutene (BCB), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-containing compounds, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the buffer layer BF may include a multilayer stacked structure of inorganic / organic / inorganic layers. In some embodiments, the buffer layer BF may cover the sides of the substrate 10 and the sidewalls of the via VH, filling pits, unevenness, or microcracks generated on the corresponding surface of the substrate 10 during the manufacturing process, reducing the risk of substrate 10 breakage.

[0055] Multiple electronic components 2 are disposed on, for example, the circuit structure ES and electrically connected to the circuit structure ES. In this embodiment, the multiple electronic components 2 include two electronic components 2a and 2b, but this disclosure is not limited to these quantities. Electronic components 2a and 2b may be, for example, high-bandwidth memory, dynamic random access memory (DRAM), static random access memory (SRAM), cache memory, graphics processing unit (GPU), central processing unit (CPU), digital signal processor (DSP), or application-specific integrated circuit (ASIC), but this disclosure is not limited thereto. Electronic component 2a can be electrically connected to the circuit structure ES through contact pad PAD3 and at least a portion of the multiple connection units CU1, and electronic component 2b can be electrically connected to the circuit structure ES through at least another portion of the multiple connection units CU1.

[0056] In this embodiment, the electronic device 10c further includes a plurality of connection units CU1 disposed on the circuit structure ES, so that the circuit structure ES can be electrically connected to the electronic component 20 through the plurality of connection units CU1. The material of the plurality of connection units CU1 may include tin, copper, nickel, silver, gold, gallium or other suitable materials.

[0057] In this embodiment, the electronic device 10c further includes an encapsulation layer MC surrounding the substrate 10 and surrounding a plurality of electronic components 2. In this embodiment, the encapsulation layer MC may expose a portion of the plurality of electronic components 2. Specifically, the upper surface of the encapsulation layer MC may be flush with the non-active surfaces of the plurality of electronic components 2, but this disclosure is not limited thereto.

[0058] In this embodiment, the electronic device 10c further includes an adhesive layer UF1 disposed between the substrate 10 and the electronic component 2, and filling the space between adjacent connecting components CU1. In some embodiments, the adhesive layer UF1 may be surrounded by an encapsulation layer MC.

[0059] In this embodiment, the electronic device 10c further includes a plurality of connection units CU2 disposed on one side of the surface 10s2 of the substrate 10 and electrically connected to the pads PAD2 in the circuit structure ES, so that the circuit structure ES can be electrically connected to the external component CB through the plurality of connection units CU2. In some embodiments, the external component CB can be electrically connected through the alignment mark AM in the substrate 10. The material of the plurality of connection units CU2 may be the same as or similar to the material of the plurality of connection units CU1.

[0060] In this embodiment, the electronic device 10c further includes an adhesive layer UF2 disposed between the substrate 10 and the external component CB, and filling the space between adjacent connecting components CU2. In some embodiments, the adhesive layer UF2 may contact the sidewall of the encapsulation layer MC. The materials of the encapsulation layer MC, the adhesive layer UF1, and the adhesive layer UF2 may include suitable inorganic or organic materials.

[0061] In this embodiment, the electronic device 10c further includes an interposer INP, for example, comprising a core layer CL, vias V, an insulating layer IL1', a conductive layer M1', an insulating layer IL2', and a conductive layer M2'. The core layer CL may be made of, for example, silicon, glass, or an organic material. In some embodiments, the edges of the core layer CL may have chamfers or rounded corners, but this disclosure is not limited thereto. For example, multiple vias V are provided and penetrate the core layer CL. In some embodiments, the vias V may also include a filling material FI disposed on the sidewalls of the vias V. The insulating layer IL1' and the conductive layer M1' are disposed, for example, above the core layer CL and located in the Z direction between the core layer CL and the substrate structure 100, wherein the insulating layer IL1' and the conductive layer M1' may be combined to form a redistribution structure so that the conductive elements 30 in the substrate structure 100 can be electrically connected to the vias V in the core layer CL. The insulating layer IL2' and the conductive layer M2' are located in the Z direction between the core layer CL and the external component CB. The insulating layer IL2' and the conductive layer M2' can be combined to form a redistribution structure so that the external component CB can be electrically connected to the through-hole V in the core layer CL through the connection unit CU3. According to some embodiments, multiple electronic components 2 can be electrically connected to the circuit board CB through the interposer layer INP.

[0062] According to some embodiments, the interposer layer INP may include an embedded die ED disposed in a groove RE of the core layer CL, which may be electrically connected to a through-hole V in the core layer CL via a conductive layer M1'.

[0063] In this embodiment, the electronic device 10c further includes a plurality of connection units CU3 disposed below the interposer layer INP and electrically connected to the conductive layer M2' in the interposer layer INP, so that the interposer layer INP is electrically connected to the external component CB through the plurality of connection units CU3.

[0064] In summary, in the manufacturing methods of electronic devices provided in some embodiments disclosed herein, by adjusting the current density and / or electroplating time in the electroplating process, the grain size of the material of the conductive parts formed in the through-hole can be limited, which can reduce the possibility of the substrate structure cracking after thermal processing, thereby improving the yield of manufacturing electronic devices.

Claims

1. A substrate structure for an electronic device, characterized in that, The substrate structure includes: substrate; Multiple through-holes penetrate the substrate, wherein the spacing between adjacent through-holes is less than or equal to 200 μm; and A conductive element is disposed in at least one of the plurality of through holes. In the cross-sectional view of the substrate structure, the conductive element has a bridge, a first portion, a second portion, and a third portion arranged sequentially along the normal direction of the substrate. The bridge is adjacent to the sidewall of at least one of the plurality of through holes, the first portion is adjacent to the sidewall of the bridge, and the first portion has an average grain size of less than or equal to 5 μm.

2. The substrate structure of the electronic device according to claim 1, wherein the second portion has an average grain size of less than or equal to 5 μm.

3. The substrate structure of the electronic device according to claim 1, wherein the substrate is a glass substrate.

4. The substrate structure of the electronic device according to claim 1, wherein the thickness of the substrate is 0.6 mm to 1 mm, and the minimum aperture of the plurality of through holes is 90 μm to 110 μm.

5. The substrate structure of the electronic device according to claim 4, wherein the average grain size of the third portion is greater than 3 μm and less than or equal to one-fifth of the minimum aperture of the plurality of vias.

6. The substrate structure of the electronic device according to claim 1, wherein the coefficient of thermal expansion of the substrate is 2.5 ppm / K to 10 ppm / K.

7. The substrate structure of the electronic device according to claim 1, wherein the aspect ratio of the plurality of through holes is 8 to 20.

8. A method for manufacturing an electronic device, characterized in that, include: A substrate structure is provided, wherein the step of providing the substrate structure includes: Provide a substrate with multiple through holes; Performing an electroplating process to form a conductive element in at least one of the plurality of through holes includes: Perform a first electroplating process to form a bridging of conductive elements in at least one of the plurality of through holes; and A second electroplating process is performed to form other portions of the conductive element in at least one of the plurality of through holes, connecting the bridge. In a cross-sectional view of the substrate structure, the other portions of the conductive element have a first portion, a second portion, and a third portion sequentially arranged along the normal direction of the substrate. The first portion is adjacent to the sidewall of the bridge and has an average grain size of less than or equal to 5 μm. The spacing between adjacent vias in the plurality of vias is less than or equal to 200 μm. The substrate structure is subjected to at least one process to form the electronic device. The current density and plating time used in the first electroplating process are greater than those used in the second electroplating process.

9. The method for manufacturing an electronic device according to claim 8, wherein the first electroplating process includes a pulsed periodic reverse electroplating process, and the second electroplating process includes a multi-stage DC electroplating process.

10. The method for manufacturing an electronic device according to claim 9, wherein the second electroplating process comprises a three-stage DC electroplating process, wherein the current density increases sequentially in the three-stage DC electroplating process, and the electroplating time decreases sequentially in the three-stage DC electroplating process.

Images