Semiconductor device with reduced warpage

Abstract

A semiconductor device includes a substrate, a first via penetrating the substrate, a second via penetrating the substrate, and an insulating pattern surrounding the first via and the second via, wherein the insulating pattern includes a first portion between the first via and the second via, the first portion includes a first pattern portion and a second pattern portion overlapping the first pattern portion, and a width of the first pattern portion is smaller than a width of the second pattern portion.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2025-0044470, filed on April 7, 2025, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a semiconductor device, and more specifically, to a semiconductor device including an insulating layer surrounding a via and an insulating pattern on the insulating layer. Background Technology

[0004] Semiconductor devices are highly regarded as important components in the electronics industry due to their characteristics such as miniaturization, versatility, and / or low manufacturing cost. Semiconductor devices can be classified into semiconductor memory devices for storing logic data, semiconductor logic devices for computing and processing logic data, and hybrid semiconductor devices that include both memory and logic components.

[0005] Recently, with the increasing speed and low power consumption of electronic devices, the semiconductor devices built into them also require high operating speeds and low operating voltages. To meet these demands, semiconductor devices with higher integration levels are needed. However, as semiconductor devices become more highly integrated, their electrical characteristics and yield may decrease. For example, higher component integration can lead to warping, thereby reducing the stability of semiconductor devices. Therefore, extensive research is underway to improve the electrical characteristics and yield of semiconductor devices. Summary of the Invention

[0006] Some embodiments of the present disclosure provide a semiconductor device with improved electrical characteristics and reliability.

[0007] According to some embodiments, a semiconductor device includes: a substrate; a first via penetrating the substrate; a second via penetrating the substrate; and an insulating pattern surrounding the first via and the second via, wherein the insulating pattern includes a first portion between the first via and the second via, the first portion including a first pattern portion and a second pattern portion overlapping the first pattern portion, and the width of the first pattern portion is smaller than the width of the second pattern portion.

[0008] According to some embodiments, a semiconductor device includes: a substrate; a first via penetrating the substrate; a second via penetrating the substrate; and an insulating pattern surrounding the first and second vias, wherein the insulating pattern includes a first portion between the first and second vias, the first portion including a first pattern portion and a second pattern portion overlapping the first pattern portion, the second pattern portion including a first part, a second part, and a third part, the second part of the second pattern portion overlapping the first pattern portion, the first and third parts of the second pattern portion being spaced apart from each other, the second part of the second pattern portion being between the first and third parts, and the height of the surface of the first pattern portion being lower than the height of the surface of the first part of the second pattern portion and the surface of the third part of the second pattern portion.

[0009] According to some embodiments, a semiconductor device includes: a substrate; a first via penetrating the substrate; a second via penetrating the substrate; an insulating pattern on the surface of the substrate and surrounding the first via; and an insulating layer on the substrate, wherein the insulating pattern includes a first portion between the first via and the second via, the first portion including a first pattern portion and a second pattern portion overlapping the first pattern portion, and the first pattern portion protruding from the second pattern portion.

[0010] According to some embodiments of this disclosure, a method for manufacturing a semiconductor device includes: forming a first via and a second via penetrating a substrate, the top surface of the substrate including a first portion spaced apart from the first via and the second via and a second portion contacting the first via; and forming an insulating pattern contacting the first portion of the substrate and spaced apart from the second portion of the substrate, wherein forming the insulating pattern includes: forming an insulating layer contacting the first and second portions of the substrate; exposing the first portion of the top surface of the substrate by partially removing the insulating layer; and forming the insulating pattern contacting the insulating layer and the first portion of the top surface of the substrate, and the insulating pattern comprising an insulating material different from the insulating layer.

[0011] According to some embodiments, a semiconductor device includes: an insulating layer surrounding a first via and a second via, wherein a first portion is spaced apart from the first via and the second via, and the insulating layer includes a first portion between a first patterned portion and the first via, and a second portion between a second patterned portion and the first via.

[0012] According to some embodiments, the insulating pattern and insulating layer include different insulating materials.

[0013] According to some embodiments, the surface of the second pattern portion is connected to the wall of the first pattern portion and the wall of the second pattern portion.

[0014] According to some embodiments, the insulating layer is in contact with the surface of the substrate, the wall of the first via, the wall of the first patterned portion, and the wall of the second patterned portion.

[0015] According to some embodiments, the surface of the second patterned portion is coplanar with the surface of the insulating layer.

[0016] According to some embodiments, the insulating layer is in contact with the surface of the second patterned portion.

[0017] According to some embodiments, the first via, the second via, and the first portion are spaced apart from each other in a first direction. The semiconductor device also includes a third via that is spaced apart from the first and second vias in a second direction intersecting the first direction. The insulating pattern also includes a planarization portion between the first and third vias, the planarization portion being spaced apart from the substrate, and the first portion being in contact with the substrate.

[0018] According to some embodiments, the first and second surfaces of the planarized portion are flat.

[0019] According to some embodiments, the first pattern portion penetrates the surface of the substrate, and the surface of the first pattern portion is spaced apart from the surface of the substrate. Attached Figure Description

[0020] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0021] Figure 1A It is a plan view of a semiconductor device according to some embodiments;

[0022] Figure 1B According to some embodiments Figure 1A A cross-sectional view taken from line I-I';

[0023] Figure 1C According to some embodiments Figure 1A A magnified view of region A;

[0024] Figure 1D According to some embodiments Figure 1C A cross-sectional view taken from line II-II';

[0025] Figure 1E According to some embodiments Figure 1C A cross-sectional view taken from line III-III';

[0026] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H , Figure 2I , Figure 2J , Figure 2K and Figure 2L The description of some embodiments is used for manufacturing according to Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E A diagram of a method for developing semiconductor devices;

[0027] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E This is a diagram illustrating a semiconductor device according to some embodiments;

[0028] Figure 4A , Figure 4B and Figure 4C This is a diagram illustrating a semiconductor device according to some embodiments;

[0029] Figure 5 This is a diagram illustrating a semiconductor device according to some embodiments;

[0030] Figure 6A , Figure 6B and Figure 6C This is a diagram illustrating a semiconductor device according to some embodiments;

[0031] Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E , Figure 7F , Figure 7G and Figure 7H The description of some embodiments is used for manufacturing according to Figure 6A , Figure 6B and Figure 6C A diagram of a method for developing semiconductor devices;

[0032] Figure 8 This is a diagram illustrating a semiconductor device according to some embodiments;

[0033] Figure 9 This is a diagram illustrating a semiconductor device according to some embodiments;

[0034] Figure 10 It is a diagram illustrating a semiconductor device according to some embodiments; and

[0035] Figure 11 This is a diagram illustrating a semiconductor device according to some embodiments. Detailed Implementation

[0036] Hereinafter, a semiconductor device according to an embodiment of the present disclosure and a method for manufacturing the semiconductor device will be described in detail with reference to the accompanying drawings.

[0037] It will be understood that although the terms first, second, third, fourth, etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0038] It will be understood that when a component or layer is referred to as being "above," "on top of," "below," "under," "connected to," or "coupled to" another component or layer, it can be directly connected to or coupled to that other component or layer, or there can be intermediate components or layers. Conversely, when a component is referred to as being "directly above," "on top of," "below," "under," "under," "directly connected to," or "directly coupled to" another component or layer, there are no intermediate components or layers.

[0039] A layer can be described as having an upper surface and a lower surface. As those skilled in the art will understand, the surface of a layer can also be described as a first surface and a second surface, wherein the first surface can be one of the upper surface and the lower surface of the layer, and the second surface can be the other of the upper surface and the lower surface of the layer.

[0040] The instruction manual uses degree terms including "substantially". In one or more examples, when the specified parameter X can be substantially the same as parameter Y, the term "substantially" can be understood as X being within 10% of Y.

[0041] Figure 1A It is a plan view of a semiconductor device according to some embodiments. Figure 1B It is along Figure 1A The cross-sectional view taken from line I-I'. Figure 1C yes Figure 1A A magnified view of region A. Figure 1D It is along Figure 1C The cross-sectional view taken from line II-II'. Figure 1E It is along Figure 1C The cross-sectional view taken from line III-III'.

[0042] refer to Figure 1Aand Figure 1B The system may include a stacked structure 100, a substrate chip 200, a lower adhesive layer 300, a lower connection terminal 400, and a molding layer 500. The lower adhesive layer 300 and the molding layer 500 may include insulating materials. For example, the lower adhesive layer 300 and the molding layer 500 may include polymer materials. The lower connection terminal 400 may be disposed on the bottom surface of the substrate chip 200. The lower connection terminal 400 may include conductive materials. The lower connection terminal 400 may be electrically connected to the substrate chip 200.

[0043] According to some embodiments, the stacked structure 100 may include a first semiconductor chip 110, a second semiconductor chip 120, a third semiconductor chip 130, and an upper semiconductor chip 140. The stacked structure 100 may include interlayer connection terminals 150, a first interlayer adhesive layer 161, a second interlayer adhesive layer 162, and a third interlayer adhesive layer 163. The interlayer connection terminals 150 may be disposed on the top surface of the substrate chip 200 and the upper surfaces of the first semiconductor chip 110, the second semiconductor chip 120, and the third semiconductor chip 130. The first interlayer adhesive layer 161, the second interlayer adhesive layer 162, or the third interlayer adhesive layer 163 may partially cover the interlayer connection terminals 150. In one or more examples, the lower adhesive layer 300 and each of the interlayer adhesive layers 161, 162, and 163 may be formed of the same material. In one or more examples, the lower adhesive layer 300 and at least one of the interlayer adhesive layers 161, 162, and 163 may be formed of different materials. In one or more examples, each of the lower adhesive layer 300 and the interlayer adhesive layers 161, 162 and 163 may have the same size and / or shape. In one or more examples, at least one of the lower adhesive layer 300 and the interlayer adhesive layers 161, 162 and 163 may have different sizes and / or shapes.

[0044] Interlayer connection terminal 150 may include a conductive material. Interlayer connection terminal 150 can electrically connect the first semiconductor chip 110 to the substrate chip 200. Interlayer connection terminal 150 can electrically connect the first semiconductor chip 110 to the second semiconductor chip 120. Interlayer connection terminal 150 can electrically connect the third semiconductor chip 130 to the second semiconductor chip 120. Interlayer connection terminal 150 can electrically connect the third semiconductor chip 130 to the upper semiconductor chip 140.

[0045] The first to third interlayer adhesive layers 161, 162, and 163 may include an insulating material. For example, the first to third interlayer adhesive layers 161, 162, and 163 may include a polymer material.

[0046] The stacked structure 100 may include three or fewer semiconductor chips, or five or more semiconductor chips. The first to third semiconductor chips 110, 120, and 130 and the upper semiconductor chip 140 may be semiconductor chips including memory integrated circuits. For example, the first to third semiconductor chips 110, 120, and 130 and the upper semiconductor chip 140 may be semiconductor chips including DRAM.

[0047] The first semiconductor chip 110 may include a first substrate 111, a first lower insulating layer 112, a first upper insulating layer 113, a first insulating pattern 114, a first line structure 115, a first lower pad 116, and a through-hole 117.

[0048] The first substrate 111 may be a semiconductor substrate. For example, the first substrate 111 may include silicon, germanium, silicon-germanium, GaP, or GaAs. According to some embodiments, the first substrate 111 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. The first substrate 111 may be in the form of a plate extending along a plane extending in a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may intersect each other. For example, the first direction D1 and the second direction D2 may be horizontal directions perpendicular to each other.

[0049] The first substrate 111 may include a top surface 111_T and a bottom surface 111_B. Circuits, including transistors, diodes, capacitors, etc., may be formed on the bottom surface 111_B of the first substrate 111. The bottom surface 111_B of the first substrate 111 may be the front surface of the semiconductor substrate. Forming circuits on the bottom surface 111_B of the first substrate 111 may include performing a front-end (FEOL) process. The top surface 111_T of the first substrate 111 may be a rear surface opposite to the front surface on which the FEOL process is performed. As understood by those skilled in the art, the FEOL process includes an IC manufacturing process in which components (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate.

[0050] A first lower insulating layer 112 may be disposed on the bottom surface 111_B of the first substrate 111. The first lower insulating layer 112 may include an insulating material. For example, the first lower insulating layer 112 may include an oxide. A first line structure 115 may be disposed in the first lower insulating layer 112. The first lower insulating layer 112 may surround the first line structure 115. The first line structure 115 may include a conductive material. The first line structure 115 may include multiple lines, contacts, or vias. A first lower pad 116 may be disposed on the first line structure 115. The first lower pad 116 may include a conductive material. The first lower pad 116 can electrically connect the first line structure 115 to the interlayer connection terminal 150.

[0051] The first upper insulating layer 113 may be disposed on the top surface 111_T of the first substrate 111. The first upper insulating layer 113 and the first insulating pattern 114 may cover the top surface 111_T of the first substrate 111. The first insulating pattern 114 may be disposed on the first upper insulating layer 113.

[0052] The first upper insulating layer 113 may include an insulating material. The first insulating pattern 114 may include an insulating material different from that of the first upper insulating layer 113. For example, the first upper insulating layer 113 may include an oxide, and the first insulating pattern 114 may include a nitride.

[0053] The through-hole 117 of the first semiconductor chip 110 can penetrate the first substrate 111. The through-hole 117 of the first semiconductor chip 110 can extend in the third direction D3. The through-hole 117 of the first semiconductor chip 110 can penetrate the top surface 111_T and the bottom surface 111_B of the first substrate 111. The through-hole 117 of the first semiconductor chip 110 can penetrate the bottom surface of the first upper insulating layer 113. The through-hole 117 of the first semiconductor chip 110 may include a first through-hole 117_1, a second through-hole 117_2, a third through-hole 117_3, a fourth through-hole 117_4, and a fifth through-hole 117_5. The second through-hole 117_2 and the fourth through-hole 117_4 can be spaced apart from each other in the first direction D1, with the first through-hole 117_1 located between the second through-hole 117_2 and the fourth through-hole 117_4. The third through-hole 117_3 and the fifth through-hole 117_5 can be spaced apart from each other in the second direction D2, with the first through-hole 117_1 located between the third through-hole 117_3 and the fifth through-hole 117_5. The second through-hole 117_2, the first through-hole 117_1, and the fourth through-hole 117_4 can be arranged sequentially in the first direction D1. The fifth through-hole 117_5, the first through-hole 117_1, and the third through-hole 117_3 can be arranged sequentially in the second direction D2.

[0054] The through-hole 117 of the first semiconductor chip 110 may be spaced apart from the first insulating pattern 114. The first insulating pattern 114 may include a side portion 114_S disposed between the through-holes.

[0055] A through-hole 117 may be partially disposed in a first upper insulating layer 113 between a first substrate 111 and a first insulating pattern 114. The through-hole 117 of the first semiconductor chip 110 may include a conductive material. The through-hole 117 of the first semiconductor chip 110 may be electrically connected to a first lower pad 116. The first upper insulating layer 113 and the first insulating pattern 114 may surround the through-hole 117 of the first semiconductor chip 110.

[0056] The second semiconductor chip 120, the third semiconductor chip 130, and the upper semiconductor chip 140 can be sequentially stacked on the first semiconductor chip 110 in a third direction D3. The third direction D3 can intersect with the first direction D1 and the second direction D2. For example, the third direction D3 can be a vertical direction perpendicular to the first direction D1 and the second direction D2. The first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 130, the upper semiconductor chip 140, and the substrate chip 200 can overlap or at least partially overlap each other in the third direction D3.

[0057] The first interlayer adhesive layer 161 can be disposed on the first upper insulating layer 113 and the first insulating pattern 114. The second semiconductor chip 120 can be disposed on the first interlayer adhesive layer 161. The second semiconductor chip 120 can be similar to the first semiconductor chip 110. The second semiconductor chip 120 may include a second substrate 121, a second lower insulating layer 122, a second upper insulating layer 123, a second insulating pattern 124, a second line structure 125, a second lower pad 126, and a through-hole 127. The shapes of the second upper insulating layer 123 and the second insulating pattern 124 can be similar to the shapes of the first upper insulating layer 113 and the first insulating pattern 114.

[0058] The second interlayer adhesive layer 162 may be disposed on the second upper insulating layer 123 and the second insulating pattern 124. A third semiconductor chip 130 may be disposed on the second interlayer adhesive layer 162. The third semiconductor chip 130 may be similar to the first semiconductor chip 110 and the second semiconductor chip 120. The third semiconductor chip 130 may include a third substrate 131, a third lower insulating layer 132, a third upper insulating layer 133, a third insulating pattern 134, a third line structure 135, a third lower pad 136, and a through-hole 137. The shapes of the third upper insulating layer 133 and the third insulating pattern 134 may be similar to the shapes of the first upper insulating layer 113 and the first insulating pattern 114. However, as those skilled in the art will understand, the embodiments are not limited to this configuration. For example, the shape of the third upper insulating layer 133 may be different from the shape of the first upper insulating layer 113, or the shape of the third insulating pattern 134 may be different from the shape of the first insulating pattern 114.

[0059] The third interlayer adhesive layer 163 may be disposed on the third upper insulating layer 133 and the third insulating pattern 134. The upper semiconductor chip 140 may be disposed on the third interlayer adhesive layer 163. Except as described below, the upper semiconductor chip 140 may be similar to the first to third semiconductor chips 110, 120 and 130. However, as those skilled in the art will understand, at least one of the semiconductor chips 110, 120, 130 and 140 may be different from the other semiconductor chips.

[0060] The upper semiconductor chip 140 may include a fourth substrate 141, a fourth lower insulating layer 142, a fourth upper insulating layer 143, a fourth insulating pattern 144, a fourth line structure 145, and a fourth lower pad 146. The shapes of the fourth upper insulating layer 143 and the fourth insulating pattern 144 may be similar to the shapes of the first upper insulating layer 113 and the first insulating pattern 114. However, as those skilled in the art will understand, the embodiments are not limited to this configuration. For example, the shape of the fourth upper insulating layer 143 may be different from the shape of the first upper insulating layer 113, or the shape of the fourth insulating pattern 144 may be different from the shape of the first insulating pattern 114.

[0061] The top surfaces of the fourth upper insulating layer 143, the fourth insulating pattern 144, and the molding layer 500 may be coplanar or substantially coplanar with each other. According to some embodiments, the upper semiconductor chip 140 may include a fourth substrate 141 and may also include through-holes electrically connected to the fourth line structure 145. The molding layer 500 may cover the substrate chip 200, the first to third semiconductor chips 110, 120, and 130, and the upper semiconductor chip 140.

[0062] Except as described below, the substrate chip 200 may be similar to the first to third semiconductor chips 110, 120, and 130, and the upper semiconductor chip 140. The substrate chip 200 may include a substrate 210, a fifth lower insulating layer 220, a fifth upper insulating layer 230, a fifth insulating pattern 240, a through-hole 250, and a fifth line structure 260. The shapes of the fifth upper insulating layer 230 and the fifth insulating pattern 240 may be similar to the shapes of the first upper insulating layer 113 and the first insulating pattern 114. However, as those skilled in the art will understand, the substrate chip 200 and at least one of the semiconductor chips 110, 120, 130, and 140 may differ from the other chips.

[0063] The substrate 210 may be a semiconductor substrate. A through-hole 250 of the substrate chip 200 may penetrate the substrate 210. A fifth lower insulating layer 220 may be disposed on the bottom surface of the substrate 210. A fifth upper insulating layer 230 may be disposed on the top surface of the substrate 210. The width of the substrate 210 in the first direction D1 may be greater than the width of the first to third semiconductor chips 110, 120, and 130 in the first direction D1.

[0064] The substrate chip 200 may be a buffer chip. Logic circuitry may be disposed on the bottom surface of the substrate chip 200. The substrate chip 200 may be disposed on one side of the stacked structure 100 to transmit signals from the first semiconductor chip to the third semiconductor chips 110, 120, and 130 and the upper semiconductor chip 140 to the outside, and to transmit external signals from the first semiconductor chip to the third semiconductor chips 110, 120, and 130 and the upper semiconductor chip 140. According to some embodiments, the semiconductor device may be a high-bandwidth memory (HBM) package including stacked memory devices.

[0065] refer to Figure 1C , Figure 1D and Figure 1E The side portion 114_S may include a first side portion 114_S1, a second side portion 114_S2, a third side portion 114_S3, and a fourth side portion 114_S4. Except as described below, the first to fourth side portions 114_S1, 114_S2, 114_S3, and 114_S4 may be similar to each other. The corner portion 114_C may include a first corner portion 114_C1 and a second corner portion 114_C2.

[0066] The first side portion 114_S1 and the third side portion 114_S3 can be spaced apart from each other in the second direction D2 by a first through hole 117_1. The second side portion 114_S2 and the fourth side portion 114_S4 can be spaced apart from each other in the first direction D1, with the first through hole 117_1 between the second side portion 114_S2 and the fourth side portion 114_S4. The first side portion 114_S1 can be disposed between the first through hole 117_1 and the third through hole 117_3. The second side portion 114_S2 can be disposed between the first through hole 117_1 and the fourth through hole 117_4. The third side portion 114_S3 can be disposed between the first through hole 117_1 and the fifth through hole 117_5. The fourth side portion 114_S4 can be disposed between the first through hole 117_1 and the second through hole 117_2.

[0067] The first upper insulating layer 113 may be partially disposed between the first side portion 114_S1 and the third side portion 114_S3, and between the second side portion 114_S2 and the fourth side portion 114_S4.

[0068] The first corner portion 114_C1 and the second corner portion 114_C2 may be spaced apart from each other in the second direction D2, and the fourth side portion 114_S4 is between the first corner portion 114_C1 and the second corner portion 114_C2.

[0069] Corner portion 114_C can connect side portion 114_S. ​​First corner portion 114_C1 can connect first side portion 114_S1 to fourth side portion 114_S4. Second corner portion 114_C2 can connect third side portion 114_S3 to fourth side portion 114_S4. According to... Figure 1C On the plan view, the corner portion 114_C can have a quadrilateral shape.

[0070] The side portion 114_S may include a first side pattern portion 114_SP1 and a second side pattern portion 114_SP2. The second side pattern portion 114_SP2 may be disposed on the first side pattern portion 114_SP1. The first upper insulating layer 113 may include a first portion 113_1, a second portion 113_2, and a third portion 113_3. The third portion 113_3 of the first upper insulating layer 113 may be disposed on the second portion 113_2.

[0071] The second side pattern portion 114_SP2 can be positioned at a height higher than the first side pattern portion 114_SP1. The third portion 113_3 of the first upper insulating layer 113 can be positioned at a height higher than the first portion 113_1 and the second portion 113_2. The first side pattern portion 114_SP1 can be positioned at the same height as the first portion 113_1 and the second portion 113_2 of the first upper insulating layer 113. The second side pattern portion 114_SP2 can be positioned at the same height as the third portion 113_3 of the first upper insulating layer 113.

[0072] The second side pattern portion 114_SP2 may include a first portion 114_SP21, a second portion 114_SP22, and a third portion 114_SP23. The second portion 114_SP22 of the second side pattern portion 114_SP2 may overlap with the first side pattern portion 114_SP1 in the third direction D3. The first portion 114_SP21 and the third portion 114_SP23 of the second side pattern portion 114_SP2 may not overlap with the first side pattern portion 114_SP1 in the third direction D3.

[0073] A first portion 113_1 and a second portion 113_2 of the first upper insulating layer 113 may be disposed between the first through-hole 117_1 and the first side pattern portion 114_SP1. A third portion 113_3 of the first upper insulating layer 113 may be disposed between the first through-hole 117_1 and the second side pattern portion 114_SP2.

[0074] A first portion 113_1 of the first upper insulating layer 113 may overlap with the second side pattern portion 114_SP2 in the third direction D3. A second portion 113_2 of the first upper insulating layer 113 may overlap with a third portion 113_3 of the first upper insulating layer 113 in the third direction D3.

[0075] The width W1 of the first side pattern portion 114_SP1 in the first direction D1 may be smaller than the width W2 of the second side pattern portion 114_SP2 in the first direction D1. The width W1 of the first side pattern portion 114_SP1 in the first direction D1 may be the same as the width of the second portion 114_SP22 of the second side pattern portion 114_SP2 in the first direction D1. The first side pattern portion 114_SP1 may protrude from the second side pattern portion 114_SP2.

[0076] The first sidewall 114_SP1S1 of the first side pattern portion 114_SP1 can be connected to the bottom surface 114_SP21B of the first portion 114_SP21 of the second side pattern portion 114_SP2. The bottom surfaces 114_SP21B and 114_SP23B of the first portion 114_SP21 and the third portion 114_SP23 of the second side pattern portion 114_SP2 can be spaced apart from each other in the first direction D1. The bottom surface 114_SP1B of the first side pattern portion 114_SP1 can be located at a height lower than the bottom surface 114_SP21B of the first portion 114_SP21 and the bottom surface 114_SP23B of the third portion 114_SP23 of the second side pattern portion 114_SP2.

[0077] The sidewalls 114_SP21S of the first portion 114_SP21 of the second side pattern portion 114_SP2 and the sidewalls 114_SP23S of the third portion 114_SP23 can be opposite to each other. The sidewalls 114_SP21S of the first portion 114_SP21 of the second side pattern portion 114_SP2 can be connected to the bottom surface 114_SP21B of the first portion 114_SP21 of the second side pattern portion 114_SP2. The sidewalls 114_SP21S of the first portion 114_SP21 of the second side pattern portion 114_SP2 can be spaced apart from the first sidewall 114_SP1S1 of the first side pattern portion 114_SP1 in the first direction D1.

[0078] The sidewall 114_SP23S of the third portion 114_SP23 of the second side pattern portion 114_SP2 can be connected to the bottom surface 114_SP23B of the third portion 114_SP23 of the second side pattern portion 114_SP2. The sidewall 114_SP23S of the third portion 114_SP23 of the second side pattern portion 114_SP2 can be spaced apart from the second sidewall 114_SP1S2 of the first side pattern portion 114_SP1 in the first direction D1.

[0079] The bottom surface 114_SP1B of the first side pattern portion 114_SP1 can contact a first portion 111_T1 of the top surface 111_T of the first substrate 111. The first portion 111_T1 of the top surface 111_T of the first substrate 111 can be disposed between the first through-hole 117_1 and the second through-hole 117_2. The first portion 111_T1 of the top surface 111_T of the first substrate 111 can be spaced apart from the first through-hole 117_1 and the second through-hole 117_2 in the first direction D1.

[0080] The first side pattern portion 114_SP1 may not overlap with the second portion 111_T2 of the top surface 111_T of the first substrate 111 on the third direction D3. The second portion 111_T2 of the top surface 111_T of the first substrate 111 may be disposed between the first through-hole 117_1 and the second through-hole 117_2. The second portion 111_T2 of the top surface 111_T of the first substrate 111 may contact the sidewall of the first through-hole 117_1.

[0081] A first portion 113_1 of the first upper insulating layer 113 may contact the second sidewall 114_SP1S2 of the first side pattern portion 114_SP1. The first portion 113_1 of the first upper insulating layer 113 may contact the bottom surface 114_SP23B of the third portion 114_SP23 of the second side pattern portion 114_SP2. The third portion 113_3 of the first upper insulating layer 113 may contact the sidewall 114_SP23S of the third portion 114_SP23 of the second side pattern portion 114_SP2. The first portion 113_1 of the first upper insulating layer 113 may be spaced apart from the first through-hole 117_1 in the first direction D1.

[0082] The top surface 114_SP2T of the second side pattern portion 114_SP2, the top surface 113_T of the first upper insulating layer 113, and the top surface 117_T of the through hole 117 can be coplanar or substantially coplanar with each other.

[0083] The sidewalls of the first side pattern portion 114_SP1 and the second side pattern portion 114_SP2 of the first side portion 114_S1 can extend in the first direction D1. The sidewalls of the first side pattern portion 114_SP1 and the second side pattern portion 114_SP2 of the third side portion 114_S3 can extend in the first direction D1.

[0084] The sidewalls of the first side pattern portion 114_SP1 and the second side pattern portion 114_SP2 of the second side portion 114_S2 can extend in the second direction D2. The sidewalls 114_SP1S1 and 114_SP1S2 of the first side pattern portion 114_SP1 and the sidewalls 114_SP21S and 114_SP23S of the second side pattern portion 114_SP2 of the fourth side portion 114_S4 can extend in the second direction D2.

[0085] The corner portion 114_C may include a first corner pattern portion 114_CP1 and a second corner pattern portion 114_CP2. The second corner pattern portion 114_CP2 may be positioned at a height higher than the first corner pattern portion 114_CP1 in direction D3. The first corner pattern portion 114_CP1 may be positioned at the same height as the first side pattern portion 114_SP1. The second corner pattern portion 114_CP2 may be positioned at the same height as the second side pattern portion 114_SP2.

[0086] The first corner pattern portion 114_CP1 can be connected to the first side pattern portion 114_SP1. The second corner pattern portion 114_CP2 can be connected to the second side pattern portion 114_SP2. According to... Figure 1C On the plan view, the first corner pattern portion 114_CP1 can have a cross shape. According to... Figure 1C On the plan view, the second corner pattern portion 114_CP2 can have a quadrilateral shape.

[0087] The semiconductor device according to some embodiments may include insulating patterns 114, 124, 134, 144, and 240, which include insulating materials different from those of the upper insulating layers 113, 123, 133, 143, and 230 on the upper insulating layers 113, 123, 133, 143, and 230 to reduce warpage. Therefore, the stability of the semiconductor device can be improved.

[0088] Since the upper insulating layers 113, 123, 133, 143 and 230 in the semiconductor device according to some embodiments comprise oxides and the insulating patterns 114, 124, 134, 144 and 240 comprise nitrides, warpage can be reduced.

[0089] Since the insulating patterns 114, 124, 134, 144 and 240 in the semiconductor devices according to some embodiments also include a first side pattern portion 114_SP1 having a width smaller than the second side pattern portion 114_SP2, warping can be reduced.

[0090] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H , Figure 2I , Figure 2J , Figure 2K and Figure 2L It describes the materials used in manufacturing according to... Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E A diagram illustrating the method for developing semiconductor devices.

[0091] refer to Figure 2A The system may include interlayer connection terminals 150, a first substrate 111, a first lower insulating layer 112, a first wire structure 115, a first lower pad 116, and a preliminary through-hole 117p. The first lower insulating layer 112 and the first wire structure 115 may be disposed on the first adhesive member GLa, and the interlayer connection terminals 150 may be disposed in the first adhesive member GLa. The first adhesive member GLa may be disposed on the first carrier substrate CRa.

[0092] The initial through-hole 117p can penetrate the first substrate 111. The initial through-hole 117p may include conductive material.

[0093] A first preliminary upper insulating layer 113p can be formed on the first substrate 111 and the preliminary through-hole 117p. The first preliminary upper insulating layer 113p can cover the first substrate 111 and the preliminary through-hole 117p. The first preliminary upper insulating layer 113p can include an upper portion 113p_U that overlaps with the preliminary through-hole 117p and is disposed at a height higher than the preliminary through-hole 117p on a third direction D3, and a lower portion 113p_L that contacts the top surface 111_T of the first substrate 111 and is disposed at the same height as the preliminary through-hole 117p. The first preliminary upper insulating layer 113p can include an insulating material. For example, the first preliminary upper insulating layer 113p can include an oxide material.

[0094] refer to Figure 2BA photosensitive layer PR can be formed covering the first primary upper insulating layer 113p. The photosensitive layer PR can conformally cover the first primary upper insulating layer 113p. The photosensitive layer PR can include a photosensitive material. The photosensitive layer PR can be a photoresist layer that receives light to undergo a chemical change.

[0095] refer to Figure 2C The photosensitive layer PR can be partially removed. Partial removal of the photosensitive layer PR can include exposure and development processes. For example, the exposure and development processes can be photolithography using a photomask. The photosensitive layer PR can be partially removed to partially expose the top surface of the first preliminary upper insulating layer 113p.

[0096] refer to Figure 2D The first preliminary upper insulating layer 113p can be patterned. The first preliminary upper insulating layer 113p can be patterned to expose a first portion 111_T1 of the top surface 111_T of the first substrate 111. The first portion 111_T1 of the top surface 111_T of the first substrate 111 can be spaced apart from the preliminary through-hole 117p in the first direction D1. The first portion 111_T1 of the top surface 111_T of the first substrate 111 can not overlap with the first preliminary upper insulating layer 113p in the third direction D3. A second portion 111_T2 of the top surface 111_T of the first substrate 111 can overlap with the patterned first preliminary upper insulating layer 113p in the third direction D3. The second portion 111_T2 of the top surface 111_T of the first substrate 111 can contact the preliminary through-hole 117p. The patterning of the first preliminary upper insulating layer 113p can be performed using a photosensitive layer PR as an etching mask.

[0097] refer to Figure 2E The photosensitive layer PR can be removed. A first preliminary insulating pattern 114p can be formed covering the first preliminary upper insulating layer 113p and the top surface 111_T of the first substrate 111. The first preliminary insulating pattern 114p may include an insulating material. The first preliminary insulating pattern 114p may include an insulating material different from the first preliminary upper insulating layer 113p. For example, the first preliminary insulating pattern 114p may include a nitride. The first preliminary insulating pattern 114p may contact a first portion 111_T1 of the top surface 111_T of the first substrate 111 and the sidewall of the first preliminary upper insulating layer 113p.

[0098] refer to Figure 2F A sacrificial layer SP can be formed covering the first preliminary insulating pattern 114p. The sacrificial layer SP may include an insulating material. According to some embodiments, the sacrificial layer SP may include the same insulating material as the first preliminary upper insulating layer 113p. For example, the sacrificial layer SP may include an oxide.

[0099] refer to Figure 2G A portion of the first preliminary upper insulating layer 113p, a portion of the first preliminary insulating pattern 114p, and the sacrificial layer SP can be etched. Etching a portion of the first preliminary upper insulating layer 113p, a portion of the first preliminary insulating pattern 114p, and the sacrificial layer SP can include performing a chemical mechanical polishing (CMP) process. The first preliminary upper insulating layer 113p, the first preliminary insulating pattern 114p, and the preliminary through-hole 117p can be defined as the first upper insulating layer 113, the first insulating pattern 114, and the through-hole 117, respectively.

[0100] refer to Figure 2H The first adhesive member Gla and the first carrier substrate CRa can be removed. After removing the first adhesive member Gla and the first carrier substrate CRa, a dicing process can be performed along the first dicing line CL1 and the second dicing line CL2.

[0101] refer to Figure 2I The system can be configured with a second carrier substrate CR, a second adhesive member GL on the second carrier substrate CR, a preliminary substrate chip 200p on the second adhesive member GL, and a lower connection terminal 400 on the bottom surface of the preliminary substrate chip 200p.

[0102] The preliminary substrate chip 200p may include a preliminary substrate 210p, a fifth preliminary lower insulating layer 220p, a fifth preliminary upper insulating layer 230p, a fifth preliminary insulating pattern 240p, a through-hole 250, and a fifth line structure 260. The preliminary substrate 210p may be a semiconductor substrate. The fifth preliminary upper insulating layer 220p may include an insulating material. It can be connected to... Figures 2A to 2H The process described herein forms a fifth preliminary upper insulating layer 230p and a fifth preliminary insulating pattern 240p.

[0103] refer to Figure 2J It can be configured with an adhesive layer 300, interlayer connection terminals 150, and multiple first semiconductor chips 110. It can be connected to... Figures 2A to 2H The first semiconductor chip 110 is formed using a process similar to that described herein. For example, the first semiconductor chip 110 can be coupled to a preliminary substrate chip 200p by performing a thermo-pressing process.

[0104] refer to Figure 2K A second semiconductor chip 120, a third semiconductor chip 130, an upper semiconductor chip 140, an interlayer connection terminal 150, a first interlayer adhesive layer 161, a second interlayer adhesive layer 162, and a third interlayer adhesive layer 163 can be formed on the first semiconductor chip 110. This can be achieved through... Figure 2JA process similar to that described herein combines a first semiconductor chip 110, a second semiconductor chip 120, a third semiconductor chip 130, an upper semiconductor chip 140, an interlayer connection terminal 150, a first interlayer adhesive layer 161, a second interlayer adhesive layer 162, and a third interlayer adhesive layer 163. The first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 130, the upper semiconductor chip 140, the interlayer connection terminal 150, the first interlayer adhesive layer 161, the second interlayer adhesive layer 162, and the third interlayer adhesive layer 163 can be defined as a stacked structure 100 (see [link to documentation]). Figure 1B ).

[0105] refer to Figure 2L A preliminary molding layer 500p can be formed covering the preliminary substrate chip 200p, the stacked structure 100, and the lower adhesive layer 300. The preliminary molding layer 500p may include a polymer material.

[0106] refer to Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E The second carrier substrate CR and the second adhesive member GL can be removed. A dicing process can be performed on the preliminary substrate chip 200p and the preliminary molding layer 500p. The preliminary substrate chip 200p on which the dicing process is performed can be defined as substrate chip 200. The preliminary substrate substrate 210p on which the dicing process is performed can be defined as substrate substrate 210. The fifth preliminary lower insulating layer 220p on which the dicing process is performed can be defined as fifth lower insulating layer 220. The fifth preliminary upper insulating layer 230p on which the dicing process is performed can be defined as fifth upper insulating layer 230. The fifth preliminary insulating pattern 240p on which the dicing process is performed can be defined as fifth insulating pattern 240. The preliminary molding layer 500p on which the dicing process is performed can be defined as molding layer 500.

[0107] A method for manufacturing a semiconductor device according to some embodiments may include patterning the first preliminary upper insulating layer 113p before forming a first preliminary insulating pattern 114p on the first preliminary upper insulating layer 113p. Thus, the first insulating pattern may form a first side pattern portion 114_SP1 (see...). Figure 1D Therefore, warping during the hot pressing process can be reduced.

[0108] A method for manufacturing a semiconductor device according to some embodiments may include patterning the first preliminary upper insulating layer 113p before forming a first preliminary insulating pattern 114p on the first preliminary upper insulating layer 113p. Therefore, a first side pattern portion 114_SP1 can be formed along the pattern of the patterned first preliminary upper insulating layer 113p. Through this process, the shape of the first side pattern portion 114_SP1 can be formed differently along the warp direction. By making the shape of the first side pattern portion 114_SP1 different along the warp direction, warpage can be reduced.

[0109] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E This is a diagram illustrating a semiconductor device according to some embodiments. Figure 3B It is along Figure 3A The cross-sectional view taken from line IV-IV'. Figure 3C yes Figure 3A A magnified view of region B. Figure 3D It is along Figure 3C A cross-sectional view taken from line V-V'. Figure 3E It is along Figure 3C A cross-sectional view taken from line VI-VI'. Except as described below, according to Figures 3A to 3E Semiconductor devices and according to Figures 1A to 1E Similar to semiconductor devices.

[0110] refer to Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E The stacked structure 100a may include a first semiconductor chip 110a, a second semiconductor chip 120a, a third semiconductor chip 130a, and an upper semiconductor chip 140a. The first semiconductor chip 110a may include a first upper insulating layer 113a and a first insulating pattern 114a. The second semiconductor chip 120a may include a second upper insulating layer 123a and a second insulating pattern 124a. The third semiconductor chip 130a may include a third upper insulating layer 133a and a third insulating pattern 134a. The upper semiconductor chip 140a may include a fourth upper insulating layer 143a and a fourth insulating pattern 144a.

[0111] The first insulating pattern 114a may include a side portion 114_Sa disposed between the through-holes 117 of the first semiconductor chip 110a. The side portion 114_Sa of the first insulating pattern 114a may include a first side portion 114_S1a and a second side portion 114_S2a. The first side portion 114_S1a may be disposed between the first through-hole 117_1 and the second through-hole 117_2. The second side portion 114_S2a may be disposed between the first through-hole 117_1 and the fourth through-hole 117_4.

[0112] The first insulating pattern 114a may include planarization portions 114_P disposed between the through-vias 117 of the first semiconductor chip 110a. The planarization portions 114_P of the first insulating pattern 114a may include a first planarization portion 114_P1 and a second planarization portion 114_P2. The first planarization portion 114_P1 may be disposed between the first through-via 117_1 and the third through-via 117_3. The second planarization portion 114_P2 may be disposed between the first through-via 117_1 and the fifth through-via 117_5. The first through-via 117_1 may be disposed between the first planarization portion 114_P1 and the second planarization portion 114_P2.

[0113] The first upper insulating layer 113a may include a fourth portion 113_4 overlapping the first planarization portion 114_P1, and a fifth portion 113_5 disposed at the same height as the first planarization portion 114_P1. The fourth portion 113_4 of the first upper insulating layer 113a may overlap with the fifth portion 113_5 in the third direction D3. The fourth portion 113_4 of the first upper insulating layer 113a may be disposed at a lower height than the fifth portion 113_5. The first planarization portion 114_P1 may be disposed at the same height as the second side pattern portion 114_SP2. The thickness of the first planarization portion 114_P1 in the third direction D3 may be the same as the thickness of the second side pattern portion 114_SP2 in the third direction D3.

[0114] The top surface 113_4T of the fourth portion 113_4 of the first upper insulating layer 113a can contact the bottom surface 114_P1B of the first planarization portion 114_P1. The bottom surface 113_4B of the fourth portion 113_4 of the first upper insulating layer 113a can contact the top surface 111_T of the first substrate 111. The fifth portion 113_5 of the first upper insulating layer 113a can contact the sidewall of the first planarization portion 114_P1.

[0115] The top and bottom surfaces of the planarized portion of the first insulating pattern 114a may be flat or substantially flat. The top surface 114_P1T and bottom surface 114_P1B of the first planarized portion 114_P1 may be flat or substantially flat. The top surface 114_P1T and bottom surface 114_P1B of the first planarized portion 114_P1 may be parallel to each other. The top surface 114_P1T and bottom surface 114_P1B of the first planarized portion 114_P1 may be parallel to the top surface 111_T of the first substrate 111. The top surface 114_P1T of the first planarized portion 114_P1 may be coplanar or substantially coplanar with the top surface of the fifth portion 113_5 of the first upper insulating layer 113a. According to some embodiments, in accordance with Figure 3E In the cross-sectional view, the planarized portion of the first insulating pattern 114a can have a quadrilateral shape.

[0116] Figure 4A , Figure 4B and Figure 4C This is a diagram illustrating a semiconductor device according to some embodiments. Figure 4B It is along Figure 4A The cross-sectional view taken from line VII-VII'. Figure 4C yes Figure 4B A magnified view of region C. Except as described below, according to... Figure 4A , Figure 4B and Figure 4C Semiconductor devices can be used with... Figures 1A to 1E Similar to semiconductor devices. Figure 4C It can correspond to Figure 1D .

[0117] refer to Figure 4A , Figure 4B and Figure 4C The stacked structure 100b may include a first semiconductor chip 110b, a second semiconductor chip 120b, a third semiconductor chip 130b, and an upper semiconductor chip 140b. The stacked structure 100b may be disposed on a substrate chip 200b. The first semiconductor chip 110b may include a first upper insulating layer 113b and a first insulating pattern 114b. The second semiconductor chip 120b may include a second upper insulating layer 123b and a second insulating pattern 124b. The third semiconductor chip 130b may include a third upper insulating layer 133b and a third insulating pattern 134b. The upper semiconductor chip 140b may include a fourth upper insulating layer 143b and a fourth insulating pattern 144b. The second substrate chip 200b may include a fifth upper insulating layer 230b and a fifth insulating pattern 240b.

[0118] The first insulating pattern 114b may include a side portion 114_Sb. The side portion 114_Sb of the first insulating pattern 114b may include a first side pattern portion 114_SP1b, a second side pattern portion 114_SP2b, and a third side pattern portion 114_SP3b. The first side pattern portion 114_SP1b and the second side pattern portion 114_SP2b may overlap with the third side pattern portion 114_SP3b in a third direction D3. The first side pattern portion 114_SP1b and the second side pattern portion 114_SP2b may be positioned at a lower height than the third side pattern portion 114_SP3b. The first side pattern portion 114_SP1b and the second side pattern portion 114_SP2b may be spaced apart from each other in a first direction D1.

[0119] The first upper insulating layer 113b may include a first portion 113_1b overlapping the third side pattern portion 114_SP3b on the third direction D3, a second portion 113_2b connected to the first portion 113_1b, a third portion 113_3b in contact with the sidewall of the third side pattern portion 114_SP3b, and a fourth portion 113_4b disposed between the first side pattern portion 114_SP1b and the second side pattern portion 114_SP2b.

[0120] The first portion 113_1b, the second portion 113_2b, and the fourth portion 113_4b of the first upper insulating layer 113b, as well as the first side pattern portion 114_SP1b and the second side pattern portion 114_SP2b, can be disposed at the same height. The third side pattern portion 114_SP3b may include a first bottom surface 114_SP3B1b, a second bottom surface 114_SP3B2b, and a third bottom surface 114_SP3B3b.

[0121] The first bottom surface 114_SP3B1b, the second bottom surface 114_SP3B2b, and the third bottom surface 114_SP3B3b of the third side pattern portion 114_SP3b can be spaced apart from each other in the first direction D1. The first bottom surface 114_SP3B1b, the second bottom surface 114_SP3B2b, and the third bottom surface 114_SP3B3b of the third side pattern portion 114_SP3b can be set at the same height.

[0122] The first bottom surface 114_SP3B1b of the third side pattern portion 114_SP3b can be connected to the first sidewall 114_SP3S1b and the first sidewall 114_SP1S1b of the first side pattern portion 114_SP1b. The second bottom surface 114_SP3B2b of the third side pattern portion 114_SP3b can be connected to the second sidewall 114_SP1S2b of the first side pattern portion 114_SP1b and the first sidewall 114_SP2S1b of the second side pattern portion 114_SP2b. The third bottom surface 114_SP3B3b of the third side pattern portion 114_SP3b can be connected to the second sidewall 114_SP2S2b of the second side pattern portion 114_SP2b.

[0123] The fourth portion 113_4b of the first upper insulating layer 113b may contact the second sidewall 114_SP1S2b of the first side pattern portion 114_SP1b, the first sidewall 114_SP2S1b of the second side pattern portion 114_SP2b, and the bottom surface 114_SP3B2b of the third side pattern portion 114_SP3b. A first portion 113_1b of the first upper insulating layer 113b may contact the bottom surface 114_SP3B3b of the third side pattern portion 114_SP3b and the second sidewall 114_SP2S2b of the second side pattern portion 114_SP2b.

[0124] Figure 5 A semiconductor device according to some embodiments is shown. Except as described below, according to Figure 5 Semiconductor devices can be used with... Figures 1A to 1E Similar to semiconductor devices. Figure 5 It can correspond to Figure 1D .

[0125] refer to Figure 5 The first side pattern portion 114_SP1c can penetrate the top surface 111_Tc of the first substrate 111. The first side pattern portion 114_SP1c can penetrate the bottom surface 113B of the first upper insulating layer 113.

[0126] The first side pattern portion 114_SP1c may include a first part 114_SP11c and a second part 114_SP12c. The first part 114_SP11c of the first side pattern portion 114_SP1c may overlap with the second part 114_SP12c in a third direction D3. The first part 114_SP11c of the first side pattern portion 114_SP1c may be located at a lower height than the second part 114_SP12c.

[0127] The bottom surface 114_SP11Bc of the first portion 114_SP11c of the first side pattern portion 114_SP1c can be disposed at a height lower than the top surface 111_Tc of the first substrate 111c. The sidewall 114_SP11Sc of the first portion 114_SP11c of the first side pattern portion 114_SP1c can contact the first substrate 111c. The first substrate 111c may include a recess 111Rc, and the first portion 114_SP11c of the first side pattern portion 114_SP1c can be disposed on the recess 111Rc. The bottom surface 114_SP11Bc and the sidewall 114_SP11Sc of the first portion 114_SP11c of the first side pattern portion 114_SP1c can contact the recess 111Rc of the first substrate 111c.

[0128] The bottom surface 114_SP11Bc of the first portion 114_SP11c of the first side pattern portion 114_SP1c may be spaced apart from the top surface 111_Tc of the first substrate 111c in the third direction D3. The bottom surface 114_SP11Bc of the first portion 114_SP11c of the first side pattern portion 114_SP1c may be spaced apart from the bottom surface 113_B of the first upper insulating layer 113 in the third direction D3.

[0129] In a semiconductor device according to some embodiments, since the first side pattern portion 114_SP1c includes a first portion 114_SP11c and a second portion 114_SP12c, the thickness of the first side pattern portion 114_SP1c on the third direction D3 can be relatively large. Therefore, warpage can be effectively reduced.

[0130] Figure 6A , Figure 6B and Figure 6C This is a diagram illustrating a semiconductor device according to some embodiments. Figure 6B yes Figure 6A An enlarged view of region D in the image. Figure 6C It is along Figure 6B A cross-sectional view taken from line VIII-VIII'. Except as described below, according to... Figure 6A , Figure 6B and Figure 6C Semiconductor devices can be used with... Figures 1A to 1E Similar to semiconductor devices.

[0131] refer to Figure 6A , Figure 6B and Figure 6CThe first insulating pattern 114d may include a first portion 114_1d containing a first insulating material and a second portion 114_2d containing a second insulating material. The first insulating material and the second insulating material may be different from each other. For example, the first insulating material may include an oxide material, and the second insulating material may include a nitride material.

[0132] A first portion 114_1d of the first insulating pattern 114d may include a side portion 114_1Sd disposed between the through holes 117 and a corner portion 114_1Cd disposed between the side portions 114_1Sd.

[0133] The second portion 114_2d of the first insulating pattern 114d may include a side portion 114_2Sd that contacts the side portion 114_1Sd of the first portion 114_1d, and an inner side portion 114_2Id spaced apart from the first portion 114_1d of the first insulating pattern 114d. The inner side portion 114_2Id of the second portion 114_2d of the first insulating pattern 114d may surround the first through-hole 117_1. The inner side portion 114_2Id of the second portion 114_2d of the first insulating pattern 114d may contact the sidewall of the first through-hole 117_1.

[0134] The side portion 114_1Sd of the first part 114_1d of the first insulating pattern 114d and the side portion 114_2Sd of the second part 114_2d of the first insulating pattern 114d can correspond to according to Figures 1A to 1E The side portion 114_S of the first insulating pattern 114. The side portion 114_1Sd of the first part 114_1d of the first insulating pattern 114d can correspond to the second part 114_SP22 of the second side pattern portion 114_SP2 of the side portion 114_S of the first insulating pattern 114. The side portion 114_2Sd of the second part 114_2d of the first insulating pattern 114d can correspond to the first part 114_SP21 or the third part 114_S23 of the second side pattern portion 114_SP2 of the side portion 114_S of the first insulating pattern 114.

[0135] The bottom surface 114_1SBd of the side portion 114_1Sd of the first part 114_1d of the first insulating pattern 114d, the bottom surface 114_2SBd of the side portion 114_2Sd of the second part 114_2d, and the bottom surface 114_2IBd of the inner side portion 114_2Id of the second part 114_2d may be coplanar or substantially coplanar with each other.

[0136] The top surface 114_1STd of the side portion 114_1Sd of the first part 114_1d of the first insulating pattern 114d, the top surface 114_2STd of the side portion 114_2Sd of the second part 114_2d, and the top surface 114_2ITd of the inner side portion 114_2Id of the second part 114_2d may be coplanar or substantially coplanar with each other.

[0137] The side portions 114_1Sd of the first portion 114_1d of the first insulating pattern 114d, the side portions 114_2Sd of the second portion 114_2d, and the inner side portions 114_2Id of the second portion 114_2d can have the same thickness in the third direction D3. The side portions 114_1Sd of the first portion 114_1d of the first insulating pattern 114d, the side portions 114_2Sd of the second portion 114_2d, and the inner side portions 114_2Id of the second portion 114_2d can be positioned at the same height. The side portions 114_1Sd of the first portion 114_1d of the first insulating pattern 114d can contact the side portions 114_2Sd of the second portion 114_2d.

[0138] In a semiconductor device according to some embodiments, the first insulating pattern 114d may include a first portion 114_1d and a second portion 114_2d comprising different insulating materials. Depending on the warp direction of the semiconductor device, the first portion 114_1d and the second portion 114_2d of the first insulating pattern 114d may be patterned in different forms. Therefore, warpage can be effectively reduced.

[0139] Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E , Figure 7F , Figure 7G and Figure 7H It describes the materials used in manufacturing according to... Figure 6A , Figure 6B and Figure 6C A diagram illustrating a method for developing a semiconductor device. Except as described below, according to... Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E , Figure 7F , Figure 7G and Figure 7H The method for manufacturing semiconductor devices can be compared with that based on Figures 2A to 2L The methods used to manufacture semiconductor devices are similar.

[0140] refer to Figure 7AA first preliminary insulating pattern 114dp can be formed on the first substrate 111. The first preliminary insulating pattern 114dp may include an insulating material. For example, the first preliminary insulating pattern 114dp may include a nitride. The first preliminary insulating pattern 114dp may conformally cover the first substrate 111 and the preliminary through-hole 117p.

[0141] refer to Figure 7B A sacrificial layer SPd can be formed on the first preliminary insulating pattern 114dp. The sacrificial layer SPd can include an insulating material. For example, the sacrificial layer SPd can include an oxide.

[0142] refer to Figure 7C The sacrificial layer SPd and the first preliminary insulating pattern 114dp can be partially etched. Partial etching of the sacrificial layer SPd and the first preliminary insulating pattern 114dp can include performing a chemical mechanical polishing (CMP) process. The top surface of the partially etched first preliminary insulating pattern 114dp can be coplanar or substantially coplanar with the top surface of the through via 117.

[0143] refer to Figure 7D A photosensitive layer PR can be formed on the first preliminary insulating pattern 114dp after partial etching.

[0144] refer to Figure 7E It can pattern the photosensitive layer PR.

[0145] refer to Figure 7F The first preliminary insulating pattern 114dp can be patterned. Patterning of the first preliminary insulating pattern 114dp can be performed by using the patterned photosensitive layer PR as an etching mask. The patterned first preliminary insulating pattern 114dp can be defined as a second portion 114_2d of the first insulating pattern 114d. The first preliminary insulating pattern 114dp can be patterned to partially expose the top surface 111_T of the first substrate 111.

[0146] refer to Figure 7G It can remove the photosensitive layer (PR).

[0147] refer to Figure 7H A first portion 114_1d of the first insulating pattern 114d can be formed. Forming the first portion 114_1d of the first insulating pattern 114d may include: forming an insulating structure covering a portion of the top surface 111_T of the first substrate 111, a through-hole 117, and a second portion 114_2d of the first insulating pattern 114d, and partially etching the insulating structure.

[0148] Figure 8This is a diagram illustrating a semiconductor device according to some embodiments. Except as described below, according to... Figure 8 Semiconductor devices can be used with... Figures 6A to 6C Similar to semiconductor devices. Figure 8 It can correspond to Figure 6C .

[0149] refer to Figure 8 The side portion 114_1Se of the first part 114_1e of the first insulating pattern 114e may include a lower part 114_1SLe and an upper part 114_1SUe. The side portion 114_1Se of the first part 114_1e of the first insulating pattern 114e may correspond to the second part 114_SP22 of the second side pattern portion 114_SP2 of the first insulating pattern 114. The side portion 114_1Se of the first part 114_1e of the first insulating pattern 114e may correspond to the first side pattern portion 114_SP1 of the first insulating pattern 114.

[0150] The upper part 114_1SUe of the side portion 114_1Se of the first part 114_1e of the first insulating pattern 114e may overlap with the lower part 114_1SLe in the third direction D3. The upper part 114_1SUe of the side portion 114_1Se of the first part 114_1e of the first insulating pattern 114e may be located at a height higher than the lower part 114_1SLe. The upper part 114_1SUe of the side portion 114_1Se of the first part 114_1e of the first insulating pattern 114e may be located at the same height as the second part 114_2e of the first insulating pattern 114e.

[0151] The thickness of the upper portion 114_1SUe of the side portion 114_1Se of the first part 114_1e of the first insulating pattern 114e in the third direction D3 can be the same as the thickness of the second part 114_2e of the first insulating pattern 114e in the third direction D3. The thickness of the side portion 114_1Se of the first part 114_1e of the first insulating pattern 114e in the third direction D3 can be greater than the thickness of the second part 114_2e in the third direction D3. The thickness of the side portion 114_1Se of the first part 114_1e of the first insulating pattern 114e in the third direction D3 can be defined as the sum of the thickness of the upper portion 114_1SUe of the side portion 114_1Se of the first part 114_1e of the first insulating pattern 114e in the third direction D3 and the thickness of the lower portion 114_1SeLe in the third direction D3.

[0152] The sidewall 114_1SLSe and bottom surface 114_1SLBe of the lower portion 114_1SLe of the side portion 114_1Se of the first part 114_1e of the first insulating pattern 114e can contact the first substrate 111. The lower portion 114_1SLe of the side portion 114_1Se of the first part 114_1e of the first insulating pattern 114e can be disposed at a height lower than the top surface 111_T of the first substrate 111 and the bottom surface of the second part 114_2e of the first insulating pattern 114e.

[0153] Figure 9 This is a diagram illustrating a semiconductor device according to some embodiments. Except as described below, according to... Figure 9 Semiconductor devices can be used with... Figures 1A to 1E Similar to semiconductor devices.

[0154] refer to Figure 9 The first semiconductor chip 110f may include a first substrate 111f, a first lower insulating layer 113f, a first upper insulating layer 112f, a first insulating pattern 114f, a first line structure 115f, a first upper pad 116f, and a through-hole 117f.

[0155] The first upper insulating layer 112f can be disposed on the top surface 111_Tf of the first substrate 111f. The first lower insulating layer 113f can be disposed on the bottom surface 111_Bf of the first substrate 111f. The top surface 111_Tf of the first substrate 111f can be the front surface of the semiconductor device, and the bottom surface 111_Bf can be the rear surface of the semiconductor device. The first upper insulating layer 112f can be disposed at a height higher than the first substrate 111f and the first lower insulating layer 113f.

[0156] The first insulating pattern 114f can be disposed at the same height as the first lower insulating layer 113f. The first side pattern portion 114_SP1f of the side portion 114_Sf of the first insulating pattern 114f can be disposed at a height higher than the second side pattern portion 114_SP2f. The first side pattern portion 114_SP1f of the side portion 114_Sf of the first insulating pattern 114f can contact the bottom surface of the first substrate 111f. The second side pattern portion 114_SP2f of the side portion 114_Sf of the first insulating pattern 114f can contact the lower adhesive layer 300. The first upper pad 116f can be electrically connected to the first line structure 115f. The first upper pad 116f can be disposed at a height higher than the first substrate 111f. The first line structure 115f can be disposed within the first upper insulating layer 112f. Figure 9 The first semiconductor chip 110f can have the following properties: Figure 1B The first semiconductor chip 110 is in an upside-down shape.

[0157] The second semiconductor chip 120f may include a second substrate 121f, a second lower insulating layer 123f, a second upper insulating layer 122f, a second insulating pattern 124f, a second line structure 125f, a second upper pad 126f, and a through-hole 127f.

[0158] The third semiconductor chip 130f may include a third substrate 131f, a third lower insulating layer 133f, a third upper insulating layer 132f, a third insulating pattern 134f, a third line structure 135f, a third upper pad 136f, and a through-hole 137f.

[0159] The upper semiconductor chip 140f may include a fourth substrate 141f, a fourth lower insulating layer 143f, a fourth upper insulating layer 142f, a fourth insulating pattern 144f, a fourth line structure 145f, a fourth upper pad 146f, and a through-hole 147f. The second semiconductor chip 120f, the third semiconductor chip 130f, and the upper semiconductor chip 140f may be similar to the first semiconductor chip 110f.

[0160] Figure 9 The second semiconductor chip 120f can have the following properties: Figure 1B The second semiconductor chip 120 is inverted. Figure 9 The third semiconductor chip 130f can have the ability to... Figure 1B The third semiconductor chip 130 is inverted.

[0161] The semiconductor chip 140f can have the following properties: Figure 1B The upper semiconductor chip 140 has a similar shape that is inverted. The through-hole 147f of the upper semiconductor chip 140f can be electrically connected to the interlayer connection terminal 150 and the fourth line structure 145f. The through-hole 147f of the upper semiconductor chip 140f can penetrate the fourth substrate 141f. The fourth upper insulating layer 142f can cover the fourth line structure 145f.

[0162] Figure 10 This is a diagram illustrating a semiconductor device according to some embodiments. Except as described below, according to... Figure 10 Semiconductor devices can be used with... Figures 1A to 1E Similar to semiconductor devices.

[0163] refer to Figure 10 A package substrate 1000 may be provided. For example, the package substrate 1000 may be a printed circuit board (PCB). External terminals 600 electrically connected to the package substrate 1000 may be provided. The external terminals 600 may include conductive material. The external terminals 600 may include solder balls or bumps electrically connected to external devices.

[0164] The first lower adhesive layer 300f, the second lower adhesive layer 301f, and the third lower adhesive layer 302f can be disposed on the packaging substrate 1000. The first stacked structure 100f can be disposed on the first lower adhesive layer 300f, the second stacked structure 101f can be disposed on the second lower adhesive layer 301f, and the third stacked structure 102f can be disposed on the third lower adhesive layer 302f.

[0165] The first to third stacked structures 100f, 101f, and 102f can be arranged in the first direction D1. The first to third stacked structures 100f, 101f, and 102f can be spaced apart from each other in the first direction D1. The first to third stacked structures 100f, 101f, and 102f can be electrically connected to the package substrate 1000. The first to third stacked structures 100f, 101f, and 102f can be connected to... Figure 1B The stacked structure is similar to 100.

[0166] An external molding layer 1100 may be provided to cover the first to third stacked structures 100f, 101f, and 102f and the packaging substrate 1000. The external molding layer 1100 may include an insulating material. For example, the external molding layer 1100 may include a polymer material.

[0167] Figure 11 This is a diagram illustrating a semiconductor device according to some embodiments. Except as described below, according to... Figure 11 Semiconductor devices can be used with... Figure 10 Similar to semiconductor devices.

[0168] refer to Figure 11 An interposer 2000 overlapping with the package substrate 1000 may be provided. The interposer 2000 may include a substrate, an insulating layer, wires, and vias. The interposer 2000 may be electrically connected to the package substrate 1000. A first internal terminal 2100 and a first underfill 2200 surrounding the first internal terminal 2100 may be provided between the interposer 2000 and the package substrate 1000. The first internal terminal 2100 may include a conductive material.

[0169] The first internal terminal 2100 may be electrically connected to the package substrate 1000 and the interposer 2000. The first underfill 2200 may include an insulating material. For example, the first underfill 2200 may include a polymer material.

[0170] The second underfill 3100, the third underfill 3200, and the fourth underfill 3300 may be disposed on the interposer 2000. The second to fourth underfills 3100, 3200, and 3300 may include insulating materials. For example, the second to fourth underfills 3100, 3200, and 3300 may include polymer materials.

[0171] The second internal terminal 3110 can be disposed in the second bottom filler 3100. The third internal terminal 3210 can be disposed in the third bottom filler 3200. The fourth internal terminal 3310 can be disposed in the fourth bottom filler 3300.

[0172] A first substrate chip 200g can be disposed on a second bottom filler 3100. A first lower adhesive layer 300g can be disposed on the first substrate chip 200g. A first stacked structure 100g can be disposed on the first lower adhesive layer 300g. A first molding layer 500g can be disposed covering the first substrate chip 200g, the first lower adhesive layer 300g, and the first stacked structure 100g. A second internal terminal 3110 can be electrically connected to the first substrate chip 200g and the interposer layer 2000.

[0173] The second substrate chip 201g can be disposed on the fourth bottom filler 3300. The second lower adhesive layer 301g can be disposed on the second substrate chip 201g. The second stack structure 101g can be disposed on the second lower adhesive layer 301g. A second molding layer 501g can be disposed covering the second substrate chip 201g, the second lower adhesive layer 301g, and the second stack structure 101g. The fourth internal terminal 3310 can be electrically connected to the second substrate chip 201g and the interposer layer 2000.

[0174] The logic chip 4000 may be disposed on the third bottom fill layer 3200. For example, the logic chip 4000 may include a central processing unit (CPU), a graphics processing unit (GPU), or an application-specific integrated circuit (ASIC). The logic chip 4000 may send signals to or receive signals from the first stack structure 100g or the second stack structure 101g. The third internal terminal 3210 may be electrically connected to the logic chip 4000 and the interposer layer 2000.

[0175] The logic chip 4000 can be disposed between the first stacked structure 100g and the second stacked structure 101g. The first stacked structure 100g, the second stacked structure 101g and the logic chip 4000 can be arranged on a first direction D1. The first stacked structure 100g, the second stacked structure 101g and the logic chip 4000 can be spaced apart from each other on the first direction D1.

[0176] An external molding layer 1100g can be configured to cover the first bottom filler 2200, the interposer 2000, the second bottom filler 3100, the third bottom filler 3200, the fourth bottom filler 3300, the first substrate chip 200g, the second substrate chip 201g, the logic chip 4000, the first molding layer 500g, and the second molding layer 501g.

[0177] The outer molding layer 1100g may include an insulating material. For example, the outer molding layer 1100g may include a polymer material.

[0178] Because the semiconductor device according to embodiments of the present disclosure includes an insulating pattern comprising different insulating materials on an insulating layer, warpage can be reduced. Therefore, the stability of the semiconductor device can be improved.

[0179] In the semiconductor device according to embodiments of the present disclosure, warpage can be reduced because the insulating layer comprises an oxide and the insulating pattern comprises a nitride with relatively high stress.

[0180] In the semiconductor device according to embodiments of the present disclosure, since the insulating pattern also includes a first side pattern portion having a width smaller than that of the second side pattern portion, warping can be reduced.

[0181] A method for manufacturing a semiconductor device according to embodiments of the present disclosure may include patterning a preliminary insulating layer. Therefore, the insulating pattern may include a first side pattern portion and a second side pattern portion. This can reduce warpage during the hot-pressing process.

[0182] In the method for manufacturing a semiconductor device according to embodiments of the present disclosure, a first side pattern portion can be formed along the pattern of a patterned preliminary insulating layer. Therefore, the shape of the first side pattern portion can be formed differently along the warp direction. By making the shape of the first side pattern portion different along the warp direction, warping can be reduced.

[0183] In the semiconductor device according to embodiments of the present disclosure, the first side pattern portion can penetrate the top surface of the substrate to be formed. Therefore, the thickness of the first side pattern portion can be relatively increased. Thus, warpage can be effectively reduced.

[0184] In a semiconductor device according to embodiments of the present disclosure, an insulating pattern may include a first portion and a second portion comprising different insulating materials. Depending on the warp direction of the semiconductor device, the first and second portions of the first insulating pattern may be patterned in different shapes. Therefore, warp can be effectively reduced.

[0185] Although embodiments of the present disclosure have been described, it should be understood that the present disclosure is not intended to be limited to these embodiments, and various changes and modifications can be made by those skilled in the art as described in the spirit and scope of the present disclosure. Therefore, it should be understood that the above embodiments are exemplary in all respects and are not intended to be limiting.

Claims

1. A semiconductor device, comprising: Substrate; The first via penetrates the substrate; A second via penetrates the substrate; as well as An insulating pattern surrounds the first via and the second via. The insulating pattern includes a first portion between the first via and the second via. The first part includes a first pattern portion and a second pattern portion that overlaps with the first pattern portion, and The width of the first pattern portion is smaller than the width of the second pattern portion.

2. The semiconductor device of claim 1, further comprising an insulating layer surrounding the first via and the second via, in, The first portion is spaced apart from the first via and the second via, and The insulating layer includes a first portion between the first patterned portion and the first via, and a second portion between the second patterned portion and the first via.

3. The semiconductor device according to claim 2, wherein, The insulating pattern and the insulating layer comprise different insulating materials.

4. The semiconductor device according to claim 2, wherein, The surface of the second pattern portion is connected to the wall of the first pattern portion and the wall of the second pattern portion.

5. The semiconductor device according to claim 2, wherein, The insulating layer is in contact with the surface of the substrate, the wall of the first via, the wall of the first patterned portion, and the wall of the second patterned portion.

6. The semiconductor device according to claim 2, wherein, The surface of the second patterned portion is coplanar with the surface of the insulating layer.

7. The semiconductor device according to claim 2, wherein, The insulating layer is in contact with the surface of the second patterned portion.

8. The semiconductor device according to claim 1, wherein, The first via, the second via, and the first portion are spaced apart from each other in a first direction. The semiconductor device further includes a third via spaced apart from the first via and the second via in a second direction intersecting the first direction. The insulating pattern further includes a planarization portion between the first via and the third via. Wherein, the planarized portion is spaced apart from the substrate, and The first portion is in contact with the substrate.

9. The semiconductor device according to claim 8, wherein, The first and second surfaces of the planarized portion are flat.

10. The semiconductor device according to claim 1, wherein, The first patterned portion penetrates the surface of the substrate, and The surface of the first patterned portion is spaced apart from the surface of the substrate.

11. A semiconductor device, comprising: Substrate; The first via penetrates the substrate; A second via penetrates the substrate; as well as An insulating pattern surrounds the first via and the second via. The insulating pattern includes a first portion between the first via and the second via. The first part includes a first pattern portion and a second pattern portion that overlaps with the first pattern portion. The second pattern portion includes a first part, a second part, and a third part. Wherein, a second portion of the second pattern portion overlaps with the first pattern portion. In this design, the first and third portions of the second pattern are spaced apart from each other. Wherein, the second portion of the second pattern is between the first portion and the third portion, and Wherein, the height of the surface of the first pattern portion is lower than the height of the surface of the first part of the second pattern portion and the height of the surface of the third part of the second pattern portion.

12. The semiconductor device according to claim 11, wherein, Both the first and third portions of the second patterned portion include a first insulating material. Wherein, the second portion of the second patterned portion includes a second insulating material that is different from the first insulating material, and The first patterned portion includes the second insulating material.

13. The semiconductor device according to claim 12, wherein, The first insulating material comprises nitride, and The second insulating material includes oxides.

14. The semiconductor device of claim 11, further comprising: An insulating layer, located between the first portion and the first via, comprises an insulating material different from the insulating pattern. The insulating layer is in contact with the surface of the substrate.

15. The semiconductor device according to claim 14, wherein, The surfaces of the first portion of the second pattern portion, the second portion of the second pattern portion, the third portion of the second pattern portion, and the surface of the insulating layer are coplanar with each other.

16. The semiconductor device according to claim 11, wherein, The wall of the first patterned portion is in contact with the substrate.

17. A semiconductor device, comprising: Substrate; The first via penetrates the substrate; A second via penetrates the substrate; An insulating pattern is formed on the surface of the substrate and surrounds the first via. as well as An insulating layer on the substrate, The insulating pattern includes a first portion between the first via and the second via. The first part includes a first pattern portion and a second pattern portion that overlaps with the first pattern portion, and The first pattern portion protrudes from the second pattern portion.

18. The semiconductor device according to claim 17, wherein, The second pattern portion includes a first wall and a second wall that are opposite to each other. The first pattern portion is spaced apart from the first wall and the second wall of the second pattern portion.

19. The semiconductor device according to claim 17, wherein, The first via, the second via, and the first portion are spaced apart from each other in a first direction. The semiconductor device further includes a corner portion connected to the first portion, and Wherein, the corner portion and the first via are spaced apart from each other in a second direction intersecting the first direction, and the corner portion and the second via are spaced apart from each other in the second direction.

20. The semiconductor device according to claim 19, wherein, The corner portion includes a corner pattern portion connected to the first pattern portion, and The corner pattern portion has a cross shape.

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