Chip package structure and packaging method

Abstract

The application provides a chip packaging structure and a packaging method. The structure comprises: a glass substrate, a micro-fluid cooling channel is integrated in the interior or surface of the glass substrate; a plurality of glass vias with a high depth-width ratio greater than 10:1, which are arranged through the glass substrate and filled with conductive filling materials; the inner wall of the glass via has a surface active layer treated by plasma; a stress buffer layer is arranged on the first surface and the second surface opposite to the first surface of the glass substrate and is made of a polymer-based composite material; at least one chip is arranged on the first surface and embedded in or placed on the stress buffer layer; a first wiring layer is arranged on the stress buffer layer of the first surface and is connected with the chip and the glass via; and a second wiring layer is arranged on the stress buffer layer of the second surface and is electrically connected with the glass via. The application solves the problems of the existing packaging scheme, such as the difficulty in forming the high depth-width ratio of TGV, the stress cracking of copper and glass thermal mismatch, the accumulation of residual stress of multi-layer stacking and the low heat dissipation caused by low thermal conductivity.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a chip packaging structure and packaging method. Background Technology

[0002] As Moore's Law continues to slow, the miniaturization of traditional semiconductor manufacturing processes is approaching the "double ceiling" of physical limits and economic costs. Simply relying on shrinking transistor size is no longer sufficient to meet the exponential demands on chip performance, bandwidth, and integration caused by the explosive growth of artificial intelligence (AI) computing power. Against this backdrop, advanced packaging technology has become a key path to break through chip performance bottlenecks and continue improving system-level performance.

[0003] Currently, mainstream advanced packaging solutions, such as TSMC's CoWoS (Chip-on-Wafer-on-Substrate) technology, mainly rely on the combination of silicon interposer and organic substrate (such as ABF). However, as AI chip sizes continue to increase and power consumption continues to rise, both of these traditional material solutions have revealed fundamental technical bottlenecks, as follows: First, the limitations of silicon interposers are becoming increasingly apparent. As a semiconductor material, silicon generates significant electromagnetic coupling effects and eddy current losses when transmitting high-frequency signals, leading to a deterioration in signal integrity, especially in high-frequency applications where losses are severe. In addition, silicon interposers are limited by the manufacturing process of 12-inch circular wafers, with an area utilization rate of only 65% ​​to 75%, which is difficult to meet the ever-increasing photomask size and packaging area requirements of next-generation AI chips, resulting in problems of "not being able to fit" and "serious waste".

[0004] Secondly, the inherent defects of organic substrates also restrict technological evolution. The coefficient of thermal expansion (CTE) of organic substrates (such as ABF) is about 12-17 ppm / ℃, while the CTE of silicon chips is only 2.6 ppm / ℃. The difference is huge. In large-size, high-power AI chip packaging, this thermal mismatch can cause serious warping problems, resulting in a yield drop of up to 15% to 20%. At the same time, the poor planarity and high dielectric loss of organic materials also limit the processing capability of fine lines and the transmission quality of high-frequency signals.

[0005] To overcome the inherent shortcomings of the aforementioned materials, glass substrates (based on TGV glass through-hole technology) have become a core direction for next-generation advanced packaging substrates due to their unique physicochemical properties. Glass substrates possess several core advantages, mainly reflected in the following aspects: Firstly, by adjusting the composition of borosilicate glass, its CTE can be precisely controlled at 3-5 ppm / ℃, almost perfectly matching that of silicon chips. This fundamentally alleviates the warpage problem in large-size packaging, controlling the warpage to 30-50%. Within m, it reduces the efficiency by more than 70% compared to organic substrates.

[0006] Secondly, glass, as an excellent insulator, has extremely low dielectric constant and loss factor (loss tangent < 0.002 at 30GHz). High-frequency signal transmission loss is reduced by 2-3 orders of magnitude compared to organic substrates, and signal delay is reduced by more than 15%, which can support PAM4 ultra-high-speed interconnects above 112G.

[0007] Third, glass is easy to produce large-size, ultra-thin square panels (such as 310×310mm to 515×510mm), which can increase the area utilization rate from 45% of round wafers to more than 80%. The output of a single panel is equivalent to 4-8 12-inch wafers, and the overall manufacturing cost is reduced by 66% compared with the silicon interposer solution.

[0008] However, glass substrates still face four major systemic challenges in moving from the laboratory to large-scale mass production, specifically: Firstly, there is the challenge of TGV forming: glass materials are hard and brittle, and traditional mechanical drilling is prone to generating microcracks. Currently, the industry tends to use laser-induced etching technology to achieve high aspect ratio (1:10 to 1:50) through-hole forming, but the final yield of TGV is still a key bottleneck. If it cannot be stably achieved to more than 75%, it will be difficult to support large-scale mass production.

[0009] Secondly, there is the issue of stress matching at the metallization interface: the smooth surface of glass has poor adhesion to the metal layer, and direct metallization is prone to delamination or peeling. At the same time, the thermal expansion coefficients of copper (CTE about 16.7 ppm / ℃) and glass (CTE about 3 ppm / ℃) differ by several times. During the thermal cycling process in manufacturing, huge stress will accumulate at the interface, leading to radial cracks, circumferential cracks, or interface delamination.

[0010] Third, stress accumulation in multilayer wiring: Although glass substrates exhibit better warping performance than organic substrates, the stress accumulation effect between copper and glass cannot be ignored when the number of stacked layers exceeds ten. Simulation analysis shows that the edge of the via opening is the area of ​​highest stress concentration, and the more layers stacked, the greater the stress, posing a challenge to structural reliability.

[0011] Fourth, a weakness in thermal management: the thermal conductivity of glass is only about 1 W / (m·K), far lower than silicon's 150 W / (m·K). For AI chips with power consumption exceeding 700W, heat is difficult to dissipate effectively through the glass substrate. The industry is exploring the use of high-density copper-filled TGV arrays to construct vertical heat conduction channels in order to improve local effective thermal conductivity. Summary of the Invention

[0012] To address the shortcomings of existing technologies, this invention provides a chip packaging structure and packaging method that solves the problems of difficult high aspect ratio molding of TGV, thermal mismatch stress cracking between copper and glass, residual stress accumulation in multilayer stacking, and low heat dissipation due to low thermal conductivity in existing glass substrate packaging solutions.

[0013] According to an embodiment of the present invention, a chip packaging structure includes: A glass substrate, the interior or surface of which is integrated with microfluidic cooling channels for transporting cooling media; Multiple glass vias are disposed through the glass substrate, the aspect ratio of the glass vias is greater than 10:1, and the glass vias are filled with conductive filler material; the inner wall of the glass vias has a surface active layer for enhancing metal adhesion, the surface active layer being a glass surface treated with plasma. A stress buffer layer is disposed on a first surface and a second surface opposite to the first surface of the glass substrate to absorb stress generated during thermal cycling; the stress buffer layer is made of a polymer-based composite material. At least one chip is disposed on the first surface of the glass substrate and embedded in or disposed on the stress buffer layer; A first wiring layer is disposed on the stress buffer layer of the first surface, and electrically connects the chip to the glass via. The second wiring layer is disposed on the stress buffer layer of the second surface and is electrically connected to the glass through-hole.

[0014] According to another embodiment of the present invention, a chip packaging structure packaging method includes the following steps: A glass substrate is provided, wherein microfluidic cooling channels for conveying cooling medium are integrated inside or on the surface of the glass substrate; Multiple glass vias are formed in the glass substrate, and conductive filler material is filled in the glass vias to form a vertical interconnect structure. The inner walls of the glass vias are then subjected to plasma treatment to form a surface-active layer that enhances metal adhesion. The aspect ratio of the glass vias is greater than 10:1. Stress buffer layers are formed on a first surface of the glass substrate and a second surface opposite to the first surface, respectively. The stress buffer layers are made of polymer-based composite materials to absorb stress generated during thermal cycling. At least one chip is disposed on the first surface of the glass substrate, and the chip is embedded in the stress buffer layer or disposed on the stress buffer layer; A first wiring layer is formed on the stress buffer layer of the first surface, and the first wiring layer electrically connects the chip to the glass via. A second wiring layer is formed on the stress buffer layer of the second surface, and the second wiring layer is electrically connected to the glass via.

[0015] Compared with the prior art, the present invention has the following beneficial effects: By fabricating glass vias (TGVs) with an aspect ratio greater than 10:1 in the glass substrate and subjecting their inner walls to plasma treatment to form a surface-active layer that enhances metal adhesion, dense and void-free copper filling is achieved under conditions of large aperture and high aspect ratio. This technology effectively overcomes the problem of difficult high aspect ratio TGV molding in existing glass substrate packaging solutions and successfully achieves defect-free, high aspect ratio metallization filling of vias.

[0016] By providing the stress buffer layer made of polymer-based composite material on the first and second surfaces of the glass substrate, the polymer-based composite material has superior flexibility compared to rigid glass and metal, and can effectively dissipate stress through its own deformation, preventing cracks from propagating in the brittle glass substrate. At the same time, the surface active layer formed by plasma treatment significantly improves the interfacial bonding strength, fundamentally suppressing the stress concentration and delamination problems caused by the mismatch of the coefficients of thermal expansion (CTE) between copper and glass, and significantly improving the reliability of the packaging structure under thermal cycling conditions.

[0017] By employing the stress buffer layer on both the top and bottom sides, embedding or placing the chip on the buffer layer, and constructing the first and second wiring layers on this basis, the stress buffer layer acts as a multi-directional stress absorption area, effectively absorbing and dissipating residual stress from different directions. This solves the warping problem caused by residual stress accumulation in the multi-layer stacked structure of existing glass substrate packaging solutions, achieving stress balance and release, and significantly improving the overall flatness and long-term stability of the packaging structure.

[0018] By integrating the microfluidic cooling channels for transporting cooling media inside or on the surface of the glass substrate, and combining them with the TGV filled with the conductive filling material, a highly efficient dual-channel active heat dissipation system is constructed. On the one hand, the microfluidic channels directly remove the heat generated by the chip and substrate through forced convection of the medium, with heat dissipation efficiency far exceeding that of traditional air cooling or passive heat dissipation. On the other hand, the glass vias filled with the conductive filling material can act as highly efficient thermally conductive heat pipes, quickly transferring the heat from the chip to the heat sink or cooling channels, thereby effectively solving the heat dissipation bottleneck problem caused by the low thermal conductivity of the glass substrate and significantly improving the overall heat dissipation performance. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the overall structure of a chip packaging structure according to Embodiment 1 of the present invention.

[0020] Figure 2This is a cross-sectional schematic diagram along the microfluidic cooling channel in Embodiment 1 of the present invention.

[0021] Figure 3 This is a cross-sectional view along the glass through hole in Embodiment 1 of the present invention.

[0022] Figure 4 This is a schematic cross-sectional view along the glass substrate according to Embodiment 1 of the present invention.

[0023] Figure 5 This is a flowchart illustrating the packaging method of a chip packaging structure according to Embodiment 2 of the present invention.

[0024] In the above figures: 1. Glass substrate; 2. Glass via; 3. Stress buffer layer; 4. Chip; 5. First wiring layer; 6. Second wiring layer; 11. Microfluidic cooling channel; 21. Surface active layer. Detailed Implementation

[0025] The technical solutions of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0026] Example 1 like Figures 1-4 As shown, an embodiment of the present invention proposes a chip packaging structure, including: A glass substrate 1, with microfluidic cooling channels 11 integrated inside or on its surface for conveying cooling medium; Specifically, the glass substrate 1 has a thickness of 100 mm. m-500 The glass substrate 1 is made of quartz glass, borosilicate glass, or soda-lime glass of m thickness. A microfluidic cooling channel 11 for transporting a cooling medium is integrated within the glass substrate 1. The microfluidic cooling channel 11 is formed inside the substrate using precision laser processing or photolithography and etching techniques. Preferably, the microfluidic cooling channel 11 is a serpentine or mesh-like channel formed inside the glass substrate 1, with its inlet and outlet located on the sidewall of the glass substrate 1. The cross-sectional dimension of the microfluidic cooling channel 11 is 100 mm. m 200 m, spacing 300 m, an external cooling medium (such as water, ethylene glycol solution or dielectric coolant) circulation system is connected to the microfluidic cooling channel 11 through an inlet and an outlet, which can directly remove the heat generated by the chip 4, achieving efficient heat dissipation "near chip 4" and significantly reducing thermal resistance.

[0027] Multiple glass through-holes 2 are disposed through the glass substrate 1. The aspect ratio of the glass through-holes 2 is greater than 10:1, and the glass through-holes 2 are filled with conductive filler material. The inner wall of the glass through-holes 2 has a surface active layer 21 for enhancing metal adhesion. The surface active layer 21 is a glass surface that has been plasma treated. Specifically, a plurality of glass through holes 2 are provided through the glass substrate 1, and the aspect ratio of the glass through holes 2 is greater than 10:1. For example, corresponding to 300 The glass substrate 1 is m thick and has a hole diameter of approximately 25 μm. m.

[0028] Preferably, to improve the metal filling effect and reliability, the diameter of the glass via 2 varies in a gradient along its length, wherein the diameter near the first wiring layer 5 and / or the second wiring layer 6 (e.g., 30mm) is gradually increased. m) is larger than the aperture inside the glass substrate 1 (e.g., 20). This "trumpet-shaped" structure (m) facilitates the filling of subsequent conductive materials (such as copper) and reduces voids.

[0029] The inner wall of the glass through-hole 2 has a surface-active layer 21 for enhancing metal adhesion. The surface-active layer 21 is a glass surface treated with oxygen plasma or argon plasma. The treated surface will generate active groups such as hydroxyl groups or form nanoscale roughness. For example, oxygen plasma (O2) is used to perform surface activation treatment on the inner wall of the glass through-hole 2. The treatment power is 100-300W, the treatment time is 5-30min, and the treatment pressure is 10-50Pa. After treatment, the contact angle of the glass surface is reduced from the original 40-50 degrees to less than 5 degrees, which significantly improves the surface energy, thereby enhancing the bonding force between the glass and the conductive filler material (such as copper), avoiding voids or delamination in the subsequent electroplating process, and effectively preventing the metal layer from peeling off during thermal cycling.

[0030] The glass via 2 is completely filled with the conductive filler material, such as metallic copper, thereby forming a reliable vertical interconnect. The glass via 2 filled with the conductive filler material can act as a highly efficient heat-conducting via, quickly transferring the heat of the chip 4 to the heat sink or cooling channel, effectively improving the heat dissipation effect.

[0031] A stress buffer layer 3 is disposed on a first surface and a second surface opposite to the first surface of the glass substrate 1, and is used to absorb stress generated during thermal cycling; the stress buffer layer 3 is made of a polymer-based composite material. Specifically, stress buffer layers 3 are formed on a first surface (such as the upper surface) and a second surface (such as the lower surface) opposite to the first surface of the glass substrate 1, respectively. The stress buffer layers 3 are made of polymer-based composite materials, such as at least one of epoxy resin, polyimide (PI), or benzocyclobutene (BCB). Preferably, the thickness of the stress buffer layer 3 is 10. m-100 m, the coefficient of thermal expansion of the polymer-based composite material used in the stress buffer layer 3 is between that of the chip 4 (approximately 2.6 ppm / ℃) and the glass substrate 1 (e.g., 5-8 ppm / ℃, depending on the glass type). For example, an epoxy resin doped with silica filler is used, whose coefficient of thermal expansion (CTE) can be adjusted to approximately 4.5 ppm / ℃, effectively mitigating the CTE mismatch between the chip 4 and the glass substrate 1.

[0032] More preferably, the stress buffer layer 3 is dispersed with thermally conductive filler, which is at least one of boron nitride, aluminum oxide or diamond. These fillers not only improve the thermal conductivity of the stress buffer layer 3 (thermal conductivity can reach 1-5 W / m·K), but also provide an additional heat dissipation path for the chip 4.

[0033] At least one chip 4 is disposed on the first surface of the glass substrate 1 and embedded in or disposed on the stress buffer layer 3; Specifically, the chip 4 (which may be a single high-performance computing chip or a large chip structure composed of multiple chips) is disposed on the first surface of the glass substrate 1. The chip 4 has its microbumps embedded in the stress buffer layer 3 by flip-chip bonding or other methods (the microbumps may also be disposed on the stress buffer layer 3). If the chip 4 is a large chip structure composed of multiple chips, the multiple chips can be interconnected through the first wiring layer 5 or the second wiring layer 6.

[0034] The first wiring layer 5 is disposed on the stress buffer layer 3 on the first surface, and electrically connects the chip 4 to the glass through-hole 2; The second wiring layer 6 is disposed on the stress buffer layer 3 on the second surface and is electrically connected to the glass through-hole 2.

[0035] Specifically, the first wiring layer 5 is formed on the stress buffer layer 3 on the first surface. It is formed by photolithography and electroplating processes and contains fine lines and dielectric layers. The first wiring layer 5 electrically connects the I / O ports of the chip 4 to the top of the glass via 2 below. The second wiring layer 6 is formed on the stress buffer layer 3 on the second surface and electrically connects to the bottom of the glass via 2. Solder balls (BGA balls) can be fabricated on the second wiring layer 6 for mounting the entire package structure onto the PCB board.

[0036] In this embodiment, a chip packaging structure of the present invention solves the core problem of glass packaging through a three-layer collaborative design: In terms of heat dissipation, when the chip 4 is operating, the stress generated by rapid thermal cycling is absorbed by the stress buffer layer 3, while the microfluidic cooling channel 11 can quickly remove heat, reducing the amplitude and frequency of thermal cycling. The combination of the two achieves a dual effect of "active cooling + passive energy absorption". While using the cooling channel alone can reduce temperature, thermal stress will still act rapidly on the fragile glass substrate 1; while using the stress buffer layer 3 alone can absorb some stress, the accumulation of high temperature will lead to the degradation of the buffer layer's performance. The synergy of the two significantly improves the reliability and lifespan of the packaging structure under extreme temperature changes (such as -55℃ to 125℃), a "qualitative change" that cannot be achieved by a single feature.

[0037] In terms of stress management, since the chip 4 embedded package (Fan-out) itself can shorten the interconnection distance, when the chip 4 is embedded in the stress buffer layer 3 made of polymer-based composite material, the stress buffer layer 3 not only plays a role in mechanical support and stress buffering, but also serves as a base for the chip 4, effectively bridging the huge difference in coefficient of thermal expansion (CTE) between the chip 4 and the glass substrate 1. At the same time, the double-layer buffer layer design on the upper and lower surfaces forms a CTE gradient transition layer, dispersing the concentrated stress at the chip 4-glass interface to the entire package, avoiding cracks or delamination caused by local stress concentration.

[0038] Regarding electrical interconnect reliability, the surface active layer 21 on the inner wall of the glass via 2 after plasma treatment can uniformly form an adhesion layer throughout the entire inner wall (including the depth) of the glass via 2, so that the glass via 2 with a high aspect ratio (greater than 10:1) can be uniformly filled, thereby realizing high-density interconnection on the ultra-thin glass substrate 1 and ensuring the electrical performance and long-term reliability of the high aspect ratio metallized via.

[0039] Example 2 like Figure 5 As shown, another embodiment of the present invention proposes a packaging method for a chip packaging structure, comprising the following steps: S1. A glass substrate 1 is provided, and microfluidic cooling channels 11 for conveying cooling medium are integrated inside or on the surface of the glass substrate 1. S2. A plurality of glass through holes 2 are formed in the glass substrate 1, and conductive filler material is filled in the glass through holes 2 to form a vertical interconnection structure. Then, the inner wall of the glass through holes 2 is subjected to plasma treatment to form a surface active layer 21 that enhances the adhesion of metal. The aspect ratio of the glass through holes 2 is greater than 10:1. The glass substrate 1 is made of quartz glass, borosilicate glass, or soda-lime glass, and the thickness of the glass substrate 1 is 100 mm. m-500 m; the surface active layer 21 is a glass surface treated with oxygen plasma or argon plasma.

[0040] S3. Stress buffer layers 3 are formed on the first surface of the glass substrate 1 and the second surface opposite to the first surface, respectively. The stress buffer layers 3 are made of polymer-based composite materials to absorb the stress generated during thermal cycling. The polymer-based composite material comprises at least one of epoxy resin, polyimide, or benzocyclobutene, and is formed on the first and second surfaces of the glass substrate 1 by spin coating, spraying, or lamination processes, with a thickness of 10. m-100 m.

[0041] S4. At least one chip 4 is disposed on the first surface of the glass substrate 1, and the chip 4 is embedded in the stress buffer layer 3 or disposed on the stress buffer layer 3. The chip 4 is a single chip 4 or a large chip 4 structure composed of multiple chips, and the multiple chips are interconnected through the first wiring layer 5 or the second wiring layer 6; the inlet and outlet of the microfluidic cooling channel 11 are respectively connected to an external cooling medium circulation system.

[0042] S5. A first wiring layer 5 is formed on the stress buffer layer 3 on the first surface, and the first wiring layer 5 electrically connects the chip 4 to the glass via 2. S6. A second wiring layer 6 is formed on the stress buffer layer 3 on the second surface, and the second wiring layer 6 is electrically connected to the glass through-hole 2.

[0043] In this embodiment, the specific steps of the packaging method for a chip packaging structure of the present invention are as follows: (1) Providing and processing glass substrate 1: Provide a 100mm thick sheet m-500 The glass substrate 1 (such as borosilicate glass) of m uses laser-induced etching or photosensitive glass technology to form the microfluidic cooling channel 11 for transporting cooling medium inside the glass substrate 1. The channel has a serpentine or mesh structure, and its inlet and outlet are located at predetermined sidewall positions of the glass substrate 1.

[0044] (2) Forming glass through-hole 2 (TGV) and treating the inner wall: Multiple through-holes 2 are formed within the glass substrate 1 using femtosecond laser or photolithography and deep reactive ion etching (DRIE) technology. By adjusting process parameters, the aperture size is controlled to exhibit a gradient change, with the top and bottom apertures larger than those in the middle region. Subsequently, the inner walls of the glass through-holes 2 are subjected to plasma treatment, for example, oxygen plasma (O2) is used for surface activation treatment of the inner walls of the glass through-holes 2. The treatment power is 100-300W, the treatment time is 5-30min, and the treatment pressure is 10-50Pa. This step introduces polar functional groups such as hydroxyl and carbonyl groups onto the surface of the glass through-holes 2, forming a surface active layer 21 that enhances metal adhesion.

[0045] (3) Filling glass through-hole 2 (TGV): On the glass substrate 1 after plasma treatment, a titanium / copper seed layer is deposited by physical vapor deposition (PVD). Due to the presence of the surface active layer 21, the bonding force between the seed layer and the glass is greatly enhanced. Subsequently, the glass via 2 is filled from both the top and bottom surfaces of the glass substrate 1 by electroplating copper to ensure that there are no voids and to form a conductive pillar with a high aspect ratio.

[0046] (4) Formation of stress buffer layer 3: A stress buffer layer 3 is formed on the first and second surfaces of the glass substrate 1 by spin coating, spraying, or lamination processes. The stress buffer layer 3 is made of a polymer-based composite material, such as epoxy resin mixed with boron nitride thermally conductive filler and silica CTE regulating filler. By adjusting the formulation, its coefficient of thermal expansion is made to be between that of the chip 4 and the glass substrate 1. After curing, the thickness of the stress buffer layer 3 is controlled to be 10 mm. m-100 m.

[0047] (5) Install chip 4 and form a wiring layer: At least one chip 4 is disposed on or within the stress buffer layer 3 on the first surface of the glass substrate 1 using a flip-chip reflow soldering process. Subsequently, using standard semiconductor back-end processes, the first wiring layer 5 is fabricated on the surface of the soldered chip 4. The first wiring layer 5 is formed by steps such as opening holes in the stress buffer layer 3, sputtering metal, electroplating, and etching, to achieve electrical connection between the microbumps of the chip 4 and the top of the glass via 2. Similarly, the second wiring layer 6 is fabricated on the stress buffer layer 3 on the second surface of the glass substrate 1 to achieve electrical connection between the bottom of the glass via 2 and the outside. Finally, solder balls are fabricated on the second wiring layer 6.

[0048] (6) Connect the cooling system: The inlet and outlet of the microfluidic cooling channel 11 on the sidewall of the glass substrate 1 are connected to an external coolant circulation system through pipes to complete the entire encapsulation.

[0049] Compared with the prior art, the chip packaging structure and packaging method provided by the present invention have the following significant advantages, as detailed below: (1) Excellent heat dissipation performance: By integrating the microfluidic cooling channel 11, direct liquid cooling of the bottom of the chip 4 is achieved. Compared with traditional air cooling or heat dissipation through a heat spreader, the thermal resistance is expected to be reduced by 30%-50%. Combined with the high thermal conductivity filler in the stress buffer layer 3, a highly efficient three-dimensional heat dissipation network is formed, which can support a heat flux density of more than 1000W / cm², thus solving the heat dissipation bottleneck of the high-performance AI chip 4.

[0050] (2) Extremely high packaging reliability: By setting the stress buffer layer 3 made of polymer-based composite material with matching thermal expansion coefficient, the thermal stress between the chip 4 and the glass substrate 1 is effectively absorbed. Simulation data shows (based on finite element analysis of the same package size) that after 1000 thermal cycle tests from -55℃ to +125℃, the fatigue life of the solder joint is more than 5 times higher than that of the glass package structure without buffer layer. At the same time, the stress buffer layer 3 also significantly reduces the risk of breakage of the glass substrate 1.

[0051] (3) Excellent electrical interconnect quality: By plasma treatment of the inner wall of the glass via 2 (TGV), active functional groups are formed, which increases the bonding force between the metal seed layer and the glass by more than 80% (based on ASTM D3359 cross-cut test). This not only ensures the filling quality of the high aspect ratio via, but also eliminates signal integrity problems and reliability risks caused by interface separation.

[0052] (4) High design freedom and integration: It allows multiple chips with different functions to be integrated on the same glass substrate 1, and high-speed interconnection between chips 4 is achieved through a high-density wiring layer. At the same time, the design of the glass via 2 with gradient aperture further optimizes the electroplating filling effect, supports higher density I / O layout, and adapts to the future development trend of large size and multi-chip packaging.

[0053] (5) Strong process compatibility: The manufacturing method of the present invention is mainly based on mature laser processing, semiconductor thin film deposition and electroplating technologies. There is no need to introduce disruptive new equipment, which facilitates the technological upgrading and rapid industrialization on existing packaging production lines. Among them, TGV electroplating technology has a high degree of technical compatibility with existing PCB and semiconductor electroplating processes.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A chip packaging structure, characterized in that, include: A glass substrate, the interior or surface of which is integrated with microfluidic cooling channels for delivering cooling media; Multiple glass vias are disposed through the glass substrate, the aspect ratio of the glass vias is greater than 10:1, and the glass vias are filled with conductive filler material; the inner wall of the glass vias has a surface active layer for enhancing metal adhesion, the surface active layer being a glass surface treated with plasma. A stress buffer layer is disposed on a first surface and a second surface opposite to the first surface of the glass substrate to absorb stress generated during thermal cycling; the stress buffer layer is made of a polymer-based composite material. At least one chip is disposed on the first surface of the glass substrate and embedded in or disposed on the stress buffer layer; A first wiring layer is disposed on the stress buffer layer of the first surface, and electrically connects the chip to the glass via. The second wiring layer is disposed on the stress buffer layer of the second surface and is electrically connected to the glass through-hole.

2. The chip packaging structure as described in claim 1, characterized in that, The diameter of the glass via varies in a gradient along its length, wherein the diameter of the via near the first wiring layer and / or the second wiring layer is larger than the diameter of the via inside the glass substrate.

3. The chip packaging structure as described in claim 1, characterized in that, The coefficient of thermal expansion of the polymer-based composite material used in the stress buffer layer is between that of the chip and the glass substrate.

4. A chip packaging structure as described in claim 1 or 3, characterized in that, The stress buffer layer contains thermally conductive fillers, which are at least one of boron nitride, aluminum oxide, or diamond.

5. The chip packaging structure as described in claim 1, characterized in that, The microfluidic cooling channel is a serpentine or mesh-like channel formed inside the glass substrate, with its inlet and outlet located on the sidewall of the glass substrate.

6. A packaging method for a chip packaging structure, applied to the chip packaging structure according to any one of claims 1-5, characterized in that, Includes the following steps: A glass substrate is provided, wherein microfluidic cooling channels for conveying cooling medium are integrated inside or on the surface of the glass substrate; Multiple glass vias are formed in the glass substrate, and conductive filler material is filled in the glass vias to form a vertical interconnect structure. The inner walls of the glass vias are then subjected to plasma treatment to form a surface-active layer that enhances metal adhesion. The aspect ratio of the glass vias is greater than 10:

1. Stress buffer layers are formed on a first surface of the glass substrate and a second surface opposite to the first surface, respectively. The stress buffer layers are made of polymer-based composite materials to absorb stress generated during thermal cycling. At least one chip is disposed on the first surface of the glass substrate, and the chip is embedded in or disposed on the stress buffer layer. A first wiring layer is formed on the stress buffer layer of the first surface, and the first wiring layer electrically connects the chip to the glass via. A second wiring layer is formed on the stress buffer layer of the second surface, and the second wiring layer is electrically connected to the glass via.

7. The packaging method for a chip packaging structure as described in claim 6, characterized in that, The glass substrate is made of quartz glass, borosilicate glass, or soda-lime glass, and the thickness of the glass substrate is 100 mm. m-500 m; the surface active layer is a glass surface treated with oxygen plasma or argon plasma.

8. The packaging method for a chip packaging structure as described in claim 6, characterized in that, The polymer-based composite material comprises at least one of epoxy resin, polyimide, or benzocyclobutene, and is formed on the first and second surfaces of the glass substrate by spin coating, spraying, or lamination processes, with a thickness of 10. m-100 m.

9. The packaging method for a chip packaging structure as described in claim 6, characterized in that, The chip is a single chip or a large chip structure composed of multiple chips, and the multiple chips are interconnected through the first wiring layer or the second wiring layer; the inlet and outlet of the microfluidic cooling channel are respectively connected to an external cooling medium circulation system.

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