Bending-resistant dpc ceramic substrate with stress buffer gradient structure and preparation method

Abstract

The application discloses a DPC ceramic substrate with stress buffering function and a preparation method thereof, and belongs to the technical field of semiconductor packaging. The substrate comprises a ceramic base body, and a gradient stress buffering composite layer and a DPC precise copper circuit layer are sequentially stacked on the surface of the ceramic base body; the gradient stress buffering composite layer comprises a nano ceramic transition layer, a porous flexible metal buffering layer and a dense metal transition layer. The application adopts a gradient modulus buffering structure, realizes smooth transition of mechanical and thermal properties from the ceramic base body to the metal circuit, completely solves the industry pain point of stress concentration at the interface of the traditional DPC substrate, and inhibits delamination and cracking failure; the porous flexible metal buffering layer has excellent stress absorption capacity, and the bending resistance, mechanical impact resistance and fatigue resistance of the substrate are greatly improved, and the substrate is suitable for high-vibration complex working conditions such as vehicle-mounted and portable devices; the homologous nano ceramic transition layer realizes seamless combination of the base body, the interface bonding force is improved by more than 50%, and the reliability is significantly better than that of the traditional structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor DPC ceramic substrate technology, and in particular to a bending-resistant DPC ceramic substrate with a stress buffer gradient structure and its preparation method. It has excellent bending and impact resistance, high reliability, and is suitable for packaging scenarios with extremely high requirements for substrate mechanical reliability, such as automotive vibration conditions, portable power devices, and flexible packaging modules. Background Technology

[0002] Directly plated copper (DPC) ceramic substrates have become a core material for high-power semiconductor device packaging due to their high thermal conductivity, high insulation, and precision circuit forming capabilities. Traditional DPC ceramic substrates typically employ a structure where a hard ceramic substrate (such as alumina or aluminum nitride) is directly composited with electroplated copper circuitry. However, ceramic materials are inherently brittle, while electroplated copper layers are highly ductile, resulting in significant differences in their coefficients of thermal expansion (CTE) and mechanical modulus. Under the complex operating conditions of electronic devices, such as equipment vibration, module bending, and thermal cycling, the interface between the copper layer and the ceramic substrate experiences continuous shear stress due to material property mismatch. Long-term exposure to this stress can easily lead to fatal failures such as copper layer peeling, delamination, microcracks in the ceramic substrate, and even circuit breakage, severely impacting the long-term reliability of the substrate.

[0003] To address the aforementioned issues, existing solutions often employ methods such as thickening the copper layer or adding a single transition metal layer (e.g., nickel or titanium) to alleviate interfacial stress. However, these solutions still have significant drawbacks: a single transition layer cannot create a buffer structure with a gradual modulus change between the ceramic and copper circuitry, stress cannot be gradually released along the thickness direction, and stress concentration remains a prominent problem. Especially in demanding operating conditions with high vibration and high reliability requirements, such as automotive electronics and industrial control, the substrate is frequently subjected to mechanical vibration and temperature shocks. Existing structures, lacking effective stress buffering mechanisms, exhibit extremely poor mechanical fatigue resistance and a significantly shortened service life.

[0004] The limitations of traditional DPC ceramic substrates in terms of bending resistance and thermal cycling fatigue resistance make it difficult to meet the high flexibility and high reliability requirements of packaging substrates in emerging fields such as automotive semiconductors and portable power modules, severely restricting the widespread adoption of DPC ceramic substrates in these applications. Therefore, the industry urgently needs a novel DPC ceramic substrate structure and fabrication method that can fundamentally achieve stress gradient release and possess excellent bending resistance to solve these technical challenges. Summary of the Invention

[0005] In view of this, the present invention addresses the shortcomings of the prior art, and its main objective is to provide a bending-resistant DPC ceramic substrate with a stress buffer gradient structure and a preparation method thereof, which can effectively solve the technical defects of existing DPC ceramic substrates, such as stress concentration at the ceramic-metal interface, poor bending resistance, easy failure under vibration conditions, and weak fatigue resistance.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: A bending-resistant DPC ceramic substrate with a stress-buffered gradient structure includes a ceramic substrate, a gradient stress-buffered composite layer, and a DPC precision copper circuit layer. The gradient stress-buffered composite layer is integrally deposited on the surface of the ceramic substrate, and the DPC precision copper circuit layer is formed on the surface of the gradient stress-buffered composite layer. The gradient stress-buffered composite layer consists of a nano-ceramic transition layer, a porous flexible metal buffer layer, and a dense metal transition layer from the inside to the outside. The nano-ceramic transition layer, the porous flexible metal buffer layer, and the dense metal transition layer together constitute a stress-relieving structure with a gradually changing modulus.

[0007] As a preferred embodiment, the thickness of the nano-ceramic transition layer is 0.5–1 μm, and the material of the nano-ceramic transition layer is homologous to the material of the ceramic matrix.

[0008] As a preferred embodiment, the nano-ceramic transition layer is made of alumina or aluminum nitride nanopowder sintered layer.

[0009] As a preferred embodiment, the thickness of the porous flexible metal buffer layer is 3 to 6 μm, and the porous flexible metal buffer layer is a nickel-copper alloy porous structure with a porosity of 15% to 25%.

[0010] As a preferred embodiment, the thickness of the dense metal transition layer is 2–4 μm, and the dense metal transition layer is a pure copper dense plating layer.

[0011] As a preferred embodiment, the thickness of the ceramic substrate is 0.2–0.8 mm, and the thickness of the DPC precision copper circuit layer is 25–120 μm.

[0012] As a preferred embodiment, the DPC precision copper circuit layer consists of a circuit body layer and a circuit transition layer, wherein the circuit transition layer is sandwiched between the circuit body layer and the dense metal transition layer.

[0013] A method for preparing a bending-resistant DPC ceramic substrate with a stress-buffered gradient structure includes the following steps: S1. Precision pretreatment of the substrate: The ceramic substrate is subjected to double-sided grinding, polishing, and ultrasonic degreasing. Plasma is used to roughen and activate the ceramic surface to obtain a ceramic matrix and improve the interfacial bonding performance of the ceramic matrix. S2, In-situ grown nano-ceramic transition layer; S3, Electrodeposited porous flexible metal buffer layer; S4. Electroplated dense metal transition layer: A pure copper dense layer is electroplated on the surface of the porous flexible metal buffer layer to seal the surface pores and form a flat conductive substrate, thus obtaining a dense metal transition layer. S5. Photolithography-formed DPC circuit: Precision copper circuit layer of DPC is prepared by photolithography, pattern electroplating and etching processes; S6. Low-temperature stress annealing: Anneal at a low temperature of 180-200℃ for 20-40 minutes to eliminate residual stress in the multilayer structure and complete the preparation of the finished product.

[0014] As a preferred embodiment, in step S2, a homologous nano-ceramic coating is deposited in situ on the surface of the ceramic substrate using a sol-gel process, and a dense, seamless nano-ceramic transition layer is formed by low-temperature sintering.

[0015] As a preferred embodiment, in step S3, a pulse segmented electroplating process is used to control the current density and deposit a nickel-copper alloy with controllable porosity on the surface of the nano-ceramic transition layer to form a porous flexible metal buffer layer.

[0016] Compared with the prior art, the present invention has obvious advantages and beneficial effects. Specifically, as can be seen from the above technical solution: By innovatively designing a gradient stress buffer composite layer, a nano-ceramic transition layer, a porous flexible metal buffer layer, and a dense metal transition layer are sequentially formed between the ceramic substrate and the DPC precision copper circuit layer. This achieves a continuous and gradual modulus transition from hard ceramic to high-ductility copper circuitry, fundamentally eliminating abrupt changes in mechanical and thermal properties at the interface. It completely solves the industry pain point of stress concentration at the interface of traditional DPC ceramic substrates, effectively preventing copper layer peeling, delamination, and ceramic microcracks under thermal cycling and vibration conditions. The porous flexible metal buffer layer possesses excellent stress absorption and dissipation capabilities, significantly improving the substrate's resistance to bending, mechanical impact, and fatigue, making it fully adaptable to harsh, high-vibration, and complex operating conditions such as automotive electronics and portable devices. Simultaneously, the nano-ceramic transition layer, made of the same material as the ceramic substrate, achieves seamless bonding with the substrate surface through in-situ deposition or sintering. The interfacial bonding strength is increased by more than 50% compared to traditional structures, ensuring that the substrate remains free of delamination and peeling during long-term use, with significantly superior reliability compared to existing products. Furthermore, the gradient stress buffer composite layer can be integrally deposited and formed, which is simple to prepare, highly compatible, and does not require large-scale modification of existing DPC production lines. It is easy to achieve mass production, and the mass production cost is low and the yield is high, which has a strong advantage for industrialization and promotion.

[0017] To more clearly illustrate the structural features and effects of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0018] Figure 1 This is an exploded view of the present invention.

[0019] Explanation of reference numerals in the attached diagram: 10. Ceramic matrix; 20. Gradient stress buffer composite layer 21. Nano-ceramic transition layer; 22. Porous flexible metal buffer layer 23. Dense metal transition layer; 30. DPC precision copper circuit layer 31. Main line layer; 32. Transition line layer. Detailed Implementation

[0020] Please refer to Figure 1 As shown, it illustrates the specific structure of a bending-resistant DPC ceramic substrate with a stress-buffered gradient structure according to the present invention, including a ceramic substrate 10, a gradient stress-buffered composite layer 20, and a DPC precision copper circuit layer 30.

[0021] The gradient stress buffer composite layer 20 is integrally deposited on the surface of the ceramic substrate 10, and the DPC precision copper circuit layer 30 is formed on the surface of the gradient stress buffer composite layer 20. The gradient stress buffer composite layer 20 consists of a nano-ceramic transition layer 21, a porous flexible metal buffer layer 22, and a dense metal transition layer 23 from the inside to the outside. The nano-ceramic transition layer 21, the porous flexible metal buffer layer 22, and the dense metal transition layer 23 together constitute a stress relief structure with a gradually changing modulus.

[0022] Specifically, the thickness of the ceramic substrate 10 is 0.2–0.8 mm. The thickness of the nano-ceramic transition layer 21 is 0.5–1 μm. The material of the nano-ceramic transition layer 21 is homologous to that of the ceramic substrate 10, achieving seamless bonding and eliminating interfacial porosity. The material of the nano-ceramic transition layer 21 is an alumina or aluminum nitride nanopowder sintered layer. The porous flexible metal buffer layer 22 has a microporous structure, which can absorb and buffer shear stress generated by bending and thermal expansion and contraction. The thickness of the porous flexible metal buffer layer 22 is 3–6 μm. The porous flexible metal buffer layer 22 is a nickel-copper alloy porous structure with a porosity of 15%–25%. The thickness of the dense metal transition layer 23 is 2–4 μm. The dense metal transition layer 23 is a pure copper dense plating layer. The dense metal transition layer 23 ensures the bonding strength and conductivity consistency with the DPC precision copper circuit layer 30. The thickness of the DPC precision copper circuit layer 30 is 25–120 μm, and the entire substrate can withstand repeated bending at small angles without cracking or delamination failure. Furthermore, the DPC precision copper circuit layer 30 is composed of a circuit body layer 31 and a circuit transition layer 32, with the circuit transition layer 32 sandwiched between the circuit body layer 31 and the dense metal transition layer 23.

[0023] This invention also discloses a method for preparing the aforementioned stress-buffered gradient structure-equipped, bend-resistant DPC ceramic substrate, comprising the following steps: S1. Precision pretreatment of the substrate: The ceramic substrate is subjected to double-sided grinding, polishing, and ultrasonic degreasing. The ceramic surface is roughened and activated by plasma to obtain the ceramic substrate 10, thereby improving the interfacial bonding performance of the ceramic substrate 10.

[0024] S2. In-situ growth of nano-ceramic transition layer 21. Specifically, a homologous nano-ceramic coating is deposited in-situ on the surface of a ceramic substrate using a sol-gel process, and a dense and seamless nano-ceramic transition layer 21 is formed by low-temperature sintering.

[0025] S3. Electrodeposition of a porous flexible metal buffer layer 22. Specifically, a pulse segmented electroplating process is used to control the current density and deposit a nickel-copper alloy with controllable pores on the surface of the nano-ceramic transition layer 21 to form a porous flexible metal buffer layer 22.

[0026] S4. Electroplating dense metal transition layer 23: Electroplating a dense pure copper layer on the surface of the porous flexible metal buffer layer 22 to seal the surface pores and form a flat conductive substrate, thereby obtaining the dense metal transition layer 23.

[0027] S5. Photolithography-formed DPC circuit: DPC precision copper circuit layer 30 is prepared by photolithography, pattern electroplating, and etching processes.

[0028] S6. Low-temperature stress annealing: Anneal at a low temperature of 180-200℃ for 20-40 minutes to eliminate residual stress in the multilayer structure and complete the preparation of the finished product.

[0029] The present invention will be further described in detail below with reference to several embodiments: Example 1: First, a 0.4 mm thick alumina ceramic substrate was selected and polished on both sides until the surface roughness Ra ≤ 0.05 μm. After ultrasonic degreasing and argon plasma activation for 6 min, ceramic substrate 10 was obtained.

[0030] Next, an 0.8 μm nano-ceramic coating was deposited in situ using an alumina sol-gel process and sintered at a low temperature of 150 °C to obtain a nano-ceramic transition layer 21. A 4 μm thick nickel-copper alloy with a porosity of 20% was prepared on the nano-ceramic transition layer 21 by segmented pulse electroplating to obtain a porous flexible metal buffer layer 22. Subsequently, 3 μm of pure copper was electroplated on the porous flexible metal buffer layer 22 to obtain a dense metal transition layer 23, thus forming a gradient stress buffer composite layer 20.

[0031] Then, a 50 μm thick DPC precision copper circuit layer 30 is prepared by pattern electroplating on the surface of the dense metal transition layer 23 of the gradient stress buffer composite layer 20, and residual stress is eliminated by low-temperature annealing at 190°C for 30 min.

[0032] Tests showed that the substrate interface bonding strength in this embodiment can reach 35 N / mm. After 1500 cycles of thermal cycling from -40℃ to 125℃ and 1000 cycles of micro-angle bending tests, the substrate showed no cracks, no delamination, and no circuit breakage. Its mechanical reliability far exceeds that of traditional DPC ceramic substrates.

[0033] Example 2: First, a 0.2 mm thick alumina ceramic substrate was selected and polished on both sides until the surface roughness Ra ≤ 0.05 μm. After ultrasonic degreasing and argon plasma activation for 4 min, ceramic substrate 10 was obtained.

[0034] Next, a 1 μm nano-ceramic coating was deposited in situ using an alumina sol-gel process and sintered at a low temperature of 140 °C to obtain a nano-ceramic transition layer 21. A 3 μm thick nickel-copper alloy with a porosity of 15% was prepared on the nano-ceramic transition layer 21 by segmented pulse electroplating to obtain a porous flexible metal buffer layer 22. Subsequently, 2 μm of pure copper was electroplated on the porous flexible metal buffer layer 22 to obtain a dense metal transition layer 23, thus forming a gradient stress buffer composite layer 20.

[0035] Then, a 70 μm thick DPC precision copper circuit layer 30 is prepared by pattern electroplating on the surface of the dense metal transition layer 23 of the gradient stress buffer composite layer 20, and residual stress is eliminated by low-temperature annealing at 180°C for 20 min.

[0036] Tests showed that the substrate interface bonding strength in this embodiment can reach 33 N / mm. After 1500 cycles of thermal cycling from -40℃ to 125℃ and 1000 cycles of micro-angle bending, the substrate showed no cracks, no delamination, and no circuit breakage. Its mechanical reliability far exceeds that of traditional DPC ceramic substrates.

[0037] Example 3: First, a 0.8 mm thick aluminum nitride ceramic substrate was selected and polished on both sides until the surface roughness Ra ≤ 0.05 μm. After ultrasonic degreasing and argon plasma activation for 10 min, ceramic substrate 10 was obtained.

[0038] Next, a 0.6 μm nano-ceramic coating was deposited in situ using an aluminum nitride sol-gel process and sintered at a low temperature of 160 °C to obtain a nano-ceramic transition layer 21. A 5 μm thick nickel-copper alloy with a porosity of 25% was prepared on the nano-ceramic transition layer 21 by segmented pulse electroplating to obtain a porous flexible metal buffer layer 22. Subsequently, 4 μm of pure copper was electroplated on the porous flexible metal buffer layer 22 to obtain a dense metal transition layer 23, thus forming a gradient stress buffer composite layer 20.

[0039] Then, a 120 μm thick DPC precision copper circuit layer 30 is prepared by pattern electroplating on the surface of the dense metal transition layer 23 of the gradient stress buffer composite layer 20, and residual stress is eliminated by low-temperature annealing at 200℃ for 40 min.

[0040] Tests showed that the substrate interface bonding strength in this embodiment can reach 32 N / mm. After 1500 cycles of thermal cycling from -40℃ to 125℃ and 1000 cycles of micro-angle bending, the substrate showed no cracks, no delamination, and no circuit breakage. Its mechanical reliability far exceeds that of traditional DPC ceramic substrates.

[0041] Example 4: First, a 0.5 mm thick aluminum nitride ceramic substrate was selected and polished on both sides until the surface roughness Ra ≤ 0.05 μm. After ultrasonic degreasing and argon plasma activation for 8 min, ceramic substrate 10 was obtained.

[0042] Next, a 0.7 μm nano-ceramic coating was deposited in situ using an aluminum nitride sol-gel process and sintered at a low temperature of 145 °C to obtain a nano-ceramic transition layer 21. A 6 μm thick nickel-copper alloy with a porosity of 22% was prepared on the nano-ceramic transition layer 21 by segmented pulse electroplating to obtain a porous flexible metal buffer layer 22. Subsequently, 2.5 μm of pure copper was electroplated on the porous flexible metal buffer layer 22 to obtain a dense metal transition layer 23, thus forming a gradient stress buffer composite layer 20.

[0043] Then, a 100 μm thick DPC precision copper circuit layer 30 is prepared by pattern electroplating on the surface of the dense metal transition layer 23 of the gradient stress buffer composite layer 20, and residual stress is eliminated by low-temperature annealing at 195 °C for 25 min.

[0044] Tests showed that the substrate interface bonding strength in this embodiment can reach 30N / mm. After 1500 cycles of thermal cycling from -40℃ to 125℃ and 1000 cycles of micro-angle bending, the substrate showed no cracks, no delamination, and no circuit breakage. Its mechanical reliability far exceeds that of traditional DPC ceramic substrates.

[0045] Example 5: First, a 0.3 mm thick alumina ceramic substrate was selected and polished on both sides until the surface roughness Ra ≤ 0.05 μm. After ultrasonic degreasing and argon plasma activation for 11 min, ceramic substrate 10 was obtained.

[0046] Next, a 0.9 μm nano-ceramic coating was deposited in situ using an alumina sol-gel process and sintered at a low temperature of 155 °C to obtain a nano-ceramic transition layer 21. A 4.5 μm thick nickel-copper alloy with a porosity of 18% was prepared on the nano-ceramic transition layer 21 by segmented pulse electroplating to obtain a porous flexible metal buffer layer 22. Subsequently, 3.5 μm of pure copper was electroplated on the porous flexible metal buffer layer 22 to obtain a dense metal transition layer 23, thus forming a gradient stress buffer composite layer 20.

[0047] Then, an 80 μm thick DPC precision copper circuit layer 30 is prepared by pattern electroplating on the surface of the dense metal transition layer 23 of the gradient stress buffer composite layer 20, and residual stress is eliminated by low-temperature annealing at 185 °C for 35 min.

[0048] Tests showed that the substrate interface bonding strength in this embodiment can reach 35 N / mm. After 1500 cycles of thermal cycling from -40℃ to 125℃ and 1000 cycles of micro-angle bending tests, the substrate showed no cracks, no delamination, and no circuit breakage. Its mechanical reliability far exceeds that of traditional DPC ceramic substrates.

[0049] Example 6: First, a 0.6 mm thick alumina ceramic substrate was selected and polished on both sides until the surface roughness Ra ≤ 0.05 μm. After ultrasonic degreasing and argon plasma activation for 8 min, ceramic substrate 10 was obtained.

[0050] Next, a 0.5 μm nano-ceramic coating was deposited in situ using an alumina sol-gel process and sintered at a low temperature of 160 °C to obtain a nano-ceramic transition layer 21. A 3.5 μm thick nickel-copper alloy with a porosity of 24% was prepared on the nano-ceramic transition layer 21 by segmented pulse electroplating to obtain a porous flexible metal buffer layer 22. Subsequently, 3 μm of pure copper was electroplated on the porous flexible metal buffer layer 22 to obtain a dense metal transition layer 23, thus forming a gradient stress buffer composite layer 20.

[0051] Then, a 90 μm thick DPC precision copper circuit layer 30 is prepared by pattern electroplating on the surface of the dense metal transition layer 23 of the gradient stress buffer composite layer 20, and residual stress is eliminated by low-temperature annealing at 188 °C for 38 min.

[0052] Tests showed that the substrate interface bonding strength in this embodiment can reach 31 N / mm. After 1500 cycles of thermal cycling from -40℃ to 125℃ and 1000 cycles of micro-angle bending, the substrate showed no cracks, no delamination, and no circuit breakage. Its mechanical reliability far exceeds that of traditional DPC ceramic substrates.

[0053] The key design focus of this invention is the innovative design of a gradient stress buffer composite layer. This layer sequentially forms a nano-ceramic transition layer, a porous flexible metal buffer layer, and a dense metal transition layer between the ceramic substrate and the DPC precision copper circuit layer. This achieves a continuous, gradual modulus transition from hard ceramic to highly ductile copper circuitry, fundamentally eliminating abrupt changes in mechanical and thermal properties at the interface. It completely solves the industry pain point of stress concentration at the interface of traditional DPC ceramic substrates, effectively preventing copper layer peeling, delamination, and ceramic microcracks under thermal cycling and vibration conditions. The porous flexible metal buffer layer possesses excellent stress absorption and dissipation capabilities, significantly improving the substrate's resistance to bending, mechanical impact, and fatigue, making it fully adaptable to harsh, high-vibration, and complex operating conditions such as automotive electronics and portable devices. Simultaneously, the use of a nano-ceramic transition layer of the same material as the ceramic substrate, achieved through in-situ deposition or sintering, results in a seamless bond with the substrate surface. The interfacial bonding strength is increased by more than 50% compared to traditional structures, ensuring that the substrate remains free of delamination and peeling during long-term use, with significantly superior reliability compared to existing products. Furthermore, the gradient stress buffer composite layer can be integrally deposited and formed, which is simple to prepare, highly compatible, and does not require large-scale modification of existing DPC production lines. It is easy to achieve mass production, and the mass production cost is low and the yield is high, which has a strong advantage for industrialization and promotion.

[0054] The technical principles of the present invention have been described above with reference to specific embodiments. These descriptions are merely for explaining the principles of the invention and should not be construed as limiting the scope of protection of the invention in any way. Based on this explanation, those skilled in the art can readily conceive of other specific embodiments of the invention without inventive effort, and these embodiments will all fall within the scope of protection of the present invention.

Claims

1. A bending-resistant DPC ceramic substrate with a stress-buffered gradient structure, characterized in that: It includes a ceramic substrate, a gradient stress buffer composite layer, and a DPC precision copper circuit layer; the gradient stress buffer composite layer is integrally deposited on the surface of the ceramic substrate, and the DPC precision copper circuit layer is formed on the surface of the gradient stress buffer composite layer. The gradient stress buffer composite layer consists of a nano-ceramic transition layer, a porous flexible metal buffer layer, and a dense metal transition layer from the inside to the outside. The nano-ceramic transition layer, the porous flexible metal buffer layer, and the dense metal transition layer together constitute a stress relief structure with a gradually changing modulus.

2. The bending-resistant DPC ceramic substrate with a stress-buffered gradient structure as described in claim 1, characterized in that: The thickness of the nano-ceramic transition layer is 0.5–1 μm, and the material of the nano-ceramic transition layer is of the same origin as the ceramic matrix.

3. The bending-resistant DPC ceramic substrate with a stress-buffered gradient structure as described in claim 1 or 2, characterized in that: The nano-ceramic transition layer is made of alumina or aluminum nitride nanopowder sintered layer.

4. The bending-resistant DPC ceramic substrate with a stress-buffered gradient structure as described in claim 1, characterized in that: The thickness of the porous flexible metal buffer layer is 3 to 6 μm, and the porous flexible metal buffer layer is a nickel-copper alloy porous structure with a porosity of 15% to 25%.

5. The bending-resistant DPC ceramic substrate with a stress-buffered gradient structure as described in claim 1, characterized in that: The thickness of the dense metal transition layer is 2-4 μm, and the dense metal transition layer is a pure copper dense plating layer.

6. The bending-resistant DPC ceramic substrate with a stress-buffered gradient structure as described in claim 1, characterized in that: The thickness of the ceramic substrate is 0.2–0.8 mm, and the thickness of the DPC precision copper circuit layer is 25–120 μm.

7. The bending-resistant DPC ceramic substrate with a stress-buffered gradient structure as described in claim 1, characterized in that: The DPC precision copper circuit layer consists of a circuit body layer and a circuit transition layer, with the circuit transition layer sandwiched between the circuit body layer and the dense metal transition layer.

8. A method for preparing a bending-resistant DPC ceramic substrate with a stress-buffered gradient structure as described in any one of claims 1 to 7, characterized in that: Includes the following steps: S1. Precision pretreatment of the substrate: The ceramic substrate is subjected to double-sided grinding, polishing, and ultrasonic degreasing. Plasma is used to roughen and activate the ceramic surface to obtain a ceramic matrix and improve the interfacial bonding performance of the ceramic matrix. S2, In-situ grown nano-ceramic transition layer; S3, Electrodeposited porous flexible metal buffer layer; S4. Electroplated dense metal transition layer: A pure copper dense layer is electroplated on the surface of the porous flexible metal buffer layer to seal the surface pores and form a flat conductive substrate, thus obtaining a dense metal transition layer. S5. Photolithography-formed DPC circuit: Precision copper circuit layer of DPC is prepared by photolithography, pattern electroplating and etching processes; S6. Low-temperature stress annealing: Anneal at a low temperature of 180-200℃ for 20-40 minutes to eliminate residual stress in the multilayer structure and complete the preparation of the finished product.

9. The method for preparing a bending-resistant DPC ceramic substrate with a stress-buffered gradient structure as described in claim 8, characterized in that: In step S2, a homologous nano-ceramic coating is deposited in situ on the surface of the ceramic substrate using a sol-gel process, and a dense, seamless nano-ceramic transition layer is formed by low-temperature sintering.

10. The method for preparing a bending-resistant DPC ceramic substrate with a stress-buffered gradient structure as described in claim 8, characterized in that: In step S3, a pulse segmented electroplating process is used to control the current density and deposit a nickel-copper alloy with controllable pores on the surface of the nano-ceramic transition layer to form a porous flexible metal buffer layer.

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