Vertical balun for differential to single-ended conversion of millimeter wave signals

Abstract

A multi-layer package-level package substrate is formed with a compact vertical balun for converting between a single-ended signal and a differential signal, wherein the vertical balun includes: a first non-phase shifting conductive balun path element having one or more vertically aligned conductive structures formed in at least two package layers and connected between a first differential-ended signal balun node and a single-ended signal balun node; a second phase shifting conductive balun path element having a plurality of conductive structures formed in at least two package layers and connected between a second differential-ended signal balun node and the single-ended signal balun node; and a single-ended contact element integrally formed with the single-ended signal balun node at a package layer location where the first non-phase shifting conductive balun path element is directly electrically connected to the second phase shifting conductive balun path element.

Description

Technical Field

[0001] This disclosure generally relates to the field of integrated circuit devices. In one aspect, this disclosure relates to a packaged integrated circuit assembly having a built-in balun. Background Technology

[0002] Modern integrated circuits (ICs) are becoming increasingly complex, miniaturized, and cost-constrained as they integrate various circuit components and devices into a single package. For example, automotive radar chips now include complex RF front-end circuitry integrated with digital circuitry systems on a shared semiconductor substrate. Simultaneously, there is a need to miniaturize radar systems for autonomous driving and ADAS (Advanced Driver Assistance Systems) applications. The increasing complexity and the competing demand for miniaturization present a challenge in minimizing chip size while routing numerous signal and ground paths within the radar chip package. Low-cost, high-efficiency, and performance-driven packaging technologies can be achieved by using ball grid array (BGA) based packaging structures to connect monolithic microwave integrated circuit (MMIC) input / output (IO) signals to printed circuit boards (PCBs). Examples of these packages are embedded wafer-level ball grid arrays (eWLB), flip-chip chip-level packages (FCCSP), and flip-chip ball grid arrays (FCBGA). In such packaged component solutions, a current connection from the MMIC silicon die to the PCB is typically used, which includes two intermediate transitions. In the first die-to-package transition, the die is connected to the package substrate laminate or to a metallization layer on top of the dielectric layer of the package substrate. In the die, a differential signal implementation of the silicon circuitry is typically used to reduce the sensitivity of the active circuitry to external common-mode signals present, such as those on PCB traces or lines on the package laminate. As a result of the differential signal circuitry implementation, the first die-to-package transition will also be differential. In the second package-to-PCB interface transition, a solder ball grid array is used to connect the package to the PCB using an interface that can be differential or single-ended. In applications where the PCB uses a single-ended connection, for example, to feed a single-ended antenna, the package will include balun circuitry to convert the differential signal to a single-ended signal; however, conventional planar balun components are quite large and expensive, increasing package size and cost.

[0003] As can be seen from the foregoing, existing designs and manufacturing processes for IC packaging components have not yet provided the cost, size, and electrical performance required for cutting-edge integrated circuit component packaging. Other limitations and disadvantages of conventional processes and techniques will become apparent to those skilled in the art after reviewing the remainder of this application with reference to the accompanying drawings and detailed description. Summary of the Invention

[0004] It should be understood that a compact vertical balun formed in a multilayer panel-level package substrate for switching between single-ended and differential signals, and an associated manufacturing method, are provided. As disclosed, the compact vertical balun includes a first non-phase-shifting conductive balun path element having one or more vertically aligned conductive structures formed in at least two package layers and connecting a first differential signal balun node and a single-ended signal balun node. Additionally, the disclosed compact vertical balun includes a second phase-shifting conductive balun path element having multiple conductive structures formed in at least two package layers and connecting a second differential signal balun node and a single-ended signal balun node. The disclosed compact vertical balun also includes a single-ended contact element integrally formed with the single-ended signal balun node at a package layer location where the first non-phase-shifting conductive balun path element is directly electrically connected to the second phase-shifting conductive balun path element. In a selected embodiment, the single-ended contact element includes a third conductive structure formed as a third linear segment in the second encapsulation layer, the third linear segment extending orthogonally from a second proximal end of the second conductive structure to form the single-ended signal balun node. In a selected embodiment, the second phase-shifting conductive balun path element includes a first conductive structure formed in the first encapsulation layer as a first linear segment extending from a first proximal end to a first distal end at a first lateral distance. Additionally, the second phase-shifting conductive balun path element includes a second conductive structure formed in the second encapsulation layer as a second linear segment extending from a second proximal end to a second distal end at a second lateral distance. As disclosed, the first and second linear segments are parallel-aligned and connected together by a conductive via structure connecting the first and second distal ends of the first and second linear segments to extend perpendicularly through the multilayer encapsulation. In a selected embodiment, the sum of the first and second lateral distances is substantially equal to half the electrical wavelength of the expected operating frequency of the differential signal. In a selected embodiment, the first non-phase-shifting conductive balun path element and the second phase-shifting conductive balun path element are connected and configured to split a single-ended signal with a specified operating frequency received at a single-ended signal balun node into a first differential signal and a second differential signal with approximately equal amplitude and a 180-degree phase difference at a first differential signal balun node and a second differential signal balun node. In other selected embodiments, the first non-phase-shifting conductive balun path element and the second phase-shifting conductive balun path element are connected and configured to combine differential signals with a specified operating frequency and a 180-degree phase difference received at a first differential signal balun node and a second differential signal balun node into a single-ended signal at a single-ended signal balun node.In selected embodiments, the compact vertical balun may further include: one or more first coplanar ground metal layers that substantially surround a first conductive structure in a first package layer and are laterally separated from the first conductive structure by uniform gaps; and one or more second coplanar ground metal layers that substantially surround a second conductive structure in a second package layer and are laterally separated from the second conductive structure by uniform gaps. In selected embodiments, the compact vertical balun may be formed in a multilayer panel-level package substrate selected from the group consisting of: double-layer panel-level package (2L PLP), multilayer flip-chip chip-level package (FCCSP), fan-out wafer-level package (FOWLP), emitter-level package (LiP), or substrate-based package.

[0005] In another form, an integrated circuit package and associated manufacturing method are provided. As disclosed, the integrated circuit package includes a multilayer package (e.g., a multilayer panel-level package) having vertical baluns. During formation, the vertical balun includes one or more vertically aligned conductive structures formed in at least two layers of the multilayer package and connecting a first differential-ended signal balun node and a single-ended signal balun node in the multilayer package. Additionally, the vertical balun includes a plurality of conductive structures formed in at least two layers of the multilayer package to form a vertically stacked U-shaped path connecting a second differential-ended signal balun node and a single-ended signal balun node. In a selected embodiment, the plurality of conductive structures includes a first conductive structure formed in a first layer of the multilayer package as a first linear segment extending from a first proximal end to a first distal end at a first lateral distance. Additionally, the plurality of conductive structures includes a second conductive structure formed in a second layer of the multilayer package as a second linear segment, the second linear segment being parallel to and aligned with the first linear segment and extending from a second proximal end to a second distal end at a second lateral distance. The plurality of conductive structures further include conductive via structures formed in the multilayer package to electrically connect the first and second distal ends of the first linear segment and the second linear segment. In a selected embodiment, the sum of the first lateral distance and the second lateral distance is substantially equal to half the electrical wavelength of the expected operating frequency of the differential-ended signal provided to the first and second differential-ended signal balun nodes. The vertical balun also includes a single-ended contact electrically coupled at a single-ended signal balun node. In a selected embodiment, the integrated circuit package may further include an antenna electrically coupled to the single-ended contact, and an integrated circuit (IC) die mounted to the multilayer package and having first and second electrical ports respectively coupled to the first and second differential-ended signal balun nodes, wherein the IC die communicates with an external network via the antenna and the vertical balun. In a selected embodiment, the IC die includes a receiver circuit system, and the vertical balun is configured to split a single-ended signal received by the antenna at a specified operating frequency into a first differential signal and a second differential signal at a first electrical port and a second electrical port of the receiver circuit system, wherein the first differential signal and the second differential signal have approximately equal amplitudes and a 180-degree phase difference. In other selected embodiments, the IC die includes a transmitter circuit system, and the vertical balun is configured to combine differential signals provided by the transmitter circuit system at a specified operating frequency and having a 180-degree phase difference into a single-ended signal for transmission by the antenna. In selected embodiments, the integrated circuit package may further include one or more first coplanar ground metal layers that substantially surround one or more vertically aligned conductive structures in the multilayer package and are laterally spaced from the one or more vertically aligned conductive structures by uniform gaps.Additionally, the integrated circuit package may further include one or more second coplanar ground metal layers, which substantially surround and are laterally spaced from the plurality of conductive structures in the multilayer package with uniform gaps. In other selected embodiments, the integrated circuit package may further include a printed circuit board attached to a first surface of the multilayer package and an integrated circuit (IC) die mounted to a second surface of the multilayer package.

[0006] In another embodiment, a packaged integrated circuit assembly and an associated method of manufacturing are provided. As disclosed, the method includes providing an integrated circuit die having a first differential signal die pad and a second differential signal die pad. Additionally, the disclosed method includes forming a multilayer package on the integrated circuit die, the multilayer package having a vertical balun formed between a bottom surface and a top surface of the multilayer package to electrically connect the first differential signal die pad and the second differential signal die pad to a single-ended signal line. During formation, the vertical balun includes a first non-phase-shifted conductive balun path, the first non-phase-shifted conductive balun path including one or more vertically aligned conductive structures formed in at least two package layers and connecting the first differential signal die pad to the single-ended signal line. Additionally, the vertical balun includes a second phase-shifted conductive balun path, the second phase-shifted conductive balun path including a plurality of conductive structures formed in at least two package layers and connecting the second differential signal die pad to the single-ended signal line. The disclosed method further includes attaching a first solder ball connector, which is in direct electrical contact with the single-ended signal line, to the top surface of the multilayer package. Additionally, the disclosed method includes attaching a first solder ball connector to a circuit board. In a selected embodiment, a multilayer package is formed by forming a first rewiring stack on an integrated circuit die, and then forming a second rewiring stack on the first rewiring stack. During formation, the first rewiring stack includes a first conductive structure perpendicularly aligned to a first differential signal die pad, and a second conductive structure overlapping a second differential signal die pad and extending from a first proximal end to a first distal end over a first lateral distance. Furthermore, the second rewiring stack includes a third conductive structure perpendicularly aligned to the first differential signal die pad, and a fourth conductive structure parallelly aligned to the second conductive structure and extending from a second proximal end to a second distal end over a second lateral distance. During formation, the second conductive structure and the fourth conductive structure are connected together via a conductive via structure connecting the first distal end and the second distal end of the second conductive structure and the fourth conductive structure. Attached Figure Description

[0007] Many objectives, features, and advantages of the invention and its implementation will be understood when the following detailed description of preferred embodiments is considered in conjunction with the following figures.

[0008] Figures 1A-1B Cross-sectional and planar views of an encapsulated die attached to a PCB using a package are shown, wherein the package includes a conventional planar balun.

[0009] Figure 2 A perspective view of a vertical balun according to a selected embodiment of the present disclosure is shown.

[0010] Figure 3A , Figure 3B Cross-sectional and plan views of an encapsulated die attached to a package having a vertical balun, according to a selected embodiment of the present disclosure, are shown.

[0011] Figure 4 A cross-sectional view of a manufacturing process for forming a package with an integrated vertical balun, according to a selected embodiment of the present disclosure, is shown.

[0012] Figure 5 The simulated RF performance of a vertical balun according to a selected embodiment of this disclosure is shown. Detailed Implementation

[0013] A vertical balun device and associated manufacturing method are described in a package substrate for converting differential die signals to single-ended signals, wherein package conductor layers are sequentially formed or stacked in at least two package layers to define a compact vertical balun using a smaller area than conventional horizontal balun designs. In a selected embodiment, the vertical balun device is formed in a multilayer panel-level package (PLP) and connects first and second differential signal nodes (formed in a first layer of the multilayer package) to single-ended signal nodes (formed in a second layer of the multilayer package). As disclosed, the vertical balun device includes a first non-phase-shifting conductive balun element (connected between the first differential signal node and the single-ended signal node) and a second phase-shifting conductive balun element (connected between the second differential signal node and the single-ended signal node). Specifically, the first non-phase-shifting conductive balun element has one or more vertically stacked conductive layers extending through the multilayer package to directly electrically connect the first differential signal node and the single-ended signal node. Additionally, the second phase-shifting conductive balun element has first and second conductive elements that are parallel-aligned and extend through the multilayer package to directly electrically connect the second differential signal node and the single-ended signal node. In the first package layer, the first conductive element is spaced apart from one or more vertically stacked conductive layers and extends laterally a first distance to its distal end. In the second package layer, the second conductive element is formed aligned with the first conductive element and extends laterally a second distance from its distal end to make direct electrical contact with one or more vertically stacked conductive layers. Furthermore, the vertical balun device may include a first through-hole conductor element connecting the distal ends of the first and second conductive elements. By controlling the combined length of the first and second extension distances to be equal to half the electrical wavelength of the signal frequency of the differential die signal, the path difference of the input signal emitted across the second phase-shifting conductive balun element transforms the input differential signal into a single-ended signal at the single-ended signal node.

[0014] This disclosure describes a packaging substrate and a method of manufacturing for forming an improved vertical balun structure formed in first and second metal substrate layers having vertically oriented windings to convert differential (DE) signals from an IC die into single-ended (SE) signals for output at the packaging substrate, addressing various problems in the art, whereby the various limitations and disadvantages of conventional solutions and techniques will become apparent to those skilled in the art after reading the remainder of this application with reference to the accompanying drawings and the detailed description provided herein. Various illustrative embodiments of the invention will now be described in detail with reference to the accompanying drawings. While various details are set forth in the following description, it should be understood that the invention can be practiced without these specific details, and many implementation-specific decisions can be made regarding the invention described herein to achieve specific objectives of the device designer, such as compliance with process requirements or design-related constraints that may vary from implementation to implementation. While such research and development may be complex and time-consuming, it is merely a routine task for those skilled in the art who will benefit from this disclosure. For example, simplified cross-sectional and plan views of the reference package substrate depict selected aspects but do not include every device feature or geometry to avoid limiting or obscuring the invention. Such descriptions and representations are generally used by those skilled in the art to describe and convey the gist of their work to others skilled in the art. It should also be noted that throughout this specific embodiment, some elements are shown in the figures for simplicity and clarity and are not necessarily drawn to scale. Additionally, the dimensions of some elements in the figures may be enlarged relative to other elements to aid in understanding the embodiments of this disclosure. Furthermore, reference numerals have been repeated in the figures to indicate corresponding or similar elements. Additionally, the depicted device layers shown as being deposited and / or etched are represented by simplified line drawings; however, it should be understood that in practice, the actual profile or dimensions of the device layers will be non-linear, for example, when the described etching process is applied at different rates to different materials, or when the described deposition or growth process generates layers based on the underlying material.

[0015] To better understand selected embodiments of this disclosure, reference is now made to Figures 1A-1B , Figures 1A-1B Cross-sectional and planar views of integrated circuit package assemblies 1A and 1B are depicted. Integrated circuit package assemblies 1A and 1B include encapsulated integrated circuit (IC) dies or chips 17 encapsulated in a molded package structure 18 and mounted or attached to a package 10. Specifically, Figure 1A Depicting as from Figure 1B Perspective shown Figure 1A Cross-section of the integrated circuit packaging component Figure 1A ,and Figure 1B Depicting as from Figure 1A Perspective shown Figure 1BPlanar view of integrated circuit packaging components Figure 1B The integrated circuit package assembly 1A, implemented as a flip-chip package, includes a first-level interconnect 16 connecting a discrete IC die 17 to a package substrate 10, and a second-level interconnect 7 connecting the package substrate 10 to a printed circuit board 2 for wiring to external circuitry (not shown). As depicted, the IC die or chip 17 is positioned and attached with a downward-facing conductor to align with and connect to an embedded upward-facing conductor in the package substrate 10 via the first-level interconnect 16. For example, the first-level interconnect 16 may be implemented using an array of conductive wafer vias, pillars, or bumps that are aligned and positioned to provide a direct electrical connection between the IC chip 17 and the package substrate 10. However, it should be understood that the IC chip 17 may be positioned and arranged with any suitable configuration of downward-facing patterned conductors to align and attach to the top of the package substrate 10 via the first-level interconnect 16.

[0016] The depicted package substrate 10 has one or more substrate layers, which have an interlayer of insulating material (e.g., glass, silicon, plastic, and / or fiberglass) containing patterned conductive lines and / or via structures for routing signals and power through the package substrate structure 10 for electrical connection via second-level interconnects 7 on the PCB 2. Although not shown, it should be understood that the package substrate 10 may include a stack of redistribution (RDL) layers formed on the upper and / or bottom surfaces of the package substrate 10 to provide fine-pitch wiring layers that electrically connect the circuitry of the IC die 17 to the PCB 2 using first-level interconnects 16 and second-level interconnects 7.

[0017] As depicted, the package substrate 10 includes one or more planar baluns 13A, 13B, each planar balun 13A, 13B formed in a single metal substrate layer 13A, 13B, wherein the windings are horizontally oriented to convert differential signals from the IC die 17 into single-ended signals at extended conductive microstrip linear segments 15A, 15B. The package substrate 10 also includes DE input vias 14A, 14B for connecting the planar baluns 13A, 13B to the IC die 17 generating the DE input signal via selected first-level interconnects 16. Additionally, the package substrate 10 includes SE output vias 12A, 12B for connecting to PCB vias 5, 6 via selected second-level interconnects 7 for output on output lines 3, 4 in the printed circuit board 2.

[0018] like Figure 1BAs best seen, each balun 13A, 13B is constructed of a metal microstrip line (shown in black), the thickness of which may be less than its width, and is formed in a hairpin shape, wherein two elongated conductive microstrip linear segments are connected at one end to differential input via conductors 14A, 14B, and at the opposite end to conductive microstrip U-shaped segments. Each balun 13A, 13B is formed with elongated conductive microstrip linear segments parallel to each other separated by a first interval. Additionally, each balun 13A, 13B also includes conductive microstrip linear segments 15A, 15B extending orthogonally from one of the elongated conductive microstrip linear segments. During formation, the extended conductive microstrip linear segments 15A, 15B directly connect one of the elongated conductive microstrip linear segments to a single-ended (SE) via or pin 12A, 12B. Although not shown, it should be understood that a coplanar grounding metal layer is also formed in a single metal substrate layer of the package substrate 10 to surround (but not contact) each balun 13A, 13B and the protruding conductive microstrip linear segments 15A, 15B, so as to separate them from the balun 13A, 13B and the protruding conductive microstrip linear segments 15A, 15B by a substantially uniform gap or spacing. As depicted, the positions of the protruding conductive microstrip linear segments 15A, 15B are shown as substantially at the center of the elongated conductive microstrip linear segments, but it should be understood that the actual intersection position is determined by the wavelength of the expected target operating frequency of the signal processed by the balun. More specifically, the electrical length of the longer path from the protruding conductive microstrip linear segments 15A, 15B to the differential input via conductors 14A, 14B is half a wavelength longer than the electrical length of the shorter path from the protruding conductive microstrip linear segments 15A, 15B to the other differential input via conductors 14A, 14B.

[0019] As seen earlier, the challenges of using horizontal baluns to transform DE package input signals to SE package output signals can increase package size and thus the cost of integrated circuit package assemblies 1A and 1B. Specifically, the conventional approach of using planar baluns (grounded in the second layer) within a single package layer requires the lateral extent of the balun to allow for at least λ / 2 of the length of one of the elongated conductive microstrip linear segments of each balun 13A and 13B, where λ is the wavelength obtained by dividing the speed of light by the frequency of the differential signal (e.g., λ = 3.7 mm for an 80 GHz differential signal). The resulting planar balun is bulky and requires a large area in the package.

[0020] Now refer to Figures 2-5 Various illustrative embodiments of the present invention are described in detail below. Figures 2-5A compact packaged balun is described for implementing vertical or stacked DE-to-SE signal transformation using a two-layer package, resulting in a compact balun that uses approximately one-third the area of ​​a standard planar balun design. While specific example materials, thicknesses, and processes are described herein, those skilled in the art will recognize that other materials, thicknesses, and processes with similar properties or characteristics can be substituted without loss of functionality. It should be noted that throughout this detailed description, certain material layers will be deposited and removed to form the said integrated circuit package assembly. Unless a specific process for processing such layers or such layer thicknesses is described in detail below, conventional techniques known to those skilled in the art should be used to deposit, remove, form, or otherwise process such layers to achieve an appropriate thickness. Such details are well-known and are not to be considered necessary to teach those skilled in the art how to manufacture or use this disclosure.

[0021] To better understand selected embodiments of this disclosure, reference is now made to Figure 2 , Figure 2 A perspective view of a vertical balun 2 used to convert differential terminal die signals into single-ended signals is depicted. Generally, the vertical balun includes a first non-phase-shifting conductive balun element 27B / 23B / 24B and a second phase-shifting conductive balun element 27A / 23A, 24A, 25 connected as shown between differential terminal signal nodes 20, 21 and single-ended signal node 26.

[0022] As depicted, the vertical balun 2 is connected to die copper pads 22A, 22B to receive individual components of the differential signal arriving at the first conductive trace or microstrip 20 and the second conductive trace or microstrip 21 from the IC die. In a selected embodiment, the first conductive trace 20 transmits a negative DE signal input, and the second conductive trace 21 transmits a positive DE signal input. Although not shown, the IC die may include a communication circuitry that generates differential signals at first and second ports that together form differential ports for transmitting differential signals. The communication circuitry may represent any suitable receiver circuitry for receiving differential RF signals or any suitable transmitter circuitry for providing differential RF signals for transmission. In an alternative embodiment, the communication circuitry may be configured as a transceiver circuitry having a receiver mode for receiving signals and a transmitter mode for transmitting signals. It should be understood that the individual components of the differential signal arriving at the conductive microstrips 20, 21 have approximately equal amplitudes and a 180-degree phase difference, regardless of whether the signal is input to or output from the balun 2. In the selected embodiment, the target operating frequency of the differential signal is within a target bandwidth of 76-81 GHz, and more specifically approximately 78 GHz.

[0023] Additionally, the vertical balun 2 includes a first conductive via 27A and a second conductive via 27B connected to the die copper pads 22A and 22B, respectively. In a selected embodiment, the first conductive via, pillar, or bump 27A and the second conductive via, pillar, or bump 27B can be formed as conductive via structures in patterned openings in the top dielectric layer on the IC die, for direct electrical contact with the die copper pads 22A and 22B. Alternatively, the first conductive via 27A and the second conductive via 27B can be formed as conductive via, pillar, or bump structures in patterned openings in the dielectric layer of the package substrate, for direct electrical contact with the die copper pads 22A and 22B.

[0024] Additionally, the vertical balun 2 includes a first patterned conductive layer 23A and a second patterned conductive layer 23B formed in a first encapsulation layer and respectively connected to a first conductive wafer via, pillar, or bump 27A and a second conductive wafer via, pillar, or bump 27B. In a selected embodiment, the first patterned conductive layer 23A may be formed as a first patterned length extension (L1 extension) metal layer within a first RDL layer of the encapsulation substrate to directly contact the first conductive wafer via, pillar, or bump 27A. Additionally, the second patterned conductive layer 23B may be formed as a patterned metal layer within the first encapsulation layer to directly contact the second patterned conductive layer 23B. In the first encapsulation layer, the first patterned conductive layer 23A has a proximal end spaced from the second patterned conductive layer 23B by a minimum specified separation distance, and the first patterned conductive layer 23A extends laterally in a first horizontal direction by a first lateral extension distance L1 to a distal end. As depicted, the patterned conductive microstrip forming the second patterned conductive layer 23B may be circular, but any suitable shape may be used. Additionally, the patterned conductive microstrip forming the first patterned conductive layer 23A can be a linear segment extending laterally a first extension distance L1 to its distal end. In a selected embodiment, both the first patterned conductive layer 23A and the second patterned conductive layer 23B are formed with patterned conductive microstrip lines having a thickness (e.g., 20 μm) smaller than their width, and these patterned conductive microstrip lines are formed in the first RDL layer of the package substrate. It should be understood that a patterned coplanar ground metal layer (not shown) can be formed in the first package layer on opposite sides of the first patterned conductive layer 23A and the second patterned conductive layer 23B. Furthermore, an additional ground metal layer (not shown) can be located below (or above) the first patterned conductive layer 23A and the second patterned conductive layer 23B to extend to and beyond the entire length and width of the balun 2. Typically, ground current flows in either or both ground metal layers, thus electromagnetic signals can propagate in microstrip transmission mode, coplanar transmission line mode, or a combination of both. It should be noted that either of the ground metal layers can be omitted in different configurations.

[0025] Additionally, the vertical balun 2 includes a first panel via 24A and a second panel via 24B respectively connected to the distal ends of the first patterned conductive layer 23A and the second patterned conductive layer 23B. In a selected embodiment, the first panel via 24A and the second panel via 24B may be formed as conductive via structures in patterned openings of a second encapsulation layer, such as a dielectric layer having a predetermined thickness (e.g., 25 μm) in an encapsulation substrate.

[0026] Additionally, the vertical balun 2 includes a third patterned conductive layer 25 formed in the second encapsulation layer and connected to the first panel via 24A and the second panel via 24B. In a selected embodiment, the third patterned conductive layer 25 may be formed as a second patterned length extension (L2 extension) metal layer within the second RDL layer of the encapsulation substrate to provide direct electrical contact between the first panel via 24A and the second panel via 24B. In the second encapsulation layer, the second patterned conductive layer 25 has a distal end extending below the first panel via 24A to provide direct electrical contact with the first panel via 24A. Furthermore, the second patterned conductive layer 23B extends laterally from the distal end in the opposite horizontal direction and extends through a second lateral extension distance L2 to a proximal end, which extends below the second panel via 24B to provide direct electrical contact with the second panel via 24B. Similarly, the shape of the patterned conductive microstrip forming the third patterned conductive layer 25 may be a linear segment extending laterally through a second extension distance L2 > L1. In a selected embodiment, the third patterned conductive layer 25 is formed with patterned conductive microstrip lines having a thickness (e.g., 20 μm) smaller than its width and is formed in the second RDL layer of the package substrate. It should be understood that a patterned coplanar ground metal layer (not shown) may be formed in the second package layer on the opposite side of the third patterned conductive layer 25. Additionally, an additional ground metal layer (not shown) may be located below (or above) the third patterned conductive layer 25 to extend to and beyond the entire length and width of the balun 2. Typically, ground current flows in either or both ground metal layers, thus electromagnetic signals can propagate in microstrip transmission mode, coplanar transmission line mode, or a combination of both. It should be noted that either of the ground metal layers may be omitted in different configurations.

[0027] Additionally, the vertical balun 2 includes a patterned single-ended signal node layer 26 formed in the second encapsulation layer to extend orthogonally from the proximal end of the third patterned conductive layer 25. In a selected embodiment, the patterned single-ended signal node layer 26 may be integrally formed with the proximal end of the third patterned conductive layer 25 as a patterned metal layer within the second RDL layer of the encapsulation substrate for direct electrical contact with the third patterned conductive layer 25. It should be understood that any single-ended signal generated at the patterned single-ended signal node layer 26 can be routed or transmitted via the encapsulation substrate to or from an external circuit system using a printed circuit board (not shown).

[0028] As disclosed herein, the vertical balun 2 can be configured to utilize any suitable multilayer packaging technology (e.g., a two-layer panel-level package (2L PLP) device) for vertical conversion to provide a compact stacked design for converting differential-ended signals to single-ended signals. When configured, the longer balun path distance (e.g., L indicated by the dashed line) will result in a more compact stacked design for converting differential-ended signals to single-ended signals. NEG The collective geometry of the conductive microstrip linear segments 23A, 24A, and 25 on the substrate provides stacked U-shaped segments with combined horizontal lengths (e.g., L1 + L2) across multiple stacked substrate layers. These combined horizontal lengths are controlled to maintain a relatively long balun path distance L. NEG Compared to shorter Baron path distances (e.g., L indicated by the dashed line) POS The distance between L and L is a half-wavelength interval to be used for receiving differential signals at the target operating frequency. In the equation, L NEG = L POS + L1 + L2 = L POS + λ / 2, where wavelength λ is the effective wavelength, which refers to the wavelength of the frequency within the substrate material.

[0029] In operation, a single-ended signal with a specified operating frequency received at SE signal node 26 is split by balun 2 into a differential signal between a first die copper pad 22A and a second die copper pad 22B. This differential signal is then transmitted to a first conductive trace or microstrip 20 and a second conductive trace or microstrip 21 of the millimeter-wave circuit system. The individual components of the differential signal arriving at the millimeter-wave circuit system via shorter and longer balun paths have approximately equal amplitudes and a 180-degree phase difference. Conversely, the differential signals output by the communication circuit system at the first die copper pad 22A and the second die copper pad 22B, both at the specified operating frequency and with a 180-degree phase difference, are combined by balun 2 into a single-ended signal provided to SE signal node 26.

[0030] To better understand selected embodiments of this disclosure, reference is now made to Figures 3A-3B , Figures 3A-3BCross-sectional and planar views of integrated circuit package components 3A and 3B are depicted. These components have encapsulated IC dies or chips 52 encapsulated within a molded package structure 53 and mounted or attached to a package 40. Specifically, Figure 3A Depicting as from Figure 3B Perspective shown Figure 3A Cross-section of the integrated circuit packaging component Figure 3A ,and Figure 3B Depicting as from Figure 3A Perspective shown Figure 3B Planar view of integrated circuit packaging components Figure 3B As can be seen, integrated circuit packaging components 3A and 3B are similar to those in the previous reference. Figure 1A and Figure 1B The baluns 1A and 1B of the integrated circuit package components described differ in that vertically or stacked baluns 41-47 are formed in the package substrate 40, as described more fully below.

[0031] When implemented as a flip-chip package, the integrated circuit package assembly 3A includes a first-level interconnect 51 connecting discrete IC dies 52 to a package substrate 40, and a second-level interconnect 35 connecting the package substrate 40 to a printed circuit board 30 for wiring to external circuitry (not shown). The IC dies or chips 52, positioned and attached via downward-facing conductors, are aligned for connection via the first-level interconnect 51 to embedded upward-facing conductors in the package substrate 40. Furthermore, the package substrate 40 has one or more interlayer dielectric layers and patterned conductive lines and / or via structures for routing signals and power through the package substrate structure 40 to electrically connect to the PCB 30 via the second-level interconnect 35. In selected embodiments, the package substrate 40 may include a stack of redistribution (RDL) layers formed on the upper and / or bottom surfaces of the package substrate 40 to provide fine-pitch wiring layers that electrically connect the circuitry of the IC die 52 to the PCB 30 using the first-level interconnect 51 and the second-level interconnect 35.

[0032] In the disclosed package substrate 40, one or more vertical baluns 41A-47A, 41B-47B are formed in multiple stacked metal substrate layers, wherein each vertical balun includes a shorter balun path (e.g., 42A) and a longer balun path (e.g., 41A, 43A-45A), wherein the windings are vertically oriented to convert differential signals from IC die 52 to single-ended signal nodes at extended conductive microstrip linear segments 46A, 46B. As depicted, package substrate 40 includes DE input vias 41A / B, 42A / B for connecting vertical balun segments 43A / B-46A / B to the IC die 52 generating the DE input signal via selected first-level interconnects 51. Additionally, package substrate 40 includes SE output vias 47A, 47B for connecting to PCB vias 33, 34 via selected second-level interconnects 35 for output on output lines 31, 32 in the printed circuit board 30.

[0033] As best in Figure 3AAs seen, each vertical balun (e.g., 41A-47A) includes a first non-phase-shifting conductive balun path element (connecting the first differential signal node and the single-ended signal node) and a second phase-shifting conductive balun path element (connecting the second differential signal node and the single-ended signal node). In a selected embodiment, the first non-phase-shifting conductive balun path element has one or more vertically stacked conductive layers 42A extending through the multilayer package 40 to directly electrically connect the first differential signal node and the single-ended signal node segment 46A from the IC die 52. Additionally, the second phase-shifting conductive balun path element has a first conductive element 43 and a second conductive element 45, which are parallelly aligned and extend through the multilayer package 40 to directly electrically connect the second differential signal node and the single-ended signal node segment 46A from the IC die 52. In the first RDL package layer, the first conductive elements 43A and 43B may be constructed from first elongated microstrip lines (shown in black) having a uniform width and thickness, spaced apart from the vertically stacked conductive layer 42A, and extending laterally a first extension distance L1 to the distal end in a first direction. In the second RDL package layer, the second conductive elements 45A and 45B may be constructed from second elongated microstrip lines (shown in gray) having a uniform width and thickness, the second elongated microstrip lines being aligned with the first conductive elements 43A and 43B and extending laterally a second extension distance L2 from the distal end in a second opposite direction to directly contact the vertically stacked conductive layer 42A. The first conductive elements 43 and 45, formed parallel to each other in different package layers, are vertically separated by a first spacing distance. A first conductive element 43 and a second conductive element 45, connected at the distal end via panel via structures 44A and 44B, form a U-shaped longer balun path. This balun path connects at one end to differential input via conductors 41A and 41B and at the opposite end to a shorter balun path formed by vertically stacked conductive layers 42A and 42B. A single-ended signal node segment 46A, integrally formed at the connection point between the longer and shorter balun paths, extends orthogonally from one of the second conductive elements 45A and 45B and can be routed via SE output vias 47A and 47B to connect to vias 33 and 34 of the PCB 30 via selected second-level interconnects 35. It should be understood that a coplanar ground metal layer may also be formed in the multilayer package 40 to surround (but not contact) each conductive element in the vertical balun.

[0034] In operation, the vertical balun disclosed herein is configured to convert a balanced differential signal into an unbalanced single-ended signal and transform the differential signal Z. DE (From the die) and single-ended signal Z SE The impedance between them is used for maximum power delivery. For this purpose, the vertical balun branches the differential signal from the IC die to a longer balun path (e.g., ...). Figure 2 The L shown NEG and shorter Baron paths (e.g., L) POS In the given information, the length L of the longer Baron path is... NEG An additional electrical wavelength length λ / 2 = L1 + L2 is added to compensate for the 180° phase difference in the differential signals. By extending the electrical wavelength λ / 2 with the longer balun path length, the two balanced signals are added in phase. Therefore, the shorter balun path L... POS and longer Baron path L NEG Differential signal impedance Z DE ( Then according to the equation Transformed into single-ended signal impedance ( To evaluate impedance transformation, the insertion loss from the DE signal input to the SE signal output is used to assess the impedance matching of the vertical balun at the signal input and output. Additionally, the common-mode rejection ratio (CMR) is used to evaluate the transformation from the DE signal input to the SE signal output.

[0035] To better understand selected embodiments of this disclosure, reference is now made to Figure 4 , Figure 4 A cross-section of the manufacturing process used to form a packaged integrated circuit assembly is shown. Figure 4 The packaged integrated circuit assembly has integrated vertical baluns formed in multiple layers of the package substrate. In the subsequent description of the manufacturing stages, newly added features at each stage are identified with cross-shading and additional reference numerals, without retaining the previously listed reference numerals. Although the manufacturing stages of the packaged integrated circuit assembly in the disclosed sequence are shown as forming a 2L PLP package with a two-layer redistribution (RDL) connecting the die pads to the external conductors of the solder balls, it should be understood that additional or fewer RDL layers may be formed, and / or other external conductors, such as copper pillars or bumps, may be used.

[0036] In the first stage (A) of the disclosed embodiment, the integrated circuit substrate 60 is provided with one or more die pads 61A, 61B formed on any side of the IC substrate 60. This side may be a silicon substrate layer on the back or front side of the IC die, or it may be a passivation layer or interconnect layer formed on the back or front side of the IC die. Before or after forming the die pads 61A / B, a passivation layer 62 is formed on the IC substrate 60, for example by depositing and polishing one or more suitable dielectric layers to leave one or more exposed contact areas of the die pads 61A / B. Subsequently, a molded package structure 63 is formed to encapsulate the back side of the IC substrate 60.

[0037] In the second stage (B), a first patterned dielectric layer 64 is formed on the IC substrate, for example by spin coating or depositing one or more dielectric material layers to a predetermined thickness or height (e.g., 25 μm), and then any suitable selective etching process is used to sequentially pattern, etch and / or develop the dielectric material layers to define wafer via openings 65 that expose the underlying die pads 61A / B.

[0038] In the third stage (C), conductive via structures 66 and 67 are formed in the via opening 65 of the first patterned dielectric layer 64 to contact the underlying die pads 61A / B. For example, the conductive via structures 66 and 67 can be formed by depositing one or more conductive layers on the IC substrate to fill the via opening 65, and then polishing, etching, or otherwise planarizing the conductive layers to form the first conductive via structure 66 and the second conductive via structure 67. During formation, the first conductive via structure 66 is electrically connected to a first differential signal provided by the die pad 61A, and the second conductive via structure 67 is electrically connected to a second differential signal provided by the die pad 61B.

[0039] In the fourth stage (D), the first set of conductive balun path elements 69 is formed as a patterned first redistribution layer (RDL) in the second patterned dielectric layer 68 to at least contact the underlying conductive wafer via structures 66, 67. For example, the second patterned dielectric layer 68 can be formed by spin-coating or depositing one or more dielectric material layers to a predetermined thickness or height (e.g., 20 μm), followed by sequentially patterning, etching, and / or developing the dielectric material layers using any suitable selective etching process to define via openings that expose the underlying conductive wafer via structures 66, 67. Subsequently, one or more conductive layers can be deposited on the IC substrate to fill the via openings in the second patterned dielectric layer 68, followed by polishing, etching, or other planarization (e.g., chemical mechanical polishing) to form the first set of conductive balun path elements 69. Alternatively, the first set of conductive balun path elements 69 can be formed as a patterned first RDL by sputtering a seed layer over a second patterned dielectric layer 68; forming a patterned photoresist mask having mask openings overlapping the conductive wafer via structures 66, 67; electroplating one or more conformal conductive layers to fill the mask openings; stripping the patterned photoresist mask; and then etching the exposed seed layer from the surface of the second patterned dielectric layer 68 to define the first set of conductive balun path elements 69. During formation, the first set of conductive balun path elements 69 includes a first conductive layer 69A electrically connected through the conductive wafer via structure 66 to a first differential terminal signal provided by a die pad 61A. Additionally, the first set of conductive balun path elements 69 includes a second conductive layer 69B electrically connected through the second conductive wafer via structure 67 to a second differential terminal signal provided by a die pad 61B.

[0040] In the fifth stage (E), an additional patterned dielectric layer 70 is formed on the IC substrate to define a panel via opening 71, which exposes the underlying first set of conductive balun path elements 69. For example, the additional patterned dielectric layer 70 can be formed by spin-coating or depositing one or more dielectric material layers to a predetermined thickness or height (e.g., 35 μm), followed by sequentially patterning, etching, and / or developing the dielectric material layers to define the panel via opening 71 using any suitable selective etching process.

[0041] In the sixth stage (F), a conductive panel via structure 72 is formed in the panel via opening 71 of an additional patterned dielectric layer 70 to contact the underlying conductive balun path element 69. For example, the conductive panel via structure 72 can be formed by depositing one or more conductive layers on the IC substrate to fill the panel via opening 71, and then polishing, etching, or otherwise planarizing the conductive layers to simultaneously form a first conductive panel via structure 72A and a second conductive panel via structure 72B. During formation, the first conductive panel via structure 72A is electrically connected to a first differential terminal signal provided by the die pad 61A via a first conductive layer 69A and a first conductive die via structure 66. Additionally, the second conductive panel via structure 72B is electrically connected to a second differential terminal signal provided by the die pad 61B via a second conductive layer 69B and a second conductive die via structure 67.

[0042] In stage seven (G), the second set of conductive balun path elements 73 is formed as a patterned second RDL to at least contact the underlying first conductive panel via structure 72A and the second conductive panel via structure 72B. For example, the second set of conductive balun path elements 73 can be formed by depositing one or more conductive layers on the IC substrate to a predetermined thickness or height (e.g., 20 μm), and then applying a suitable selective etching process to sequentially pattern and etch the conductive layers to define the second set of conductive balun path elements 73A-C. Alternatively, the second set of conductive balun path elements 73 can be formed as a patterned second RDL by: sputtering a seed layer on the IC substrate; forming a patterned photoresist mask having mask openings overlapping the intended locations of the second set of conductive balun path elements 73; electroplating one or more conformal conductive layers to fill the mask openings; stripping the patterned photoresist mask; and then etching the exposed seed layer to define the second set of conductive balun path elements 73. During formation, the second set of conductive balun path elements 73 includes a third conductive layer 73B electrically connecting the conductive panel via structures 72A, 72B, thereby coupling the first and second differential terminal signals provided by the die pads 61A, 61B to a shared node around the ring formed by the vertical stack segments 61A / 66 / 69A / 72A and the U-shaped segments 61B / 67 / 69B / 72B / 73B. Although in Figure 4 The cross-sectional view is not shown, but the second set of conductive balun path elements 73 formed in the patterned second RDL also includes a single-ended signal node layer that extends orthogonally to the longitudinal direction of the third conductive layer 73B and is vertically aligned with the first conductive wafer via structure 66.

[0043] As disclosed herein, manufacturing stages (A)-(G) may be repeated one or more additional times as necessary to form additional balun path elements in other package layers. As disclosed herein, vertical baluns can be designed as part of a 2L-PLP package in the first and second RDLs; however, vertical baluns can be designed in any other suitable package stack. For example, in a four-layer FCCSP package stack, vertical baluns can be designed in the second and third metal layers (M2 and M3) of the package, and the top metal layer (M4) and bottom metal layer (M1) can be used to form ground plane layers for the balun signal lines in M2 and M3. Such vertical shielding will allow for a better return path for differential signals and thus result in better common-mode rejection, a fundamental quality factor characterizing the balun. Additionally, the increased height between layers M2 and M3 can also be used to better optimize RF performance. Therefore, vertical baluns can be designed using different stacking rules, such as staggered vias, microvia pad sizes, and different layer heights, to achieve optimal RF performance, especially for common-mode rejection ratio. In addition, vertical baluns can be designed to have multiple layers, allowing for the use of stacked vertical heights, and vertical baluns can be further miniaturized, resulting in smaller packages and lower costs.

[0044] At a certain point, an external conductor can be formed that makes electrical contact with the balun path elements. For example, in stage eight (H), a molding layer 75 is applied or formed to completely cover the second set of conductive balun path elements 73, thereby forming an encapsulation or molding compound body 75 for encapsulating the package substrate. For example, the molding material can be any suitable encapsulation having properties suitable for providing mechanical support and structural integrity to maintain the physical arrangement of the package substrate and the IC substrate. For example, the molding 75 can use silica-filled epoxy molding compounds, plastic encapsulation resins, and other polymeric materials such as silicone resins, polyimides, phenolic plastics, and polyurethanes. The molding 75 can be applied using various standard processing techniques used in encapsulation, including, for example, printing, pressure molding, injection molding, film-assisted molding, and spin coating. Once the molding material is applied, the panel can be cured by exposing the material to a certain temperature for a period of time, or by applying a curing agent, or both. Additionally, grinding or etching processes can be applied to planarize the molding layer 75 to achieve the desired panel thickness.

[0045] In the ninth stage (i), a bump under-metallization (UBM) structure 76 is formed in the molding layer 75 to contact at least the third conductive layer 73B. For example, controlled laser etching can be applied to form a UBM opening in the molding layer 75, which exposes the underlying third conductive layer 73. The UBM structure 76 in the UBM opening can be formed by: sputtering a seed layer onto the molding layer 75; forming a patterned photoresist mask with mask openings overlapping the UBM opening; electroplating one or more conformal conductive layers in the UBM opening; stripping the patterned photoresist mask; and then etching the exposed seed layer from the surface of the molding layer 75 to define the UBM structure 76.

[0046] In stage 10 (J), the solder ball connectors 77-79 are formed using any suitable bump flow. For example, the solder ball connectors 77-79 can be formed by: forming a patterned photoresist mask with contact openings exposing the underlying UBM structure 76; electroplating a solder layer in the contact openings; stripping the patterned photoresist mask; and then reflowing the solder layer to define the solder ball connectors 77-79. It should be understood that alternatives exist for forming the solder ball connectors 77-79, such as forming copper pillar structures on the UBM structure 76.

[0047] As described above, the first sequence of manufacturing steps is used to form a multilayer package with a vertical balun and a surrounding ground plane. This begins with the fabrication of a first die pad 61A and a second die pad 61B on the IC substrate (stage 4(A)), where differential signals are generated from the power amplifier output of the transmitter or provided to the low-noise amplifier input of the receiver. Next, the multilayer packaging process uses vias 66 and 67, as well as patterned conductive ground layers 69 and balun layers 69A and 69B, to connect the differential signals from the die pads 61A and 61B to a first package layer (e.g., RDL1) (stages 4(B)-(D)). Following this, the multilayer packaging process uses panel vias 72A and 72B, as well as patterned conductive ground layers 73A and 73B and balun layer 73B, to connect the differential signals from patterned conductive balun layers 69A and 69B to a second package layer (e.g., RDL2) (stages 4(E)-(G)). During formation, the first differential signal (e.g., DE+) travels directly through the vertical balun along a shorter linear balun path between RDL1 and RDL2 using panel via 72A. However, the second differential signal (e.g., DE-) travels through the vertical balun along a longer U-shaped balun path between RDL1 and RDL2 using patterned conductive balun layer 69B, panel via 72B, and patterned conductive balun layer 73B. Specifically, the second differential signal moves a certain length (approximately λ / 4) in the lateral direction along patterned conductive balun layer 69B in the first encapsulation layer RDL1, migrates between the first and second encapsulation layers (RDL1 to RDL2) using panel via 72B, and then returns a certain length (approximately λ / 4) in the opposite lateral direction along patterned conductive balun layer 73B in the second encapsulation layer RDL2 until it reaches the first differential signal line. At the junction between the first and second differential signals, a single-ended signal is drawn from a patterned single-ended signal node layer formed in the second encapsulation layer RDL2, extending orthogonally from the patterned conductive balun layer 73B, as the SE output of the balun. If the electrical length of the second differential signal from RDL1 to RDL2 is equal to λ / 2, the first and second differential signals will be added in phase, and the differential signal will be converted into a single-ended signal. As shown, the patterned conductive ground layers 69, 73A, 73C and the connecting panel via 72 are located on opposite sides of the vertical balun element. Additionally, conductive ground layers are formed on each lateral side of the patterned conductive balun layer 69B and the patterned conductive layer 73B extending in the same lateral direction to form a coplanar waveguide (CPW) transmission line. For microstrip modes traversing the transmission line, the patterned conductive ground layer should be as close as possible to the balun signal line.

[0048] Additionally, the second sequence of manufacturing processes routes single-ended signals to / from the vertical balun to a second-level interconnect for connection to printed circuit board conductors via multilayer packaging. Initially, a package molding 75 (Stage 4(H)) is formed or applied to cover the multilayer package. Next, the multilayer packaging process forms a UBM structure 76 (Stage 4(I)) within the package molding, positioned for direct electrical connection to the vertical balun and the conductive ground layer. Subsequently, the multilayer packaging process forms solder ball connectors 77-79 positioned for direct electrical connection to the UBM structure 76. Specifically, ground solder ball connectors 77 and 79 are connected to the ground layer, and the SE signal solder ball 78 is connected to a patterned single-ended signal node layer formed in the second package layer RDL2.

[0049] Now for reference Figure 5 The diagram depicts simulated waveforms 5 illustrating selected RF performance parameters of a vertical balun in a 2L-PLP package according to a selected embodiment of the present disclosure. In the simulation, the die-side input impedance is assumed to be 40 Ω, and the output impedance presented by the vertical balun on the package side is set to 100 Ω. The transition from the SE output of the vertical balun to the first metal layer of the PCB can then be designed to be converted to 50 Ω on the PCB side for customer antenna applications.

[0050] The first analog RF performance parameter is the insertion loss waveform 81, which characterizes the insertion loss of the signal as it is converted from DE to SE by the vertical balun. As depicted, an acceptable insertion loss of approximately 1 dB can be achieved in the 76-81 GHz band using the VB in a 2L PLP package.

[0051] The simulated RF performance parameters also include package-side impedance matching waveform 82 and die-side impedance matching waveform 83, characterizing the impedance matching performance of the vertical balun. As depicted, the vertical balun has a wide bandwidth and very good impedance matching (e.g., greater than -15 dB matching) in the band of interest (i.e., 76-81 GHz).

[0052] Additionally, waveform 84 shows that a CMRR value below -15 dB can be achieved using a vertical balun. It should be understood that the CMRR performance parameter can be further improved by modifying the length matching of the SE arm of the vertical balun.

[0053] While the exemplary embodiments described herein relate to various IC package component structures and methods of manufacturing thereof, the invention is not necessarily limited to the example embodiments shown that are applicable to a wide variety of processes and / or devices. Therefore, the specific embodiments disclosed above are illustrative only and should not be considered as limiting the invention, as the invention can be modified and implemented in different but equivalent ways, which will be apparent to those skilled in the art who benefit from the teachings herein. Accordingly, the foregoing description is not intended to limit the invention to the specific forms set forth, but rather is intended to cover such alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims, so that those skilled in the art will understand that they can make various changes, substitutions, and alterations without departing from the spirit and scope of the invention as presented in its broadest form.

[0054] The benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, these benefits, advantages, solutions to problems, and any elements that may make any benefit, advantage, or solution occur or become more significant should not be construed as essential, necessary, or fundamental features or elements of any or all claims. As used herein, the terms “comprises,” “comprising,” or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not simply include those elements, but may include other elements not expressly listed or not inherent to such process, method, article, or apparatus.

Claims

1. A compact vertical balun formed in a multilayer panel-level packaging substrate for converting between single-ended and differential signals, characterized in that, include: A first non-phase-shifting conductive balun path element includes one or more vertically aligned conductive structures formed in at least two encapsulation layers and connected between a first differential signal balun node and a single-ended signal balun node. The second phase-shifting conductive balun path element includes a plurality of conductive structures formed in at least two encapsulation layers and connected between the second differential signal balun node and the single-ended signal balun node, and A single-ended contact element is integrally formed with the single-ended signal balun node at the location where the first non-phase-shifting conductive balun path element is directly electrically connected to the encapsulation layer of the second phase-shifting conductive balun path element.

2. The compact vertical balun according to claim 1, characterized in that, The second phase-shifting conductive balun path element includes: A first conductive structure, which is formed in a first encapsulation layer as a first linear segment extending from a first proximal end to a first distal end over a first lateral distance, and The second conductive structure is formed in the second encapsulation layer as a second linear segment extending from the second proximal end to the second distal end over a second lateral distance. The first linear segment and the second linear segment are aligned in parallel and connected together by a conductive via structure, wherein the conductive via structure connects the first distal end and the second distal end of the first linear segment and the second linear segment to extend vertically through the multilayer package.

3. The compact vertical balun according to claim 2, characterized in that, The first non-phase-shifted conductive balun path element and the second phase-shifted conductive balun path element are connected and configured to split a single-ended signal with a specified operating frequency received at the single-ended signal balun node into a first differential signal and a second differential signal with approximately equal amplitude and a 180-degree phase difference at the first differential signal balun node and the second differential signal balun node.

4. The compact vertical balun according to claim 2, characterized in that, Additionally, a third conductive structure is included, which is formed as a third linear segment in the second encapsulation layer. The third linear segment extends orthogonally from the second proximal end of the second conductive structure to form the single-ended signal balun node.

5. The compact vertical balun according to claim 1, characterized in that, In addition, including: One or more first coplanar grounded metal layers, which substantially surround the first conductive structure in the first encapsulation layer and are laterally separated from the first conductive structure by uniform gaps, and One or more second coplanar grounded metal layers substantially surround the second conductive structure in the second encapsulation layer and are laterally separated from the second conductive structure by uniform gaps.

6. An integrated circuit package, characterized in that, include: Multi-layer packaging; as well as A vertical balun, formed within the multilayer package, wherein the vertical balun comprises: One or more vertically aligned conductive structures are formed in at least two layers of the multilayer package and connected between the first differential signal balun node and the single-ended signal balun node; Multiple conductive structures formed in at least two layers of the multilayer package to form a vertically stacked U-shaped path connecting the second differential signal balun node and the single-ended signal balun node; and A single-ended contact, whose conductive coupling is at the single-ended signal balun node.

7. The integrated circuit package according to claim 6, characterized in that, The plurality of conductive structures include: A first conductive structure is formed in the first layer of the multilayer package as a first linear segment extending from a first proximal end to a first distal end over a first lateral distance; A second conductive structure is formed as a second linear segment in the second layer of the multilayer package, the second linear segment being parallel and aligned with the first linear segment and extending from a second proximal end to a second distal end at a second lateral distance; and A conductive via structure is formed in the multilayer package to electrically connect the first distal end and the second distal end of the first linear segment and the second linear segment.

8. The integrated circuit package according to claim 6, characterized in that, In addition, including: One or more first coplanar ground metal layers substantially surround the one or more vertically aligned conductive structures in the multilayer package and are laterally separated from the one or more vertically aligned conductive structures by uniform gaps. One or more second coplanar ground metal layers substantially surround the plurality of conductive structures in the multilayer package and are laterally separated from the plurality of conductive structures by uniform gaps.

9. A method for manufacturing packaged integrated circuit components, characterized in that, include: Provides an integrated circuit die having a first differential signal die pad and a second differential signal die pad; A multilayer package is formed on the integrated circuit die, the multilayer package having a vertical balun formed between the bottom and top surfaces of the multilayer package to electrically connect the first differential signal die pad and the second differential signal die pad to a single-ended signal line, wherein the vertical balun includes: A first non-phase-shifting conductive balun path includes one or more vertically aligned conductive structures formed in at least two package layers and connected between the first differential signal die pad and the single-ended signal line. The second phase-shifting conductive balun path includes a plurality of conductive structures formed in at least two encapsulation layers and connected between the second differential signal die pad and the single-ended signal line; The first solder ball connector, which is in direct electrical contact with the single-ended signal line, is attached to the top surface of the multilayer package; and Attach the first solder ball connector to the circuit board.

10. The method according to claim 9, characterized in that, Forming the multilayer package includes: A first wiring stack is formed on the integrated circuit die, the first wiring stack comprising: The first conductive structure is perpendicularly aligned with the pad of the first differential terminal signal die, and A second conductive structure, which overlaps with the second differential terminal signal die pad and extends from a first proximal end to a first distal end over a first lateral distance; and A second wiring stack is formed on the first wiring stack, the second wiring stack comprising: The third conductive structure is perpendicularly aligned with the pad of the first differential terminal signal die, and A fourth conductive structure is aligned parallel to the second conductive structure and extends from the second proximal end to the second distal end over a second lateral distance; The second conductive structure and the fourth conductive structure are connected together by a conductive via structure, which connects the first distal end and the second distal end of the second conductive structure and the fourth conductive structure.

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