Integrated circuit device and method of manufacturing the same

Abstract

Embodiments of the present application disclose an integrated circuit device and a method of manufacturing the same. The integrated circuit device includes a die, an interconnect at least partially overlapping the die, and a plurality of bumps in an area where the interconnect overlaps the die. The interconnect includes at least a first conductive layer and a second conductive layer, and the plurality of bumps includes first and second bumps spaced apart along a first direction. Each of the first and second conductive layers includes a plurality of signal conductors between the first and second bumps and a plurality of ground conductors between the first and second bumps. All of the signal conductors in each of the first and second conductive layers between the first and second bumps are between respective pairs of ground conductors in the respective conductive layer, and the pairs of ground conductors are continuously coupled from a first side of the plurality of signal conductors to a second side of the plurality of signal conductors within the first and second conductive layers.

Description

Technical Field

[0001] Embodiments of this application relate to integrated circuit devices and methods for manufacturing the same. Background Technology

[0002] As technology advances, integrated circuit devices are becoming increasingly complex. While device designs that perform various different functions on a single die may be advantageous, yield challenges can offset these advantages as dies become larger and more complex. Furthermore, advancements in process nodes make it advantageous to partition functions among two or more dies manufactured differently, each optimized for its own process node. Therefore, some integrated circuit devices comprise two or more dies coupled together in the same package. Summary of the Invention

[0003] According to one aspect of the present application, an integrated circuit device is provided, comprising: a die; an interconnect that at least partially overlaps with the die; and a plurality of bumps located in the region where the interconnect overlaps with the die, wherein: the interconnect includes at least a first conductive layer and a second conductive layer, the plurality of bumps includes first bumps and second bumps spaced apart along a first direction, each of the first conductive layer and the second conductive layer includes a plurality of signal conductors located between the first bumps and the second bumps and a plurality of ground conductors located between the first bumps and the second bumps, and all signal conductors in each of the first conductive layer and the second conductive layer between the first bumps and the second bumps are located between corresponding pairs of ground conductors in the corresponding conductive layer, and the pairs of ground conductors are continuously coupled from a first side of the plurality of signal conductors to a second side of the plurality of signal conductors within the first conductive layer and the second conductive layer.

[0004] According to another aspect of the embodiments of this application, an integrated circuit device is provided, comprising: a die; an interconnect that at least partially overlaps with the die; and a plurality of bumps located in the region where the interconnect overlaps with the die, wherein: the interconnect includes at least a first conductive layer and a second conductive layer, the plurality of bumps includes at least a first bump and a second bump spaced apart in a first direction, each of the first conductive layer and the second conductive layer includes a signal conductor and a ground conductor located in a region between the first bump and the second bump, and each signal conductor in each of the first conductive layer and the second conductive layer in the region between the first bump and the second bump completely perpendicularly overlaps with a ground conductor in one of the first conductive layer or the second conductive layer in a first direction.

[0005] According to another aspect of the embodiments of this application, a method for manufacturing an integrated circuit device is provided, the method comprising: forming an interconnect comprising at least a first conductive layer and a second conductive layer, wherein: the first conductive layer and the second conductive layer for forming the interconnect comprise forming a plurality of signal conductors between a first bump location for a first bump and a second bump location for a second bump, and forming a plurality of ground conductors between the first bump location and the second bump location, forming the plurality of signal conductors and the plurality of ground conductors comprises forming each of the plurality of signal conductors between a corresponding pair of ground conductors in a corresponding conductive layer, and forming the plurality of ground conductors comprises continuously coupling the plurality of ground conductors in each of the first conductive layer and the second conductive layer from a first side of the plurality of signal conductors to a second side of the plurality of signal conductors; and mounting a die to the interconnect in a region where the interconnect overlaps with a die using a plurality of bumps, the plurality of bumps including a first bump and a second bump. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 This is a schematic cross-section of an integrated circuit device according to some embodiments.

[0008] Figure 2A This is a schematic cross-section of an interconnect according to some embodiments.

[0009] Figure 2B This is a plan view of interconnects according to some embodiments.

[0010] Figure 2C This is a schematic cross-section of an integrated circuit (IC) device according to some embodiments.

[0011] Figure 3 According to some embodiments Figure 2A A detailed view of the area with continuous grounding wiring structure.

[0012] Figure 4 This is a schematic cross-section of an interconnect according to some embodiments.

[0013] Figure 5 This is a schematic cross-section of an interconnect according to some embodiments.

[0014] Figure 6 This is a schematic cross-section of an interconnect according to some embodiments.

[0015] Figure 7 This is a schematic cross-section of an interconnect according to some embodiments.

[0016] Figure 8 These are plan views and schematic cross-sectional views of interconnects according to some embodiments.

[0017] Figure 9 This is a schematic cross-section of an interconnect according to some embodiments.

[0018] Figure 10 This is a schematic cross-section of an interconnect according to some embodiments.

[0019] Figure 11A This is a flowchart of a method for manufacturing an integrated circuit device according to some embodiments.

[0020] Figure 11B This is a flowchart of a method for manufacturing an integrated circuit device according to some embodiments.

[0021] Figure 12 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0022] Figure 13 This is a block diagram of an integrated circuit (IC) manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0023] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0024] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0025] According to some embodiments, an integrated circuit device includes a die that is physically and electrically coupled to an interconnect serving as a next-stage substrate via a plurality of conductive bumps. Conductive paths in the interconnect that transmit signals to and / or from the die, such as from one die to another, may affect signal integrity.

[0026] As device integration increases and / or device structures become smaller and denser, large numbers of signals may be transmitted through closely spaced conductive structures. Increasing the number and / or size of signal conductors (wiring) helps maintain signal integrity, but this increase may involve reducing the number and / or size of ground conductors, which can reduce signal integrity.

[0027] According to some embodiments, signal, power, and ground wiring in the interconnect is designed to enhance the width of the signal conductors while providing a ground wiring structure that helps maintain signal integrity. Multiple conductive layers in the interconnect are used to route signals, power, and ground within the interconnect (e.g., in wiring between first and second dies mounted adjacent to each other on the surface of the interconnect). The interconnect includes a continuous ground wiring structure formed in multiple conductive layers adjacent to the mounting surface to enhance signal integrity. Compared to an alternative approach that does not use a continuous ground wiring structure, the width of the signal lines in the interconnect is increased.

[0028] Figure 1 This is a schematic cross-section of an integrated circuit (IC) device 101 along the XY plane according to some embodiments.

[0029] The integrated circuit device 101 includes a first die 102a and a second die 102b (the first and second dies 102a and 102b may be referred to individually or collectively as die 102). The first and second dies 102a and 102b are spaced apart in a first direction parallel to the X-axis. In some embodiments, the first die 102a and the second die 102b are each integrated circuit dies, such as semiconductor dies, wherein a plurality of active and / or passive circuits are formed.

[0030] The first and second dies 102a and 102b are interconnected via interconnect 104. The first and second dies 102a and 102b and interconnect 104 are located in the same package.

[0031] First and second dies 102a and 102b are bonded to the surface of interconnect 104 in at least a portion of the region where the respective dies overlap with interconnect 104. Interconnect 104 transmits a reference voltage (e.g., at least one power supply voltage and a ground voltage) to / from first die 102a and second die 102b and / or between first die 102b and second dies 102a and 102b. Interconnect 104 also transmits signals to / from first die 102a and second die 102b and / or between first die 102a and second die 102b. In some embodiments, the reference voltage is substantially constant (e.g., always power supply, ground, etc.) during device operation, compared to signals that vary with device operation (e.g., vary during circuit operation to turn the gate on and off, such as when processing, transmitting, or receiving data).

[0032] exist Figure 1 In this embodiment, interconnect 104 is mounted or embedded in a next-level substrate 108, such as an organic substrate including FR4. In some embodiments, the next-level substrate 108 includes multiple conductive layers, such as multiple metal layers coupled together through multiple vias. In other embodiments, no next-level substrate is used.

[0033] In some embodiments, the first die 102a is a memory die such as a high-bandwidth memory (e.g., HBM2, HBM3, etc.), and the second die 102b is a logic die such as a processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), etc.), an ASIC, etc. In some embodiments, the first die 102a is one of a processor and a coprocessor, and the second die 102b is the other of a processor and a coprocessor. In some embodiments, the first and / or second dies 102a and 102b are bare dies, while in other embodiments they are packaged as chips.

[0034] In some embodiments, interconnect 104 is a local silicon interconnect (LSI), a silicon interposer (e.g., having through-silicon vias and controlled collapse chip connection bumps on opposite sides), etc., embedded in an organic substrate. In some embodiments, interconnect 104 is part of a motherboard, an organic substrate including FR4, a printed circuit board, a printed wiring board, a redistribution layer, etc.

[0035] In some embodiments, the integrated circuit device 101 is implemented as a package or part of a package, such as an integrated fan-out package, an integrated fan-out package with a package-on-package structure, a chip-on-a-substrate package, a flip-chip package, an embedded multi-chip interconnect bridge, a 2.5D or 3D package, etc.

[0036] exist Figure 1In this embodiment, each of the first die 102a and the second die 102b completely and perpendicularly overlaps with the interconnect 104, where perpendicularly means a second direction parallel to the Y-axis. That is, the first die 102a does not extend beyond the first side 106a of the interconnect 104, and the second die 102b does not extend beyond the second side 106b of the interconnect 104. In other embodiments, one or both of the first and second dies 102a and 102b partially overlap with the interconnect 104. Figure 1 (not shown in the diagram), such that the first die 102a extends beyond the first side 106a of the interconnect 104 and / or the second die 102b extends beyond the second side 106b of the interconnect 104.

[0037] Figure 2A This is a schematic cross-section along the YZ plane of interconnect 204A according to some embodiments.

[0038] In some embodiments, interconnect 204A corresponds to interconnect 104. Interconnect 204A has a connection with... Figure 1 The interconnecting element 104 described herein is a component with a similar structure and function, having the same component symbol but with the addition of 100, unless otherwise stated or otherwise clearly distinguished.

[0039] exist Figure 2A In this embodiment, substrate 210 is provided with multiple conductive wirings, wherein conductive layer Mz is disposed closest to the first surface S1 (bump surface) of substrate 210, conductive layer Mz-1 is disposed below conductive layer Mz, conductive layer Mi is disposed below conductive layer Mz-1, and conductive layer Mi-1 is disposed below conductive layer Mi. In some embodiments, substrate 210 is a silicon substrate or the like.

[0040] In some embodiments, conductive layer Mz is the conductive layer closest to the first surface S1 among all conductive layers (i.e., wiring layers) in interconnect 204A (e.g., in the case where interconnect 204A includes seventeen conductive layers, conductive layer Mz is the seventeenth conductive layer, although this is merely for illustrative purposes and embodiments may have any suitable number of conductive layers). In some embodiments, an additional conductive layer is provided below conductive layer Mi-1.

[0041] The conductive layers in substrate 210 provide wiring such as signal wiring, power and ground wiring (e.g., power delivery networks), power planes, ground planes, etc. In some embodiments, at least some conductive layers provide wiring in the first and second dies mounted to interconnect 204A. Figure 2A Signal wiring carrying signals between (not shown in the image).

[0042] First, second, and third conductive bumps 212a, 212b, and 212c (collectively or individually referred to as conductive bump 212) are respectively arranged in the first column coln, the second column coln+1, and the third column coln+2 at the first surface S1. The first, second, and third columns coln, coln+1, and coln+2 are three columns out of a set of m columns, where n is a positive integer and m is a positive integer of 3 or greater, such as m=8, m=10, m=16, etc. These columns are spaced apart in a third direction parallel to the Z-axis and extend parallel to the X-axis. In some embodiments, the edge of the die (e.g., the first die 102a or the second die 102b) extends parallel to the Z-axis, and the columns extend perpendicular to the edge of the die.

[0043] The conductive bump 212 provides the interconnect 204A and the die that is engaged at the first surface S1. Figure 2A Electrical connections between (not shown) such as the first or second die 102a or 102b described above. In some embodiments, one or more conductive bumps 212 also provide mechanical or bonding connections between the interconnect 204A and the die. In some embodiments, the conductive bumps 212 are arranged according to a bump map. In some embodiments, the bump map corresponds to or is based on a specification such as the Universal Chipplet Interconnect Express (UCIe) specification.

[0044] exist Figure 2A In the diagram, the first conductive bump 212a and the third conductive bump 212c are located in the same row, while the second conductive bump 212b is located in a different row from the first conductive bump 212a and the third conductive bump 212c (therefore, the second conductive bump 212b is shown with a dashed circle). In some embodiments, each row extends parallel to the Z-direction, for example, parallel to the die edge. The first, second, and third conductive bumps 212a, 212b, and 212c are spaced at a regular pitch in the Z-direction (in... Figure 2A The columns are separated by a pitch of 212CP.

[0045] In some embodiments, the column pitch 212CP is set with reference to a specification such as the UCIe specification. By way of example only, in a non-limiting embodiment, an example value for the column pitch 212CP is 38.88 μm, although larger or smaller column pitches are used in various embodiments. Figure 2A In the same row, the first and third conductive bumps 212a and 212c are spaced apart by twice the column pitch 212CP. By way of example only, in a non-limiting embodiment, the center-to-center distance of the first and third conductive bumps 212a and 212c along the row is an example of 77.76 μm, although larger or smaller distances are used in various embodiments.

[0046] In some embodiments, the first, second, and third columns coln, coln+1, and coln+2 are three of ten columns included in a first connection module that connects a first die to interconnect 204A (e.g., the first die 102a described above) and communicates with a second ten-column connection module that connects a second die (e.g., the second die 102b described above) to interconnect 204A. It should be understood that ten columns are merely an example. In other embodiments, more than or less than ten columns are used, such as eight or sixteen columns. Furthermore, each die can be coupled to interconnect 204A via multiple modules, each module including multiple columns of conductive bumps 212.

[0047] At least some conductive bumps 212 transmit signals between the die and the interconnect 204A. At least a portion of the signal is routed through signal wiring in conductive layers Mz and Mz-1 within the interconnect 204A. Conductive layers Mz and Mz-1 also include ground wiring corresponding to the signal wiring configuration in conductive layers Mz and Mz-1 to enhance signal integrity and control factors such as insertion loss, return loss, near-end crosstalk, and far-end crosstalk. The ground wiring is configured such that at least a portion of it is continuous in the area of ​​the interconnect 204A providing signal wiring. In some embodiments, the continuous ground wiring structure of the interconnect 204A significantly reduces crosstalk while having equivalent insertion loss and return loss values ​​compared to another method that does not use a continuous ground wiring structure.

[0048] exist Figure 2A In this configuration, grounding wire 214 includes a first plurality of grounding wires 214a in conductive layer Mz and a second plurality of grounding wires 214b in the lower adjacent conductive layer Mz-1. Similarly, signal wire 216 includes a first plurality of signal wires 216a in conductive layer Mz and a second plurality of signal wires 216b in the lower adjacent conductive layer Mz-1. In some embodiments, conductive layers Mz and Mz-1 include interconnect wiring structures, wherein a first plurality of ground lines 214a extend in conductive layer Mz along a first direction (e.g., parallel to the X-axis), a first plurality of signal lines 216a extend in conductive layer Mz along the first direction and alternate with ground lines 214a in conductive layer Mz along a third direction (e.g., parallel to the Z-axis), and a second plurality of ground lines 214b extend in conductive layer Mz-1 along a first direction (e.g., below the first plurality of ground lines 214a and the first plurality of signal lines 216a relative to a second direction (parallel to the Y-axis), wherein at least a portion of the first plurality of ground lines 214a is coupled to at least a portion of the second plurality of ground lines 214b to form a continuous ground wiring structure.

[0049] exist Figure 2AIn this example, grounding wires 214a-1 to 214b-n are included in a continuous grounding wiring structure within conductive layers Mz and Mz-1 (the continuous grounding wiring structure within conductive layers Mz and Mz-1 is considered to include via structure 218 in the via layer Vz connecting conductive layers Mz / Mz-1). That is, there is an uninterrupted grounding wiring structure within conductive layers Mz and Mz-1. Figure 3 More details are shown in the middle. Figure 2A The continuous grounding wiring structure in area 214R.

[0050] On the other hand, Figure 2A In the diagram, for example only, another ground wire 214x is shown in conductive layer Mz. Ground wire 214x is not connected to another ground wire in conductive layers Mz and Mz-1 through vias in layer Vz. Therefore, ground wire 214x is not part of the continuous ground wiring structure within conductive layers Mz and Mz-1.

[0051] In some embodiments, signal lines 216 and ground lines 214 are arranged within each of conductive layers Mz and Mz-1 such that each signal line 216 is separated from an adjacent signal line 216 within the same conductive layer Mz or Mz-1 by a ground line 214 (in the Z-axis direction). For example, signal line 216a-1 (in the Z-axis direction) is separated from an adjacent signal line 216a-2 within conductive layer Mz by a ground line 214a-2. As another example, signal line 216b-1 is separated from an adjacent signal line 216b-2 within conductive layer Mz-1 by a ground line 214b-2 (in the Z-axis direction).

[0052] In some embodiments, at least one signal from a first die (e.g., the first die 102a described above) is coupled to an interconnect 204A via one or more conductive bumps 212, transmitted through the interconnect 204A via one or more of a first plurality of signal lines 216a in conductive layer Mz and / or a second plurality of signal lines 216b in conductive layer Mz-1, and coupled from the interconnect 204A to a second die (e.g., the second die 102b described above) via one or more corresponding conductive bumps 212. At least a portion of this signal path is defined by a region (e.g., region 214R) of a continuous ground wiring structure in conductive layers Mz and Mz-1. In some embodiments, all signal lines 216 in either conductive layer Mz or Mz-1 between a given conductive bump 212 and a conductive bump 212 in an adjacent column are defined on both sides (relative to the Z-axis direction or the bump pitch direction) by ground wires of a continuous ground wiring structure within the corresponding conductive layer Mz or Mz-1.

[0053] exist Figure 2AIn the interconnect 204A, a plurality of the first plurality of ground wires 214a perpendicularly overlap with a plurality of the second plurality of ground wires 214b, and are connected to them through a vertical via structure 218 in a via layer Vz-1 extending between conductive layers Mz and Mz-1. Therefore, a portion of the continuous ground wiring structure in the interconnect 204A includes a first ground wire 214a1 in conductive layer Mz, a first via structure 218-1 in via layer Vz-1, a second ground wire 214b-1 in conductive layer Mz-1, a second via structure 218-2 in via layer Vz-1, and a third ground wire 214a-2 in conductive layer Mz. A first signal line 216a-1 in conductive layer Mz is located between the first and third ground wires 214a-1 and 214a-2 in conductive layer Mz, and is located above the second ground wire 214b-1 in conductive layer Mz-1.

[0054] exist Figure 2A In the middle, the ground wire 214 is continuously coupled together across all the signal lines 216 in the conductive layers Mz and Mz-1 located between the first and third conductive bumps 212a and 212c, that is, the ground wire 214 is continuously coupled together from the first side of the first signal line 216a-1 to the second side of the nth signal line 216a-n.

[0055] In other embodiments, the ground wire 214 is continuously coupled together across all signal lines 216 in the conductive layers Mz and Mz-1 between the bumps in adjacent columns. Examples of this arrangement are described below. Figure 9 and Figure 10 As shown in the image.

[0056] In some embodiments, each of the plurality of signal lines 216 in the conductive layers Mz and Mz-1 and between the conductive bumps 212 of adjacent columns (e.g., coln and coln+1, or coln+1 and coln+2) is disposed between pairs of ground lines 214 of the respective conductive layers Mz or Mz-1, and these pairs of ground lines 214 are continuously coupled from the first side (e.g., through via structure 218) to the second side within the first and second conductive layers Mz and Mz-1. Figure 2A An example of this arrangement is shown in the figure.

[0057] In some embodiments, each signal line 216 in the conductive layers Mz and Mz-1 in the region between two adjacent bumps (e.g., the region between the first conductive bump 212a and the second conductive bump 212b) completely vertically overlaps with the ground line 214 in one of the conductive layers Mz or Mz-1. Figure 2A An example of this arrangement is shown in the figure. It should be understood that the term "vertical overlap" refers to overlap relative to the Y-axis direction. Figure 2AThe virtual vertical reference line RL1 intersects with the nth signal line 216b-n and the nth ground line 214a-n, so the signal line 216b-n overlaps vertically with the nth ground line 214a-n. Furthermore, the overall width WDS of the nth signal line 216b-n overlaps vertically with the nth ground line 214a-n. Therefore, the nth signal line 216b-n and the nth ground line 214a-n completely overlap vertically.

[0058] In some embodiments, interconnect 204A is a silicon interconnect or a local silicon interconnect comprising an organic substrate (e.g., FR4, etc.), and conductive bumps 212 are disposed between and coupled to the die and the silicon interconnect or local silicon interconnect. In some embodiments, the silicon interconnect or local silicon interconnect includes a through-silicon via (TSV). Figure 2A In the diagram, the first TSV 220a is aligned with the first column coln of the conductive bump 212, and the second TSV 220b is aligned with the third column coln+2 of the conductive bump 212. TSVs may be referred to individually or collectively as TSV 220.

[0059] In some embodiments, the ground wire 214 is continuously coupled together across all signal lines 216 in conductive layers Mz and Mz-1 located between adjacent TSVs 220 (e.g., between first and second TSVs 220a and 220b). In some embodiments, each signal line 216 in conductive layers Mz and Mz-1 in the region between adjacent TSVs 220 (e.g., between first and second TSVs 220a and 220b) completely perpendicularly overlaps with the ground wire 214 in one of conductive layers Mz or Mz-1.

[0060] Interconnector 204A also includes a first power / ground pair 224a comprising a power line 222a and a ground line 214c-1, and a second power / ground pair 224b comprising a power line 222b and a ground line 214c-2. The power / ground pairs may be referred to individually or collectively as power / ground pair 224. Figure 2A In this embodiment, the first and second power / ground pairs 224a and 224b are both located in conductive layer Mz-1. In other embodiments, the power / ground pairs 224 are located together in different conductive layers. In still other embodiments, the power / ground pairs 224 are separated or distributed in multiple conductive layers. Figure 2A In this configuration, the first power / ground pair 224a corresponds to the first column coln of the conductive bump 212, and the second power / ground pair 224b corresponds to the third column coln+2 of the conductive bump 212. In other embodiments, power / ground pairs 224 are provided to correspond to each column of conductive bump 212 ( Figure 9 and Figure 10An example of this arrangement is shown in the diagram. The power / ground pair 224 can help reduce IR drop in the interconnect 204A.

[0061] exist Figure 2A In this embodiment, the grounding wires 214c-1 and 214c-2 of the first and second power / ground pairs 224a and 224b are electrically connected via conductive layer Mi to a continuous grounding wiring structure including a first plurality of grounding wires 214a and a second plurality of grounding wires 214b. In other embodiments, electrical connections within conductive layers Mz and Mz-1 are used to replace or supplement the electrical connections in conductive layer Mi to electrically connect the grounding wires 214c-1 and 214c-2 to the continuous grounding wiring structure.

[0062] In some embodiments, one or more power / ground pairs 224 are aligned with corresponding TSV 220. For example, in Figure 2A In this configuration, a first power / ground pair 224a is aligned with a first TSV 220a, and a second power / ground pair 224b is aligned with a second TSV 220b. In some embodiments, the power or ground line of the power / ground pair 224 is coupled to the TSV 220. Aligning one or more power / ground pairs 224 with their respective TSVs 220 simplifies the connection between the power / ground pairs 224 and the TSVs 220. In some embodiments, the TSVs are arranged in rows and / or columns in the region where conductive bumps 212 are provided, and multiple TSVs in the rows and / or columns are alternately coupled to ground or power.

[0063] Figure 2B This is a plan view of interconnect 204B in the XZ plane according to some embodiments.

[0064] exist Figure 2B In the diagram, line A-A' extending parallel to the Z-axis corresponds to... Figure 2A The line AA′. In interconnect 204B, it has a connection with... Figure 2A The elements of interconnect 204A described herein have similar structure and function to those of interconnect 204B, and have the same element symbols but with the addition of 100, unless otherwise stated or otherwise clearly distinguished.

[0065] Figure 2B Columns of conductive bumps 312 extending parallel to the X-axis are shown, and these columns are spaced apart from each other along the Z-axis. Figure 2B Also shown is a TSV 320 arranged to substantially overlap with the column of conductive bumps 312.

[0066] Figure 2C This is a schematic cross-section of an integrated circuit (IC) device 201 along the XY plane according to some embodiments.

[0067] In integrated circuit device 201, there is a similar Figure 1 The components of the integrated circuit device 101 described herein have similar structures and functions, and have the same component symbols but are marked with 100, unless otherwise stated or otherwise clearly distinguished.

[0068] The integrated circuit device 201 includes a first die 202a and a second die 202b. The first and second dies 202a and 202b are spaced apart in a first direction parallel to the X-axis. In some embodiments, each of the first die 202a and the second die 202b is an integrated circuit die, such as a semiconductor die.

[0069] The first die 202a and the second die 202b are interconnected via an interconnect 204C. The first die 202a and the second die 202b are bonded to the surface of the interconnect 204C in at least a portion of the region where the respective die overlaps with the interconnect 204C. Figure 2C In this embodiment, interconnect 204C is an active next-stage substrate (e.g., a local silicon interconnect (LSI) in an organic substrate, a monolithic silicon interposer, etc.). The active next-stage substrate includes first and second circuits 204AC1 and 204AC2, and a plurality of conductive layers, wherein wiring 204W is formed between the first and second circuits 204AC1 and 204AC2. In some embodiments, at least one of the first circuit 204AC1 and the second circuit 204AC2 includes an active circuit. In some embodiments, at least one of the first circuit 204AC1 and the second circuit 204AC2 includes both active and passive circuits. In some embodiments, at least one of the first circuit 204AC1 and the second circuit 204AC2 includes only passive circuits. In some embodiments, interconnect 204C is a passive next-stage substrate, and both the first and second circuits 204AC1 and 204AC2 include only passive circuits.

[0070] Electrical connections provided by a plurality of conductive bumps 212 between the first die 202a and the interconnect 204C couple the power, ground, and signal connections between the third circuit 202AC1 in the first die 202a and the first circuit 204AC1 in the interconnect 204C. For clarity, Figure 2C A conductive bump 212 is shown between the first die 202a and the interconnect 204C, and a conductive bump 212 is shown between the second die 202b and the interconnect 204C. However, it should be understood that in practice, multiple conductive bumps 212 are located between the first die 202a and the interconnect 204C, and multiple conductive bumps 212 are located between the second die 202b and the interconnect 204C.

[0071] In some embodiments, the third circuit 202AC1 is a transmitting circuit and the first circuit 204AC1 is a receiving circuit. In some embodiments, the third circuit 202AC1 and the first circuit 204AC1 are transceivers. In other embodiments, different and / or additional circuitry is implemented in one or both of the third and first circuits 202AC1 and 204AC1.

[0072] Electrical connections provided by a plurality of conductive bumps 212 between the second die 202b and the interconnect 204C couple power, ground, and signal connections between the fourth circuit 202AC2 in the second die 202b and the second circuit 204AC2 in the interconnect 204C. In some embodiments, the fourth circuit 202AC2 is a receiving circuit and the second circuit 204AC2 is a transmitting circuit. In some embodiments, the fourth circuit 202AC2 and the second circuit 204AC2 are transceivers. In other embodiments, different and / or additional circuitry is implemented in one or both of the fourth and second circuits 202AC2 and 204AC2.

[0073] In some embodiments, the channel distance in interconnect 204C is about 3000 μm or less, for example from 1000 μm to 2000 μm. The channel distance represents the length of wiring and / or circuitry (including first and second circuits 204AC1 and 204AC2 and wiring 204W) between the first and second dies 202a and 202b in interconnect 204C.

[0074] In some embodiments, the above-mentioned combination Figure 2A The discussed continuous grounding wiring structure exists in a conductive layer in interconnect 204C, which is located between conductive bumps 212 and the first and second circuits 204AC1 and 204AC2. For example, in some embodiments, the above-described... Figure 2A The grounding wires 214a-1 to 214b-n discussed exist in the interconnects 204C in the conductive layers Mz and Mz-1, which are located below the conductive bumps 212 and above the first and second circuits 204AC1 and 204AC2.

[0075] Figure 3 According to some embodiments Figure 2A Detailed view of area 214R of the continuous grounding cabling structure.

[0076] Reference Figure 3In the conductive layer Mz, adjacent signal lines 216 of the first plurality of signal lines 216a are arranged with a pitch 301P in the Z-axis direction. The signal lines 216 have a uniform width a in the Z-axis direction. The via structure 218 has a uniform width a' in the Z-axis direction. In some embodiments, the width a' of the via structure 218 corresponds to the overlap width between the ground lines 214 connected by the via structure 218, for example, in... Figure 3 In this configuration, ground wire 214a overlaps ground wire 214b in the Z-axis direction by the width a' of via structure 218a. In some embodiments, the width a' of via structure 218 in the Z-axis direction is equal to the width a of signal line 216 in the Z-axis direction. Signal line 216 is spaced apart from adjacent conductors in the corresponding conductive layer Mz or Mz-1 by a distance b in the Z-axis direction. In some embodiments, the distance b is greater than the width a of signal line 216, for example, approximately 25% greater. Ground wire 214 has a uniform width c in the Z-axis direction.

[0077] Pitch 301P includes two signal line widths a, two via widths a', and four pitches b. By way of example only, in a non-limiting embodiment, the signal line width a is 0.36 μm, the via width a' is 0.36 μm, and the pitch b is 0.45 μm. The value of pitch 301P is (2 × 0.36 μm) + (2 × 0.36 μm) + (4 × 0.45 μm) = 3.24 μm, although larger or smaller values ​​for various widths are used in various embodiments.

[0078] In some embodiments, depending on the manufacturing process, the pitch 301P is approximately 10% or less of the column pitch 212CP. In some embodiments, depending on the manufacturing process, the minimum value of the pitch 301P is approximately 8% of the column pitch 212CP.

[0079] In some embodiments, the combined width of the signal lines 216 is approximately 20% or more of the pitch 301P. Because the ground wire 214 is connected in a continuous ground wiring structure throughout the pitch 301P, the combined width of the signal lines 216 is also approximately 20% or more of the ground wiring width for each pitch 301P. In some embodiments, the combined width of the signal lines 216 for each pitch 301P is approximately 20% or more of the ground wiring width, which helps ensure the integrity of signals transmitted using the signal lines 216 by providing a relatively large signal line width to ground line width ratio, while also providing a relatively dense signal line 216.

[0080] Figure 4 This is a schematic cross-section along the YZ plane of interconnect 404 according to some embodiments.

[0081] In interconnect 404, there is a connection with Figure 2AThe interconnecting element 204A described herein is a component with a similar structure and function, having the same component symbol but with the addition of 200, unless otherwise stated or otherwise clearly distinguished.

[0082] Compared to the interconnect 204A described above, in some embodiments, the interconnect 404 includes more signal lines 416 in conductive layers Mz and Mz-1, while in other embodiments, it includes fewer signal lines 416 in conductive layers Mz and Mz-1. In some embodiments, the number of signal lines 416 in each of conductive layers Mz and Mz-1 is even, while in other embodiments, the number of signal lines 416 in each of conductive layers Mz and Mz-1 is odd. In yet another embodiment, the number of signal lines 416 in one of conductive layers Mz or Mz-1 is even, while the number of signal lines 416 in the other of conductive layers Mz or Mz-1 is odd.

[0083] In some embodiments, regardless of the number of signal lines 416 in conductive layers Mz and Mz-1, the signal lines 416 are disposed between a first boundary ground line 414z-1 on a first side of the signal line 416 relative to the Z-axis direction and a second boundary ground line 414z-2 on a second side of the signal line 416 relative to the Z-axis direction, wherein the first and second boundary ground lines 414z-1 and 414z-2 are coupled together within conductive layers Mz and Mz-1 as part of a continuous ground wiring structure in conductive layers Mz and Mz-1.

[0084] In some embodiments, regardless of the number of signal lines 416 in conductive layers Mz and Mz-1, all signal lines 416 in either of the conductive layers Mz and Mz-1 between a bump 412 in a given column (e.g., column coln) and a bump 412 in an adjacent column (e.g., column coln+1) are defined on both sides (relative to the Z-axis direction or the bump pitch direction) by ground lines 414 of a continuous ground wiring structure within the respective conductive layer Mz or Mz-1.

[0085] Furthermore, in some embodiments, regardless of the number of signal lines 416 in conductive layers Mz and Mz-1, the signal lines 416 and ground lines 414 are arranged in each conductive layer Mz / Mz-1 such that each signal line 416 is separated from the adjacent signal line 416 in the same conductive layer Mz or Mz-1 (in the Z-axis direction) by the ground line 414 of the continuous ground wiring structure in the corresponding conductive layer Mz or Mz-1.

[0086] Furthermore, in some embodiments, regardless of the number of signal lines 416 in conductive layers Mz and Mz-1, the width of the region of the continuous ground wiring structure in the Z-axis direction is at least as wide as the region including all signal lines 416, such that all signal lines 216 perpendicularly overlap the continuous ground wiring structure. Figure 4 As an example, ground lines 414z-1 to 414z-2 are included in a continuous grounding wiring structure within conductive layers Mz and Mz-1. In some embodiments, the continuous grounding wiring structure within conductive layers Mz and Mz-1 is continuous across all signal lines 416 between a first bump in a given row and an adjacent second bump in a given row. In some embodiments, the continuous grounding wiring structure within conductive layers Mz and Mz-1 is continuous across all signal lines 416 between a first column and an adjacent second column. In some embodiments, the continuous grounding wiring structure within conductive layers Mz and Mz-1 is continuous across all signal lines 416 between a first TSV and an adjacent second TSV. Continuous grounding wiring structures can enhance signal integrity and control over factors such as insertion loss, return loss, near-end crosstalk, and far-end crosstalk. In some embodiments, the continuous grounding wiring structure of interconnect 404 significantly reduces crosstalk while having equivalent insertion loss and return loss values ​​compared to an alternative method that does not use continuous grounding wiring structures.

[0087] Figure 5 This is a schematic cross-section along the YZ plane of interconnect 504 according to some embodiments.

[0088] In interconnect 504, there is a connection with Figure 2A The components of interconnect 204A described herein have similar structure and function to those of other components, but with the same component symbol but with the addition of 300, unless otherwise stated or otherwise clearly distinguished.

[0089] exist Figure 5 In the middle, the arrangement of signal lines is relative to Figure 4 There are some differences. Furthermore, compared to the interconnect 204A described above, in some embodiments, the interconnect 504 includes more signal lines 516 in conductive layers Mz and Mz-1, while in other embodiments it includes fewer signal lines 516 in conductive layers Mz and Mz-1.

[0090] In some embodiments, regardless of the number of signal lines 516 in conductive layers Mz and Mz-1, the signal lines 516 are disposed between a first boundary ground line 514z-1 on the first side of the signal line 516 relative to the Z-axis direction and a second boundary ground line 514z-2 on the second side of the signal line 516 relative to the Z-axis direction, wherein the first and second boundary ground lines 514z-1 and 514z-2 are coupled together within conductive layers Mz and Mz-1 as part of a continuous ground wiring structure in conductive layers Mz / Mz-1.

[0091] Furthermore, in some embodiments, the number and / or arrangement of ground lines 514 can vary regardless of the number of signal lines 516 in conductive layers Mz and Mz-1. For example, in Figure 5 Even if there is no signal line in the conductive layer Mz adjacent to the grounding line 514z-1, the grounding line 514z-1 encircled in the conductive layer Mz forms part of a continuous grounding wiring structure, so that even if no signal line 516 is provided in this area, the continuous grounding wiring structure is continuous in the area of ​​conductive layers Mz / Mz-1. As another example, although Figure 4 The boundary grounding wires 414z-1 and 414z-2 are located in different conductive layers, but Figure 5 The boundary grounding wires 514z-1 and 514z-2 are located in the same conductive layer Mz. In other embodiments, the boundary grounding wires at the ends of the continuous grounding wiring structure are arranged such that the grounding wires are all located in the conductive layer Mz-1. Figure 5 (Not shown in the image).

[0092] Figure 6 This is a schematic cross-section along the YZ plane of interconnect 604 according to some embodiments.

[0093] In interconnect 604, there is a connection with Figure 2A The components of interconnect 204A described herein have similar structure and function to those of other components, but with the same component symbol but increased by 400, unless otherwise stated or otherwise clearly distinguished.

[0094] exist Figure 6 In the middle, the arrangement of signal lines is relative to Figure 4 There are differences. (As mentioned above) Figure 4 In this configuration, all signal lines 416 are positioned between a first boundary grounding line 414z-1 on a first side of the signal line 416 relative to the Z-axis direction and a second boundary grounding line 414z-2 on a second side of the signal line 416 relative to the Z-axis direction. The first and second boundary grounding lines 414z-1 and 414z-2 are coupled together within conductive layers Mz and Mz-1, forming part of a continuous grounding wiring structure within conductive layers Mz and Mz-1. In contrast, in... Figure 6In the text, the ground wires corresponding to the first and second boundary ground wires 414z-1 and 414z-2 are omitted.

[0095] In other words, Figure 6 In the above, signal line 616z-1 has a ground wire 614-1 on one side of its conductive layer Mz (which is part of a continuous ground wiring structure within conductive layers Mz and Mz-1, and all signal lines 616 are continuous across the first TSV 620a and the adjacent second TSV 620b), but the continuous ground wiring structure does not include another ground wire on the other side of signal line 616z-1 in region Ma of conductive layer Mz. Similarly, signal line 616z-2 includes a ground wire 614-2 (which is part of a continuous ground wiring structure) on one side of conductive layer Mz-1, but the continuous ground wiring structure does not include another ground wire on the other side of signal line 616z-2 in region Mb of conductive layer Mz-1. Nevertheless, the grounding wires 614 of the continuous grounding wiring structure (including at least grounding wires 614-1, 614-2, and 614-3) extend laterally in the Z-axis direction beyond all signal lines 616 located between the first TSV 620a and the adjacent second TSV 620b, as shown, wherein grounding wire 614-3 extends laterally beyond signal line 616z-1 by a distance of distance Da, and wherein grounding wire 614-2 extends laterally beyond signal line 616z-2 by a distance of distance Db.

[0096] In some embodiments, such as Figure 6 As shown in the example, regardless of the number of signal lines 616 in conductive layers Mz and Mz-1, the ground line 614 of the continuous ground wiring structure extends laterally in the Z-axis direction beyond all signal lines 616 between the bump 612 in a given column and the bump 612 in the adjacent column (e.g., coln and coln+1, or coln+1 and coln+2).

[0097] In some embodiments, such as Figure 6 In the example, regardless of the number of signal lines 616 in conductive layers Mz and Mz-1, all signal lines 616 located between bumps 612 in a given column and bumps 612 in adjacent columns (e.g., coln and coln+1, or coln+1 and coln+2) have ground lines 614 on both sides in the respective conductive layer (which are contained in a continuous ground wiring structure).

[0098] In some embodiments, such as Figure 6As shown in the example, regardless of the number of signal lines 616 in conductive layers Mz and Mz-1, all signal lines 616 in either conductive layer Mz / Mz-1 between the bumps 612 in a given column and the bumps 612 in the adjacent columns (e.g., coln and coln+1, or coln+1 and coln+2) completely and perpendicularly overlap with the ground wire 614 of the continuous ground wiring structure within the corresponding conductive layer Mz or Mz-1.

[0099] Figure 7 This is a schematic cross-section along the YZ plane of interconnect 704 according to some embodiments.

[0100] In interconnect 704, there is a connection with Figure 2A The components of interconnect 204A described herein have similar structure and function to those of other components, but with the same component symbol but increased by 500, unless otherwise stated or otherwise clearly distinguished.

[0101] exist Figure 7 In, the number of conductive layers used for signal lines and continuous ground wiring structures, for example, relative to Figure 4 And change. Figure 7 An example is shown where signal lines and ground lines / vias are arranged in three conductive layers Mz, Mz-1, and Mz-2. In other embodiments, more than three conductive layers are used. In some embodiments, the three conductive layers Mz, Mz-1, and Mz-2 are the three conductive layers closest to the bonding surface (bump surface) of the interconnect 704 among all conductive layers (i.e., wiring layers) of the interconnect 704.

[0102] In some embodiments, such as Figure 7 As shown in the example, regardless of the number of conductive layers used for signal lines 716, all signal lines 716 located between the first TSV 720a and the adjacent second TSV 720b have ground lines 714 on both sides of the respective conductive layer (which are included in the continuous ground wiring structure).

[0103] In some embodiments, such as Figure 7 As shown in the example, regardless of the number of conductive layers used for signal lines 716, all signal lines 716 located between the first TSV 720a and the immediately adjacent second TSV 720b completely overlap vertically with at least one ground line 714 in the conductive layers (which is included in the continuous ground wiring structure).

[0104] In some embodiments, such as Figure 7In the example, regardless of the number of conductive layers used for signal lines 716, all signal lines 716 located between bumps 712 in a given column and bumps 712 in adjacent columns (e.g., coln and coln+1, or coln+1 and coln+2) have ground lines 714 on both sides of the corresponding conductive layer (which are contained in a continuous ground wiring structure).

[0105] In some embodiments, such as Figure 7 As shown in the example, regardless of the number of conductive layers used for signal lines 716, all signal lines 716 in the conductive layers between bumps 712 in a given column and bumps 712 in the adjacent columns (e.g., coln and coln+1, or coln+1 and coln+2) completely overlap vertically with the ground line 714 within one of the conductive layers (which is included in a continuous ground wiring structure).

[0106] Figure 8 (A) is a plan view of interconnect 804 in the XZ plane according to some embodiments. Figure 8 (B) is a schematic cross-sectional view of interconnect 804 in the XY plane.

[0107] Figure 8 (A) in the figure is a partial enlarged view of interconnect 204B.

[0108] In interconnect 804, there is a connection with Figure 2A The components of interconnect 204A described herein have similar structure and function to those of other components, but with the same component symbol but increased by 600, unless otherwise stated or otherwise clearly distinguished.

[0109] Reference Figure 8 In some embodiments, TSVs 820a to 820l are arranged sequentially along the X-axis (where "l" means "last"). That is, TSV 820a is directly adjacent to TSV 820b, such that no other TSVs are inserted between TSV 820b and TSV 820a in the X-axis direction.

[0110] Reference Figure 8 Along the X-axis, some TSVs are connected to the power supply, and some TSVs are grounded. In some embodiments, the TSVs arranged along the X-axis are alternately connected to the power supply and ground. For example, refer to... Figure 8 In (B) of the above embodiments, TSV 820a and TSV 820c are connected to a power supply, TSV 820B is connected to ground, and the alternating pattern continues through any additional TSVs aligned along the X-axis (e.g., the fourth to the first TSV).

[0111] Figure 9This is a schematic cross-section along the YZ plane of interconnect 904 according to some embodiments.

[0112] In interconnect 904, there is a connection with Figure 2A The components of interconnect 204A described herein have similar structure and function to those of other components, but with the same component symbol but increased by 700, unless otherwise stated or otherwise clearly distinguished.

[0113] exist Figure 9 In this embodiment, a power / ground pair 924 is provided for each column of conductive bumps 912 (including conductive bumps 912a, 912b, and 921c in the corresponding column). In the power / ground pair 924, the power line 922 has a width WDP in the Z-axis direction (i.e., in the direction of the column pitch 912CP), and the ground line 914 has a width WDG in the Z-axis direction. In some embodiments, the combined width (i.e., WDP+WDG) of the power and ground lines of the power / ground pair 924 is approximately 15% or more of the column pitch 912CP. By way of example only, in a non-limiting embodiment, the column pitch 912CP is 38.88 μm, and both WDP and WDG are 3.1 μm, ((2 × 3.1 μm) / 38.88 μm) × 100 = 15.9%, although larger or smaller values ​​of various widths are used in various embodiments.

[0114] In some embodiments, the first TSV 920a and the adjacent second TSV 920b are spaced apart by twice the column pitch 912CP. In some embodiments, the interconnect 904 includes 32 channels per cluster and two power / ground pairs 924 per cluster. In some embodiments, the width WDP is approximately the same as the width WDG. In some embodiments, the width WDG is approximately six to seven times the distance Dpg-s between the power / ground pairs 924 and the adjacent signal lines 616 in the same conductive layer (e.g., conductive layer Mz-1).

[0115] exist Figure 9 In the first continuous grounding wiring structure, the ground wire 914 is continuously coupled together with all signal lines 916 in the conductive layers Mz and Mz-1 between the bumps in adjacent columns coln and coln+1. Furthermore, in the second continuous grounding wiring structure, the ground wire 914 is continuously coupled together with all signal lines 916 across the conductive layers Mz and Mz-1 between the bumps in adjacent columns coln+1 and coln+2.

[0116] Figure 10 This is a schematic cross-section along the YZ plane of interconnect 1004 according to some embodiments.

[0117] In the interconnect 1004, there is a connection with Figure 2AThe components of interconnect 204A described herein have similar structure and function to those of other components, but with the same component symbol but with the addition of 800, unless otherwise stated or otherwise clearly distinguished.

[0118] In the above Figure 2A In the description, it should be noted that Figure 2A The electrical connection in the conductive layer Mi can be used to connect the grounding wire in the conductive layer Mz-1. Figure 10 The interconnect 1004 in the conductive layer Mi-1 illustrates an example structure of such an electrical connection.

[0119] Reference Figure 2A and Figure 10 The conductive layer Mi-1 (corresponding to Figure 2A The conductive layer Mi includes a grounding structure 1026, which is covered with the conductive layer Mi (corresponding to...). Figure 2A The grounding wire 1014 in the conductive layer Mz-1 is electrically connected.

[0120] exist Figure 10 In the first continuous grounding wiring structure, the ground wire 1014 is continuously coupled together across the conductive layers Mz and Mz-1 between the bumps in adjacent columns coln and coln+1. Furthermore, in the second continuous grounding wiring structure, the ground wire 1014 is continuously coupled together across the conductive layers Mz and Mz-1 between the bumps in adjacent columns coln+1 and coln+2.

[0121] Figure 11A This is a flowchart of a method 1100A for manufacturing an integrated circuit device according to some embodiments.

[0122] exist Figure 11A In this method 1100A, there are blocks 1100A-1 and 1100A-2. Block 1100A-1 includes sub-blocks 1100A-1a, 1100A-1b and 1100A-1c.

[0123] Block 1100A-1 includes interconnects forming at least a first conductive layer and a second conductive layer. Examples of interconnects formed in block 1100A-1 include the aforementioned interconnects 104, 204A, 204B, 204C, 404, 504, 604, 704, 804, and 904.

[0124] In subblock 1100A-1a, the first and second conductive layers forming the interconnects include forming a plurality of signal conductors between a first bump position of the first bump and a second bump position of the second bump, and forming a plurality of ground conductors between the first bump position and the second bump position.

[0125] In subblock 1100A-1b, forming a plurality of signal conductors and a plurality of ground conductors includes forming each of the plurality of signal conductors between a corresponding pair of ground conductors in a corresponding conductive layer.

[0126] In subblock 1100A-1c, forming a plurality of grounding conductors includes continuously coupling a plurality of grounding wires within the first and second conductive layers from a first side of a plurality of signal conductors to a second side of a plurality of signal conductors.

[0127] Block 1100A-2 includes mounting a die onto an interconnect, having a plurality of bumps in the area where the interconnect overlaps with the die, the plurality of bumps including a first bump and a second bump.

[0128] Figure 11B This is a flowchart of a method 1100B for manufacturing an integrated circuit device according to some embodiments.

[0129] According to some embodiments, method 1100B can, for example, use EDA system 1200 ( Figure 12 (Discussed below) and Integrated Circuit (IC) Manufacturing System 1300 ( Figure 13 (As discussed below) can be achieved. Examples of integrated circuit devices that can be manufactured according to method 1100B include the aforementioned integrated circuit devices 101 and 201, etc.

[0130] exist Figure 11B In method 1100B, blocks 1102 and 1104 are included. At block 1102, a layout diagram is generated. According to some embodiments, for example, an EDA system 1200 can be used. Figure 12 (Discussed below) to implement block 1102. In some embodiments, block 1102 includes generating a shape corresponding to the structure to be represented in the semiconductor diagram.

[0131] At block 1104, based on the layout diagram, at least one of the following is performed: (A) one or more photolithographic exposures are performed, or (B) one or more semiconductor masks are fabricated, or (C) one or more components in an integrated circuit (IC) device (e.g., semiconductor device) layer are fabricated. See below for more details. Figure 13 The discussion.

[0132] Figure 12 This is a block diagram of an electronic design automation (EDA) system 1200 according to some embodiments.

[0133] In some embodiments, the EDA system 1200 includes an Automatic Placement and Routing (APR) system. According to one or more embodiments, the method of designing a layout diagram described herein represents a wiring arrangement, which, for example, can be implemented using the EDA system 1200 according to some embodiments.

[0134] In some embodiments, the EDA system 1200 is a general-purpose computing device including a hardware processor 1202 and a non-transient computer-readable storage medium 1204. Among other things, the computer-readable storage medium 1204 is encoded with (i.e., stores) computer program code 1206 (i.e., a set of executable instructions). Execution of the instructions 1206 by the processor 1202 represents (at least partially) an EDA tool that implements some or all of the methods described herein (hereinafter referred to as the processes and / or methods) according to one or more embodiments.

[0135] Processor 1202 is electrically coupled to computer-readable storage medium 1204 via bus 1208. Processor 1202 is also electrically coupled to I / O interface 1210 via bus 1208. Network interface 1212 is also electrically connected to processor 1202 via bus 1208. Network interface 1212 is connected to network 1214, enabling processor 1202 and computer-readable storage medium 1204 to be connected to external components via network 1214. Processor 1202 is configured to execute computer program code 1206 encoded in computer-readable storage medium 1204 to make EDA system 1200 available for performing part or all of the processes and / or methods. In one or more embodiments, processor 1202 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0136] In one or more embodiments, the computer-readable storage medium 1204 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1204 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 1204 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video optical disc (DVD).

[0137] In one or more embodiments, computer-readable storage medium 1204 stores computer program code 1206 configured to enable EDA system 1200 (where such execution representation (at least partially) EDA tools) to perform some or all of the said processes and / or methods. In one or more embodiments, computer-readable storage medium 1204 also stores information facilitating the performance of some or all of the said processes and / or methods. In one or more embodiments, computer-readable storage medium 1204 stores a standard cell library 1207 comprising the standard cells disclosed herein. In one or more embodiments, computer-readable storage medium 1204 stores one or more layout figures 1209 corresponding to one or more layouts disclosed herein.

[0138] EDA system 1200 includes an I / O interface 1210. The I / O interface 1210 is coupled to external circuitry. In one or more embodiments, the I / O interface 1210 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 1202.

[0139] EDA system 1200 also includes a network interface 1212 coupled to processor 1202. Network interface 1212 allows EDA system 1200 to communicate with a network 1214 to which one or more other computer systems are connected. Network interface 1212 includes a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and / or methods are implemented in two or more EDA systems 1200.

[0140] EDA system 1200 is configured to receive information via I / O interface 1210. The information received via I / O interface 1210 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 1202. This information is transmitted to processor 1202 via bus 1208. EDA system 1200 is also configured to receive information related to the user interface (UI) via I / O interface 1210. This information is stored as UI 1242 in computer-readable storage medium 1204.

[0141] In some embodiments, part or all of the process and / or method is implemented as a standalone software application executed by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application as part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by EDA system 1200. In some embodiments, a layout diagram including standard cells is generated using a tool such as VIRTUOSO® available from CADENCEDESIGN SYSTEMS, Inc. or another suitable layout generation tool.

[0142] In some embodiments, these processes are implemented as the functions of a program stored in a non-transient computer-readable recording medium. Examples of non-transient computer-readable recording media include, but are not limited to, one or more of external / removable and / or internal / built-in storage or storage units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROMs), RAMs, memory cards, etc.

[0143] Figure 13 This is a block diagram of an integrated circuit (IC) manufacturing system 1300 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on the layout diagram, the IC manufacturing system 1300 is used to manufacture at least one of: (A) one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer.

[0144] exist Figure 13 In this IC manufacturing system 1300, entities such as design room 1320, mask room 1330, and IC manufacturing plant / fabrication (Fab) 1350 interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC devices 1360. The entities in IC manufacturing system 1300 are connected via a communication network. In some embodiments, the communication network is a single network. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design room 1320, mask room 1330, and IC manufacturing plant 1350 are owned by a single, larger company. In some embodiments, two or more of design room 1320, mask room 1330, and IC manufacturing plant 1350 coexist in a shared facility and use shared resources.

[0145] Design studio (or design team) 1320 generates IC design layout 1322. IC design layout 1322 includes various geometric patterns designed for IC device 1360. These geometric patterns correspond to patterns of metal, oxide, or semiconducting layers that constitute the various components of the IC device 1360 to be manufactured. These layers combine to form various IC features. For example, portions of IC design layout 1322 include various IC features such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for pads, which will be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design studio 1320 implements appropriate design processes to form IC design layout 1322. These design processes include one or more of logic design, physical design, or location and routing. IC design layout 1322 is presented in the form of one or more data files containing geometric pattern information. For example, IC design layout 1322 can be represented in GDSII or DFII file format.

[0146] Mask chamber 1330 includes mask data preparation 1332 and mask fabrication 1344. Mask chamber 1330 uses an IC design layout 1322 to fabricate one or more masks 1345 for fabricating various layers of an IC device 1360 according to the IC design layout 1322. Mask chamber 1330 performs mask data preparation 1332, in which the IC design layout 1322 is converted into a representative data file (RDF). Mask data preparation 1332 provides the RDF to mask fabrication 1344. Mask fabrication 1344 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (marker) 1345 or a substrate 1353, such as a semiconductor wafer 1353. The IC design layout 1322 is manipulated by mask data preparation 1332 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fabrication plant 1350. Figure 13 In this embodiment, mask data preparation 1332 and mask fabrication 1344 are shown as separate elements. In some embodiments, mask data preparation 1332 and mask fabrication 1344 may be collectively referred to as mask data preparation.

[0147] In some embodiments, mask data preparation 1332 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other process effects. OPC adjusts the IC design layout (Figure 1322). In some embodiments, mask data preparation 1332 includes further resolution enhancement techniques (RET), such as off-axis illumination, subresolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0148] In some embodiments, mask data preparation 1332 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout 1322 processed by OPC. This set of mask generation rules includes certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1322 to compensate for lithographic implementation effects during mask fabrication 1344, which can undo some modifications performed by OPC to satisfy the mask creation rules.

[0149] In some embodiments, mask data preparation 1332 includes a lithography process inspection (LPC), which simulates a process performed by an IC manufacturing plant 1350 to manufacture an IC device 1360. The LPC simulates this process based on an IC design layout 1322 to create a simulated manufactured device, such as IC device 1360. Process parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, or combinations thereof. In some embodiments, after the LPC has created a simulated manufactured device, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1322.

[0150] It should be understood that, for clarity, the above description of mask data preparation 1332 has been simplified. In some embodiments, mask data preparation 1332 includes additional features, such as modifying the logic operations (LOPs) of the IC design layout 1322 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1322 during mask data preparation 1332 can be performed in various different sequences.

[0151] Following mask data preparation 1332 and during mask fabrication 1344, a mask 1345 or a set of masks 1344 is fabricated based on a modified IC design layout 1322. In some embodiments, mask fabrication 1344 includes performing one or more photolithographic exposures based on the IC design layout 1322. In some embodiments, a pattern is formed on the mask (photomask or mask plate) 1345 using a mechanism of electron beam (e-beam) or multiple electron beams based on the modified IC design layout 1322. The mask 1345 can be formed using various techniques. In some embodiments, a binary technique is used to form the mask 1345. In some embodiments, the mask pattern includes opaque regions and transparent regions. Radiation beams, such as ultraviolet (UV) beams, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer are blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask version of the mask 1345 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, a phase-shifting technique is used to form mask 1345. In the phase-shifting mask (PSM) version of mask 1345, various features in the pattern formed on the phase-shifting mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase-shifting mask can be attenuated PSM or alternating PSM. The mask produced by mask fabrication 1344 is used in various processes. For example, the mask is used in ion implantation processes to form various doped regions in semiconductor wafer 1353, in etching processes to form various etched regions in semiconductor wafer 1353, and / or in other suitable processes.

[0152] IC manufacturing plant 1350 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC manufacturing plant 1350 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, a second manufacturing facility for providing back-end manufacturing (back-end process (BEOL) fabrication) for interconnecting and packaging of IC products, and a third manufacturing facility for providing other services for foundry operations.

[0153] IC manufacturing plant 1350 includes manufacturing tools 1352 configured to perform various manufacturing operations on semiconductor wafers 1353 to manufacture IC devices 1360 according to a mask (e.g., mask 1345). In various embodiments, manufacturing tools 1352 include one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes described herein.

[0154] IC fabrication plant 1350 uses a mask 1345, fabricated by mask chamber 1330, to fabricate IC device 1360. Therefore, IC fabrication plant 1350 uses IC design layout 1322 at least indirectly to fabricate IC device 1360. In some embodiments, semiconductor wafer 1353 is fabricated by IC fabrication plant 1350 using mask 1345 to form IC device 1360. In some embodiments, IC fabrication includes performing one or more photolithographic exposures based at least indirectly on IC design layout 1322. Semiconductor wafer 1353 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 1353 also includes one or more of various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent fabrication steps).

[0155] In some embodiments, the integrated circuit device includes: a die; an interconnect that at least partially overlaps with the die; and a plurality of bumps located in the region where the interconnect overlaps with the die, wherein: the interconnect includes at least a first conductive layer and a second conductive layer; the plurality of bumps includes first bumps and second bumps spaced apart along a first direction; each of the first conductive layer and the second conductive layer includes a plurality of signal conductors located between the first bumps and the second bumps and a plurality of ground conductors located between the first bumps and the second bumps; and all signal conductors in each of the first conductive layer and the second conductive layer between the first bumps and the second bumps are located between corresponding pairs of ground conductors in the respective conductive layer; and the pairs of ground conductors are continuously coupled from a first side of the plurality of signal conductors to a second side of the plurality of signal conductors within the first conductive layer and the second conductive layer.

[0156] In some embodiments, the first conductive layer and the second conductive layer include a first power and ground conductor pair arranged side-by-side at the first bump and a second power and ground conductor pair arranged side-by-side at the second bump. In some embodiments, the first bump and the second bump are spaced apart from each other by a bump pitch, and the combined width of the power and ground conductors of the first power and ground conductor pair is approximately 10% or more of the bump pitch. In some embodiments, the combined width is approximately 15% or more of the bump pitch. In some embodiments, among a plurality of ground conductors, the ground conductor in the first conductive layer perpendicularly overlaps the ground conductor in the second conductive layer. In some embodiments, the integrated circuit device further includes a via structure located between the ground conductors in the first conductive layer and the second conductive layer, wherein the ground conductor in the first conductive layer perpendicularly overlaps the ground conductor in the second conductive layer. In some embodiments, each signal conductor in the first conductive layer and the second conductive layer located in the region between the first bump and the second bump completely perpendicularly overlaps with the ground conductor in each of the first conductive layer and the second conductive layer in a first direction. In some embodiments, the interconnect includes a first through-silicon via (TSV) and a second TSV spaced apart in a first direction, and a first conductive layer and a second conductive layer include a first power and ground conductor pair arranged side-by-side at the first TSV and a second power and ground conductor pair arranged side-by-side at the second TSV. In some embodiments, all signal conductors in the first conductive layer and the second conductive layer between the first TSV and the second TSV are located between corresponding ground conductor pairs in the respective conductive layers, and the ground conductor pairs are continuously coupled from the first TSV to the second TSV within the first conductive layer and the second conductive layer. In some embodiments, the interconnect is bonded to a die and a second die, and at least some of the signal conductors are configured to couple signals between the die and the second die.

[0157] In some embodiments, the integrated circuit device includes: a die; an interconnect that at least partially overlaps with the die; and a plurality of bumps located in the region where the interconnect overlaps with the die, wherein: the interconnect includes at least a first conductive layer and a second conductive layer, the plurality of bumps includes at least a first bump and a second bump spaced apart in a first direction, each of the first conductive layer and the second conductive layer includes a signal conductor and a ground conductor located in the region between the first bump and the second bump, and each signal conductor in each of the first conductive layer and the second conductive layer in the region between the first bump and the second bump completely perpendicularly overlaps with the ground conductor in one of the first conductive layer or the second conductive layer in the first direction.

[0158] In some embodiments, the interconnect includes a first through-silicon via (TSV) and a second TSV spaced apart in a first direction, and a first conductive layer and a second conductive layer include a first power and ground conductor pair arranged side-by-side at the first TSV and a second power and ground conductor pair arranged side-by-side at the second TSV. In some embodiments, signal conductors in the first and second conductive layers between the first and second TSVs are located between ground conductor pairs in the respective conductive layers, and the ground conductor pairs are continuously coupled from the first TSV to the second TSV. In some embodiments, the first and second bumps are spaced apart from each other by a bump pitch, and the combined width of the power and ground conductors of the first power and ground conductor pair is approximately 10% or more of the bump pitch. In some embodiments, the combined width is approximately 15% or more of the bump pitch. In some embodiments, the first and second TSVs are spaced apart by approximately twice the bump pitch. In some embodiments, the interconnect includes a third TSV, a second TSV located between the first TSV and the third TSV, a first conductive layer and a second conductive layer including a third power and ground conductor pair arranged side-by-side at the third TSV, the first TSV and the third TSV being coupled to one of the power conductors or ground conductors in the respective first power and ground conductor pair and the third power and ground conductor pair, and the second TSV being coupled to the other of the power conductors or ground conductors in the second power and ground conductor pair. In some embodiments, the interconnect includes a first active circuit perpendicularly overlapping the first power and ground conductor pair and a second active circuit perpendicularly overlapping the second power and ground conductor pair.

[0159] In some embodiments, a method of manufacturing an integrated circuit device includes: forming an interconnect comprising at least a first conductive layer and a second conductive layer, wherein: the first conductive layer and the second conductive layer of forming the interconnect include forming a plurality of signal conductors between a first bump location for a first bump and a second bump location for a second bump, and forming a plurality of ground conductors between the first bump location and the second bump location; forming the plurality of signal conductors and the plurality of ground conductors includes forming each of the plurality of signal conductors between a corresponding pair of ground conductors in a respective conductive layer; and forming the plurality of ground conductors includes continuously coupling the plurality of ground conductors in each of the first conductive layer and the second conductive layer from a first side of the plurality of signal conductors to a second side of the plurality of signal conductors; and mounting a die to the interconnect using a plurality of bumps, the plurality of bumps including a first bump and a second bump, in a region where the interconnect overlaps with a die.

[0160] In some embodiments, forming a plurality of grounding conductors includes: forming grounding conductors in a first conductive layer to perpendicularly overlap with grounding conductors in a second conductive layer, and forming a via structure between the grounding conductors in the first conductive layer and the second conductive layer, wherein the grounding conductors in the first conductive layer and the grounding conductors in the second conductive layer perpendicularly overlap.

[0161] In some embodiments, the semiconductor device includes: a first die and a second die; and an interconnect structure located below the first and second dies, wherein the interconnect structure includes: a plurality of first ground lines extending along a first direction; a plurality of first signal lines extending along the first direction, wherein the first ground lines and the first signal lines are alternately arranged along a second direction; and a plurality of second ground lines extending along the first direction below the first ground lines and the first signal lines, wherein the first and second ground lines are coupled together and alternately arranged along the second direction.

[0162] In some embodiments, the semiconductor device includes: a first die and a second die spaced apart along an X-axis direction; and an interconnect structure coupling a signal and / or a reference voltage between the first and second dies, wherein the interconnect structure includes: a plurality of first ground lines spaced apart along an X-axis direction in a first conductive layer; a plurality of first signal lines in the first conductive layer, located in the space between the first ground lines such that the first ground lines and the signal lines alternate along the X-axis direction; and a plurality of second ground lines spaced apart along an X-axis direction in a second conductive layer.

[0163] In some embodiments, the first and second ground wires are coupled together to form a continuous ground wire. In some embodiments, all first signal lines are located between the outermost ground wires forming the continuous ground wire. In some embodiments, two metal layers Mz, such as the two uppermost metal layers, are used for signal routing.

[0164] In some embodiments, in the first and second grounding wires, the first grounding wire in the first conductive layer is closest to the first and second dies, the first conductive layer is located between the second conductive layer and the first and second dies, and the first conductive layer is spaced apart from the second conductive layer in a third-direction orientation. In some embodiments, the first grounding wire and the second grounding wire overlap vertically, and the first grounding wire is coupled to the second grounding wire through a via.

[0165] In some embodiments, one or more through-silicon vias (TSVs) are coupled to one or more ground lines and / or one or more signal lines, and extend along a third direction away from the signal lines away from the first and second dies.

[0166] In some embodiments, multiple TSVs are arranged alternately along a second direction.

[0167] In some embodiments, the conductive layer Mn located directly beneath the two Mz layers is thinner in the third direction than either the first or second conductive layer beneath the two Mz layers.

[0168] As used herein, although terms such as “first,” “second,” and “third” describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Unless the context clearly indicates otherwise, the terms “first,” “second,” and “third,” as used herein, do not imply order or sequence.

[0169] While the numerical ranges and parameters illustrating the broad scope of this disclosure are approximations, the values ​​illustrated in the specific examples are reported as precisely as possible. However, any numerical value inherently contains some errors, which are necessarily caused by the standard deviation found in the corresponding test measurement. Furthermore, as used herein, the terms “substantially,” “about,” and “approximately” generally mean a value or range that can be considered by a person skilled in the art. Alternatively, the terms “substantially,” “about,” and “approximately” mean within an acceptable standard error of the mean when considered by a person skilled in the art. Those skilled in the art will understand that acceptable standard errors may vary depending on the technology. Except in the operational / working examples, or unless expressly stated otherwise, all numerical ranges, quantities, values, and percentages disclosed herein, such as material quantity, duration, temperature, operating conditions, quantity ratios, etc., should in all cases be understood as “substantially,” “about,” and “approximately.” Therefore, unless otherwise stated, the numerical parameters set forth in this disclosure and the appended claims are approximations that can vary as needed. At a minimum, each numerical parameter should be interpreted based at least on the number of significant figures reported and by applying common rounding techniques. A range herein may be expressed as from one endpoint to another or between two endpoints. Unless otherwise stated, all scopes disclosed herein include endpoints.

[0170] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. An integrated circuit device, comprising: Core; The interconnecting element at least partially overlaps with the die; as well as Multiple bumps are located in the region where the interconnect overlaps with the die, wherein: The interconnect includes at least a first conductive layer and a second conductive layer. The plurality of bumps includes a first bump and a second bump spaced apart along a first direction. Each of the first conductive layer and the second conductive layer includes a plurality of signal conductors located between the first bump and the second bump, and a plurality of ground conductors located between the first bump and the second bump. All the signal conductors in each of the first and second conductive layers between the first and second bumps are located between corresponding ground conductor pairs in the respective conductive layers, and the ground conductor pairs are continuously coupled from a first side of the plurality of signal conductors to a second side of the plurality of signal conductors within the first and second conductive layers.

2. The integrated circuit device according to claim 1, wherein: The first conductive layer and the second conductive layer include a first power supply and ground conductor pair arranged side by side at the first bump and a second power supply and ground conductor pair arranged side by side at the second bump.

3. The integrated circuit device according to claim 2, wherein: The first bump and the second bump are spaced apart from each other by a bump pitch, and The combined width of the power supply and grounding conductors of the first power supply and grounding conductor pair is approximately 10% or more of the bump pitch.

4. The integrated circuit device according to claim 1, wherein: Among the plurality of grounding conductors, the grounding conductor in the first conductive layer overlaps perpendicularly with the grounding conductor in the second conductive layer.

5. The integrated circuit device according to claim 4, further comprising: A through-hole structure is located between the ground conductors in the first conductive layer and the second conductive layer, wherein the ground conductors in the first conductive layer and the ground conductors in the second conductive layer overlap perpendicularly.

6. The integrated circuit device according to claim 4, wherein: Each signal conductor in the first conductive layer and the second conductive layer, located in the region between the first bump and the second bump, completely and perpendicularly overlaps with the ground conductor in each of the first conductive layer and the second conductive layer in a first direction.

7. The integrated circuit device according to claim 1, wherein: The interconnect includes a first through-silicon via and a second through-silicon via spaced apart in the first direction, and The first conductive layer and the second conductive layer include a first power and ground conductor pair arranged side by side at the first through-silicon via and a second power and ground conductor pair arranged side by side at the second through-silicon via.

8. The integrated circuit device according to claim 7, wherein: All the signal conductors in the first and second conductive layers between the first and second through-silicon vias are located between corresponding ground conductor pairs in the respective conductive layers, and the ground conductor pairs are continuously coupled from the first through-silicon via to the second through-silicon via within the first and second conductive layers.

9. An integrated circuit device, comprising: Core; The interconnecting element at least partially overlaps with the die; as well as Multiple bumps are located in the region where the interconnect overlaps with the die, wherein: The interconnect includes at least a first conductive layer and a second conductive layer. The plurality of bumps includes at least a first bump and a second bump spaced apart in a first direction. Each of the first conductive layer and the second conductive layer includes a signal conductor and a ground conductor located in the region between the first bump and the second bump, and In the region between the first bump and the second bump, each signal conductor in each of the first and second conductive layers completely and perpendicularly overlaps with a ground conductor in one of the first or second conductive layers in the first direction.

10. A method for manufacturing an integrated circuit device, the method comprising: An interconnect comprising at least a first conductive layer and a second conductive layer is formed, wherein: the first conductive layer and the second conductive layer forming the interconnect include forming a plurality of signal conductors between a first bump location for a first bump and a second bump location for a second bump, and forming a plurality of ground conductors between the first bump location and the second bump location; forming the plurality of signal conductors and the plurality of ground conductors includes forming each of the plurality of signal conductors between a corresponding pair of ground conductors in a corresponding conductive layer; and forming the plurality of ground conductors includes continuously coupling the plurality of ground conductors in each of the first conductive layer and the second conductive layer from a first side of the plurality of signal conductors to a second side of the plurality of signal conductors; and In the region where the interconnect overlaps with the die, a plurality of bumps are used to mount the die to the interconnect, the plurality of bumps including a first bump and a second bump.

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