Fabrication plant compatible ultra-low resistance under bump metallization for electroplated bumps

Abstract

A semiconductor structure comprising: a semiconductor base substrate; a barrier layer disposed on the substrate; an electroplated seed layer disposed on the barrier layer; wherein the barrier layer is configured to mitigate atomic diffusion from the seed layer to the substrate; a cap layer disposed on the seed layer and configured to resist oxidation of the seed layer; and a solder bump disposed on the cap layer.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor fabrication. Specific embodiments relate to a semiconductor structure, a semiconductor system, and a method for fabricating the same. Background Technology

[0002] 3D heterogeneous integration offers a viable path to building large-scale integrated systems, such as quantum computers. One of the key requirements for this realization is the development of superconducting bumps, which are crucial for bonding multiple chips together, routing signals between chips, and electrically connecting different ground planes of chips to minimize crosstalk. Indium (In), a flexible superconducting metal, has become a popular choice for bump materials in low-temperature applications. However, depending on the deposition or growth techniques used, the fabrication of indium presents some challenges.

[0003] To date, most demonstrations of indium bumps have focused on lift-off processes, in which indium is evaporated and patterned onto a bump-under metallization (UBM) layer on top of the superconducting material that forms the quantum circuit. The UBM is needed to prevent indium from forming an intermetallic compound (IMC) with the quantum circuit material. These UBM layers, patterned using evaporation and lift-off techniques, also facilitate indium adhesion. The main advantages of lift-off techniques are ease of fabrication and the versatility of material choices for experimenting with UBM layers without concern for the etching selectivity of different materials.

[0004] However, in semiconductor foundry manufacturing, stripping is avoided, and subtractive etching (wet / dry) is the preferred method for patterning metal layers. Electrochemical deposition (ECD) is the technology of choice for growing / depositing solder bump material on a seed layer. The seed layer is a low-resistivity material that provides the necessary conduction path for current during the bump solder plating process. Typically, in standard semiconductor foundry processing of semiconductor integrated circuits, copper (Cu) is the preferred seed material in the plating process. For superconducting bump applications, indium plating is the preferred material choice. However, copper is a non-superconducting material and is known to form IMC with indium, potentially leading to losses in bump stacks in low-temperature applications such as superconducting or quantum applications. Plating indium or any other suitable bump material directly on the superconducting material acting as the seed layer presents another challenge: these superconducting materials typically have extremely high resistivity and form native oxides at room temperature. Therefore, this can lead to failure to plating or result in uneven plating on the wafer during ECD processes at room temperature or other known temperatures.

[0005] Rosenberg, D. et al., 3D integrated superconducting qubits, npj Quantum Inf 3, 42 (2017) (Nature Collaboration Journal) Quantum Information, Volume 3, Article 42, 2017 (hereinafter referred to as the "MIT approach") describes an indium bump under-ubiquitous membrane (UBM) consisting of Ti (20 nm) / Pt (50 nm) / Au (100 nm). The resistance of the described bump stack is approximately 240 nanoohms / bump at the operating temperature. The UBM layer and indium bumps are fabricated using an evaporation and stripping process.

[0006] Yu, J. et al., Indium-Based Flip-Chip Interconnection by Electroplating Method for Superconducting Quantum 3D Integration Architecture, IEEE Electron Device Lett. 45, 2021–2024 (2024), describes an indium-plated bump with copper as a seed layer. However, this bump is not superconducting, suggesting that IMC may hinder this. This is shown in the critical temperature (Tc) measurement plot in the paper. However, the paper does not mention the effect of IMC on superconductivity. Summary of the Invention

[0007] Building large-scale integrated semiconductor systems (such as, for example, quantum computers using solid-state qubits such as superconducting qubits) requires functionality that can be enabled through heterogeneous 3D integration used in today's computing devices. One key element of this expansion path is the development of superconducting bumps, which are used to electrically connect different dies in a 3D stack. In advanced foundry semiconductor manufacturing processes employing techniques such as thermoforming bonding, ECD (electrode plated), for example, is a preferred method for bump growth. The plating or deposition process may require a seed material, typically a low-resistivity material such as copper (Cu), which provides a high-conductivity path for the plating current during processing, thus ensuring uniform bump plating on the wafer. In the case of indium (In, a superconducting soft metal), it is known to form an intermetallic compound (IMC) with copper. This formed IMC interface can increase losses in the bumps, thus limiting their current-carrying capacity and causing decoherence of qubits, for example, in exemplary quantum computing devices.

[0008] The purpose of this disclosure is to provide an under-bump metallization layer in a semiconductor foundry-compatible scenario that allows for the fabrication of ultra-low resistance, IMC-free, uniform bumps on semiconductor wafers (e.g., 300 mm wafers). The ultra-low resistance must be achieved under cryogenic or superconducting operating conditions, which may differ from the fabrication conditions of UBM. Note that embodiments according to this disclosure are not necessarily limited to superconducting quantum applications.

[0009] According to certain exemplary embodiments of this disclosure, the formation of IMC is avoided by introducing a capping material on top of the seed layer. Bumps can be electroplated over this capping material without compromising the high conductivity and uniformity required for the electroplating process. Although the seed layer material is non-superconductor, it is still possible, according to certain exemplary embodiments of this disclosure, to make the seed layer approach superconductivity and ensure a fully superconducting bump stack. This integrated structure can be applied to foundry-compatible processes to fabricate ultra-low resistance (potentially superconducting) UBMs and associated bumps for quantum computing and / or other cryogenic applications.

[0010] Unlike the "MIT method" of the prior art described above, according to certain exemplary embodiments of this disclosure, UBM can be prepared using sputtered materials and indium can be electroplated using a resist mask. The UBM layer can be etched using a subtractive technique.

[0011] The embodiments according to this disclosure are intended to solve at least some of the problems described above.

[0012] Therefore, the first aspect of this disclosure provides a semiconductor structure, comprising: Semiconductor substrate; A barrier layer disposed on a substrate; A seed layer disposed on the barrier layer; The barrier layer is configured to mitigate atomic diffusion from the seed layer to the substrate; A capping layer disposed on the seed layer and configured to resist oxidation of the seed layer; and Solder bumps are set on the capping layer.

[0013] This solution can help improve wafer uniformity of bumps from the wafer center to the edge without forming IMC between the seed layer and the bump material.

[0014] Barrier layers can be used to protect semiconductor substrates (e.g., those containing semiconductor circuits, especially quantum circuits) from further processing steps. Furthermore, barrier layers can improve the adhesion of seed layers compared to seed layers directly disposed on the substrate.

[0015] Note that, in the sense that a solder bump is a part of a structure designed to couple with an external conductor (such as an external conductor present on another die in a heterogeneous system), a solder bump can also be referred to as an electrode.

[0016] The substrate may preferably be a semiconductor substrate (e.g., a silicon substrate), or a substrate on which quantum circuitry is disposed.

[0017] The substrate may preferably include a conductive pattern made of a material configured to be superconducting at a critical temperature threshold to achieve superconductivity in operation.

[0018] The capping layer can preferably be deposited in situ.

[0019] Capping layers can also be used to mitigate or even completely prevent the formation of IMC during processing and / or bonding.

[0020] Note that the statement "A is set on B" should be understood as A being set on top of B and in physical contact with B.

[0021] In one embodiment, the barrier layer is made of a material configured to have superconductivity at a critical temperature threshold.

[0022] In one embodiment, the capping layer is made of a material configured to have superconductivity at a critical temperature threshold.

[0023] In one embodiment, the capping layer is made of an antioxidant material.

[0024] In one embodiment, the seed layer is made of a metallic material with a sheet resistance of less than 0.3 Ohm / sq at any suitable temperature during room temperature or electroplating process.

[0025] The physical parameter “thin sheet resistance” does not have a standardized International System of Units (SI) unit, but the academic and industrial communities generally use Ohm / sq as the recognized unit.

[0026] In one embodiment, the seed layer comprises any one or more of the following materials: copper (Cu), aluminum (Al), silver (Ag), ruthenium (Ru), and molybdenum (Mo).

[0027] If the seed layer is made of pure elements, its conductivity is superior to that of an alloy. Alloys of the above materials are also possible, and are included within the scope of protection of this embodiment by the word "made of".

[0028] Some of the listed materials (such as copper and silver) are not superconducting. However, they may be acceptable in certain superconducting scenarios due to their sufficiently low resistance.

[0029] In one embodiment, the barrier layer comprises any one or more of the following materials: titanium nitride (TiN) and tantalum nitride (TaN).

[0030] In one embodiment, the solder bump is made of a material configured to have superconductivity at a critical temperature threshold, and wherein the solder bump is preferably made of indium or an indium-tin alloy.

[0031] Solder bumps are preferably made of indium because indium is a material configured to exhibit superconductivity below a critical temperature threshold. Furthermore, indium is also an excellent soldering material.

[0032] In one embodiment, the capping layer comprises any one or more of the following materials: TiN, TaN, and Ru.

[0033] In one embodiment, the barrier layer has a thickness in the range of 50-100 nm; and / or the seed layer has a thickness in the range of 25-100 nm; and / or the capping layer has a thickness in the range of 10-50 nm; and / or the solder bump has a thickness in the range of 5-15 μm; wherein each of the above thicknesses is measured in the direction from the solder bump to the portion of the substrate closest to the solder bump.

[0034] In a second aspect of this disclosure, a semiconductor system is provided, comprising: The first semiconductor structure according to any of the preceding claims; and The second semiconductor structure according to any of the preceding claims; and The solder bumps of the first semiconductor structure also serve as solder bumps of the second semiconductor structure; and From the perspective of the solder bumps they share, the first semiconductor structure and the second semiconductor structure are preferably arranged relative to each other in diameter.

[0035] It should be clarified that after the first semiconductor structure and the second semiconductor structure are bonded, a semiconductor system is formed, wherein the solder bumps of the two semiconductor structures can be regarded as a single solder bump. Therefore, the solder bumps of the two semiconductor structures serve a common purpose and can be considered as a single solder bump. The scope of protection of the claims includes the following two situations: each of the two semiconductor structures has its own solder bump before bonding, and after bonding, their respective solder bumps are combined to form a single solder bump. The scope of protection also includes the following situation: only one of the two semiconductor structures to be bonded has a solder bump according to the first aspect of the invention. The second semiconductor structure does not have a solder bump before bonding. However, after bonding, the second semiconductor structure does fall within the scope of protection of the first aspect of the invention because the solder bumps of the opposing semiconductor structures now become a common solder bump, as in the second aspect of the invention. A semiconductor structure that does not have a solder bump before bonding must have a barrier layer, a seed layer, and a capping layer before bonding to ensure that the features of the claims corresponding to the second embodiment are satisfied.

[0036] In a third aspect of this disclosure, a method for producing a semiconductor structure is provided, the method comprising: Provide semiconductor substrates; A barrier layer is formed on a substrate, wherein the barrier layer is configured to block atomic diffusion from the seed layer to the substrate; A seed layer is formed on the barrier layer; A capping layer is formed on the seed layer, wherein the capping layer is configured to resist oxidation of the seed layer; and Solder bumps are formed on the capping layer.

[0037] In one embodiment, the method includes removing any oxides from the capping layer prior to the step of forming solder bumps.

[0038] In a fourth aspect of this disclosure, a method for manufacturing a semiconductor system is provided, the method comprising: Production of the first semiconductor structure according to any one of claims 12-13; and To produce the second semiconductor structure according to any one of claims 12-13; The solder bump of the first semiconductor structure also serves as the solder bump of the second semiconductor structure; and from the perspective of the solder bump they share, the first semiconductor structure and the second semiconductor structure are preferably arranged relative to each other on a diameter.

[0039] The method according to the fourth aspect covers two scenarios: both semiconductors have solder bumps before bonding; and it also covers the scenario where only one semiconductor has solder bumps before bonding, while the other does not. In the latter scenario, the step of "forming solder bumps on the capping layer" in the third embodiment can be considered as the bonding process. Therefore, the solder bumps of the first semiconductor that exist before bonding and are prepared in the "providing" step of the first semiconductor can be considered as solder bumps used in the second semiconductor structure. Therefore, the scope of protection of the claims related to the fourth aspect covers both scenarios.

[0040] Those skilled in the art will understand that various specific features, advantages, and technical considerations applicable to the above embodiments of the electronic structures according to this disclosure, after necessary modifications, are also applicable to the method embodiments. Specifically, any structural embodiment described above or below in this disclosure will be understood by those skilled in the art to have or potentially have a corresponding method embodiment, and vice versa. Attached Figure Description

[0041] The above embodiments are presented in an illustrative rather than restrictive manner. Those skilled in the art will gain a more complete understanding of the invention with the aid of the accompanying drawings, in which: Figure 1A cross-sectional view of a prior art bump is shown, in which bump material (indium) is electroplated onto a seed layer (copper), forming an IMC. Due to the formation of the IMC, the solder bump is consumed, and the lateral dimensions decrease.

[0042] Figure 2 Some exemplary embodiments of semiconductor structures according to this disclosure are shown.

[0043] Figure 3 Some exemplary embodiments according to this disclosure are shown, illustrating the integration of bumps on the top of a superconducting material according to a third aspect of the invention.

[0044] Figure 4 Two exemplary embodiments according to the present disclosure are shown, illustrating a method for producing a semiconductor structure according to the present disclosure. Detailed Implementation

[0045] It will be understood that the following detailed description is intended to be illustrative only, and the scope of protection of the invention shall be determined by the appended claims.

[0046] Figure 1 A cross-sectional view of a prior art bump is shown, in which bump material (6) (indium) is electroplated on a seed layer (4) (copper), thereby forming an IMC (7). This IMC can lead to increased losses in the bump stack, which can limit the current-carrying capacity of the bump when used to connect signal lines in quantum circuits.

[0047] To alleviate this problem, according to exemplary embodiments of this disclosure, a capping material (5) (preferably superconducting) is employed (see Figure 2 It prevents the formation of IMC (7) between the (indium) bump material (6) and the seed layer (4) (copper). The capping layer (5) does not compromise the high conductivity required for bump plating because the resistance of the capping layer (5) is in parallel with that of the seed layer (4). The conductivity of the three-layer stack is still dominated by the seed layer (4), thus ensuring the uniformity of the plating process. Figure 3 One scenario is shown where two quantum chips are bonded using bumps, and arrows indicate the superconducting path.

[0048] Figure 1 The diagram shows bumps directly disposed on top of the seed layer (4) in the prior art. It shows that the bumps and the seed material form an IMC (7). This can result in a lossy interface in the bump stack.

[0049] Figure 2 Some embodiments according to this disclosure are shown, wherein a highly conductive capping material (5) (preferably superconducting) is introduced, which prevents the formation of IMC and is also used to bring the seed material closer to superconductivity.

[0050] Figure 3 A cross-section of a device in which bumps are fabricated on a suitable superconducting material using the proposed invention is shown. The bumps are part of a signal line connecting the bottom and top structures according to a second aspect of this disclosure. This signal path has ultra-low resistance (potential superconductivity) during operation.

[0051] In other words, Figure 3 The illustration shows certain exemplary embodiments according to a second aspect of this disclosure, illustrating the integration of bumps on top of a superconducting material, thus forming a semiconductor system. Two semiconductor structures, dies, chips, or equivalents (bottom and top) may each have superconducting circuitry (e.g., quantum circuitry), using the claimed and... Figure 4 The bumps shown are bonded together using the same fabrication process. After the electroplating process, the cap (5), seed (4), and barrier (3) materials are selectively etched relative to the other circuit materials.

[0052] One advantage of the solution according to this disclosure is the possibility of using proximity-induced superconductivity. It is possible to make the seed layer (4) approach superconductivity by selecting appropriate superconducting materials for the barrier layer and the capping layer. Thus, fully superconducting bump connections can be achieved even if the seed layer (4) is a non-superconducting metal. This functionality will make the integration of such devices simpler without introducing potentially detrimental interfaces (such as IMC (7)).

[0053] Examples of different layers and their corresponding functions / characteristics are presented below. Materials can be selected accordingly.

[0054] The barrier layer (3) can act as a barrier layer between the seed layer and the substrate (1). The substrate can also contain a circuit (2), which can be a superconducting circuit, a low-temperature circuit, or a quantum circuit. Therefore, the barrier layer (3) can also protect any circuit (2) that may exist as part of the substrate (1) during further processing. The barrier layer (3) can also act as an adhesive layer between the seed layer and the substrate. The barrier layer is located between the outer layer of the substrate (1) (or the outer layer of the circuit (2) if present) and the seed layer (4).

[0055] Ideally, the barrier layer is superconducting with a high critical temperature (Tc), has good adhesion to silicon (Si), and / or can be selectively etched relative to the exposed material.

[0056] The barrier layer may comprise TiN or TaN, or alternatively, a stacked combination of TiN and TaN. Those skilled in the art will recognize that other materials or their stacked structures configured to mitigate atomic diffusion from the seed layer (4) to the substrate are also possible and are included within the scope of the independent claims.

[0057] The seed layer (4) can be used in ECD, i.e., electroplating process, and / or can help ensure electroplating uniformity.

[0058] Ideally, the seed layer has high conductivity, can be a superconductor (ruthenium, denoted as Ru), has a resistivity comparable to copper at room temperature, has good adhesion to the barrier layer, is preferably deposited in situ with the barrier layer, is thin enough to achieve uniform electroplating, and / or can be selectively etched relative to the barrier layer and other exposed materials during the etching process.

[0059] The capping layer (5) can help minimize or completely prevent the formation of IMC (7) between the bump (6) and the seed layer (4).

[0060] Ideally, the capping layer is superconducting and preferably has a high Tc, is free from natural oxidation, can be plated with bump material (indium), does not form IMC (7) with the bump material (indium), is thin, preferably can be deposited in situ with the barrier layer (3) and the seed layer, and / or can be selectively etched relative to the seed layer and any other exposed material during etching.

Claims

1. A semiconductor structure, comprising: Semiconductor substrate (1); A barrier layer (3) is disposed on the substrate (1); Seed layer (4) disposed on the barrier layer (3); The barrier layer (3) is configured to mitigate atomic diffusion from the seed layer (4) to the substrate (1); A capping layer (5) disposed on the seed layer (4) and configured to resist oxidation of the seed layer (4); and Solder bumps (6) are provided on the capping layer (5).

2. The semiconductor structure according to claim 1, characterized in that, The barrier layer (3) is made of a material configured to be superconducting at a critical temperature threshold.

3. The semiconductor structure according to any of the preceding claims, characterized in that, The capping layer (5) is made of a material configured to be superconducting at a critical temperature threshold.

4. The semiconductor structure according to any of the preceding claims, characterized in that, The capping layer (5) is made of an antioxidant material.

5. The semiconductor structure according to any of the preceding claims, characterized in that, The seed layer (4) is made of a metallic material with a thin-film resistivity of less than 0.3 Ohm / sq.

6. The semiconductor structure according to any of the preceding claims, characterized in that, The seed layer (4) comprises any one or more of the following materials: Cu, Al, Ag, Ru, and Mo.

7. The semiconductor structure according to any of the preceding claims, characterized in that, The barrier layer (3) comprises any one or more of the following materials: TiN and TaN.

8. The semiconductor structure according to any of the preceding claims, characterized in that, The capping layer (5) comprises any one or more of the following materials: TiN, TaN, and Ru.

9. The semiconductor structure according to any of the preceding claims, characterized in that, The solder bump (6) is made of a material configured to have superconductivity at a critical temperature threshold, and the solder bump (6) is preferably made of indium or an indium-tin alloy.

10. The semiconductor structure according to any of the preceding claims, characterized in that: The barrier layer (3) has a thickness in the range of 50-100 nm; and / or The seed layer (4) has a thickness in the range of 50-100 nm; and / or The capping layer (5) has a thickness in the range of 25-50 nm; and / or The solder bump (6) has a thickness in the range of 5-15 µm; Each of the thicknesses is measured in the direction from the solder bump (6) to the portion of the substrate (1) closest to the solder bump.

11. A semiconductor system, comprising: The first semiconductor structure according to any of the preceding claims; as well as The second semiconductor structure according to any of the preceding claims; as well as The solder bump of the first semiconductor structure also serves as the solder bump (6) of the second semiconductor structure; and From the perspective of the solder bumps they share, the first semiconductor structure and the second semiconductor structure are preferably arranged relative to each other in diameter.

12. A method for producing a semiconductor structure, the method comprising: Provide semiconductor substrate (1); A barrier layer (3) is formed on the substrate, wherein the barrier layer (3) is configured to block atomic diffusion from the seed layer (4) to the substrate; A seed layer is formed on the barrier layer (4); A capping layer (5) is formed on the seed layer, wherein the capping layer (5) is configured to resist oxidation of the seed layer (4); and Solder bumps (6) are formed on the capping layer.

13. The method according to claim 12, characterized in that, Before the step of forming the solder bumps (6), any oxides are removed from the capping layer (5).

14. A method for manufacturing a semiconductor system, the method comprising: The first semiconductor structure is prepared using the method of claim 12 or 13; as well as The second semiconductor structure is prepared using the method of claim 12 or 13; The solder bump (6) of the first semiconductor structure also serves as the solder bump of the second semiconductor structure; and From the perspective of the solder bumps they share, the first semiconductor structure and the second semiconductor structure are preferably arranged relative to each other in diameter.

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