Semiconductor device and method of fabricating a double-sided molded system in package with high components and patterning electronic strips

Abstract

Semiconductor devices and methods of fabricating a double-sided molded system in package with high components and patterned electronic strips are provided. The semiconductor device has a substrate. An opening is formed through the substrate. An insulating film is laminated onto a first surface of the substrate. A first electrical component is disposed on the insulating film in the opening. A second electrical component is disposed on a second surface of the substrate opposite the first surface. A first encapsulant is deposited over the first electrical component and the second electrical component. The insulating film is removed. A third electrical component is disposed over the first surface of the substrate. An electronic strip is disposed on the first surface of the substrate. A second encapsulant is deposited over the third electrical component and the electronic strip.

Description

Technical Field

[0001] This invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods for fabricating double-sided molded system-in-packages with high-component and patterned electronic bars (e-bars). Background Technology

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide variety of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electricity, and creating visual images for television displays. Semiconductor devices are used in communications, power conversion, networking, computers, entertainment, and consumer products. They are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0003] Semiconductor device manufacturers are continuously striving to create smaller semiconductor devices to meet the needs of both electronics manufacturers and consumers. Simultaneously, increasingly complex semiconductor devices are being demanded by device manufacturers. Portable devices require larger batteries to maintain real-time responsiveness. Larger batteries, in turn, require larger inductors and capacitors, which are typically housed as discrete components within the electronics along with semiconductor packages used to control battery charging and discharging.

[0004] In recent years, large inductors and capacitors have been moved into system-in-package (SiP) modules instead of being used as discrete components, which helps reduce the total footprint required in electronic devices. However, placing large capacitors and inductors in SiP modules increases the package height and introduces other problems. Therefore, there is a need for methods for fabricating semiconductor devices and double-sided molded SiPs with high-construction and patterned electronic strips. Attached Figure Description

[0005] Figures 1a-1c The illustration shows a semiconductor wafer with multiple semiconductor dies separated by saw marks; Figure 2a-2k The illustration shows the formation of a double-sided molded system-in-package with high-performance components; Figures 3a-3d The diagram illustrates the alternative process flow; Figures 4a-4h The illustration shows the use of patterned electronic strips; and Figure 5a and 5b The illustration shows an electronic device with a dual-sided molded system-in-package. Detailed Implementation

[0006] In the following description with reference to the accompanying drawings, the invention is described in one or more embodiments, and similar numerals in the drawings denote the same or similar elements. While the invention is described with respect to the best mode for carrying out the objectives of the invention, those skilled in the art will appreciate that the invention is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents (supported by the following disclosure and drawings). Features shown in the drawings are not necessarily drawn to scale. Elements assigned the same reference numerals in the drawings have similar functions and descriptions to each other. As used herein, the terms "semiconductor die" and "die" are synonymous and refer to both the singular and plural forms of the words, and therefore may refer to both a single semiconductor device and multiple semiconductor devices.

[0007] Semiconductor devices are generally manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves the formation of multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional electrical circuit. Active electrical components (such as transistors and diodes) have the ability to control the flow of electrical current. Passive electrical components (such as capacitors, inductors, and resistors) create the voltage-current relationship necessary for the electrical circuit to function.

[0008] Back-end manufacturing involves dicing or singulating finished wafers into individual semiconductor dies and packaging these dies for structural support, electrical interconnection, and environmental isolation. To singulate a semiconductor die, the wafer is scribed and diced along non-functional areas (known as serrations or scribing). The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor dies are placed on a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed on top of the semiconductor die are then connected to contact pads within the package. Electrical connections can be achieved using conductive layers, bumps, column bumps, conductive paste, or wirebonds. A sealant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system, making the functionality of the semiconductor device available to other system components.

[0009] Figure 1aA semiconductor wafer 100 with a substrate material 102 is shown, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials used for structural support. Multiple semiconductor dies or components 104, separated by non-active inter-die wafer regions or sawtooth 106, are formed on the wafer 100. The sawtooth 106 provides dicing regions to individualize the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0010] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or non-active surface 108 and an active surface 110, the active surface 110 containing analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuitry, such as digital signal processors (DSPs), application-specific integrated circuits (ASICs), memory, or other signal processing circuitry. The semiconductor die 104 may also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0011] A conductive layer 112 is formed over the active surface 110 using physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, electroless plating, or other suitable metal deposition processes. The conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 functions as contact pads that are electrically connected to circuitry on the active surface 110.

[0012] Conductive bump material is deposited on conductive layer 112 using evaporation, electroplating, electroless plating, drop balling, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed to form solder balls or bumps 114 by heating the material above its melting point. In one embodiment, bumps 114 are formed over under-bump metallization (UBM) having a wetting layer, a barrier layer, and an adhesive layer. Bumps 114 can also be compression bonded or thermocompressed bonded to conductive layer 112. Bumps 114 represent a type of interconnect structure that can be formed on conductive layer 112. Interconnect structures can also utilize bonded wiring, conductive paste, column bumps, microbumps, or other electrical interconnects.

[0013] exist Figure 1c In this process, a saw blade or laser cutting tool 118 is used to singulate the semiconductor wafer 100 into individual semiconductor dies 104 by cutting through the saw groove 106. After singulation, the individual semiconductor dies 104 can be inspected and electrically tested for identification of known qualified dies (KGD) or known qualified units (KGU).

[0014] Figure 2a-2k The illustration shows the process for forming a dual-sided molded system-in-package (DSmSiP) with high-performance components. Figure 2a A cross-sectional view of a multilayer interconnect substrate 120 is shown, which includes a conductive layer 122 and an insulating layer 124. While only a single substrate 120 suitable for forming a single semiconductor package is shown, hundreds or thousands of units are typically fabricated and processed as part of a single substrate 120 before being individualized, using the same steps described herein and performed in batches. Individual substrates 120 can also be used for each unit being fabricated, which is individualized prior to the steps shown herein, and multiple individual substrates are placed on a common carrier for processing.

[0015] The conductive layer 122 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layer 122 can be formed using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. The conductive layer 122 provides horizontal electrical interconnections across the substrate 120 and vertical electrical interconnections between the top surface 126 and the bottom surface 128 of the substrate 120. Depending on the design and function of the semiconductor die 104 and the formed DSmSiP, portions of the conductive layer 122 can be electrically connected or electrically isolated.

[0016] The insulating layer 124 comprises one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials with similar insulating and structural properties. The insulating layer can be formed using PVD, CVD, printing, lamination, spin coating, spraying, sintering, thermal oxidation, or other suitable processes. The insulating layer 124 provides isolation between the conductive layers 122. In other embodiments, any other suitable type of packaging substrate or lead frame is used for the substrate 120.

[0017] Region 130 of substrate 120 is reserved for use Figure 2b The subsequent formation of the opening 132. The occupied area of ​​region 130 typically (but not necessarily) remains without the conductive layer 122 to simplify the formation of the opening 132. The opening 132 is formed by laser ablation using laser 134. A focused laser beam from laser 134 ablates or vaporizes the material of substrate 120 to form the opening 132. In other embodiments, the opening 132 is formed by mechanical drilling, chemical or plasma etching, stamping, or another suitable process. The opening 132 is formed completely through substrate 120 (from surface 126 to surface 128).

[0018] exist Figure 2c and 2d In the middle, the insulating film 138 is laminated onto the bottom surface 128. Figure 2c It is a perspective view of an exemplary layout, and Figure 2d It is another local cross-section. Figure 2c The layout view shows: contact pad 122a, on which discrete components will be subsequently mounted; and region 122b, on which the semiconductor die 104 will be mounted. For illustration purposes, individual flip-chip pads are not shown in region 122b, and instead only the boundary of the region is shown. In practice, region 122b will have numerous contact pads (significantly smaller than contact pad 122a) suitable for flip-chip mounting the semiconductor die 104.

[0019] In some embodiments, the insulating film 138 is accompanied by a pre-applied pressure-sensitive adhesive or heat-activated adhesive, or a thin adhesive layer may be applied to the film or substrate 120 prior to lamination. Temporary or low-tack adhesives (e.g., heat-release or UV-release adhesives) are used to allow the film to be subsequently removed. The film 138 is at least large enough to cover the opening 132 and is typically as large as or slightly larger than the substrate 120. The material of the film 138 may be polyimide, polyester, polyolefin, PVC, solder mask film, temporary mask, or another suitable material. In other embodiments, the insulating film 138 may include a conductive material, such as copper foil.

[0020] exist Figure 2e In this process, semiconductor die 104, along with any other desired electrical components 140, is picked up and placed over substrate 120, and then mounted onto the substrate. Semiconductor die 104 is from... Figure 1c The semiconductor component 140 may be one of the semiconductor dies, or another semiconductor die with different functions but formed in a similar manner. Electrical component 140 may be a discrete active or passive electrical device, such as a diode, transistor, resistor, capacitor, or inductor. Electrical component 140 may include additional semiconductor dies, semiconductor packages, surface mount devices, RF components, discrete active or passive electrical devices, and may include integrated passive devices (IPDs). Component 140 is electrically and physically coupled to substrate 120 by reflowing solder paste 146 between terminals 148 and contact pads of conductive layer 124 while solder bumps 114 are reflowed to attach semiconductor die 104. Underfill may optionally be used under any component in the mounted component, as desired.

[0021] Electrical component 140 and semiconductor die 104 are mounted on top surface 126. Additionally, a higher component 150 (e.g., an inductor) is picked up and positioned above opening 132. Figure 2f In this embodiment, the higher component 150 is mounted onto an insulating film 138 within an opening 132. Terminals 148 of the higher component 150 are optionally embedded in the insulating film 138. In other embodiments, the higher component 150 has flat contact pads laid flat on the insulating film 138, with optional solder bumps that can be embedded in the insulating film 138.

[0022] The higher component 150 mounted in the opening 132 is typically an inductor or capacitor, but any electrical component can be placed in the opening. Generally, the opening 132 will only be used for components that are higher than those mounted directly on the surface 126 of the substrate 120. In this context, "higher" means higher than the highest component mounted on the top surface 126 of the substrate 120. In some embodiments, the higher component 150 in the opening 132 is 20%–50% higher than the highest component on the surface 126.

[0023] Compared to an alternative scenario where the higher component is mounted on surface 126, positioning the higher component 150 in the opening 132 lowers it so that the top surface of the higher component is approximately flush with the top surface of the component on surface 126. In some embodiments, the higher component 150 continues to extend significantly above the component on surface 126, but positioning it in the opening 132 still provides the benefit of reducing the overall package size. In other embodiments, the higher component 150 is only slightly higher than the component on surface 126, and positioning it in the opening 132 lowers the top of the higher component to a level significantly lower than the top of the component mounted on surface 126 compared to placing it on surface 126.

[0024] exist Figure 2g In this process, a sealant or molding compound 154 is deposited over a substrate 120, a semiconductor die 104, an electrical component 140, and a higher component 150. The sealant 154 extends into an opening 132 to completely seal the higher component 150. The sealant 154 is deposited using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable applicator. The sealant 154 can be a liquid or particulate polymer composite, such as an epoxy resin, epoxy acrylate, or another suitable polymer with or without fillers (e.g., silica).

[0025] Sealant 154 is non-conductive, provides structural support, and environmentally protects embedded electrical components from external elements and contaminants. For example... Figure 2g As shown, the resulting sealed assembly is characterized by a sealant 154 that forms a continuous protective coating that adheres to the substrate 120 and encapsulates the semiconductor die 104, electrical components 140, and higher components 150. This configuration shields the fragile structure from mechanical stress, thermal cycling, and environmental factors such as humidity or dust, thereby enhancing the reliability and lifespan of the semiconductor package.

[0026] exist Figure 2hIn this configuration, the substrate 120 and the sealed assembly are flipped so that the bottom surface 128 of the substrate 120 is available for processing. Any desired additional electrical components 160 are mounted onto surface 128. Electrical components 160 may include discrete active or passive components, chips, semiconductor packages, semiconductor dies, or any other type of electrical component. Additionally, one or more PCB strips or electronic strips 170 are mounted onto the substrate 120.

[0027] Electronic strips 170 are formed on a thin dielectric substrate or core 172 (such as a glass-reinforced epoxy laminate (e.g., FR-4) or a high-density interconnect (HDI) material). Subsequently, using laser drilling or mechanical drilling techniques, a series of micro-drilled holes are formed through the dielectric substrate, defining the locations of conductive vias 174. These vias are then plated with a conductive material (typically copper) via an electroplating process, thereby ensuring a continuous electrical path through the core 172.

[0028] Contact pads 176 are optionally plated above the top and bottom surfaces of the core 172 simultaneously with the plating of the via 174, or plated above the top and bottom surfaces of the core 172 in separate photolithography and etching processes. The resulting electronic strip 170 is a compact, rigid structure customized to specific packaging requirements, typically ranging in thickness from 0.1 mm to 1.0 mm. The size of the occupied area of ​​the electronic strip 170 can include any suitable length and width and does not need to be strictly rectangular in plan view. In some embodiments, the electronic strip 170 extends over the entire length or width of the substrate 120. In one embodiment, four electronic strips 170 are used to form the perimeter of the electronic strip around the substrate, wherein one of the electronic strips runs along each of the four sides of the unit substrate 120. A plurality of electronic strips 170 can be provided, wherein each of the plurality of electronic strips is provided along a different corresponding edge of the substrate 120.

[0029] As described above regarding the formation of solder bump 114, solder bump 178 is formed on contact pad 176 on one side of electronic strip 170. Electronic strip 170 is configured such that solder bump 178 is oriented toward substrate 120. Electronic strip 170a is mounted onto substrate 120 above higher component 150. Although not described in... Figure 2h As shown, however, electronic strip 170a is directly mounted to substrate 120 in other cross-sections. Electronic strip 170b is mounted to substrate 120 and may extend above other higher components 150 in other cross-sections. Figure 2iIn this process, solder bumps 178 are reflowed onto the contact pads of the conductive layer 122 to physically and electrically couple the electronic strip 170 to the substrate 120. Some solder bumps 178 are also reflowed onto the contact pads or terminals 148 of the higher component 150.

[0030] exist Figure 2j In this process, using any of the processes and materials described above for sealant 154, sealant 184 is deposited over electronic strip 170 and electrical component 160. Using film-assisted molding, sealant 184 is deposited so that it is coplanar with electronic strip 170. Component 160 has a lower height above substrate 120 than electronic strip 170 and is therefore completely covered by sealant 184. In other embodiments, component 160 has a surface exposed from or coplanar with sealant 184. In some embodiments, electronic strip 170 is covered by sealant 184 and an opening is subsequently formed through the sealant by back-grinding or by chemical etching, laser drilling, or another suitable process, exposing contact pad 176. Solder bumps 186 are formed on contact pad 176 as described above for bumps 114 on contact pad 112.

[0031] exist Figure 2k In this process, the substrate 120, sealants 154 and 184, and the panel of the sealed assembly are flipped so that the sealant 154 can be oriented upwards again or otherwise made available for processing. The large panels of multiple DSmSiP modules 190 are typically formed together and are subsequently monomerized through the substrate 120 and the sealants 154 and 184 to separate the DSmSiP modules from one another.

[0032] To address electromagnetic interference (EMI), radio frequency interference (RFI), harmonic distortion, and other inter-device interference, a shielding layer 192 may optionally be formed over the DSmSiP module 190. The shielding layer 192 may be formed by deposition, printing, sputtering, plating, or other methods. Plating may be performed using CVD, PVD, other sputtering methods, electroplating, electroless plating, or another suitable metal deposition process. The shielding layer 192 comprises one or more layers of Al, Cu, Sn, Ni, Au, Ag, stainless steel, or other suitable conductive materials.

[0033] Monomerization is performed through sealing layer 154, substrate 120, and sealing layer 184 to form individual DSmSiP modules 190 prior to the formation of shielding layer 192, allowing the shielding layer to be formed on the side surface of the DSmSiP module. The shielding layer 192, extending downward along the side surface of the DSmSiP module 190, helps protect against lateral incident EMI. In some embodiments, portions of conductive layer 122 are exposed on the side surface of substrate 120 to be physically and electrically connected to shielding layer 192, thereby grounding the shielding layer to improve performance.

[0034] Figure 2k The completed DSmSiP module 190 is shown, which uses an efficient packaging structure to achieve taller electrical components 150 within a shorter package than in the prior art. The taller components 150 are positioned within openings or trenches 132 in the substrate 120, reducing the overall package height.

[0035] Figures 3a-3d The diagram illustrates an alternative process flow, in which the bottom surface 128 of substrate 120 is processed before the top surface 126. Figure 3a In this configuration, substrate 120 already has a formed opening 132. The opening 132 can be formed from either side of substrate 120. As described above, electronic strip 170 and electrical components 160 are mounted onto surface 128. Electronic strip 170a extends above opening 132. As described above, in Figure 3b In this stage, sealant 184 is deposited. Solder bumps 186 are optionally formed.

[0036] exist Figure 3c In this process, the panel is flipped over, thus exposing surface 126 for processing. As described above, in Figure 3d In this configuration, electrical components 140, semiconductor dies 104, and higher-level components 150 are mounted. However, the higher-level components 150 are mounted directly onto the electronic strip 170a through opening 132, rather than being first mounted onto a separate insulating film as in the previous embodiments. As described above, sealant 154 and shielding layer 192 are formed to complete the DSmSiP module.

[0037] Figures 4a-4h The illustration shows the use of the patterned electronic strip 200. Figure 4a A cross-sectional view of the electronic strip 200 is shown. The electronic strip 200 is formed and structured similarly to the electronic strip 170 above. In the plan view, the electronic strip 200 has multiple rows and columns of conductive vias 174. Each conductive via 174 has a UBM or contact pad 176 at its top and bottom. Figure 4b and 4cIn this process, a conductive layer 202 is formed on one surface of the electronic strip 200. Figure 4b It is a cross-sectional view and Figure 4c This is a perspective view. The conductive layer 202 is formed of the material as described above for the other conductive layers and using the methods described above for the other conductive layers. The conductive layer 202 completely covers the electronic strip 200. Each conductive via 174 and contact pad 176 is electrically connected to each other through the conductive layer 202.

[0038] exist Figure 4d and 4e In this process, the conductive layer 202 is patterned to expose selected contact pads 176 in one or more openings 204. Again, Figure 4d It is the cross-section, and Figure 4e A perspective view is shown. The conductive layer 202 can be patterned using any suitable means, such as chemical etching, photolithography, routing, or laser ablation. In some embodiments, the contact pads 176 are formed of a different material or have a different coating than the conductive layer 202 to allow the conductive layer to be etched without removing the underlying contact pads. The conductive layer 202 is removed where the higher component 150 is expected to be mounted, while elsewhere it remains covering the electronics strip 200 as additional EMI shielding. Figure 4f and 4g An exemplary higher component 150 is illustrated, mounted to an electronic strip 200 in an opening 204 of conductive layer 202. Component 150 can be any desired electrical component, such as a combination of inductors, capacitors, and semiconductor sub-packages.

[0039] Figure 4h A DSmSiP module 210 with an electronic strip 200 is shown. The electronic strip 200 is mounted to a substrate 120 before being sealed with sealants 154 and 184, and a higher component 150 is located in an opening 132. In one embodiment, a conductive layer 202 is patterned on the electronic strip 200, but the electronic strip is disposed on the substrate 120 before the higher component 150 is attached. In this embodiment, Figure 2a-2k or Figures 3a-3d The process flow can be followed, and a conductive layer 202 is added as a patterned shielding layer. By extending the electronic strip 200 to the shielding layer or through the conductive layer 122 of the substrate 120, the conductive layer 202 can be electrically connected to the shielding layer 192.

[0040] Figure 5a and 5b The illustration shows the integration of the semiconductor package described above (e.g., DSmSiP module 190) into a larger electronic device 300. Figure 5aThe illustration shows a partial cross-section of a DSmSiP module 190 mounted on a printed circuit board (PCB) or other substrate 302 as part of an electronic device 300. Solder bumps 186 are reflowed onto the conductive layer 304 of the PCB 302 to physically attach the semiconductor package to the PCB and electrically connect the semiconductor package to the PCB. In other embodiments, thermal compression or another suitable attachment and connection method is used. In some embodiments, an adhesive or underfill layer is used between the DSmSiP module 190 and the PCB 302. The semiconductor die 104 and other components in the DSmSiP module 190 are electrically coupled to the conductive layer 304 via the substrate 120, the electronic strip 170, and the solder bumps 186.

[0041] Figure 5b The illustration shows an electronic device 300 having a chip carrier substrate or PCB 302, wherein multiple semiconductor packages (including a DSmSiP module 190) are disposed on the surface of the PCB 302. Depending on the application, the electronic device 300 may have one type of semiconductor package or multiple types of semiconductor packages.

[0042] Electronic device 300 may be a standalone system that performs one or more electrical functions using a semiconductor package. Alternatively, electronic device 300 may be a sub-component of a larger system. For example, electronic device 300 may be part of a tablet computer, cellular phone, digital camera, communication system, or other electronic device. Alternatively, electronic device 300 may be a graphics card, network interface card, or other signal processing card that can be plugged into a computer. Semiconductor packages may include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor dies or electrical components. Miniaturization and weight reduction are essential for products to gain market acceptance. The distance between semiconductor devices can be reduced to achieve higher density. PCB 302 may have a more irregular shape to easily fit into more ergonomic and smaller device housings.

[0043] exist Figure 5b In this design, PCB 302 provides a common substrate for the structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 304 are formed above the surface of PCB 302 or within the layers of PCB 302 using evaporation, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 304 provide electrical communication between each semiconductor package, mounted components, and other external system components. Trace 304 also provides power and ground connections for each semiconductor package.

[0044] In some embodiments, the semiconductor device has two packaging levels. The first-level package is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second-level package involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only a first-level package, where the die is mechanically and electrically disposed directly on the PCB.

[0045] For illustrative purposes, several types of first-level packages (including bonding wire package 346 and flip chip 348) are shown on PCB 302. Additionally, several types of second-level packages are shown disposed on PCB 302, including ball grid array (BGA) 350, bump chip carrier (BCC) 352, planar grid array (LGA) 356, multi-chip module (MCM) or SIP module 358, square flat no-lead package (QFN) 360, square flat package 362, and embedded wafer-level solder ball grid array (eWLB) 364. In one embodiment, eWLB 364 is a fan-out wafer-level package (Fo-WLP) or a fan-in wafer-level package (Fi-WLP).

[0046] Depending on system requirements, any combination of semiconductor packages (configured as any combination of first and second-level packaging styles) and other electrical components can be connected to PCB 302. In some embodiments, electronics 300 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-fabricated components into electronics and systems. Because semiconductor packages contain sophisticated functions, electronics can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less prone to failure and less expensive to manufacture, resulting in lower costs for consumers.

[0047] While one or more embodiments of the present invention have been illustrated in detail, those skilled in the art will appreciate that modifications and alterations may be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: Provide substrate; An opening is formed through the substrate; An insulating film is laminated onto the first surface of the substrate; The first electrical component is disposed on the insulating film in the opening; The second electrical component is disposed on the second surface of the substrate opposite to the first surface; A first sealant is deposited over the first and second electrical components; Remove the insulating film; A third electrical component is disposed above the first surface of the substrate; An electron bar is disposed on the first surface of the substrate; as well as The second sealant is deposited over the third electrical component and electronic strip.

2. The method according to claim 1, further comprising: A conductive layer is formed above the electron strip; as well as The conductive layer is patterned before the electron strip is disposed on the first surface of the substrate.

3. The method of claim 1, further comprising forming a shielding layer over the first sealant.

4. The method of claim 1, further comprising depositing the second sealant, wherein the surface of the second sealant is coplanar with the surface of the electronic strip.

5. The method of claim 1, further comprising forming solder bumps on the electronic strip opposite to the substrate.

6. The method of claim 1, further comprising providing a plurality of electronic strips, wherein each of the plurality of electronic strips is provided along a corresponding edge of the substrate.

7. A method for manufacturing a semiconductor device, comprising: Provide substrate; An opening is formed through the substrate; The first electrical component is disposed in the opening; The second electrical component is disposed above the substrate; as well as A first sealant is deposited on top of the first and second electrical components.

8. The method of claim 7, further comprising disposing a third electrical component above the substrate opposite to the second electrical component.

9. The method of claim 7, further comprising disposing an electronic strip above the substrate opposite to the second electrical component.

10. A semiconductor device, comprising: Substrate; An opening is formed through the substrate; A first electrical component is disposed in the opening; A second electrical component is disposed above the substrate; as well as A first sealant is deposited on top of the first and second electrical components.

11. The semiconductor device of claim 10, further comprising a third electrical component disposed above the substrate opposite to the second electrical component.

12. The semiconductor device of claim 10, further comprising an electronic strip disposed above the substrate opposite to the second electrical component.

13. The semiconductor device of claim 12, further comprising a second sealant deposited over the electronic strip.

14. The semiconductor device of claim 12, further comprising a conductive layer formed over the electron strip and patterned to form an opening.

15. The semiconductor device of claim 10, further comprising a shielding layer formed over the first sealant.

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