A chip, a device, and a manufacturing method

Abstract

Embodiments of the present application provide a chip, a device and a preparation method, which can effectively improve the preparation efficiency of the chip and improve the preparation precision of the chip. The chip comprises a substrate and a functional module. The functional module is located above the substrate, the functional module is wrapped by a plastic packaging material into a plastic packaging structure, the plastic packaging structure comprises a lower part, a middle part and an upper part in the vertical direction in sequence, the functional module is located in the middle part, and the sidewall surface roughness of the middle part is less than that of the lower part and the upper part, respectively.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a chip, device, and method of fabrication. Background Technology

[0002] The method for fabricating a chip die includes: first, fabricating functional modules on a wafer; second, applying a protective layer to the surface of the wafer; third, cleaving the wafer to obtain the die; and finally, grinding the end face of the die.

[0003] To achieve wafer cleaving, a cleaving film is attached to the wafer surface. The cleaving film has structures such as a shock-guiding part and a shock-absorbing part. When the cleaving blade applies pressure to the cleaving film, a shear force is applied to the wafer through the cleaving film, and the wafer is cleaved under the action of the shear force.

[0004] However, the need to attach a diced film to the wafer surface increases the die fabrication process, reducing die fabrication efficiency. Furthermore, the diced die requires end-face grinding, which makes it difficult to precisely control the die feed rate and can easily degrade die performance, thus reducing the precision of die fabrication. For example, for elongated dies, specifically those exceeding 200 mm in length, the end-face grinding process is extremely challenging and highly prone to causing breakage. Summary of the Invention

[0005] This application provides a chip, device, and fabrication method that can effectively improve the fabrication efficiency and accuracy of chip dies.

[0006] In a first aspect, this application provides a chip, including a substrate and a functional module. The functional module may include optical waveguide devices, light-emitting diodes, photodetectors, integrated circuits, microelectromechanical systems (MEMS), power devices, microwave transmission lines, radio frequency devices, etc. The functional module is located above the substrate and is encapsulated by a molding compound to form a molding structure. The molding structure includes a lower part, a middle part, and an upper part in a vertical direction. The functional module is located in the middle part, and the surface roughness of the sidewalls of the middle part is smaller than that of the sidewalls of the lower part and the upper part, respectively.

[0007] As described in this aspect, the lower and upper sidewalls can achieve a uniform stress distribution under pressure, preventing stress from diffusing to the center. This results in the roughness of the center being less than that of the lower and upper parts, effectively reducing the roughness of the center sidewalls while improving the smoothness, flatness, and finish of the center, thus preventing the formation of microcracks. The lower and upper sidewalls directly form the low-roughness center sidewalls during chip dicing. Therefore, the formation of low-roughness center sidewalls eliminates the need for chip grinding, effectively improving chip production efficiency and precision. The low-roughness center sidewalls can effectively enhance chip performance. For example, for elongated chips, specifically those with a length of 200mm or more, low-roughness center sidewalls can be obtained without grinding the chip's end faces, simplifying the chip manufacturing process and avoiding breakage problems that can occur during end-face grinding.

[0008] Based on the first aspect, in one optional implementation, the orthographic projection of the functional module on the substrate surface lies within the orthographic projection of the upper sidewall on the substrate surface, and also within the orthographic projection of the lower sidewall on the substrate surface. Specifically, the lower sidewall has a first orthographic projection on the substrate surface, which occupies a first coverage area on the substrate surface; the upper sidewall has a second orthographic projection on the substrate surface, which occupies a second coverage area on the substrate surface; the orthographic projection of the functional module on the substrate surface lies within the first coverage area, and also within the second coverage area.

[0009] With this implementation, there is a gap between the functional module and the lower sidewall, and there is also a gap between the functional module and the upper sidewall. This effectively avoids the impact of stress on the lower and upper parts on the performance of the functional module during the die-cutting process, thereby improving the reliability of the bare chip.

[0010] Based on the first aspect, in one optional implementation, the orthographic projection of the upper sidewall on the substrate surface and the orthographic projection of the lower sidewall on the substrate surface at least partially overlap; specifically, the first coverage area and the second coverage area at least partially overlap.

[0011] Using this implementation, when the first coverage area and the second coverage area at least partially overlap, it can be guaranteed that the chip die can be successfully cleaved from the wafer.

[0012] Based on the first aspect, in one optional implementation, the substrate further includes a modified region, wherein the modified region, the lower part, the middle part and the upper part are arranged sequentially in the vertical direction, and the roughness of the sidewall surface of the modified region is greater than the roughness of the sidewall surface of the lower part and the upper part, respectively.

[0013] Using this implementation, the stress in the modified region will act on the lower part and be released by the lower part, so that the stress will not spread to the middle part, ensuring the formation of a low-roughness middle sidewall. Moreover, the stress acting on the modified region will improve the efficiency of chip dicing from the wafer.

[0014] Based on the first aspect, in one optional implementation, the roughness of the lower sidewall at different positions is equal or approximately equal, the roughness of the upper sidewall at different positions is equal or approximately equal, and the roughness of the middle sidewall at different positions is equal or approximately equal.

[0015] This implementation method reduces the difficulty of forming the lower and upper parts in the chip, and ensures the formation of low-roughness middle sidewalls. The lower and upper sidewalls can achieve uniform stress distribution under pressure.

[0016] Based on the first aspect, in an optional implementation, the lower sidewall includes a plurality of first regions arranged in a horizontal direction, with a gap between two adjacent first regions; the upper sidewall includes a plurality of second regions arranged in a horizontal direction, with a gap between two adjacent second regions; the middle sidewall includes a plurality of third regions arranged in a horizontal direction, with a gap between two adjacent third regions; and the roughness of the third regions is less than the roughness of the first regions and the second regions, respectively.

[0017] With this implementation, there is a gap between two adjacent first regions and a gap between two adjacent second regions, which improves the release of forces in the first and second regions and effectively avoids the formation of microcracks in the middle sidewall.

[0018] Based on the first aspect, in one optional implementation, the lower sidewall and the upper sidewall include a pair of first regions and second regions, which at least partially overlap each other in the vertical direction, and the third region is located between the pair of first regions and second regions.

[0019] In this implementation, in the paired first and second regions, the coverage area of ​​the first region projected onto the substrate surface at least partially overlaps with the coverage area of ​​the second region projected onto the substrate surface, thereby ensuring the successful formation of a low-roughness central sidewall.

[0020] Based on the first aspect, in one optional implementation, the chip includes W functional modules, where W is any integer greater than 1, and the W functional modules are arranged along at least one of the vertical and horizontal directions.

[0021] This implementation method effectively improves the chip's integration level and performance.

[0022] Based on the first aspect, in one optional implementation, the chip further includes a cover plate, and along the vertical direction, the molding structure is located between the substrate and the cover plate, and the contact surface between the substrate surface and the cover plate forms a laser weld, with a gap between the laser weld and the functional module.

[0023] This implementation allows for the formation of the lower, upper, and middle portions within the substrate as needed, improving chip reliability. The laser weld seam is formed by focusing a welding beam onto or near the contact surface. Because the laser weld seam is formed by welding with a welding beam, there is no need to add intermediary layers such as adhesive layers or solder between the cover plate and the substrate. This reduces the complexity of curing the cover plate and substrate, improves curing efficiency, and avoids the impact of adhesive layers, solder, and other intermediary layers on the performance of functional modules on the substrate surface, thus enhancing the reliability of the functional modules.

[0024] Based on the first aspect, in an optional implementation, the chip further includes a cover plate, and along the vertical direction, the functional module is located between the substrate and the cover plate. The cover plate includes an upper part, and a laser weld is formed at the contact surface between the substrate surface and the cover plate. There is a gap between the laser weld and the functional module.

[0025] Using this implementation, the lower and middle portions can be formed in the substrate as needed, and the upper portion can be formed in the cover plate, improving the flexibility of chip fabrication. The laser weld seam is formed by focusing a welding beam onto or near the contact surface. Because the laser weld seam is formed by welding with a welding beam, there is no need to add intermediary layers such as adhesive layers or solder between the cover plate and the substrate. This reduces the complexity of curing the cover plate and substrate, improves curing efficiency, and avoids the impact of adhesive layers, solder, and other intermediary layers on the performance of functional modules on the substrate surface, thus improving the reliability of the functional modules.

[0026] Based on the first aspect, in one optional implementation, the functional module includes an optical waveguide device made of an optical waveguide, and the middle sidewall has a coating, the coating including at least one of an antireflection coating, a high reflectivity coating, an anti-reflection coating, and a filter coating.

[0027] By adopting this implementation method, the low-roughness central sidewall can provide a foundation for subsequent coating processes. The central sidewall can ensure coating uniformity and adhesion, improve the bonding force between the coating and the chip, suppress the risk of coating contamination or peeling, and ensure the quality of coating.

[0028] In a second aspect, this application provides an apparatus comprising a package housing containing a chip as described in any of the first aspects above.

[0029] Thirdly, this application provides a fabrication method for fabricating a chip, the chip being as described in any of the first aspects above. The method includes: obtaining a cleaving module, the cleaving module including a wafer, the functional module being located on the surface of the wafer; focusing a first guiding beam and a second guiding beam onto the cleaving module to form a lower part and an upper part; under stress, the lower part and the upper part, the chip being split from the cleaving module, the substrate included in the chip being a part of the wafer. For an explanation of the beneficial effects of this aspect, please refer to the first aspect, and specific details will not be repeated here. Attached Figure Description

[0030] Figure 1 A flowchart illustrating one embodiment of the preparation method provided in this application;

[0031] Figure 2 A top view of an embodiment of the wafer provided in this application is shown as an example.

[0032] Figure 3 A welding example diagram of an embodiment of the wafer and protective layer provided in this application;

[0033] Figure 4 for Figure 3 The diagram shows an example of a top-view structure.

[0034] Figure 5 for Figure 3 Example diagram of the side view structure shown;

[0035] Figure 6 Example diagram of the module for guiding the beam of light to the fragment to be cleaved, provided in this application;

[0036] Figure 7 for Figure 6 The diagram shows a top view of the module to be cleaved.

[0037] Figure 8 An example diagram illustrating the dicing process of the dicing module provided in this application;

[0038] Figure 9a This is a structural example diagram of a first embodiment of the chip provided in this application;

[0039] Figure 9b This is a structural example diagram of a second embodiment of the chip provided in this application;

[0040] Figure 9c This is a structural example diagram of a third embodiment of the chip provided in this application;

[0041] Figure 10 This is a structural example diagram of a fourth embodiment of the chip provided in this application. Detailed Implementation

[0042] The technical solutions in this application will now be described with reference to the accompanying drawings. In the embodiments of this application, words such as "exemplary" and "for example" are used to indicate that they are examples, illustrations, or descriptions. Any embodiment or design scheme described as "exemplary" in this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the term "exemplary" is intended to present the concept in a concrete manner.

[0043] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0044] Figure 1 This is a flowchart illustrating one embodiment of the preparation method provided in this application.

[0045] Step 101: Fabricate functional modules on the wafer.

[0046] Figure 2This is a top view of an embodiment of the wafer provided in this application. The wafer 200 shown in this embodiment can be made of glass (e.g., borosilicate glass, quartz glass, etc.). This embodiment does not limit the specific material of the wafer 200. For example, the wafer 200 can also be made of lithium niobate (LiNbO3), III-V semiconductor compounds such as indium phosphide (InP), gallium arsenide (GaAs), polymers, silicon dioxide (SiO2), silicon-on-insulator (SOI), sapphire, etc. The wafer 200 includes N regions to be cleaved, where N is any integer greater than or equal to 1. After subsequent cleaving of the wafer 200, each region to be cleaved is split from the wafer 200 into a substrate 201. This embodiment does not limit the top-view structure of each substrate 201. For example, the top-view structure of each substrate 201 can be rectangular, circular, elliptical, square, polygonal, or irregularly shaped. Each substrate 201 is used to fabricate a functional module 202. This embodiment does not limit the type of functional module 202. For example, the functional module 202 can be an optical waveguide device. This optical waveguide device uses a high-energy laser beam to induce local physical or chemical changes inside or on the surface of the substrate 201 material to form the optical waveguide device. This embodiment does not limit the fabrication process of the optical waveguide device. For example, it can be fabricated using ion exchange, ion implantation, chemical vapor deposition, or ultrafast laser direct writing. This embodiment does not limit the function implemented by the optical waveguide device. For example, the optical waveguide device is used to implement an optical fiber splitter, also known as a planar lightwave circuit (PLC), which decomposes a single optical signal into two or more optical signals according to a predetermined ratio. For example, optical waveguide devices are used to implement wavelength division multiplexing (WDM). This embodiment does not limit the type of functional module 202. For example, the type of functional module 202 can also be a light emitting diode (LED), a photodetector, an integrated circuit, a micro-electro-mechanical system (MEMS), a power device, a microwave transmission line, a radio frequency device, etc.

[0047] Step 102: Solder a protective layer on the wafer surface to obtain the wafer module to be cleaved.

[0048] Figure 3This is a welding example diagram of an embodiment of the wafer and protective layer provided in this application. This embodiment shows the welding of a protective layer 300 onto the surface of wafer 200 to obtain a wafer module to be cleaved. It can be understood that the wafer module to be cleaved includes the wafer 200 in a welded state and the protective layer 300.

[0049] The process for soldering the protective layer 300 onto the surface of wafer 200 can be as follows:

[0050] First, wafer 200 is placed below and protective layer 300 is placed above. A welding fixture 310 clamps wafer 200 and protective layer 300 together. A welding beam emitted from light source 320 passes through protective layer 300, allowing it to act on the contact surface between protective layer 300 and wafer 200, thus achieving the welding of protective layer 300 and wafer 200. This embodiment does not limit the material of protective layer 300, as long as it has light-transmitting properties; for example, the transmittance of protective layer 300 to the welding beam is greater than or equal to 90%. The protective layer may also have certain mechanical strength, corrosion resistance, and other properties, enabling it to protect the functional modules fabricated on wafer 200. For example, protective layer 300 can be made of metal, plastic, glass, composite materials, ceramic, quartz, etc. Typically, protective layer 300 and wafer 200 are made of the same material to improve chip reliability. This embodiment allows for the soldering of one or more protective layers onto the surface of wafer 200, with no limitation on the number of protective layers. The light source 320 shown in this embodiment can be a laser light source, and the soldering beam emitted by the light source 320 is a laser. This embodiment does not limit the wavelength or optical power of the soldering beam, as long as the soldering beam can solder the protective layer 300 to the surface of wafer 200. For example, the pulse width of the soldering beam is less than or equal to 10 nanoseconds (ns). The pulse width of the soldering beam refers to the time that the soldering beam actually acts on the contact surface between wafer 200 and protective layer 300 per unit time. With the same optical power output from the light source 320, a narrower pulse width results in a higher peak power of the soldering beam, thereby achieving a finer soldering effect and improving soldering efficiency. This embodiment does not limit the wavelength of the soldering beam; for example, the wavelength of the soldering beam can be approximately 1030 nanometers (nm) or 1064 nm, making the soldering beam infrared or near-infrared light. The welding beam acts on the contact surface between the protective layer 300 and the wafer 200. The high energy density of the welding beam acts as a heat source, focusing the beam onto the contact surface to create a heat source region. The material of the contact surface is modified and melted, and upon cooling, a laser weld is formed. This laser weld is used to weld the protective layer 300 to the surface of the wafer 200. To ensure the formation of the laser weld, the welding beam and the contact surface must meet preset conditions. These preset conditions mean that, along the third direction Z (also known as the perpendicular direction), the focal plane of the welding beam coincides with the contact surface, or the deviation between the focal plane of the welding beam and the contact surface is within the Rayleigh length of the welding beam. Here, the third direction Z is the direction perpendicular to the surface of the wafer 200. The welding beam spot has the smallest diameter on the focal plane, thus maximizing the energy density at the focal plane. A welding beam and contact surface that meet these preset conditions allow the welding beam to fully act on the contact surface, thereby enabling the formation of a laser weld.The deviation between the focal plane of the welding beam and the contact surface is within the Rayleigh length of the welding beam, which ensures that the divergence angle of the welding beam acting on the contact surface is small and the energy of the welding beam is evenly distributed on the contact surface, thus improving the welding efficiency and stability.

[0051] The advantages of using a welding beam to weld the protective layer 300 to the wafer 200 are as follows: Because welding is performed using a welding beam, there is no need to add intermediary layers such as adhesive layers or solder between the protective layer 300 and the wafer 200. This reduces the complexity of curing the protective layer 300 and the wafer 200, improves the efficiency of curing, and avoids the impact of intermediary layers such as adhesive layers and solder on the performance of functional modules on the surface of the wafer 200, thus improving the reliability of the functional modules. Welding with a welding beam ensures that even when the chip undergoes subsequent high-temperature processes, there is no risk of detachment or contamination between the protective layer 300 and the wafer 200, further improving reliability. Because the welding beam has a stable spot, the position of the laser weld can be precisely controlled. Therefore, to avoid the laser weld affecting the performance of the functional modules, a gap exists between the laser weld and the functional module. (See [reference needed]). Figure 4 as well as Figure 5 As shown, where, Figure 4 for Figure 3 The diagram shown is a top view of the structure. Figure 5 for Figure 3The diagram shows an example of a side view structure. The relative movement of the welding beam emitted by the light source 320 relative to the protective layer 300 and the wafer 200 can be achieved using a "focusing objective-motion platform" or a "scanning galvanometer" system. This embodiment does not limit the movement trajectory of the light source 320; for example, it can be formed on the contact surface along a "Z," "bow," "return," or grating scanning pattern. In this embodiment, taking the optical waveguide device 502 as an example, the optical waveguide device 502 and the laser weld 501 are separated, and a gap 511 exists between them. The gap 511 effectively avoids the influence of the laser weld 501 on the performance of the optical waveguide device 502. This embodiment does not limit the specific size of the gap 511; for example, along a direction parallel to the surface of the substrate 201, the gap 511 between the laser weld 501 and the optical waveguide device 502 is greater than or equal to 100 μm. This embodiment does not limit the diameter of the welding beam. The diameter can be flexibly adjusted according to the required size of the laser weld seam 501. For example, the diameter of the welding beam can be between 1μm and 30μm. It can be understood that by flexibly and accurately adjusting the diameter of the welding beam, precise control over the position and size of the laser weld seam 501 is achieved. This improves the bonding strength between the protective layer 300 and the wafer 200, thereby enhancing chip reliability. It also effectively avoids the impact of the laser weld seam position on the performance of the chip's functional modules. Furthermore, welding with a welding beam results in a relatively smooth laser weld seam 501, free of slag or flash, and with a fast welding speed, improving the efficiency of welding the protective layer 300 and the wafer 200. To ensure the bonding strength between the protective layer 300 and the wafer 200, the total area of ​​the laser weld seam 501 can be greater than or equal to one-tenth of the contact surface between the protective layer 300 and the wafer 200. In this embodiment, the number of laser weld seams 501 between the protective layer 300 and the wafer 200 and the specific shape of each laser weld seam 501 are not limited. In this embodiment, there may be gaps between different laser weld seams to avoid the occurrence of microcracks in the laser weld seams, which would reduce the bonding force between the protective layer 300 and the wafer 200.

[0052] Step 103: Form the first stress guide line in the module to be cracked.

[0053] Combination Figure 6 as well as Figure 7 As shown, Figure 6 This is an example diagram of the module for guiding the beam of light to the fragment to be cleaved, provided in this application. Figure 7 for Figure 6The diagram shows a top view of the cleaving module. The cleaving stage shown in this embodiment specifically includes a support platform 601, which supports the cleaving module and has a movable function to adapt to cleaving requirements. An adhesive pressure-bearing film 602 is disposed on the surface of the support platform 601, and the cleaving module is bonded to the surface of the adhesive pressure-bearing film 602 to achieve the purpose of fixing the cleaving module to the support platform 601. Specifically, the wafer included in the cleaving module is placed on the surface of the adhesive pressure-bearing film 602. The adhesive pressure-bearing film 602 shown in this example can be an ultraviolet (UV) film or a blue film, etc., and is not specifically limited.

[0054] Light source 610 emits a first guiding beam, which is focused at a first predetermined position on the wafer, causing a first stress guiding line 631 to form at that position. The formation of the first stress guiding line 631 is explained below. Because the first guiding beam is focused at the first predetermined position, its energy density is significantly increased. Under the influence of the guiding beam, the wafer material at the first predetermined position is irradiated with a sufficiently high energy density, causing a change in the material properties at that position. This change typically includes processes such as vaporization, melting, and resolidification of the wafer material. The modifying effect of the first guiding beam at the first predetermined position forms a continuous layered structure, i.e., the first stress guiding line 631, at that position. The location of the first stress guiding line 631 is described below. Within the first plane XY, the first stress guiding line 631 is located on the sidewall of the chip, and the first plane XY intersects with a third direction Z. For example, the first plane XY includes a first direction X and a second direction Y, both of which can be referred to as horizontal directions. Of the first direction X, the second direction Y, and the third direction Z, any two directions are perpendicular to each other. It should be noted that this embodiment uses the third direction Z being perpendicular to the first plane XY as an example, but this is not limited, as long as the first plane XY intersects the third direction Z. The first plane XY is parallel to the substrate surface. This embodiment does not limit the specific shape of the first stress guiding line 631, as long as the first stress guiding line 631 extends along the sidewall of each chip, for example... Figure 7 As shown, the first stress guiding line 631 can extend along the first direction X, and can extend along the first direction X to form multiple lines. The first stress guiding line 631 also extends along the second direction Y, and can extend along the third direction Z, with each chip located in the first intersection region where multiple first stress guiding lines 631 intersect. It can be understood that because the chip is located in the first intersection region, the orthographic projection of the chip on the first plane XY is within the coverage area of ​​the orthographic projection of the first intersection region on the first plane XY, so as to avoid the first stress guiding line 631 affecting the performance of the chip's functional modules. Figure 6The first stress guide line 631 shown corresponds to Figure 7 The first stress guide line 631 extending along the second direction Y is shown as an example. In this example, during the process of the first guide beam acting on the die module to form the first stress guide line 631, the viscous pressure-bearing membrane 602 can prevent the die module from shifting, ensuring that the first stress guide line 631 can be accurately formed at the first predetermined position, and protecting the functional module from external damage.

[0055] Step 104: Form a second stress guide line in the module to be cracked.

[0056] The light source 610 is also used to emit a second guiding beam, which is focused at a second predetermined position on the wafer, so that a second stress guiding line 632 is formed at the second predetermined position on the wafer under the action of the second guiding beam. For an explanation of the formation method of the second stress guiding line 632, please refer to the explanation of the formation method of the first stress guiding line 631 above; details will not be repeated here. The location of the second stress guiding line 632 is described below. Within the first plane XY, the second stress guiding line 632 is located on the sidewall of the chip. For example, the second stress guiding line 632 can extend along the first direction X, and multiple lines can be formed along the first direction X. The second stress guiding line 632 can also extend along the second direction Y, and multiple lines can be formed along the second direction Y. Each chip is located in a second intersection region where multiple second stress guiding lines 632 intersect. For a detailed explanation, please refer to the explanation of each chip being located in the first intersection region shown above; details will not be repeated here. It is understood that since the chip is located within the second intersecting region, the orthographic projection of the chip onto the first plane XY is within the coverage area of ​​the orthographic projection of the second intersecting region onto the first plane XY, in order to avoid the second stress guiding line 632 affecting the performance of the chip's functional modules. In this embodiment, to ensure successful dicing of the N chips included in the dicing module, the coverage areas of the orthographic projections of the first intersecting region onto the first plane XY and the second intersecting region onto the first plane XY are completely coincident, without limitation. For example, in other examples, the coverage areas of the orthographic projections of the first intersecting region onto the first plane XY and the second intersecting region onto the first plane XY may partially coincide. Along the third direction Z, there is a gap between the first intersecting region and the second intersecting region. This example takes the case where both the first stress guiding line 631 and the second stress guiding line 632 are formed in the wafer, without limitation. Optionally, the first stress guiding line 631 may be formed in the wafer, and the second stress guiding line 632 may be formed in the protective layer.

[0057] This embodiment uses the example of the first and second guiding beams being emitted from the same light source 610. In other examples, the first and second guiding beams may be emitted from different light sources, and there is no specific limitation. Optionally, to ensure that the first guiding beam can be accurately focused at a first predetermined position on the wafer, and that the second guiding beam can be accurately focused at a second predetermined position on the wafer, a focusing component may be included between the light source 610 and the wafer cleaving module. The focusing component is used to focus the first guiding beam at the first predetermined position on the wafer and to focus the second guiding beam at the second predetermined position on the wafer. The focusing component may include any type of optical device such as a lens group or a high-magnification microscope objective. In this embodiment, by changing the relative position of the light source 610 and the wafer cleaving module, the first guiding beam emitted by the light source 610 can scan the first predetermined position to form a first stress guiding line, and the second guiding beam emitted by the light source 610 can scan the second predetermined position to form a second stress guiding line. Optionally, if the first and second guiding beams are emitted from different light sources, the first and second guiding beams may be sent to the wafer cleaving module simultaneously or at different times, and there is no specific limitation. In this embodiment, the light source 610 is a Gaussian-distributed laser point source. For example, if the light source 610 is a picosecond laser, then the first guiding beam and the second guiding beam are picosecond lasers. This is not limited, as long as the first guiding beam and the second guiding beam emitted by the light source 610 can form the corresponding first stress guiding line and the second stress guiding line.

[0058] Optional, see below Figure 6 As shown, the light source 610 is also used to emit a dicing beam, which is focused at a third predetermined position on the wafer so that a dicing guide line 633 is formed at the third predetermined position on the wafer under the action of the dicing beam. For an explanation of the formation method of the dicing guide line 633, please refer to the explanation of the formation methods of the first stress guide line 631 and the second stress guide line 632 above, which will not be repeated here. The position of the dicing guide line 633 is described below. The dicing guide line 633 is located on the sidewall of the chip. The dicing guide line 633 can extend along the first direction X and can extend along the first direction X to form multiple lines. The dicing guide line 633 can extend along the second direction Y and can extend along the second direction Y to form multiple lines. Each chip is located in a third intersection region where multiple dicing guide lines 633 intersect. Figure 6Taking the cleaving guide line 633 extending along the second direction Y as an example, the explanation of the third intersection region can be found in the explanations of the first and second intersection regions described above, and will not be repeated here. It can be understood that since the chip is located within the third intersection region, the orthographic projection of the chip on the first plane XY is within the coverage area of ​​the orthographic projection of the third intersection region on the first plane XY, facilitating chip cleaving. In this embodiment, to ensure successful cleaving of the N chips included in the cleaving module, the coverage areas of the orthographic projections of the first, second, and third intersection regions on the first plane XY are completely overlapping, without limitation. For example, in other examples, the coverage area of ​​the orthographic projection of the third intersection region on the first plane XY partially overlaps with the coverage area of ​​the orthographic projection of the first intersection region on the first plane XY, and / or, the coverage area of ​​the orthographic projection of the third intersection region on the first plane XY may partially overlap with the coverage area of ​​the orthographic projection of the second intersection region on the first plane XY. The cleaving guide line 633 shown in this example is formed in the wafer and extends along the third direction Z. One end of the third intersection region contacts the first intersection region, and the other end of the third intersection region contacts the bottom surface of the wafer. This embodiment does not limit the length of the cleaving guide line 633 along the third direction Z. It can be understood that the third intersection region, the first intersection region, and the second intersection region are arranged sequentially along the third direction Z. The light source 610 can be fed multiple times from the bottom surface of the wafer upwards in a scanning direct-write manner, stopping at the first stress guide line 631, until the modification effect of the cleaving beam at the third predetermined position is completed. This embodiment uses the same light source 610 emitting the first guide beam, the second guide beam, and the cleaving beam as an example. In other examples, the light source emitting the cleaving beam may be different from the light source emitting the first guide beam, and / or, the light source emitting the cleaving beam may be different from the light source emitting the second guide beam.

[0059] The properties of the first guiding beam shown in this embodiment are the same as those of the second guiding beam, and the properties of both the first and second guiding beams are different from those of the dicing beam. Taking the first guiding beam as an example, the properties of the first guiding beam specifically refer to its repetition frequency, pulse energy, etc. The properties of the first guiding beam determine the degree of quality modification of the region formed by the first guiding beam at the corresponding position on the wafer. In this example, the light source 610 is a picosecond laser. The repetition frequency of the dicing beam emitted by the light source 610 is 50kHz, meaning that the dicing beam emitted by the light source 610 includes 50,000 pulses per unit time. It should be noted that the description of the repetition frequency in this embodiment is an optional example, and the specific size is not limited. Each pulse of the dicing beam shown in this embodiment may include K sub-pulses, where K is any integer greater than 1. In this embodiment, K=2 is used as an example, so each pulse of the dicing beam may include 2 sub-pulses. The process of using a dicing laser beam to form a third intersecting region on a wafer is described. The dicing laser beam scans upwards along the third direction Z each time until it reaches the sidewall of the first intersecting region, thus completing the modification of the entire third intersecting region. The picosecond laser has a fundamental frequency of 40MHz and a sub-pulse interval of 25ns. The energy of each sub-pulse is correspondingly lower than the pulse energy. For example, if the pulse includes a first sub-pulse and a second sub-pulse, and the first sub-pulse acts inside the wafer material, the ablation of the wafer material under the first sub-pulse is much less than the burning effect of a higher-energy single pulse. This eliminates, to some extent, the micro-explosion phenomenon of the wafer material caused by higher pulse energy. Simultaneously, when the second sub-pulse arrives, the area acted upon by the first pulse has been significantly cooled after 25ns. The energy deposited inside the wafer material by the two sub-pulses is insufficient to cause a micro-explosion; only ion spraying and melting resolidification can occur at the common action site, enhancing the modification effect of the wafer material. Sufficient residual stress accumulates near the modified region (i.e., the third intersecting region), which is beneficial for the subsequent dicing process. This embodiment does not limit the number of sub-pulses included in the pulses of the first guide beam and the second guide beam.

[0060] In this embodiment, the pulse energy of the first guiding beam is less than the pulse energy of the slit beam, so that the roughness of the first intersecting region formed under the action of the first guiding beam is less than the roughness of the third intersecting region formed under the action of the slit beam, and the roughness of the second intersecting region formed under the action of the second guiding beam is less than the roughness of the third intersecting region formed under the action of the slit beam.

[0061] The above embodiments are not limited to the case where the first guide beam, the second guide beam, and the slit beam all have a Gaussian distribution. For example, the slit beam can be a Bessel beam. For instance, the Gaussian distributed beam emitted by the light source can be shaped into a needle-shaped Bessel beam by optical elements (such as an axial pyramid, a spatial light modulator, etc.). Alternatively, the light source can be a Bessel light source that can emit a needle-shaped Bessel beam. The length of the Bessel beam along the third direction Z can be adjusted as needed. Therefore, for the cleavage guide line 633, the length of the Bessel beam along the third direction Z can be adjusted to be consistent with the length of the cleavage guide line 633 along the third direction Z. The Bessel beam only needs to move relative to the cleavage module in the XY plane, without needing to move relative to the cleavage module in the third direction Z, to form the cleavage guide line 633. This improves the efficiency and accuracy of forming the cleavage guide line 633 and avoids thermal damage and mechanical stress to the cleavage module. For the explanation of forming the first stress guide line and the second stress guide line using the Bessel beam, please refer to Forming with Bessel Bessel Beam.

[0062] This embodiment does not limit the execution sequence between steps 103 and 104.

[0063] Step 105: Cleave the wafer module to be cleaved to obtain N chips.

[0064] Based on the wafer dicing process, the wafer to be diced is diced to obtain N chips, where N is any integer greater than or equal to 1. The wafer dicing process involves dividing a whole wafer containing N chips into individual chips according to their size. Please refer to the following for the specific dicing process:

[0065] Figure 8 This is an example diagram illustrating the dicing process of the wafer module to be diced provided in this application. In the case where a first intersecting region, a second intersecting region, and a third intersecting region are formed in the wafer of the wafer module to be diced, the following dicing process is performed on the wafer module: First, the adhesive pressure-bearing film 602 (e.g., on the bottom surface of the wafer) is... Figure 6The protective layer of the wafer to be cleaved (as shown) is replaced with a non-adhesive pressure-bearing film 801, and an adhesive pressure-bearing film 802 is covered on the surface of the protective layer of the wafer to be cleaved. The non-adhesive pressure-bearing film 801 is used to avoid damage to the chip during the cleaving process, and the adhesive pressure-bearing film 802 is used to prevent edge chipping caused by direct contact between the cleaving blade and the wafer surface. The wafer to be cleaved (with the upper surface covered by the adhesive pressure-bearing film 802 and the lower surface covered by the non-adhesive pressure-bearing film 801) is placed on the receiving stage. The distance between adjacent receiving stages can be set to 1.2 times the thickness of the wafer to be cleaved along the third direction Z. The cleaving blade accuracy is 5μm. It should be noted that the description of the distance between adjacent receiving stages and the cleaving blade accuracy in this embodiment are optional examples and are not limited. Next, the cleaving blade 800 is aligned with the second stress guide line 632, and pressure is slowly applied along the third direction Z until the wafer breaks and separates along the first intersection region, the second intersection region, and the third intersection region. An opening is then created on the bottom surface of the wafer, resulting in a single chip. The chip separated from the cleaving module includes a molding compound structure comprising a lower, middle, and upper portion arranged sequentially along the third direction Z. The functional module 620 is located in the middle portion. Furthermore, the chip separated from the cleaving module forms a lower sidewall at the first intersection region, an upper sidewall at the second intersection region, and a modified region sidewall at the third intersection region. This embodiment does not limit the dimensions of the lower and upper portions. For example, taking the lower portion as an example, the height of the lower portion along the third direction Z is <0.2 * (the thickness of the protective layer 300 along the third direction Z + the thickness of the wafer 200 along the third direction Z). For the requirements of the upper portion dimensions, please refer to the description of the lower portion dimensions; specific details will not be elaborated here.

[0066] Continue with Figure 6As shown, a single chip including functional module 620 and a single chip including functional module 621 are obtained. The lower and upper sidewalls can achieve uniform stress distribution under the pressure of the splitting blade. The upper sidewall guides the propagation direction of the stress generated by the splitting blade, allowing the stress to be transmitted along the upper sidewall. The stress on the sidewall of the modified region acts on the lower sidewall and is released by the lower sidewall, preventing the stress from spreading to the middle sidewall. This effectively reduces the surface roughness of the middle sidewall after splitting, giving the middle sidewall a mirror-like effect and preventing the formation of microcracks in the middle sidewall. The following explains why the middle sidewall has a mirror-like effect. Since the lower, upper, and modified sidewalls are modified regions within the wafer, when the wafer is subjected to pressure from the cleaver, the stress within the wafer concentrates on these sidewalls. Consequently, the wafer precisely fractures along these sidewalls to achieve dicing, while simultaneously reducing the stress on the middle sidewall. This significantly improves the smoothness, flatness, and finish of the middle sidewall, resulting in a mirror-like surface. The mirror-like middle sidewall is a low-roughness region, with a surface roughness lower than that of the lower, upper, and modified sidewalls. The stress on the modified sidewall further enhances the efficiency of chip dicing from the wafer.

[0067] During the dicing process, the viscous pressure-bearing film 602 (such as...) on the bottom surface of the wafer is... Figure 6 The advantage of replacing the adhesive pressure-bearing film 602 (as shown) with a non-adhesive pressure-bearing film 801 is that, during the downward pressure application of the cleaver, if the adhesive pressure-bearing film 602 is retained on the bottom surface of the wafer, then the adhesive pressure-bearing film 602 will hinder the movement of the opening on the bottom surface of the wafer to both sides. It is necessary to increase the downward pressure of the cleaver to make the opening on the bottom surface of the wafer move to both sides. However, excessive pressure can easily cause chipping on the wafer surface. Therefore, in this embodiment, the adhesive pressure-bearing film 602 is replaced with a non-adhesive pressure-bearing film 801. The non-adhesive pressure-bearing film 801 will not hinder the movement of the opening on the bottom surface of the wafer to both sides under the action of the cleaver pressure, thus avoiding chipping on the chip surface.

[0068] This embodiment uses a cleaving tool to cleave the chip module as an example, but is not limited to this. For example, a needle-shaped Bessel light source can be used to send a Bessel beam to the second intersection region of the chip module to achieve cleaving. The cleaving process is described above and will not be repeated here. Because the Bessel beam does not diffract during propagation, the energy distribution of the beam remains stable, forming a cleaving path with consistent depth and extremely narrow width in the second intersection region of the chip module. This improves cleaving accuracy, stability, and precision, reduces chip surface damage, and avoids edge chipping and microcracks. Alternatively, a CO2 laser can be used to cleave the chip module to improve cleaving accuracy and efficiency. For example, the CO2 laser spot diameter ranges from 0.1 to 4 mm, the CO2 laser scanning speed is 1 to 100 mm / s, and the CO2 laser power is greater than 50 W. This embodiment does not limit the overall shape of the chip after cleaving. For example, the overall shape can be rectangular or irregular.

[0069] Based on the above-described chip fabrication method, the structure of a single chip after dicing can be found in [reference needed]. Figure 9a As shown, where, Figure 9a This is a structural example diagram of a first embodiment of the chip provided in this application. During the dicing process described above, the module to be diced is diced into N chips. Each chip 900 includes a substrate 901, which specifically includes a first position and a second position 931 with separate positions. The first position is used for... Figure 1 The fabrication method shown forms a molding structure made of molding material, including a lower, middle, and upper portion. For a description of this molding structure, please refer to the above embodiment; details will not be repeated here. A contact surface exists between the second position 931 of the substrate 901 and the cover plate 902. A welding beam is focused on the contact surface to form a laser weld 932, which is used to weld the cover plate 902 to the surface of the substrate 901. For a description of the laser weld 932, please refer to [link to documentation]. Figure 5The specific details of the corresponding embodiments are not repeated here. The substrate 901 shown in this embodiment is a portion formed by wafer cleaving, and the cover plate 902 is a portion formed by protective layer cleaving. The sidewalls of the chip 900 include a lower sidewall 911, an upper sidewall 912, and a middle sidewall 913. For a description of the lower sidewall 911, upper sidewall 912, and middle sidewall 913, please refer to the above description; specific details are not repeated here. Along the extension direction of the chip 900 sidewalls, the middle sidewall 913 is located between the lower sidewall 911 and the upper sidewall 912. In this embodiment, the extension direction of the chip 900 sidewalls is taken as a third direction Z, but this is not limited, as long as the extension direction of the chip 900 sidewalls intersects the surface of the substrate 901. The cleaved middle sidewall 913 exhibits a mirror-like effect. For a description of the mirror-like effect, please refer to the above description; specific details are not repeated here. To protect the functional modules, the functional modules included in the chip 900 are located within the middle of the package structure. This means the functional modules are encapsulated by a plastic encapsulation structure comprising a lower, middle, and upper portion. For example, the orthographic projection of the functional module onto the third plane XZ is within the coverage area of ​​the orthographic projection of the middle sidewall 913 onto the third plane XZ. This embodiment uses the third plane XZ being perpendicular to the substrate surface as an example, but this is not limited; it is sufficient as long as the third plane intersects the substrate surface. For example, if the functional module included in the chip 900 is an optical waveguide device, since the middle sidewall 913 is directly diced to form the chip, it can achieve a mirror-like surface without grinding. Because the mirror-like middle sidewall 913 does not require mechanical grinding, the efficiency and accuracy of dicing to obtain the chip are effectively improved. The mirror-like central portion effectively improves chip performance, specifically by suppressing scattering loss introduced into the optical waveguide device and increasing optical signal coupling efficiency (e.g., the optical signal is coupled to the optical waveguide device, or the optical waveguide device couples the optical signal to the outside of the chip). Furthermore, the sidewalls in the central portion do not introduce Fresnel reflections, preventing the optical signal from being reflected back to the optical waveguide device, effectively avoiding interference with the performance of the optical waveguide device. The mirror-like sidewalls 913 in the central portion can also improve the coupling efficiency between the chip and other optical components (e.g., optical fiber, another optical chip), reducing optical signal loss during coupling. This embodiment uses an optical waveguide device as an example, but is not limited to this specific example. The key is that the mirror-like sidewalls 913 effectively improve the chip's performance. For example, if the functional module is an LED, the mirror-like sidewalls 913 effectively improve the chip's light extraction efficiency. Similarly, if the functional module is a photodetector, the mirror-like sidewalls 913 can reduce optical signal scattering and loss, thereby improving the chip's detection efficiency. For example, if the functional module is an integrated circuit, the mirror-like sidewall 913 in the middle can improve the efficiency of signal transmission in scenarios involving optoelectronic integration.For example, if the functional module is a MEMS (such as a micromirror, optical switch, optical filter, etc.), the mirror-like sidewall 913 in the middle effectively improves the propagation efficiency and quality of the optical signal and suppresses optical signal loss. Similarly, if the functional module is a power device, the mirror-like sidewall 913 in the middle effectively reduces the loss of power devices involving high frequencies or optoelectronic integration. Furthermore, if the functional module is a microwave transmission line, the mirror-like sidewall 913 in the middle effectively reduces signal loss and reflection in the microwave transmission line, improving transmission efficiency. And if the functional module is a radio frequency device, the mirror-like sidewall 913 in the middle effectively reduces signal loss and noise. This embodiment does not limit the surface roughness of the upper sidewall, the middle sidewall, or the surface roughness of the upper sidewall. Furthermore, the mirror-like sidewalls 913 in the center provide a foundation for subsequent coating processes, allowing for no limitation on the type of coating applied to the center. For example, antireflective coatings, high-reflective coatings, anti-reflective coatings, and light-filtering coatings can be applied to the center. The smooth center ensures coating uniformity and adhesion. Moreover, the chip's cover plate and substrate are joined together by laser welding, preventing the introduction of low-threshold colloids. During subsequent high-temperature coating processes in the center, there is no risk of coating contamination or peeling due to low-threshold colloids, thus ensuring coating quality.

[0070] See also Figure 9aAs shown, there is a gap between the functional module and the lower sidewall 911, and a gap between the functional module and the upper sidewall 912. This effectively avoids the influence of stress on the performance of the functional module during the cleaving process due to stress on the lower and upper parts. In this embodiment, the size of the gap between the functional module and the lower and upper parts is not limited. Specifically, the gap between the functional module and the lower sidewall 911 means that the orthographic projection of the functional module on the surface of the substrate 901 is located within the orthographic projection of the upper sidewall 912 on the surface of the substrate 901, and also within the orthographic projection of the lower sidewall 911 on the surface of the substrate 901. For example, if the surface of the substrate 901 is located within the first plane XY, then the lower sidewall 911 has a first orthographic projection on the first plane XY, and this first orthographic projection occupies a first coverage area on the first plane XY. The upper sidewall 912 has a second orthographic projection on the first plane XY, and this second orthographic projection occupies a second coverage area on the first plane XY. The orthographic projection of the functional module on the first plane XY is located within the first coverage area, and the orthographic projection of the functional module on the first plane XY is located within the second coverage area. This embodiment takes the complete overlap of the first and second coverage areas as an example, without limitation; for example, the first and second coverage areas may partially overlap. Because the orthographic projection of the functional module on the third plane XZ, the middle sidewall 913 is within the coverage area of ​​the orthographic projection on the third plane XZ, then along the third direction Z, there are gaps between the functional module and both the lower sidewall 911 and the upper sidewall 912.

[0071] Figure 9a The substrate 901 shown also includes a modified region. For a description of the modified region, please refer to the above embodiment; specific details will not be repeated here. Along the extension direction of the chip sidewalls (e.g., the third direction Z), the sidewall 921 of the modified region, the lower sidewall 911, the middle sidewall 913, and the upper sidewall 912 are arranged sequentially. The roughness of the sidewall 921 of the modified region is greater than the roughness of the lower sidewall 911, and the roughness of the sidewall 921 of the modified region is greater than the roughness of the upper sidewall 912. It can be understood that the roughness of the sidewall 921 of the modified region is greater than the roughness of the middle sidewall 913.

[0072] like Figure 9aAs shown, the lower sidewall 911 of the chip has a continuous material structure. Specifically, this means that the lower sidewall 911 does not exhibit fractures, delamination, or significant changes or gradients in the physical and chemical properties (such as hardness, toughness, conductivity, etc.) of the material. For example, if the lower sidewall 911 is connected to each other at different locations and the material is continuous without gaps, then the roughness at different locations of the lower sidewall 911 is equal or approximately equal. The upper sidewall 912, the middle sidewall 913, and the sidewall 921 of the modified region all have continuous material structures. For a detailed explanation, please refer to the description of the lower sidewall 911 having a continuous material structure; further details will not be elaborated here. It can be understood that the roughness at different locations of the upper sidewall 912 is equal or approximately equal, the roughness at different locations of the middle sidewall 913 is equal or approximately equal, and the roughness at different locations of the sidewall 921 of the modified region is equal or approximately equal.

[0073] Figure 9a As shown, taking the formation of the lower sidewall, the upper sidewall, and the sidewall of the modified area by laser modification of the substrate as an example, without limitation, or taking the formation of the lower sidewall and the sidewall of the modified area by laser modification of the substrate as an example, while the formation of the upper sidewall by laser modification of the cover plate, without limitation.

[0074] The chip specifically includes W functional modules, where W is any integer greater than 1. The W functional modules are arranged along at least one of the first direction X, the second direction Y, and the third direction Z. This embodiment does not limit the arrangement of the W functional modules at the bottom and top, as long as the orthographic projection of each of the W functional modules onto the third plane XZ is within the coverage area of ​​the orthographic projection of the middle part onto the third plane XZ. For example... Figure 9a As shown, the W functional modules specifically include functional module 931 and functional module 932, which are arranged along the second direction Y. For example... Figure 9b , Figure 9b This is a structural example diagram of a second embodiment of the chip provided in this application. The W functional modules specifically include functional module 941 and functional module 942, which are arranged along the third direction Z. For example... Figure 9c As shown, Figure 9cThis is a structural example diagram of a third embodiment of the chip provided in this application. The W functional modules specifically include functional module 951, functional module 952, and functional module 953. Functional modules 951 and 952 are arranged along a third direction Z, and functional modules 951 and 953 are arranged along a second direction Y. This embodiment may also include multiple functional modules arranged sequentially along a first direction X. For details, please refer to the above-described multiple functional modules arranged sequentially along the second direction Y or along a third direction Z; further details are omitted. This embodiment uses the example of a chip including a lower part, a middle part, and an upper part along a third direction Z. In other examples, the chip may include multiple middle parts arranged along a third direction Z. Between two adjacent middle parts arranged along a third direction Z, a modification region may be included. For details of the modification region, please refer to the descriptions of the lower and upper parts shown above; no specific limitations are imposed, as long as the sidewalls of the cleaved chip include multiple middle parts arranged along a third direction Z, and the description of the functional modules in each middle part is as shown above; further details are omitted.

[0075] Figure 10 This is a structural example diagram of a fourth embodiment of the chip provided in this application. The chip 1000 includes a substrate 1001 and a cover plate 1002 located on the surface of the substrate 1001. The substrate 1001 and the cover plate 1002 are connected by a laser weld 1020. For a description of the laser weld 1020, please refer to [link to documentation]. Figure 9a As shown, details are omitted. For a description of the substrate 1001 and the cover plate 1002, please refer to [link to documentation]. Figure 9a The corresponding explanations will not be elaborated upon here. The sidewalls of chip 1000 include a lower part, an upper part, and a middle part, which are arranged in a non-connected structure. Figure 10 Compared to Figure 9aThe difference shown is that the sidewall of the chip includes a plurality of first regions arranged along the second direction Y, such as first region 1011, first region 1012 and first region 1013, with a gap between two adjacent first regions, such as a gap 1061 between first region 1011 and first region 1012 and a gap 1062 between first region 1012 and first region 1013. The upper sidewall includes a plurality of second regions arranged along the second direction Y, such as second region 1014, second region 1015 and second region 1016, with a gap between two adjacent second regions, such as a gap 1061 between second region 1014 and second region 1015 and a gap 1062 between second region 1015 and second region 1016. The central sidewall includes a plurality of third regions arranged along the second direction Y, such as third region 1031, third region 1041, and third region 1051. Adjacent third regions are separated by gaps, for example, gap 1061 between third region 1031 and third region 1041, and gap 1062 between third region 1041 and third region 1051. The roughness of each third region is less than that of the first and second regions, respectively. In this embodiment, gaps 1061 and 1062 can be regions of the substrate that have not undergone modification (e.g., regions not affected by the guiding beam). In this embodiment, the lower sidewall and the upper sidewall include paired first regions and second regions. In the third direction Z, the paired first regions and second regions at least partially overlap each other. For example, the lower sidewall and the upper sidewall have paired first regions 1011 and second regions 1014, paired first regions 1012 and second regions 1015, and paired first regions 1013 and second regions 1016. Each third region shown in this embodiment is located between paired first regions and second regions. Therefore, third region 1031 is located between paired first regions 1011 and second regions 1014, third region 1041 is located between paired first regions 1012 and second regions 1015, and third region 1051 is located between paired first regions 1013 and second regions 1016.In this embodiment, to ensure the formation of a mirror-like third region, the paired first and second regions satisfy a preset condition. Taking the paired first region 1011 and second region 1014 as an example, the preset condition means that the coverage area of ​​the orthographic projection of the first region 1011 on the third plane XY completely overlaps or partially overlaps with the coverage area of ​​the orthographic projection of the second region 1014 on the first plane XY. When the paired first region 1011 and second region 1014 satisfy this preset condition, the chip formed by the cleaving process described above will form a mirror-like third region 1031 between the first region 1011 and the second region 1014. Similarly, the paired first region 1012 and second region 1015 satisfy the preset condition, that is, the coverage area of ​​the orthographic projection of the first region 1012 on the third plane XY completely overlaps or partially overlaps with the coverage area of ​​the orthographic projection of the second region 1015 on the first plane XY. Then, after cleaving, a mirror-like third region 1041 will be formed between the first region 1012 and the second region 1015. If the paired first region 1013 and second region 1016 satisfy a preset condition, namely, the coverage area of ​​the orthographic projection of the first region 1013 onto the third plane XY completely overlaps or partially overlaps with the coverage area of ​​the orthographic projection of the second region 1016 onto the first plane XY, then after slicing, a mirror-like third region 1051 will be formed between the first region 1013 and the second region 1016. Then, among the multiple third regions, along the first plane XY, there is a gap between two adjacent third regions, namely, there is a gap 1061 between third region 1031 and third region 1041, and a gap 1062 between third region 1041 and third region 1051. The third region 1031 is used to house the functional module 1032, such that the orthographic projection of the functional module 1032 onto the third plane XZ is within the coverage area of ​​the orthographic projection of the third region 1031 onto the third plane XZ. The third region 1041 is used to house the functional module 1042, such that the orthographic projection of the functional module 1042 onto the third plane XZ is within the coverage area of ​​the orthographic projection of the third region 1041 onto the third plane XZ. The third region 1051 is used to house the functional module 1042, such that the orthographic projection of the functional module 1052 onto the third plane XZ is within the coverage area of ​​the orthographic projection of the third region 1051 onto the third plane XZ. W functional modules are included between the paired first and second regions. For a description of the arrangement of the W functional modules between the paired first and second regions, please refer to [reference needed]. Figure 9a , Figure 9b as well as Figure 9c As shown, the specifics will not be elaborated further.

[0076] The chip shown in this application may also include a packaging structure that encapsulates the chip. The packaging structure also provides signal channels, heat dissipation, and mechanical support. For example, if the functional modules in the chip are optical waveguide devices, LEDs, photodetectors, MEMS, etc., then the signal channel included in the packaging structure is specifically an optical port, which connects to an optical fiber, enabling the transmission of optical signals between the optical fiber and the functional module. As another example, if the functional modules in the chip are integrated circuits, power devices, microwave transmission lines, radio frequency devices, etc., then the signal channel included in the packaging structure is a lead frame (e.g., solder balls, conductive wires, etc.), through which the chip transmits electrical signals.

[0077] This application also provides a device, for example, an optical device. The optical device includes a package housing, and the package housing includes a chip, as shown above, without further details. If the device is an optical device, the functional modules included in the chip are optical waveguide devices, LEDs, photodetectors, MEMS, etc. This embodiment does not limit the specific device type of the optical device. For example, if the optical device is applied to a passive optical network (PON), the optical device can be an optical network unit (ONU), an optical network terminal (ONT), or an optical line terminal (OLT). As another example, if the optical device is applied to an optical transport network (OTN), the optical device can be an OTN device. Furthermore, the optical device can be an optical transmission device, an optical access device, a router, a switch, a wireless base station, a wireless remote access device, a wireless baseband signal processing device, etc., or it can be a computing server (usually referred to as a server), a high-performance computer (HPC), a storage server, a memory resource pool, or a lidar, etc. For example, the device can be an electrical device, which includes a package housing and a chip inside the package housing, as shown above, without further details.If the device is an electrical device, the chip includes functional modules such as integrated circuits, power devices, microwave transmission lines, and radio frequency devices. This embodiment does not limit the specific type of electrical device. For example, the electrical device can be an access point (AP), a station (STA), an evolved Node B (eNB), a radio network controller (RNC), a Node B (NB), a base station controller (BSC), a base transceiver station (BTS), a home evolved Node B (or home Node B (HNB)), a baseband unit (BBU), a wireless relay node, a wireless backhaul node, a transmission point (TP), or a transmission and reception point (TRP). Alternatively, it can be a network node constituting a gNB or a transmission point, such as a building baseband unit (BBU) or a distributed unit (DU). This equipment can also be used for user equipment, access terminals, user units, user stations, mobile stations, mobile stations, remote stations, remote terminals, mobile devices, user terminals, terminals, wireless communication equipment, user agents or user devices, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to wireless modems, vehicle-mounted equipment, wearable devices, etc.

[0078] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A chip, characterized in that, The device includes a substrate and a functional module, the functional module being located above the substrate and encapsulated by a molding compound to form a molding structure. The molding structure includes a lower part, a middle part, and an upper part in a vertical direction. The functional module is located in the middle part, and the surface roughness of the sidewalls of the middle part is less than that of the sidewalls of the lower part and the upper part, respectively.

2. The chip according to claim 1, characterized in that, The orthographic projection of the functional module on the substrate surface is located within the orthographic projection of the upper sidewall on the substrate surface, and the orthographic projection of the lower sidewall on the substrate surface is also located within the orthographic projection of the lower sidewall on the substrate surface.

3. The chip according to claim 2, characterized in that, The orthographic projection of the upper sidewall onto the substrate surface and the orthographic projection of the lower sidewall onto the substrate surface at least partially overlap.

4. The chip according to any one of claims 1 to 3, characterized in that, The substrate further includes a modified region. In the vertical direction, the modified region, the lower part, the middle part, and the upper part are arranged sequentially. The roughness of the sidewall surface of the modified region is greater than that of the sidewall surface of the lower part and the upper part, respectively.

5. The chip according to any one of claims 1 to 4, characterized in that, The roughness of the lower sidewall is equal or approximately equal at different locations, the roughness of the upper sidewall is equal or approximately equal at different locations, and the roughness of the middle sidewall is equal or approximately equal at different locations.

6. The chip according to any one of claims 1 to 4, characterized in that, The lower sidewall includes a plurality of first regions arranged in a horizontal direction, with a gap between two adjacent first regions. The upper sidewall includes a plurality of second regions arranged in a horizontal direction, with a gap between two adjacent second regions. The middle sidewall includes a plurality of third regions arranged in a horizontal direction, with a gap between two adjacent third regions. The roughness of the third regions is less than that of the first regions and the second regions, respectively.

7. The chip according to claim 6, characterized in that, The lower sidewall and the upper sidewall include a pair of first regions and a second region, which at least partially overlap each other in the vertical direction, and the third region is located between the pair of first regions and the second region.

8. The chip according to any one of claims 1 to 7, characterized in that, The chip includes W functional modules, where W is any integer greater than 1, and the W functional modules are arranged along at least one of the vertical and horizontal directions.

9. The chip according to any one of claims 1 to 8, characterized in that, The chip also includes a cover plate. In the vertical direction, the molding structure is located between the substrate and the cover plate. The contact surface between the substrate surface and the cover plate forms a laser weld seam. There is a gap between the laser weld seam and the functional module.

10. The chip according to any one of claims 1 to 8, characterized in that, The chip also includes a cover plate. In the vertical direction, the functional module is located between the substrate and the cover plate. The cover plate includes an upper part. The contact surface between the substrate surface and the cover plate forms a laser weld. There is a gap between the laser weld and the functional module.

11. The chip according to any one of claims 1 to 10, characterized in that, The functional module includes an optical waveguide device made of an optical waveguide, and the middle sidewall has a coating, which includes at least one of an antireflection coating, a high reflectivity coating, an anti-reflection coating, and a filter coating.

12. A device, characterized in that, The device includes a package housing, and the package housing includes a chip as described in any one of claims 1 to 11.

13. A preparation method, characterized in that, The preparation method is used to prepare a chip, the chip being as described in any one of claims 1 to 11, the method comprising: A wafer cleaving module is obtained, the wafer cleaving module comprising a wafer, and the functional module being located on the surface of the wafer; The first guide beam and the second guide beam are respectively focused onto the module to be cleaved to form the lower part and the upper part; Under stress, the lower and upper parts cause the chip to split from the wafer module, and the substrate included in the chip is a part of the wafer.

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