Semiconductor package structure

Abstract

The present application provides a semiconductor package structure, which includes a substrate, a chip, at least one conductive pillar, an encapsulation and at least one semiconductor component. The chip and the conductive pillar are disposed on the substrate and electrically connected to the substrate. The encapsulation is disposed on the substrate and covers the chip and the conductive pillar. The encapsulation has a first surface and a second surface opposite to each other and at least one receiving recess. The receiving recess extends from the first surface to the second surface and has at least one bottom surface. The bottom surface exposes at least one top surface of the conductive pillar. The semiconductor component is disposed on the bottom surface of the receiving recess and contacts the top surface of the conductive pillar. The semiconductor component is electrically connected to the substrate through the conductive pillar. The semiconductor package structure of the present application is easy to rework and can improve the reusability of products.

Description

Technical Field

[0001] This invention relates to a packaging structure, and more particularly to a semiconductor packaging structure. Background Technology

[0002] In existing packaging structures, chips are typically tested before being mounted on a substrate for packaging. However, some active or passive components, such as diodes, capacitors, and resistors, are directly mounted on the substrate for packaging without testing. When these semiconductor components are damaged or require electrical adjustments, the entire package must be destroyed to remove and replace them. However, this rework process is extremely difficult and can easily damage the chip and its associated electrical components. Summary of the Invention

[0003] This invention relates to a semiconductor packaging structure that is easy to rework and can improve the reusability of products.

[0004] According to an embodiment of the present invention, a semiconductor package structure includes a substrate, a chip, at least one conductive pillar, an encapsulating agent, and at least one semiconductor component. The chip is disposed on the substrate and electrically connected to the substrate. At least one conductive pillar is disposed on the substrate and electrically connected to the substrate. The encapsulating agent is disposed on the substrate and covers the chip and at least one conductive pillar. The encapsulating agent has a first surface and a second surface opposite to each other and at least one receiving groove. The second surface contacts the substrate, and the at least one receiving groove extends from the first surface to the second surface and has at least one bottom surface. The at least one bottom surface exposes at least one top surface of the at least one conductive pillar. The at least one semiconductor component is disposed on at least one bottom surface of the at least one receiving groove and contacts at least one top surface of the at least one conductive pillar. The at least one semiconductor component is electrically connected to the substrate through the at least one conductive pillar.

[0005] In a semiconductor packaging structure according to an embodiment of the present invention, the semiconductor packaging structure further includes a cover plate disposed in at least one receiving groove to cover at least one semiconductor component.

[0006] In the semiconductor packaging structure according to an embodiment of the present invention, the cover plate is an insulating material, and the material of the cover plate includes glass, plastic, ceramic or glass fiber.

[0007] In a semiconductor packaging structure according to an embodiment of the present invention, the semiconductor packaging structure further includes an adhesive material disposed around the cover plate and between the cover plate and the inner wall of at least one receiving groove. The cover plate is fixed to the at least one receiving groove by the adhesive material.

[0008] In the semiconductor packaging structure according to an embodiment of the present invention, the adhesive material described above includes ultraviolet (UV) desolvation or thermal release tape.

[0009] In the semiconductor packaging structure according to an embodiment of the present invention, the semiconductor packaging structure further includes an insulating adhesive material, which fills at least one receiving groove and completely covers at least one semiconductor component.

[0010] In the semiconductor packaging structure according to an embodiment of the present invention, the above-mentioned insulating adhesive material includes ultraviolet degradable adhesive, thermal degradable adhesive film, epoxy resin, or encapsulating compound.

[0011] In the semiconductor packaging structure according to an embodiment of the present invention, the chip described above is bonded to the substrate by wire bonding or flip-chip bonding.

[0012] In the semiconductor packaging structure according to an embodiment of the present invention, the orthographic projection of at least one semiconductor component on the substrate does not overlap with the orthographic projection of the chip on the substrate.

[0013] In the semiconductor packaging structure according to an embodiment of the present invention, the above-mentioned at least one semiconductor component includes at least one passive component or at least one active component.

[0014] Based on the above, in the semiconductor packaging structure of the present invention, the encapsulating colloid covers the conductive pillars disposed on the substrate and has a receiving groove exposing the top surface of the conductive pillars. The semiconductor component is disposed within the receiving groove and contacts the top surface of the conductive pillars for electrical connection with the substrate. In other words, the semiconductor component of the present invention is not encapsulated within the encapsulating colloid. This design allows for rapid removal of the semiconductor component from the receiving groove for rework when it is damaged or requires electrical adjustments, thereby improving product reuse rate. Attached Figure Description

[0015] Figure 1A This is a cross-sectional schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention;

[0016] Figure 1B for Figure 1A A top-view diagram of area A;

[0017] Figure 2 This is a cross-sectional schematic diagram of a semiconductor packaging structure according to another embodiment of the present invention;

[0018] Figure 3 This is a cross-sectional schematic diagram of a semiconductor packaging structure according to another embodiment of the present invention;

[0019] Figure 4 This is a cross-sectional schematic diagram of a semiconductor packaging structure according to another embodiment of the present invention.

[0020] Explanation of icon numbers

[0021] 100a, 100b, 100c, 100d: Semiconductor packaging structures;

[0022] 110:Substrate;

[0023] 111: Upper surface;

[0024] 112, 114, 116: Conductive parts;

[0025] 113: Lower surface;

[0026] 120, 120': Chip;

[0027] 121: Active side;

[0028] 122, 124: Connecting pads;

[0029] 123: Back view;

[0030] 125: Adhesive crystal material;

[0031] 130: Conductive post;

[0032] 131: Top surface;

[0033] 133: Bottom;

[0034] 140, 140': Encapsulating colloid;

[0035] 141: First surface;

[0036] 143: Second surface;

[0037] 145: Receiving groove;

[0038] 150, 152: Semiconductor components;

[0039] 160: Cover plate;

[0040] 161: Top surface;

[0041] 170: Adhesive material;

[0042] 180: Kneading;

[0043] 185: Bump;

[0044] 190: Insulating adhesive;

[0045] A: Region;

[0046] B, B': Bottom surface. Detailed Implementation

[0047] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0048] The embodiments of the present invention can be understood in conjunction with the accompanying drawings, which are also considered part of the disclosure. It should be understood that the drawings of the present invention are not drawn to scale; in fact, the dimensions of the components may be arbitrarily enlarged or reduced to clearly illustrate the features of the present invention.

[0049] Figure 1A This is a cross-sectional schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention. Figure 1B for Figure 1A A top-down view of area A. Please also refer to... Figure 1A and Figure 1B In this embodiment, the semiconductor package structure 100a includes a substrate 110, a chip 120, and at least one conductive pillar (in... Figure 1A The diagram schematically shows two conductive pillars 130, while Figure 1B The diagram schematically shows four conductive pillars 130, an encapsulating colloid 140, and at least one semiconductor component (schematically showing two semiconductor components 150 and 152). A chip 120 is disposed on and electrically connected to a substrate 110. The conductive pillars 130 are disposed on and electrically connected to the substrate 110. The encapsulating colloid 140 is disposed on the substrate 110 and covers the chip 120 and the conductive pillars 130. The encapsulating colloid 140 has a first surface 141 and a second surface 143 opposite to each other, and at least one receiving groove (schematically showing one receiving groove 145). The second surface 143 contacts the substrate 110, and the receiving groove 145 extends from the first surface 141 to the second surface 143 and has a bottom surface B. The bottom surface B exposes the top surface 131 of the conductive pillars 130. Semiconductor components 150 and 152 are disposed on the bottom surface B of the receiving groove 145 and contact the top surface 131 of the conductive pillars 130. Semiconductor components 150 and 152 are electrically connected to substrate 110 via conductive pillars 130.

[0050] In detail, in this embodiment, the substrate 110 has an upper surface 111 and a lower surface 113 opposite to each other, and includes a plurality of conductive portions 112, 114, and 116. Conductive portions 112 and 114 are disposed on the upper surface 111, while conductive portion 116 is disposed on the lower surface 113. In one embodiment, conductive portions 112 and 114 may be disposed on the upper surface 111, while conductive portion 116 may be disposed on the lower surface 113. In one embodiment, conductive portions 112, 114, and 116 may be, for example, circuits, conductive vias, conductive blind vias, pads, or combinations thereof; as long as they have conductive function, they are all conductive portions as described in this disclosure. In one embodiment, the semiconductor package structure 100a can be electrically connected to an external circuit through the conductive portion 116. In one embodiment, the substrate 110 may be, for example, a printed circuit board, an Ajinomoto build-up film (ABF) substrate, a bismaleimide triazine (BT) substrate, or other suitable substrate.

[0051] Please refer to this again. Figure 1A In this embodiment, the chip 120 has an active surface 121 and a back surface 123 facing each other, and includes a plurality of pads 122 disposed on the active surface 121. Here, the chip 120 is disposed on the substrate 110 with the active surface 121 facing upward (i.e., away from the substrate 110). In other words, the chip 120 has its back surface 123 facing the upper surface 111 of the substrate 110. In this embodiment, the semiconductor package structure 100a also includes a die attach material 125 disposed between the chip 120 and the substrate 110, wherein the chip 120 is fixed to the substrate 110 by the die attach material 125. The die attach material 125 directly contacts the upper surface 111 of the substrate 110 and the back surface 123 of the chip 120. In one embodiment, the die attach material 125 is, for example, a die attach film (DAF) or other suitable material. Furthermore, the semiconductor package structure 100a of this embodiment also includes at least one wire bonding (two wire bonding 180 are schematically shown) to electrically connect the pad 122 of the chip 120 to the conductive portion 112 of the substrate 110. That is, the chip 120 of this embodiment is bonded to the substrate 110 by wire bonding.

[0052] Furthermore, in this embodiment, the conductive pillars 130 are disposed around or on one side of the chip 120, wherein the bottom surface 133 of the conductive pillars 130 is structurally and electrically connected to the conductive portion 114 of the substrate 110. The encapsulant 140 is disposed on the upper surface 111 of the substrate 110 and covers the upper surface 111, the chip 120, the die attach material 125, the wire bonding 180, and the conductive pillars 130. Here, a receiving groove 145 of the encapsulant 140 can simultaneously expose the top surfaces 131 of multiple conductive pillars 130. Only the top surface 131 of the conductive pillars 130 is exposed outside the encapsulant 140; the remaining portions are encapsulated within the encapsulant 140. In one embodiment, the conductive pillars 130 are, for example, copper pillars, but are not limited thereto.

[0053] Please also refer to Figure 1A as well as Figure 1B In this embodiment, semiconductor components 150 and 152 are disposed within the same receiving recess 145 and are electrically connected to the substrate 110 via conductive posts 130, respectively. Semiconductor components 150 and 152 are, for example, passive or active components. In one embodiment, the passive component includes a resistor, capacitor, inductor, or a combination of the above components. In one embodiment, the active component includes a transistor, diode, or a combination of the above components, but is not limited thereto. Specifically, the orthographic projections of semiconductor components 150 and 152 onto the substrate 110 do not overlap with the orthographic projection of chip 120 onto the substrate 110.

[0054] Furthermore, the semiconductor packaging structure 100a of this embodiment also includes a cover plate 160 disposed within the receiving groove 145 to cover the semiconductor components 150 and 152, thereby protecting the semiconductor components 150 and 152. That is, the cover plate 160 can be considered a protective cover. In addition, the semiconductor packaging structure 100a also includes an adhesive material 170 disposed around the cover plate 160 and between it and the inner wall of the receiving groove 145. The cover plate 160 is fixed within the receiving groove 145 by the adhesive material 170. In one embodiment, the top surface 161 of the cover plate 160 may be flush with or slightly lower than the first surface 141 of the encapsulating colloid 140. In one embodiment, the cover plate 160 is specifically embodied as an insulating material, wherein the material of the cover plate 160 is, for example, glass, plastic, ceramic, or fiberglass. In one embodiment, the glass includes colored tempered glass or transparent tempered glass. In one embodiment, the cover plate 160 may also be a coating on the glass surface. In one embodiment, the cover plate 160 may also be a silicon substrate. In one embodiment, the adhesive material 170 is, for example, a UV-dissolving or thermally releasing tape. In one embodiment, the receiving groove 145 may be selectively filled with a filling adhesive and covered by the cover plate 160.

[0055] In this embodiment, the semiconductor components 150 and 152 are not encapsulated together with the chip within the encapsulating colloid 140, but are separately disposed within the receiving groove 145 of the encapsulating colloid 140. Therefore, when the semiconductor components 150 and 152 are subsequently damaged or require adjustment of component specifications due to electrical needs, the adhesive material 170 can be disassembled and the cover plate 160 removed by direct irradiation with ultraviolet light or direct heating without damaging the encapsulation structure. This allows for rework or replacement of the semiconductor components 150 and 152 within the receiving groove 145, after which the cover plate 160 can be replaced and the encapsulating colloid (i.e., bonded with adhesive material 170) can be applied again. This embodiment improves product reuse rate. In short, the semiconductor encapsulation structure 100 of this embodiment is easy to rework, and the process is simple and fast.

[0056] It must be noted that the following embodiments use the component reference numerals and some content from the foregoing embodiments, with the same reference numerals used to represent the same or similar components, and descriptions of the same technical content omitted. For explanations of the omitted parts, please refer to the foregoing embodiments; these will not be repeated in the following embodiments.

[0057] Figure 2 This is a cross-sectional schematic diagram of a semiconductor packaging structure according to another embodiment of the present invention. Please also refer to... Figure 1A and Figure 2 The semiconductor packaging structure 100b of this embodiment is similar to the semiconductor packaging structure 100a described above, except that in this embodiment, the encapsulating colloid 140' has two receiving grooves 145 and 147. Semiconductor components 150 and 152 are located on the bottom surfaces B and B' of the receiving grooves 145 and 147, respectively, and are in direct contact with and electrically connected to the top surface 131 of the exposed conductive pillars 130 of the corresponding receiving grooves 145 and 147. The cover plate 160 simultaneously covers the semiconductor components 150 and 152 located in the different receiving grooves 145 and 147, and is fixed to the inner wall of the receiving grooves 145 and 147 by the adhesive material 170.

[0058] Figure 3 This is a cross-sectional schematic diagram of a semiconductor packaging structure according to another embodiment of the present invention. Please also refer to... Figure 1A and Figure 3 The semiconductor packaging structure 100c in this embodiment is similar to the semiconductor packaging structure 100a described above, except that in this embodiment, no semiconductor packaging structure 100a is provided. Figure 1AThe cover plate 160 and adhesive material 170 in the semiconductor package structure 100c also include an insulating adhesive 190, which fills the receiving groove 145 and completely covers the semiconductor components 150 and 152. In one embodiment, the insulating adhesive 190 is, for example, a UV-degradable adhesive, a thermally degradable adhesive film, epoxy resin, or a compound. When the insulating adhesive 190 is a UV-degradable adhesive or a thermally degradable adhesive film, the insulating adhesive 190 can be dissociated by irradiating with ultraviolet light or by direct heating to replace / repair the semiconductor components 150 and 152 located in the receiving groove 145. When the insulating adhesive 190 is epoxy resin or a compound, the insulating adhesive 190 can be locally removed by laser to replace / repair the semiconductor components 150 and 152 located in the receiving groove 145.

[0059] Figure 4 This is a cross-sectional schematic diagram of a semiconductor packaging structure according to another embodiment of the present invention. Please also refer to... Figure 1A and Figure 4 The semiconductor package structure 100d in this embodiment is similar to the semiconductor package structure 100a described above. The difference is that in this embodiment, the semiconductor package structure 100d further includes multiple bumps (two bumps 185 are schematically shown) to electrically connect the pads 124 of the chip 120' to the conductive portion 112 of the substrate 110. That is, in this embodiment, the chip 120' is bonded to the substrate 110 by flip-chip bonding.

[0060] In summary, in the semiconductor packaging structure of this invention, the encapsulating colloid covers the conductive pillars disposed on the substrate and has a receiving groove exposing the top surface of the conductive pillars. The semiconductor component is disposed within the receiving groove and contacts the top surface of the conductive pillars for electrical connection with the substrate. In other words, the semiconductor component of this invention is independently encapsulated within the receiving groove and does not interfere with the chip. With this design, when the semiconductor component is subsequently damaged or requires electrical adjustments to its specifications, it can be quickly removed from the receiving groove for rework. Compared to traditional rework methods, this invention does not damage the original encapsulating colloid and does not adversely affect the chip, thus improving product reuse rate.

[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor packaging structure, characterized in that, include: substrate; A chip is disposed on the substrate and electrically connected to the substrate; At least one conductive post is disposed on the substrate and electrically connected to the substrate; An encapsulating colloid is disposed on the substrate and covers the chip and the at least one conductive post. The encapsulating colloid has a first surface and a second surface opposite to each other and at least one receiving groove. The second surface contacts the substrate. The at least one receiving groove extends from the first surface to the second surface and has at least one bottom surface. The at least one bottom surface exposes at least one top surface of the at least one conductive post. as well as At least one semiconductor component is disposed on the at least one bottom surface of the at least one receiving groove and in contact with the at least one top surface of the at least one conductive post, and the at least one semiconductor component is electrically connected to the substrate through the at least one conductive post.

2. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: A cover plate is disposed within the at least one receiving recess to cover the at least one semiconductor component.

3. The semiconductor packaging structure according to claim 2, characterized in that, The cover plate is an insulating material, and the material of the cover plate includes glass, plastic, ceramic or fiberglass.

4. The semiconductor packaging structure according to claim 2, characterized in that, Also includes: An adhesive material is disposed around the cover plate and between the inner wall of the at least one receiving groove, the cover plate being fixed to the at least one receiving groove by the adhesive material.

5. The semiconductor packaging structure according to claim 4, characterized in that, The adhesive material includes UV-degradable or pyrolytic adhesive films.

6. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: An insulating adhesive is filled in the at least one receiving groove and completely covers the at least one semiconductor component.

7. The semiconductor packaging structure according to claim 6, characterized in that, The insulating adhesive material includes UV-dissolving adhesive, pyrolytic adhesive film, epoxy resin, or encapsulating colloid.

8. The semiconductor packaging structure according to claim 1, characterized in that, The chip is attached to the substrate by wire bonding or flip-chip bonding.

9. The semiconductor packaging structure according to claim 1, characterized in that, The orthographic projection of the at least one semiconductor component on the substrate does not overlap with the orthographic projection of the chip on the substrate.

10. The semiconductor packaging structure according to claim 1, characterized in that, The at least one semiconductor component includes at least one passive component or at least one active component.

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