Semiconductor package including pre-package and pre-package

Abstract

A semiconductor package includes a pre-package, a pre-package carrier on which the pre-package is mounted, and an encapsulant embedding the pre-package and the pre-package carrier. The pre-package includes a power transistor chip having a first side and a second side opposite the first side. The power transistor chip is a lateral semiconductor device. A plurality of source load pads and a plurality of drain load pads are arranged at the first side of the power transistor chip. A pre-pakcage body embeds the power transistor chip at least at the first side of the power transistor chip, a first side of the pre-pakcage body facing away from the first side of the power transistor chip. A structured metal layer is disposed over the first side of the pre-pakcage body. The structured metal layer includes one continuous source load structure and one continuous drain load structure. Pre-package vertical interconnects extend through material of the pre-pakcage body and are configured to connect at least some of the source load pads to the source load structure and at least some of the drain load pads to the drain load structure.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor packaging technology, and more particularly to the packaging of power transistor chips as lateral semiconductor devices. Background Technology

[0002] Packaging technology can significantly impact device performance. Packaging concepts are often designed to provide high wiring capability, high variability in footprint design, good board-level reliability (e.g., high on-board thermal cycling (TCoB) performance), good heat dissipation within the board, and low assembly costs. Furthermore, especially for power applications, packaging concepts should provide low inductance and low resistance in the internal interconnects; otherwise, customers may not be able to benefit from the low R-values ​​of power transistor chips. DS(on) .

[0003] Furthermore, packaging concepts that do not require customers to significantly alter the layout of their application boards are more market-compatible. Therefore, semiconductor packages with the same or similar footprint and terminal layout as standardized packaging solutions may be advantageous. Summary of the Invention

[0004] According to one aspect of this disclosure, a semiconductor package includes: a pre-package; a pre-package carrier, the pre-package being mounted on the pre-package carrier; and a sealant embedding the pre-package and the pre-package carrier. The pre-package includes a power transistor chip having a first side and a second side opposite to the first side. The power transistor chip is a lateral semiconductor device. A plurality of source load pads and a plurality of drain load pads are arranged at the first side of the power transistor chip. The pre-package embeds the power transistor chip at least at the first side of the power transistor chip, the first side of the pre-package facing away from the first side of the power transistor chip. A structured metal layer is disposed above the first side of the pre-package. The structured metal layer includes a continuous source load structure and a continuous drain load structure. Pre-package vertical interconnects extend through the material of the pre-package and are configured to connect at least some of the source load pads to the source load structure and at least some of the drain load pads to the drain load structure. The pre-package is mounted on the pre-package carrier, wherein the structured metal layer faces the pre-package carrier.

[0005] According to another aspect of this disclosure, a prepackage includes a power transistor chip having a first side and a second side opposite to the first side. The power transistor chip is a lateral semiconductor device. A plurality of source load pads and a plurality of drain load pads are arranged on the first side of the power transistor chip. A prepackage body embeds the power transistor chip at least on the first side of the power transistor chip, the first side of the prepackage body facing away from the first side of the power transistor chip. A structured metal layer is disposed above the first side of the prepackage body. The structured metal layer includes a continuous source load structure and a continuous drain load structure. Prepackage vertical interconnects extend through the material of the prepackage body and are configured to connect at least some of the source load pads to the source load structure and at least some of the drain load pads to the drain load structure. Attached Figure Description

[0006] In the accompanying drawings, similar reference numerals designate corresponding similar parts. Features of the various illustrated embodiments may be combined unless they are mutually exclusive; and / or may be selectively omitted if not described as essential. Embodiments are depicted in the accompanying drawings and are exemplarily detailed in the following description.

[0007] Figure 1 This is a schematic cross-sectional view of an example of a semiconductor package, including a pre-packaged example.

[0008] Figure 2 This is a schematic cross-sectional view of an example of a semiconductor package, including another example of pre-packaged packaging.

[0009] Figure 3 This includes examples. Figure 2 A schematic cross-sectional view of another example of a pre-packaged semiconductor package.

[0010] Figure 4 This is a plan view of the first side of an example power transistor chip, illustrating an exemplary layout of the source pad, drain pad, and gate pad.

[0011] Figure 5A This is a plan view of an example of a structured metal layer disposed above the first side of a power transistor chip.

[0012] Figure 5B It is along Figure 5A A schematic cross-sectional view of line AA.

[0013] Figure 5C It is along Figure 5A A schematic cross-sectional view of line BB.

[0014] Figure 6AThis is a plan view of another example of a structured metal layer positioned above the first side of a power transistor chip.

[0015] Figure 6B yes Figure 4 A plan view of the first side of the power transistor chip, showing which load pads are connected to according to... Figure 6A The designed structured metal layer.

[0016] Figure 7 This is a perspective top view of a pre-encapsulated TOLL package as disclosed herein, wherein the sealant of the TOLL package is shown as transparent.

[0017] Figure 8 Is it as in Figure 1 A schematic cross-sectional view of an example of a pre-packaged semiconductor package.

[0018] Figure 9 Is it as in Figure 2 and Figure 3 A schematic cross-sectional view of another example of pre-packaged semiconductor packaging.

[0019] Figure 10A This is a perspective top view of a power transistor chip.

[0020] Figure 10B It is embedded Figure 10A A perspective top view of an example of a pre-packaged power transistor chip, where the pre-package is shown as transparent.

[0021] Figure 10C yes Figure 10B A perspective top view of an example of a pre-packaged structure, in which the structured metal layer and the pre-packaged body are shown as transparent.

[0022] Figure 10D yes Figure 10B A perspective bottom view of a pre-packaged example.

[0023] Figure 11A This is a perspective top view of a pre-packaged SSO8 package as disclosed herein, in which the sealant of the SSO8 package is shown as transparent.

[0024] Figure 11B yes Figure 11A A perspective top view of the SSO8 package. Detailed Implementation

[0025] As used in this specification, the terms "electrically connected" or "electrically coupled" or similar terms are not intended to mean that components are in direct contact with each other; intermediate elements may be provided between components that are "electrically connected" or "electrically coupled". However, according to this disclosure, alternatively, the foregoing terms and similar terms may also have the specific meaning of components being in direct contact with each other, i.e., without providing intermediate elements between components that are "electrically connected" or "electrically coupled".

[0026] Additionally, the terms "above" or "below" in relation to a component, element, or material layer formed or located or arranged "above" or "below" a surface may be used herein to mean that the component, element, or material layer is "directly" located (e.g., placed, formed, arranged, deposited, etc.) on an implicit surface or "directly" located below an implicit surface, such as being in direct contact with the implicit surface. However, the terms "above" or "below" in relation to a component, element, or material layer formed or located or arranged "above" or "below" a surface may be used herein to mean that the component, element, or material layer is "indirectly" located (e.g., placed, formed, arranged, deposited, etc.) on an implicit surface or "indirectly" located below an implicit surface, wherein one or more additional components, elements, or layers are arranged between the implicit surface and the component, element, or material layer.

[0027] refer to Figure 1 The semiconductor package 100 includes a power transistor chip 120. The power transistor chip 120 has a first side 120A and a second side 120B opposite to the first side 120A.

[0028] Multiple load pads 122 are disposed on the first side 120A of the power transistor chip 120. The multiple load pads 122 include multiple drain load pads 122_1 and multiple source load pads 122_2. Additionally, a gate load pad 122_3 (see...) Figure 4 It can be arranged on the first side 120A of the power transistor chip 120.

[0029] The power transistor chip 120 is a lateral semiconductor device. In a lateral semiconductor device, the load current flows primarily in the lateral direction between the load pads 122. In a lateral semiconductor device, the power transistor chip 120 may have load pads 122 only on a first side 120A of the power transistor chip 120.

[0030] The power transistor chip 120 is embedded in a pre-package 140 at least at its first side 120A. The first side 140A of the pre-package 140 faces away from the first side 120A of the power transistor chip 120. A second side 140B of the pre-package 140, opposite to the first side 140A, may extend beyond the first side 120A of the power transistor chip 120, for example, such that the pre-package 140 may partially or completely cover the sidewalls of the power transistor chip 120.

[0031] In some examples, the pre-package 140 is a laminate. In other words, the pre-package is a laminated package. In a laminated package, the power transistor chip 120 is embedded in the laminated component according to well-known lamination techniques.

[0032] In other examples, the pre-package 140 may be, for example, a molded compound. In other words, the pre-package is a molded package in which the power transistor chip 120 is embedded through a molding process.

[0033] It should be noted that, for example, if the pre-packaged body 140 is made of a molding compound, it may not be formed from a laser-activated molding compound. Such known laser-activated molding compounds are doped with laser-activated additives, however, this increases the cost of the molding compound.

[0034] A structured metal layer 160 is disposed above the first side 140A of the pre-package 140. The structured metal layer 160 includes a continuous drain load structure 160_1 and a continuous source load structure 160_2. The continuous drain load structure 160_1 and the continuous source load structure 160_2 are isolated, i.e., separate from each other.

[0035] Multiple drain load pads 122_1 and multiple source load pads 122_2 are connected to drain load structure 160_1 and source load structure 160_2, respectively, via pre-packaged vertical interconnects (hereinafter referred to as vertical interconnects 150). Vertical interconnects 150 extend through the material of pre-package 140. Vertical interconnects 150 are configured to connect at least some of the drain load pads 122_1 to drain load structure 160_1 and at least some of the source load pads 122_2 to source load structure 160_2.

[0036] In other words, the drain load structure 160_1 collects at least some of the drain load current flowing through the drain load pad 122_1 of the power transistor chip 120, and the source load structure 160_2 collects at least some of the source load current flowing through the source load pad 122_2 of the power transistor chip 120.

[0037] An example of a prepackage formed by a power transistor chip 120, a load pad 122, a prepackage body 140, a vertical interconnect 150, and a structured metal layer 160, see, for example, [example not provided]. Figure 8 , Figure 8 The pre-package 800 used in semiconductor package 100 is shown.

[0038] Semiconductor package 100 further includes a pre-packaged carrier 180. The pre-packaged (e.g., Figure 8 The pre-package 800 or any other pre-package is mounted on the pre-package carrier 180, wherein the structured metal layer 160 faces the pre-package carrier 180.

[0039] The pre-packaged carrier 180 may include a drain terminal 180_1 and a source terminal 180_2. The drain terminal 180_1 is bonded to a drain load structure 160_1, and the source terminal 180_2 is bonded to a source load structure 160_2. For example, the bonding material may include solder, conductive adhesive, metal sintering paste, or diffusion solder material.

[0040] Drain terminal 180_1 and source terminal 180_2 can form package terminals configured to mount semiconductor package 100 on an application board (not shown).

[0041] Generally, the pre-package carrier 180 can be of various types, for example. The pre-package carrier 180 can be, for example, a lead frame. In this case, the drain terminal 180_1 and the source terminal 180_2 can be, for example, leads. In other examples, the pre-package carrier 180 can be, for example, a PCB (printed circuit board), or a ceramic-based carrier such as a DCB (direct copper bonding) carrier.

[0042] Sealant 190 embeds a pre-encapsulation and a pre-encapsulation carrier 180. Sealant 190 can be formed from an encapsulation molding compound. This encapsulation molding compound can be different from the molding compound of the pre-encapsulation 140 (if the pre-encapsulation is also formed from a molding compound). In this case, two separate molding processes are required to form the pre-encapsulation 140 and the sealant 190.

[0043] In many cases, the pre-package 140 is a laminate, and the sealant 190 is a molding compound. Therefore, in general, different packaging technologies can be used to generate the pre-package 140 and embed the pre-package sealant 190 in the semiconductor package 100.

[0044] The power transistor chip 120 can be of various types. The examples described herein are specifically for HEMT (High Electron Mobility Transistor) devices. The power transistor chip 120 can be, for example, a III-V compound power transistor chip having, for example, a high bandgap. The transistor chip 120 can be, for example, a GaN chip. In this case, the GaN chip 120 can be, for example, a GaN device on a lateral substrate, such as, for example, a GaN device on Si, or a GaN device on SiC, or a GaN device on sapphire.

[0045] As will be described in further detail below, the thickness T1 of the structured metal layer 160 can, for example, be significantly greater than the thickness of the internal metallization layer. For example, the thickness T1 can be between 25 µm and 105 µm, or between 35 µm and 70 µm. On the other hand, the metal thickness of the internal metallization layer (e.g., BEoL (back-end of the production line) metal layer 1 and / or metal layer 2) can be limited to a thickness of less than 5 µm. Therefore, the structured metal layer 160 is a low-ohmic layer compared to the BEoL metallization layer.

[0046] The vertical interconnect 150 may be formed from a plurality of vertical drain interconnect structures 150_1 extending through the material of the pre-package 140. The vertical drain interconnect structures 150_1 are configured to connect at least some of the drain load pads 122_1 to the drain load structure 160_1.

[0047] The pre-packaged vertical interconnect 150 may further include a plurality of vertical source interconnect structures 150_2 extending through the material of the pre-package 140. The vertical source interconnect structures 150_2 are configured to connect at least some of the source load pads 122_2 to the source load structure 160_2.

[0048] Each vertical interconnect structure 150_1, 150_2 can be formed as a via. These vias can be created by forming holes in the first side 140A of the pre-package 140 and filling them with a conductive material. For example, these holes can be created by photolithography and etching processes. These vias can also be filled, for example, by metal plating during the deposition of the structured metal layer 160. The structured metal layer 160 can be formed by metal plating (e.g., by electroplating or chemical plating).

[0049] Figure 2 Semiconductor package 200 is shown, which is largely designed based on semiconductor package 100, and reference is made to the description above to avoid repetition. Semiconductor package 200 differs from semiconductor package 100 in that a metal layer 260 is disposed above the second side 120B of the power transistor chip 120.

[0050] For example, the second side 120B of the power transistor chip 120 can be embedded in the pre-package 140. In other words, the second side 140B of the pre-package 140 can cover the second side 120B of the power transistor chip 120.

[0051] The metal layer 260 can be connected to the second side 120B of the power transistor chip 120, for example, via vertical interconnects 250. The vertical interconnects 250 can be formed in the same manner as described with respect to the vertical interconnects 150, and reference is made to the above description to avoid repetition. Specifically, the vertical interconnects 250 can extend through the material of the pre-package 140. The vertical interconnects 250 can be formed by an array of vias, which can be filled with metal, for example, during the plating process used to form the metal layer 260.

[0052] The thickness T2 of the metal layer 260 can be, for example, within the range given for the thickness T1 of the structured metal layer 160. The metal layer 260 can be used for heat dissipation and / or thermal removal. Furthermore, the metal layer 260 can be used to provide a defined potential at the back side of the power transistor chip 120. For example, the metal layer 260 can be held at a ground potential or a source potential. Such a defined potential at the back side of the power transistor chip 120 can improve the performance of the power transistor chip 120.

[0053] Figure 3 The illustration shows semiconductor package 300. The pre-packaged product used in semiconductor package 300 is the same as the pre-packaged product used in semiconductor package 200, for example, see reference... Figure 9 , Figure 9 The pre-package 900 used in semiconductor packages 200 and 300 is shown. However, in semiconductor package 300, the metal layer 260 remains exposed on the top side of the sealant 190. This allows the metal layer 260 to be coupled to a heat sink to improve heat dissipation (i.e., to provide a top-side cooled (TSC) package).

[0054] Figure 4 An exemplary layout of chip pads 122_1, 122_2, and 122_3 on a first side 120A of an exemplary power transistor chip 120 is shown. The layout of chip pads 122_1, 122_2, and 122_3 may include a plurality of drain pads (D) 122_1 and a plurality of source pads (S) 122_2. Additionally, a gate pad (G) 122_3 may be provided.

[0055] Multiple source pads (S) 122_2 and multiple drain pads (D) 122_1 can be arranged in an interdigitated load pad array. For example, the multiple source pads (S) 122_2 can be arranged in multiple (horizontal) rows parallel to the longitudinal side of the power transistor chip 120. Similarly, the multiple drain pads (D) 122_1 can be arranged in multiple (horizontal) rows parallel to the rows of source pads (S) 122_2.

[0056] exist Figure 2 In the example shown, the rows of drain pads (D) 122_1 and the rows of source pads (S) 122_2 are, for example, interleaved and / or alternated. In other examples, multiple (e.g., 2) rows of drain pads (D) 122_1 and multiple (e.g., 2) rows of source pads (S) 122_2 may be, for example, interleaved and / or alternated.

[0057] Additionally, the drain pad (D) 122_1 and the source pad (S) 122_2 may be offset from each other, for example, in the longitudinal (horizontal) direction. In other examples, the drain pad (D) 122_1 and the source pad (S) 122_2 may be aligned with each other, for example, in the longitudinal (horizontal) direction. The gate pad (G) 122_3 may be arranged at the corner of the power transistor chip 120 and may be formed, for example, by a single gate pad (G).

[0058] Generally, the number of drain pads (D) 122_1 and / or source pads (S) 122_2 of the power transistor chip 120 can each be equal to or greater than 6, 8, 10, 12, or even higher. Multiple drain pads (D) 122_1 and multiple source pads (S) 122_2 can be distributed over the main portion (e.g., equal to or greater than 70%, 80%, or 90%) of the area of ​​the first side 120A of the power transistor chip 120. Specifically, multiple drain pads (D) 122_1 and multiple source pads (S) 122_2 can be distributed over the entire active region of the power transistor chip 120.

[0059] This distributed load pad layout allows for a short, average path length for electrons to travel through the BEoL metal to the load pads, and thus optimizes electrical performance (thanks to reduced power transistor chip R). DS(on) ).

[0060] More specifically, medium-voltage (MV) GaN chip technology, for example, includes two metallization layers that collect different potentials at the epitaxial level and combine these different potentials in multiple drain pads (D) 122_1 and multiple source pads (S) 122_2 using metal runners located above the entire active chip region. These extended metal lines with finite trace thickness only provide limited redistribution of current / power load at the chip level. Therefore, for current MVGaN chip types, the source and drain pads (i.e., multiple drain pads (D) 122_1 and multiple source pads (S) 122_2) are arranged in an interdigitated pattern. Although the average path length of electrons traveling through the BEoL metal to the die pads 122 is optimized for electrical performance (by means of reduced R... DS(on) However, this pad layout complicates the integration of GaN HEMTs in standard packages.

[0061] The design freedom for rearranging the drain load pad 122_1 and source load pad 122_2 is limited by chip performance constraints. Because current is conducted laterally above the chip and the metal thickness in the BEoL is limited (currently <5 µm AlCu), long-distance wiring must be avoided to maintain low Ro within the device. DS(on) characteristic.

[0062] Figure 4 The (exemplary) layout of the chip pads S, D, G (or any other layout formed by an array of load pads distributed above the main portion of the first side 120A of the power transistor chip 120) is rewired via internal interconnects to provide single-source single-drain package terminals, such as, for example, drain terminal 180_1 and source terminal 180_2, respectively. The rewired arrangement for merging multiple drain pads (D) 122_1 and multiple source pads (S) 122_2 is performed via vertical interconnects 150 and a structured metal layer 160, i.e., via pre-packaged features rather than via internal BEoL metallization.

[0063] Figure 5A This is a plan view of the pre-packaged 500_1, showing an example with the structured metal layer 160. Cross-sectional views along lines AA and BB are shown respectively. Figure 5B and Figure 5C middle.

[0064] The structured metal layer 160 is disposed, for example, having such Figure 4The load pad layout shown is above the power transistor chip 120. As previously mentioned, a single consecutive drain load structure 160_1 merges with drain load pad 122_1, and a single consecutive source load structure 160_2 (which is separate from drain load structure 160_1) merges with source load pad 122_2. The structured metal layer 160 may further include a gate structure 160_3, which is connected to gate pad 122_3.

[0065] For example, the connection between the gate pad 122_3 and the gate structure 160_3 can be provided through multiple vertical gate interconnect structures 150_3, see [link to documentation]. Figure 5B The vertical gate interconnect structure 150_3 can be manufactured in the same way as the vertical drain and / or source interconnect structures 150_1 and 150_2.

[0066] The drain load structure 160_1 and the source load structure 160_2 may cover a major portion (e.g., equal to or greater than 60%, 70%, 80%, or 90%) of the area of ​​the first side 140A of the pre-package 140. Similarly, the metal layer 260 (if present) may cover a major portion (e.g., equal to or greater than 60%, 70%, 80%, or 90%) of the area of ​​the second side 140B of the pre-package 140.

[0067] The pre-package 500_1 may further include an insulating cover layer 510. The insulating cover layer 510 is... Figure 5A The structure is shown in a semi-transparent manner. The insulating capping layer 510 may partially cover the drain load structure 160_1, the source load structure 160_2, and / or the gate structure 160_3 to expose these structures 160_1, 160_2, and 160_3 in their uncovered portions. The insulating capping layer 510 may be, for example, a solder stop layer.

[0068] like Figure 5A As shown, the insulating capping layer 510 may, for example, define a strip-shaped uncovered region R1 of the drain load structure 160_1, and / or may, for example, define a strip-shaped uncovered region R2 of the source load structure 160_2. These strip-shaped regions R1, R2 may be designed to align with the desired terminal layout (occupying space) of the semiconductor packages 100, 200, 300 in which the pre-package 500_1 is intended to be integrated.

[0069] If passed Figure 5A As illustrated in the example, the strip regions R1 and R2 can be oriented, for example, perpendicular to the longitudinal extension of the power transistor chip 120.

[0070] Figure 6AThe diagram illustrates another design option for the structured metal layer 160 used in the structured pre-package 500_2. Here, the drain load structure 160_1 and the source load structure 160_2 can be formed in a comb-like manner with interdigitated fingers.

[0071] Furthermore, the strip regions R1 and R2 are not covered by the insulating cover layer 510. The strip regions R1 and R2 are oriented, for example, parallel to the longitudinal extension of the power transistor chip 120.

[0072] The design of the structured metal layer 160 can be selected, for example, depending on the terminal layout of the semiconductor packages 100, 200, 300 in which the pre-packages 500_1, 500_2 are intended to be integrated, and / or may also depend on the geometry (layout) of the load pad array of the power transistor chip 120. For example, given Figure 4 The load pad array layout, Figure 6B The drain load pad 122_1 and source load pad 122_2 (and gate pad 122_3) are highlighted by drawing shading lines to show which drain load pads 122_1 and 122_2 (and gate pad 122_3) are connected to the structured metal layer 160.

[0073] Generally, it is not necessary for each drain load pad 122_1 and / or each source load pad 122_2 to be connected to the structured metal layer 160 via the vertical interconnect 150. For example, as Figure 6B As shown, four of the twelve drain load pads 122_1 and four of the twelve source load pads 122_2 are not connected to the structured metal layer 160. Since these drain and source load pads 122_1, 122_2 are interconnected via in-chip metallization (e.g., conductor strips), the function of the power transistor chip 120 is not affected by some disconnected load pads. However, the better the coverage of the connected load pads 122_1, 122_2, the better the performance of the semiconductor packages 100, 200 at low Ro. DS(on) The better the performance in this aspect.

[0074] In other words, the basic idea to overcome the limitations of distributed chip pad layout is to apply an embedded chip approach, for example, to MV GaN devices as a pre-packaged device. Here, a thick metal layer 160 (e.g., T1 is 35 µm) on the bottom of the embedded chip arrangement can be used for further wiring and merging of source and drain potentials. The original pad layout of the power transistor chip 120 can be preserved (see, for example, [link to relevant documentation]). Figure 4 ).

[0075] Pre-packaged packages can be integrated into standard packages, such as, for example, Joint Electronic Devices Engineering Committee (JEDEC) packages. Figure 7The illustration shows a TOLL (leadless TO) package 700. The JEDEC registration number for the TOLL package 700 is MO-299B. Its dimensions are 10 × 11 × 2.3 mm. It is optimized for high-current applications.

[0076] Figure 7 The pre-packaged carrier 180 is also illustrated by way of example and may include a gate terminal 180_3 of package 700. The gate terminal 180_3 is coupled to the pre-packaged gate structure 160_3.

[0077] Other standard packages that can be integrated into the pre-package according to this disclosure are, for example, TOLG (leaded TO with gull-wing geometry) and TOLT (leaded TO with top-side cooling) packages.

[0078] The TOLG package has a JEDEC registration number of MO-327A. Its dimensions are 10 × 11 × 2.3 mm. This package is optimized for high TCoB performance.

[0079] The TOLT package is registered with JEDEC under registration number MO-332A. Its dimensions are 9.9 × 15 × 2.3 mm. This package is optimized for superior thermal performance.

[0080] Additionally, the pre-packaged formwork according to this disclosure can be integrated into an SSO8 package, see [link to relevant documentation]. Figure 11A and Figure 11B The SSO8 package measures 6.44 × 5.15 × 1.0 mm.

[0081] It should be noted that all these standard packages are designed and optimized for vertical device technology. Consequently, these standard packages rely on strong customer acceptance for reliability and TCoB performance; however, they fail to realize the full technological potential of lateral power transistor chips (e.g., MV GaN) at the package level. In one aspect, the pre-packaged concept disclosed herein can be viewed as a way to adapt lateral transistor chips for integration into standard packages designed for vertical devices.

[0082] The concept of integrating the pre-packaged design according to this disclosure into a standard package avoids altering the load pad layout of the power transistor chip 120 by using additional wiring through BEoL metallization. Calculations show that merging the drain and source currents on the BEoL metallization (i.e., at the chip level) will result in R in the final metallization layer DS(on) The resistance increases from approximately 0.14 mΩ to 1.7 mΩ. This can be avoided by using a pre-encapsulated structured metal layer 160 as the final redistribution layer.

[0083] In addition to the TOLx package or SSO8 package where x = T, L, or G, there are other standard package types in which the pre-package according to this disclosure can be integrated. For example, the pre-package can be integrated into a standard BGA (Ball Grid Array) package, a QFN (Quad Flat No Leads) package, or an LGA (Pad Grid Array) package.

[0084] Furthermore, the pre-packaged components according to this disclosure can be sold independently, meaning they do not need to be integrated into a package but can be sold as is. Even at the customer site, the pre-packaged components do not need to be integrated into a (standard) semiconductor package. Instead, it is also possible to use the pre-packaged components similarly as bare dies or bare die packages, i.e., to mount them directly onto an application board, such as a PCB.

[0085] Pre-packaged Figure 8 and Figure 9 The example shown is in the format of the example. The pre-packaged 800 is in Figure 1 The pre-package used in the semiconductor package 100. The pre-package 900 is respectively in... Figure 2 and Figure 3 The pre-packaged semiconductor packages 200 and 300 are used. In these examples, and generally, the structured metal layer 160 may be the only off-chip metal layer of the pre-packaged 800, 900 in a direction away from the first side 120A of the power transistor chip 120. Refer to the previous description to avoid repetition.

[0086] Figure 10A This is a perspective top view of the power transistor chip 120. The power transistor chip 120 has, as shown in the image... Figure 4 The load pad layout shown is as follows: the plurality of source load pads and the plurality of drain load pads are arranged in an interdigitated load pad array.

[0087] Figure 10B The illustration shows pre-package 1000. Pre-package 100, or "inlay," largely depends on... Figure 6A The pre-package 500_2 shown is designed as follows. It is divided into a drain load structure 160_1, a source load structure 160_2, and a gate structure 160_3 via a structured metal layer 160. The drain load structure 160_1 and the source load structure 160_2 extend along the longitudinal side of the power transistor chip 120. The pre-package (laminated) 140 is shown as transparent, and the insulating capping layer 510 is shown as translucent.

[0088] Figure 10C Diagram and Figure 10B The same pre-package 1000, however, in which the structured metal layer 160, rather than the insulating cover layer 510, is shown as transparent.

[0089] Figure 10D The diagram shows a metal layer 260 disposed on the second side 140B of the pre-packaged body 140, which is shown as transparent.

[0090] Figure 11A The illustration uses a pre-package 1000 as an inlay within an SSO8 standard semiconductor package 1110. The pre-package 1000 is flip-chip, and the sealant 190 of the semiconductor package 1100 is shown as translucent. The semiconductor package 1100 includes a drain terminal 180_1 (e.g., formed as a plate or paddle) and a source terminal 180_2 (e.g., formed as a plate or paddle). Although the integration of the pre-package 1000 within the semiconductor package 1100 differs from standard chip integration in an SSO8 package, the footprint of the semiconductor package 1100 can be the same as that of a standard SSO8 semiconductor package because clips are not used, and the pre-package 1000 is implemented in a flip-chip orientation within the semiconductor package 1100.

[0091] Figure 11B The figure shows a top view of a semiconductor package 1100, in which a sealant 190 is embedded in the semiconductor package 1100 pre-packaged 1000.

[0092] In all the examples disclosed herein, transistor chip 120 may be capable of switching high current and / or medium or high voltage, for example. Specifically, exemplary transistor packages 100, 200, 300, 700, and 1100 disclosed herein can operate in a medium voltage (MV) range, wherein the blocking voltage is equal to or greater than or less than 200 V or 150 V or 100 V or 50 V. Power transistor chip 120 operating in the MV range can be manufactured with very low Ro. DS(on) This results in a significant increase in package interconnect resistance to the overall package R. DS(on) The pre-packaged concept disclosed in this paper enables the maintenance of a very low Ro in the power transistor chip 120. DS(on) This makes it possible and simultaneously provides cost-effective and space-saving techniques for integrating the power transistor chip 120 into a package, particularly a standard package.

[0093] Example The following examples relate to other aspects of this disclosure: Example 1 is a power transistor chip package comprising: a prepackage; a prepackage carrier on which the prepackage is mounted; and a sealant for embedding the prepackage and the prepackage carrier. The prepackage includes a power transistor chip having a first side and a second side opposite to the first side. The power transistor chip is a lateral semiconductor device. A plurality of source load pads and a plurality of drain load pads are arranged on the first side of the power transistor chip. The prepackage embeds the power transistor chip at least on the first side of the power transistor chip, the first side of the prepackage facing away from the first side of the power transistor chip. A structured metal layer is disposed above the first side of the prepackage. The structured metal layer includes a continuous source load structure and a continuous drain load structure. Prepackage vertical interconnects extend through the material of the prepackage and are configured to connect at least some of the source load pads to the source load structure and at least some of the drain load pads to the drain load structure. The prepackage is mounted on the prepackage carrier, wherein the structured metal layer faces the prepackage carrier.

[0094] In Example 2, the subject of Example 1 may optionally include a pre-packaged carrier that is a lead frame.

[0095] In Example 3, the subject matter of Example 1 or 2 may optionally include a semiconductor package in which the semiconductor package is a standard Joint Electronic Devices Engineering Committee (JEDEC) package, particularly a TOLx package in which x = T, L, or G, or an SSO8 package.

[0096] In Example 4, the subject of any of the preceding examples may optionally include that the power transistor chip is a GaN transistor chip.

[0097] In Example 5, the subject of any of the preceding examples may optionally include that the pre-packaged body is a laminate.

[0098] In Example 6, the subject matter of any of the preceding Examples 1 to 4 may optionally include a pre-packaged body that is a molded compound body.

[0099] In Example 7, the subject matter of any of the preceding examples may optionally include a structured metal layer that is a plated metal layer with a thickness between 25 µm and 105 µm or between 35 µm and 70 µm.

[0100] In Example 8, the subject of any of the preceding examples may optionally include the plurality of source load pads and the plurality of drain load pads arranged in an interdigitated load pad array.

[0101] In Example 9, the subject matter of any of the preceding examples may optionally include a pre-packaged vertical interconnect comprising: a plurality of vertical source interconnect structures extending through the material of the pre-package and configured to connect at least some of the source load pads to the source load structure; and a plurality of vertical drain interconnect structures extending through the material of the pre-package and configured to connect at least some of the drain load pads to the drain load structure.

[0102] In Example 10, the subject matter of any of the preceding examples may optionally include that the sealant is a molding sealant.

[0103] Example 11 is a prepackage comprising: a power transistor chip having a first side and a second side opposite to the first side, the power transistor chip being a lateral semiconductor device; a plurality of source load pads and a plurality of drain loads disposed on the first side of the power transistor chip; a prepackage body embedding the power transistor chip at least on the first side of the power transistor chip, the first side of the prepackage body being opposite to the first side of the power transistor chip; a structured metal layer disposed above the first side of the prepackage body, the structured metal layer including a continuous source load structure and a continuous drain load structure; and a prepackaged vertical interconnect extending through the material of the prepackage body and configured to connect at least some of the source load pads to the source load structure and at least some of the drain load pads to the drain load structure.

[0104] In Example 12, the subject of Example 11 may optionally include the plurality of source load pads and the plurality of drain load pads arranged in an interdigitated load pad array.

[0105] In Example 13, the subject matter of Example 11 or 12 may optionally further include a metal layer disposed above a second side of the power transistor chip.

[0106] In Example 14, the subject matter of Example 13 may optionally further include a pre-packaged body embedding the power transistor chip at a second side of the power transistor chip, the second side of the pre-packaged body being opposite to the second side of the power transistor chip, and a metal layer disposed above the second side of the pre-packaged body.

[0107] In Example 15, the subject matter of Example 14 may optionally further include a metal layer coupled to a second side of a power transistor chip via an array of vertical interconnect structures.

[0108] In Example 16, the subject matter of any of the examples 13 to 15 may optionally include a plated metal layer with a thickness between 25 µm and 105 µm or between 35 µm and 70 µm.

[0109] In Example 17, the subject matter of any of the examples 13 through 16 may optionally include a structured metal layer that is the only off-chip metal layer pre-packaged in a direction away from the first side of the power transistor chip.

[0110] Although specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that various alternatives and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the invention be limited only by the claims and their equivalents.

Claims

1. A semiconductor package, comprising: Pre-packaged; Pre-packaged carrier, pre-packaged and mounted on the pre-packaged carrier; as well as A sealant for embedding pre-encapsulation and pre-encapsulated carriers, wherein the pre-encapsulation includes A power transistor chip having a first side and a second side opposite to the first side; the power transistor chip is a lateral semiconductor device. Multiple source load pads and multiple drain load pads are arranged on the first side of the power transistor chip; At least on the first side of the power transistor chip, a pre-package of the power transistor chip is embedded, and the first side of the pre-package is opposite to the first side of the power transistor chip; A structured metal layer is disposed above the first side of the pre-packaged body. The structured metal layer includes a continuous source load structure and a continuous drain load structure. as well as A pre-packaged vertical interconnect extends through the material of the pre-package and is configured to connect at least some of the source load pads to the source load structure and at least some of the drain load pads to the drain load structure. in The pre-packaged component is mounted on a pre-packaged carrier, with a structured metal layer facing the pre-packaged carrier.

2. The semiconductor package according to claim 1, wherein the pre-packaged carrier is a lead frame.

3. The semiconductor package according to claim 1 or 2, wherein the semiconductor package is a Joint Electronic Devices Engineering Committee (JEDEC) package, particularly a TOLx package in which x = T, L, or G, or an SSO8 package.

4. The semiconductor package according to any one of the preceding claims, wherein the power transistor chip is a GaN transistor chip.

5. The semiconductor package according to any one of the preceding claims, wherein the pre-package is a laminate.

6. The semiconductor package according to any one of claims 1 to 4, wherein the pre-package body is a molded compound body.

7. The semiconductor package according to any one of the preceding claims, wherein the structured metal layer is a plated metal layer with a thickness between 25 µm and 105 µm or between 35 µm and 70 µm.

8. The semiconductor package according to any one of the preceding claims, wherein the plurality of source load pads and the plurality of drain load pads are arranged in an interdigitated load pad array.

9. The semiconductor package according to any one of the preceding claims, wherein the pre-packaged vertical interconnect comprises: Multiple vertical source interconnect structures extend through the material of the pre-package and are configured to connect at least some of the source load pads to the source load structure; as well as Multiple vertical drain interconnect structures extend through the material of the pre-package and are configured to connect at least some of the drain load pads to the drain load structure.

10. The semiconductor package according to any one of the preceding claims, wherein the sealant is a molding sealant.

11. A pre-packaged product comprising: A power transistor chip having a first side and a second side opposite to the first side; the power transistor chip is a lateral semiconductor device. Multiple source load pads and multiple drain loads are arranged on the first side of the power transistor chip; At least on the first side of the power transistor chip, a pre-package of the power transistor chip is embedded, and the first side of the pre-package is opposite to the first side of the power transistor chip; A structured metal layer is disposed above the first side of the pre-packaged body. The structured metal layer includes a continuous source load structure and a continuous drain load structure. as well as A pre-packaged vertical interconnect extends through the material of the pre-package and is configured to connect at least some of the source load pads to the source load structure and at least some of the drain load pads to the drain load structure.

12. The pre-package of claim 11, wherein the plurality of source load pads and the plurality of drain load pads are arranged in an interdigitated load pad array.

13. The pre-packaged according to claim 11 or 12, further comprising: A metal layer disposed on the second side above the power transistor chip.

14. The prepackage according to claim 13, wherein the power transistor chip is embedded in the prepackage body on the second side of the power transistor chip, the second side of the prepackage body is opposite to the second side of the power transistor chip, and a metal layer is disposed above the second side of the prepackage body.

15. The pre-package of claim 14, wherein the metal layer is coupled to a second side of the power transistor chip via a vertical interconnect structure array.

16. The pre-package according to any one of claims 13 to 15, wherein the metal layer is a plated metal layer with a thickness between 25 µm and 105 µm or between 35 µm and 70 µm.

17. The prepackage according to any one of claims 13 to 16, wherein the structured metal layer is the only off-chip metal layer of the prepackaged in the direction away from the first side of the power transistor chip.

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