Chip package structure and packaging method

Abstract

The chip packaging structure and the packaging method provided by the embodiments of the present disclosure can realize precise liquid cooling heat dissipation of the local hotspot area of the chip, greatly shorten the heat dissipation path, make the heat dissipation more direct and more targeted, and improve the heat dissipation level of the chip at the maximum power peak. The micro flow channel and the flip chip structure are integrated in the same packaging body, and no external heat sink is needed, which is conducive to the miniaturization of the packaging and the improvement of the system integration. Meanwhile, the micro flow channel structure is integrally formed, which avoids the weak interface problem caused by the layered sealing preparation of the traditional micro flow channel, and has high overall structural stability and strong pressure resistance. The micro flow channel only needs to be arranged in a single-layer organic interposer, and complex alignment between multiple micro flow channels is not needed, thereby improving the reliability of the packaging structure.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductor packaging technology, specifically relating to a chip packaging structure and packaging method. Background Technology

[0002] Artificial intelligence requires massive computing power, which in turn consumes a significant amount of energy. The greater the computing power of a single chip, the higher its energy consumption. Current chip power consumption is already in the 2000W range, and it will be even higher in the future. The greater the power consumption, the greater the heat generated, requiring stronger heat dissipation capabilities. To improve heat dissipation performance, the industry has begun using microfluidic liquid cooling technology, which involves creating microchannels on the back of the chip to rapidly remove heat through liquid flow.

[0003] Current microfluidic designs on the back of chips are helpful in improving heat dissipation, but they still have some shortcomings. The main issue is that high-performance chips are packaged using flip-chip technology, with the circuit layer on the front and facing down. Since the heat source is on the circuit layer, the microfluidic channels need to dissipate heat through the chip itself. The chip's thickness affects heat dissipation, especially since the chip doesn't heat up uniformly and has hot spots. Back-side heat dissipation is more like surface-level heat dissipation for these hot spots, lacking specificity. Furthermore, in future 3D stacked packaging, the heat dissipation path between the back microfluidic channels and the front of the chip involves multiple chips and multiple interfaces, making the heat dissipation path even more complex.

[0004] To address the aforementioned issues, it is necessary to propose a chip packaging structure and packaging method that is reasonably designed and effectively solves these problems. Summary of the Invention

[0005] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a chip packaging structure and packaging method.

[0006] One aspect of this disclosure provides a chip packaging structure, including: substrate; An organic intermediary is disposed on the substrate, the organic intermediary including a first molding layer encapsulating a plurality of first chips and a plurality of conductive pillars disposed at thickness intervals through the first molding layer. Microchannels are disposed within the organic mediator; A redistribution layer is disposed on the side of the organic intermediate facing away from the substrate, wherein the redistribution layer is connected to the microchannel; Multiple second chips are flip-chip mounted on the redistribution layer, wherein the hot spot area of ​​the second chips is connected to the microchannel through the redistribution layer; The second molding layer encapsulates multiple second chips; wherein the second molding layer and the redistribution layer are respectively provided with inlet pipe interfaces and outlet pipe interfaces at the corresponding microchannel inlet and microchannel outlet.

[0007] Optionally, the microchannels are fabricated using a 3D printing process.

[0008] Optionally, the microchannels are S-shaped with their ends connected.

[0009] Optionally, the cross-section of the microchannel is square.

[0010] Optionally, the microchannel is based on copper alloy, and the width and height of the hollow space inside the microchannel are both greater than 20 μm.

[0011] Optionally, the second molding layer and the redistribution layer are respectively provided with a first chamber and a second chamber at the corresponding microchannel inlet and microchannel outlet; The first chamber and the second chamber are respectively provided with the inlet pipe interface and the outlet pipe interface; wherein, the inlet pipe interface is connected to the microchannel inlet, and the outlet pipe interface is connected to the microchannel outlet.

[0012] Optionally, a sealant layer is provided in the first chamber and the second chamber, the sealant layer filling the space between the first chamber and the inlet pipe interface, and filling the space between the second chamber and the outlet pipe interface.

[0013] Optionally, multiple second chips are connected to the redistribution layer via thermal bumps; The redistribution layer includes a metal layer and a dielectric layer arranged at intervals in sequence, and the metal layer is connected to the microchannel.

[0014] Optionally, the organic intermediate further includes a wiring layer disposed on the side of the first molding layer facing the substrate, and the wiring layer is provided with a plurality of conductive bumps; The organic mediator is disposed on the substrate via the conductive bumps.

[0015] Another aspect of this disclosure provides a chip packaging method for preparing the chip packaging structure described above; the packaging method includes: Provides prefabricated, one-piece molded microchannels and temporary carrier plates; Multiple conductive pillars are formed on the temporary carrier plate, and multiple first chips and the microchannel are mounted and fixed on the temporary carrier plate. A first molding layer is formed to encapsulate the plurality of conductive pillars, the plurality of first chips, and the microchannels to form an organic intermediary; A redistribution layer is formed on the surface of the organic mediator; Multiple second chips are flip-chip connected to the redistribution layer, wherein the hot spot area of ​​the second chip is connected to the microchannel through the redistribution layer; A second molding layer is formed to encapsulate multiple second chips; The thickness of the second molding layer and the redistribution layer respectively forms a first chamber and a second chamber, wherein the first chamber is connected to the microchannel inlet and the second chamber is connected to the microchannel outlet; An inlet pipe interface and an outlet pipe interface are respectively installed in the first chamber and the second chamber.

[0016] The chip packaging structure and method disclosed herein feature a packaging structure in which microchannels are embedded within an organic intermediary. A redistribution layer directly thermally connects the hot spot area of ​​the second chip to the microchannels, allowing coolant to flow precisely through the area of ​​highest heat concentration on the chip. This achieves precise liquid cooling of the local hot spot area, significantly shortening the heat dissipation path and making heat dissipation more direct and targeted, thus improving the chip's heat dissipation level at maximum power peak. The microchannels and the flip-chip structure are integrated within the same package, eliminating the need for an external heat sink, which is beneficial for miniaturization and improved system integration. Furthermore, the use of a one-piece molded microchannel structure avoids the interface weakness issues associated with traditional layered microchannel sealing, resulting in high overall structural stability and strong pressure resistance. Only a single-layer organic intermediary is required for the microchannels, eliminating the need for complex alignment between multiple microchannels, thereby improving the reliability of the packaging structure. Attached Figure Description

[0017] Figure 1 This is a cross-sectional view of a chip packaging structure according to one embodiment of the present disclosure; Figure 2 This is a top view of a chip packaging structure according to another embodiment of this disclosure, wherein, Figure 1 for Figure 2 Sectional view along line A-A'; Figure 3 for Figure 2 B-B' cross-sectional view of the chip packaging structure; Figure 4 This is a top view of a microchannel according to another embodiment of this disclosure.

[0018] Figure 5 This is a schematic flowchart of a chip packaging method according to another embodiment of this disclosure; Figures 6 to 16 This is a schematic diagram of the process of a chip packaging method according to another embodiment of this disclosure. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0020] like Figure 1 As shown, one aspect of this disclosure provides a chip packaging structure 100, including an organic interposer 110, a redistribution layer 120, a microchannel 130, a plurality of second chips 150, a second molding layer 160, and a substrate 170.

[0021] An organic intermediary 110 is disposed on the substrate 170. The organic intermediary 110 includes a first molding compound 113 encapsulating a plurality of first chips 111 and a plurality of conductive pillars 112 disposed at thickness intervals through the first molding compound 113.

[0022] The microchannel 130 is integrally formed within the organic medium 110.

[0023] A redistribution layer 120 is disposed on the side of the organic medium 110 opposite to the substrate 170, wherein the redistribution layer 120 is connected to the microchannel 130.

[0024] Multiple second chips 150 are flip-chip disposed on the redistribution layer 120, wherein the hot spot area of ​​the second chip 150 is connected to the microchannel 130 through the redistribution layer 120.

[0025] like Figure 2 and Figure 3 As shown, the second molding layer 160 encapsulates multiple second chips 150; wherein, the second molding layer 160 and the redistribution layer 120 are respectively provided with an inlet pipe interface 164 and an outlet pipe interface 165 at the corresponding microchannel inlet and microchannel outlet, so as to facilitate reliable access to the external cooling circulation system.

[0026] The chip packaging structure of this disclosure embeds microchannels within an organic intermediary and directly thermally connects the hot spot area of ​​the second chip to the microchannels via a redistribution layer. This allows the coolant to flow precisely through the areas of the chip with the highest heat concentration, achieving precise liquid cooling of local hot spots. This significantly shortens the heat dissipation path, making heat dissipation more direct and targeted, and improving the chip's heat dissipation level at maximum power peak. The microchannels and the flip-chip structure are integrated into the same package, eliminating the need for an external heat sink, which is beneficial for miniaturization and improved system integration. Furthermore, the one-piece molded microchannel structure avoids the interface weakness problem caused by traditional layered sealing fabrication of microchannels, resulting in high overall structural stability and strong pressure resistance. Only a single-layer organic intermediary is needed for the microchannels, eliminating the need for complex alignment between multiple microchannels, thus improving the reliability of the packaging structure.

[0027] For example, in this embodiment, the microchannels are fabricated using a 3D printing process.

[0028] In this embodiment, the microchannel 130 can be fabricated using 3D printing. Using 3D printing to fabricate the microchannel 130 results in high forming precision and good integration, eliminating the need for subsequent bonding or sealing treatments. This fundamentally eliminates the problems of inadequate sealing or delamination at multi-layer interfaces under pressure, further improving the long-term reliability of the microchannel under high-pressure coolant conditions. It should be noted that the microchannel 130 can also be pre-fabricated using other processes; this embodiment does not impose specific limitations, and the appropriate process can be selected based on actual needs.

[0029] For example, such as Figure 4 As shown in this embodiment, the microchannels are S-shaped with their ends connected. The S-shaped microchannels allow them to repeatedly pass through multiple hot spots under the chip, extending the contact time between the coolant and the microchannel walls, thereby removing more heat. The S-shaped curved channels can enhance the local turbulence effect, improve the convective heat transfer coefficient, and further enhance the heat dissipation capacity. The S-shaped microchannel layout can achieve multi-pass coverage of the chip's hot spots, avoiding the problem of uneven cooling from a single channel.

[0030] For example, such as Figure 1 As shown, in this embodiment, the microchannel 130 has a square cross-section. Compared to a circular cross-section, a square cross-section channel has a larger specific surface area for the same hydraulic diameter, which is beneficial for the transfer of heat from the channel wall to the coolant. Furthermore, the square channel exhibits uniform stress distribution when subjected to internal fluid pressure, further enhancing the structural stability and heat dissipation uniformity of the channel.

[0031] For example, in this embodiment, the microchannel 130 is based on copper alloy, and the width and height of the hollow space inside the microchannel are both greater than 20μm.

[0032] In this embodiment, the microchannel uses copper alloy as the base material. Copper alloy has excellent thermal conductivity and mechanical strength, and as the channel wall material, it can quickly conduct the transferred heat to the internal coolant. At the same time, the channel size with an internal space of more than 20μm ensures low flow resistance of the coolant and is compatible with the current mainstream micromachining precision, which is convenient for mass production. In addition, the thick channel wall gives it good pressure resistance, which can adapt to high pressure and high speed liquid cooling conditions and is not easy to deform or break.

[0033] For example, such as Figure 2 and Figure 3As shown, the second molding layer 160 and the redistribution layer 120 are respectively provided with a first chamber 161 and a second chamber 162 at the corresponding microchannel inlet and microchannel outlet; the first chamber 161 and the second chamber 162 are respectively provided with an inlet pipe interface 164 and an outlet pipe interface 165; wherein, the inlet pipe interface 164 is connected to the microchannel inlet, and the outlet pipe interface 165 is connected to the microchannel outlet.

[0034] The coolant is delivered to the inlet pipe interface 164 through the inlet pipe, and then enters the microchannel 130 through the microchannel inlet. After heat exchange, it enters the outlet pipe interface 165 through the microchannel outlet and flows out through the outlet pipe, thus completing the heat exchange process.

[0035] In this embodiment, independent first and second chambers are provided, offering ample installation space and positioning references for the inlet and outlet pipe interfaces, facilitating subsequent pipe sealing and connection operations. The inlet pipe interface is connected to the microchannel inlet, and the outlet pipe interface is connected to the microchannel outlet, ensuring that the coolant flows completely through all microchannel paths without the risk of bypass leakage. The inlet and outlet pipe interfaces are integrated within the package, eliminating the need for additional substrate surface space and contributing to the miniaturization of the overall package size.

[0036] For example, such as Figure 2 and Figure 3 As shown, a sealant layer 163 is provided in the first chamber 161 and the second chamber 162. The sealant layer 163 fills the space between the first chamber 161 and the inlet pipe interface 164, and fills the space between the second chamber 162 and the outlet pipe interface 165.

[0037] In this embodiment, by setting a sealing layer, the sealing connection between the external coolant pipeline and the internal microchannel is ensured, preventing the risk of electrical short circuit caused by coolant leakage. At the same time, it provides structural buffer at the interface, reducing the interface stress caused by temperature changes or vibration.

[0038] For example, such as Figure 1 and Figure 3 As shown, multiple second chips 150 are connected to the redistribution layer 120 via thermal bumps 151; the redistribution layer 120 includes a metal layer and a dielectric layer arranged at intervals in sequence, and the metal layer is connected to the microchannel 130. The number of metal layers and dielectric layers is not specifically limited in this embodiment and can be selected according to actual needs.

[0039] In this embodiment, the thermal bumps serve both as electrical signal interconnects and as heat conduction pathways to directly transfer heat from the hot spots of the second chip to the metal layer of the redistribution layer, and then to the microchannels, achieving integrated electrothermal interconnection. This constructs an ultra-short heat conduction path from the heat source to the coolant, making heat dissipation more direct and targeted, and improving the chip's heat dissipation level at maximum power peak.

[0040] For example, such as Figure 1 As shown, the organic interposer 110 further includes a wiring layer 114 disposed on the side of the first molding layer 113 facing the substrate 170, and the wiring layer 114 is provided with a plurality of conductive bumps 115; the organic interposer 110 is disposed on the substrate 170 through the conductive bumps 115. As shown, a plurality of solder balls 180 are disposed on the side of the substrate 170 opposite to the organic interposer 110, and the signals of the entire package structure are led out through the plurality of solder balls 180.

[0041] In this embodiment, the organic intermediate is flip-chip mounted on the substrate via conductive bumps, enabling vertical interconnection of electrical signals between the package and the external system. The interconnection path is short and the parasitic parameters are small, which is beneficial for high-frequency signal transmission. The wiring layer is disposed at the bottom of the organic intermediate, separated from the upper redistribution layer and microchannel layer. The electrical signal transmission path is physically isolated from the coolant flow path, avoiding interference from the liquid cooling system on electrical performance. The conductive bump array provides mechanical support and stress buffering, improving the connection reliability between the package and the substrate.

[0042] For example, such as Figure 1 As shown, an underfill layer covering the thermal bumps 151 is provided between the second chip 150 and the redistribution layer 120 to further fix the second chip 150. An underfill layer covering multiple conductive bumps 115 is provided between the organic interposer 110 and the substrate 170 to further fix the organic interposer 110.

[0043] like Figure 5 As shown, this embodiment of the present disclosure provides a chip packaging method S100, the packaging method including: S110 provides prefabricated, one-piece molded microchannels and temporary carrier plates.

[0044] like Figure 6 As shown, a prefabricated, integrally formed microchannel 130 and a temporary carrier plate B are provided. A temporary bonding layer is attached to the surface of the temporary carrier plate B.

[0045] In this embodiment, the microchannel 130 can be fabricated using 3D printing. Using 3D printing to fabricate the microchannel 130 results in high forming precision and excellent integration, eliminating the need for subsequent bonding or sealing. This fundamentally eliminates the problems of inadequate sealing or delamination at multi-layer interfaces under pressure, further improving the long-term reliability of the microchannel under high-pressure coolant conditions. The microchannel 130 can also be pre-fabricated using other processes; this embodiment does not impose specific limitations and the choice can be made according to actual needs.

[0046] S120. Multiple conductive pillars are formed on the temporary carrier plate, and multiple first chips and the microchannel are mounted and fixed on the temporary carrier plate.

[0047] like Figure 6 As shown, multiple conductive pillars 112 are formed on the temporary bonding layer of the temporary carrier B using an electroplating process. The conductive pillars 112 can be copper pillars. The conductive pillars 112 enable vertical electrical interconnection between upper and lower layers, reducing the package size.

[0048] like Figure 6 As shown, multiple first chips 111 and pre-fabricated microchannels 130 are mounted and fixed to the temporary bonding layer of the temporary carrier board B.

[0049] S130, A first molding layer is formed to encapsulate the plurality of conductive pillars, the plurality of first chips and the microchannels to form an organic intermediary.

[0050] like Figure 7 As shown, a first molding compound 113 is formed on a temporary carrier board B. The first molding compound 113 encapsulates a plurality of conductive pillars 112, a plurality of the first chips 111, and the microchannels 130 to form an organic intermediate 110. The microchannels 130 are encapsulated within the first molding compound 113. In this step, only the pre-fabricated microchannels need to be mounted inside a single-layer organic intermediate, eliminating the need for complex alignment processes between multiple channels, simplifying the process and improving process yield and reliability.

[0051] For example, after forming the first molding layer 113, the method further includes: like Figure 8 As shown, a wiring layer 114 is formed on the side of the first molding layer 111 opposite to the temporary carrier plate B; a plurality of conductive bumps 115 are formed on the wiring layer 114. That is, the organic medium 110 also includes the wiring layer 114 and the conductive bumps 115. Then, the temporary carrier plate B is removed, the organic medium 110 is inverted, and the plurality of conductive bumps 115 are fixed to the temporary glass carrier plate A. Then, other encapsulation structures are formed on the side of the first molding layer 111 opposite to the conductive bumps 115.

[0052] S140, A redistribution layer is formed on the surface of the organic medium.

[0053] like Figure 9 As shown, a redistribution layer 120 is formed on the side of the first molding layer 111 opposite to the conductive bump 115. The redistribution layer 120 increases the interconnect density of the chip.

[0054] In this embodiment, the redistribution layer 120 includes multiple layers of metal and dielectric layers spaced apart. The specific process can be as follows: first, a bottom metal layer is formed on the surface of the organic intermediate 110, wherein the bottom metal layer is connected to the conductive pillars 112 and the microchannels 130; then, a bottom dielectric layer is formed on the bottom metal layer; then, multiple layers of spaced intermediate metal and dielectric layers are formed on the bottom dielectric layer; finally, a top metal layer and a top dielectric layer are formed. It should be noted that the number of metal and dielectric layers in the redistribution layer 120 is not specifically limited and can be selected according to actual needs.

[0055] S150. A plurality of second chips are flip-chip connected to the redistribution layer, wherein the hot spot area of ​​the second chips is connected to the microchannel through the redistribution layer.

[0056] like Figure 10 As shown, multiple second chips 150 are flip-chip mounted to the opening of the uppermost dielectric layer of the redistribution layer 120 via thermal bumps 151, and electrically connected to the uppermost metal layer of the redistribution layer 120. Hot spots of the second chips 150 are connected to the microchannel 130 via thermal bumps 151 and the metal layer of the redistribution layer 120. Figure 6 As shown, an underfill layer is formed between the second chip 150 and the redistribution layer 120 to enclose the thermal bumps. The underfill layer encloses the thermal bumps, providing physical support and protecting the reliability of the bump connection.

[0057] In this step, the hot spots of the second chip are directly connected to the microchannels via thermal bumps and a redistribution layer, creating an ultra-short thermal path from the heat source to the coolant. The thermal bumps themselves are made of a highly thermally conductive metal material, which can rapidly conduct the heat generated in the local hot spots of the chip to the metal layer of the redistribution layer, and then further to the microchannels, where it is directly carried away by the flowing coolant. This makes heat dissipation more direct and targeted, improving the chip's heat dissipation level at maximum power peak.

[0058] S160, A second molding compound is formed to encapsulate the plurality of the second chips.

[0059] like Figure 10 As shown, a second molding compound 160 is formed on the surface of the redistribution layer 120, which encapsulates a plurality of the second chips 150. The second molding compound 160 protects the second chips 150.

[0060] For example, after forming the second molding layer 160, the method further includes: like Figure 11 As shown, the temporary glass substrate A can be removed using a laser debonding method. The completed wafer is then diced to form multiple independent intermediate packages. Figure 12 As shown, the intermediate package is connected to the substrate 170 via multiple conductive bumps 115, and an underfill layer is formed between the conductive bumps 115 and the substrate 170. Multiple solder balls 180 are formed on the side of the substrate 170 opposite to the chip package. Signals from the entire package structure are extracted via the solder balls 180.

[0061] S170. The thickness of the second molding layer and the redistribution layer respectively forms a first chamber and a second chamber, wherein the first chamber is connected to the microchannel inlet and the second chamber is connected to the microchannel outlet.

[0062] like Figure 13 and Figure 14 As shown, the second molding layer 160 and the redistribution layer 120 at the microchannel inlet and microchannel outlet are etched along the thickness direction to form the first chamber 161 and the second chamber 162 respectively, exposing the top wall of the microchannel 130.

[0063] like Figure 16 As shown, a laser is used to remove the top wall of the microchannel at the inlet and outlet of the microchannel, so that the first chamber 161 and the second chamber 162 are respectively connected to the inlet and outlet of the microchannel 130.

[0064] In this step, by first etching the first and second chambers on the second molding layer and the redistribution layer to expose the top wall of the microchannel, and then using a laser to remove the top wall of the microchannel, the connection port between the microchannel and the external coolant circulation system can be accurately opened without damaging the surrounding redistribution and other chip structures. This ensures the accuracy of the connection between the channel system and the external pipeline and the cleanliness of the sealed area.

[0065] S180. Install an inlet pipe interface and an outlet pipe interface in the first chamber and the second chamber, respectively.

[0066] like Figure 15 and Figure 16As shown, the inlet pipe interface 164 and the outlet pipe interface 165 are respectively installed in the first chamber 161 and the second chamber 162; then, a sealant layer 163 is filled between the first chamber 161 and the inlet pipe interface 164, and between the second chamber 162 and the outlet pipe interface 165. The inlet pipe interface 164 is connected to the inlet pipe, and the outlet pipe interface 165 is connected to the outlet pipe. The coolant is delivered to the inlet pipe interface 164 through the inlet pipe, enters the microchannel 130 through the microchannel inlet, undergoes heat exchange, enters the outlet pipe interface 165 through the microchannel outlet, and flows out through the outlet pipe, completing the heat exchange process.

[0067] By filling the space between the first chamber and the inlet pipe interface, and between the second chamber and the outlet pipe interface, a reliable sealed connection between the microchannel inlet / outlet and the external liquid cooling circulation system is achieved. The sealant filling the chambers completely seals the gaps between the pipe interface and the plastic sealant layer and copper wall, effectively preventing coolant leakage from the interface during high-pressure flow, thus improving the overall fluid sealing safety and long-term stability of the package.

[0068] The chip packaging method of this disclosure achieves precise liquid cooling of local hot spots in the chip by attaching a pre-fabricated, integrally formed microchannel inside an organic intermediate and directly connecting the hot spots of the second chip to the microchannel using a redistribution layer. This significantly shortens the heat dissipation path, making heat dissipation more direct and targeted, improving the chip's heat dissipation level at maximum power peak, and avoiding the inefficient problem of heat needing to pass through the entire chip substrate to dissipate. At the same time, the use of a pre-fabricated, integrally formed microchannel structure avoids the interface weakness problem caused by traditional microchannel layered sealing preparation, resulting in high overall structural stability and strong pressure resistance. The entire microchannel is built into the organic intermediate, eliminating the need for an external heat sink, which is beneficial for miniaturization and high-density integration of the package. In addition, this method only requires attaching the pre-fabricated microchannel within a single layer of organic intermediate, eliminating the need for complex alignment processes between multiple channels, simplifying the process, and improving process yield and reliability.

[0069] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the embodiments of this disclosure, and the embodiments of this disclosure are not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of this disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of this disclosure.

Claims

1. A chip packaging structure, characterized in that, include: substrate; An organic intermediary is disposed on the substrate, the organic intermediary including a first molding layer encapsulating a plurality of first chips and a plurality of conductive pillars disposed at thickness intervals through the first molding layer. Microchannels are integrally formed and disposed within the organic mediator; A redistribution layer is disposed on the side of the organic intermediate facing away from the substrate, wherein the redistribution layer is connected to the microchannel; Multiple second chips are flip-chip mounted on the redistribution layer, wherein the hot spot area of ​​the second chips is connected to the microchannel through the redistribution layer; The second molding layer encapsulates multiple second chips; wherein the second molding layer and the redistribution layer are respectively provided with inlet pipe interfaces and outlet pipe interfaces at the corresponding microchannel inlet and microchannel outlet.

2. The chip packaging structure according to claim 1, characterized in that, The microchannels are fabricated using 3D printing technology.

3. The chip packaging structure according to claim 1, characterized in that, The microchannels are S-shaped with their ends connected.

4. The chip packaging structure according to claim 1, characterized in that, The microchannel has a square cross-section.

5. The chip packaging structure according to claim 1, characterized in that, The microchannel is based on copper alloy, and the width and height of the hollow space inside the microchannel are both greater than 20 μm.

6. The chip packaging structure according to claim 1, characterized in that, The second molding layer and the redistribution layer are respectively provided with a first chamber and a second chamber at the corresponding microchannel inlet and microchannel outlet; The first chamber and the second chamber are respectively provided with the inlet pipe interface and the outlet pipe interface; wherein, the inlet pipe interface is connected to the microchannel inlet, and the outlet pipe interface is connected to the microchannel outlet.

7. The chip packaging structure according to claim 6, characterized in that, A sealant layer is provided in the first chamber and the second chamber, the sealant layer filling the space between the first chamber and the inlet pipe interface, and filling the space between the second chamber and the outlet pipe interface.

8. The chip packaging structure according to claim 1, characterized in that, Multiple second chips are connected to the redistribution layer via thermal bumps; The redistribution layer includes a metal layer and a dielectric layer arranged at intervals in sequence, and the metal layer is connected to the microchannel.

9. The chip packaging structure according to claim 1, characterized in that, The organic intermediate further includes a wiring layer disposed on the side of the first molding layer facing the substrate, and the wiring layer is provided with a plurality of conductive bumps. The organic mediator is disposed on the substrate via the conductive bumps.

10. A chip packaging method, characterized in that, The method is used to prepare the chip packaging structure according to any one of claims 1 to 9; the packaging method includes: Provides prefabricated, one-piece molded microchannels and temporary carrier plates; Multiple conductive pillars are formed on the temporary carrier plate, and multiple first chips and the microchannel are mounted and fixed on the temporary carrier plate. A first molding layer is formed to encapsulate the plurality of conductive pillars, the plurality of first chips, and the microchannels to form an organic intermediary; A redistribution layer is formed on the surface of the organic mediator; Multiple second chips are flip-chip connected to the redistribution layer, wherein the hot spot area of ​​the second chip is connected to the microchannel through the redistribution layer; A second molding layer is formed to encapsulate multiple second chips; The thickness of the second molding layer and the redistribution layer respectively forms a first chamber and a second chamber, wherein the first chamber is connected to the microchannel inlet and the second chamber is connected to the microchannel outlet; An inlet pipe interface and an outlet pipe interface are respectively installed in the first chamber and the second chamber.

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