Chip package structure and high-temperature curing method of chip package structure

Abstract

The application provides a chip packaging structure and a high-temperature curing method of the chip packaging structure. The chip packaging structure comprises a frame and a plastic packaging part. The surface of the frame comprises a base island area and a pin area. The base island area is located at the center of the frame and is used for mounting a chip. The pin area is arranged around the base island area and is used for electrically connecting the chip through a bonding wire. A groove is arranged in the base island area and surrounds the chip. The plastic packaging part is arranged on the frame and is used for covering the base island area, the pin area and the chip. The chip packaging structure provided by the application can reduce the influence of high temperature on the warping degree of the chip packaging structure by arranging the chip in the center and arranging the groove on the frame to form a reverse stress supplement.

Description

Technical Field

[0001] This application relates to the field of chip testing, and in particular to a chip packaging structure and a high-temperature curing method for the chip packaging structure. Background Technology

[0002] Chip packaging is the process of fixing a bare die onto a frame through processes such as mounting, bonding, and molding, and then wrapping it with molding compound for protection. Pins for input and output are brought out, thus forming a complete device that provides mechanical support, electrical connection, heat dissipation protection, and environmental isolation for the bare die. It is a bridge between the chip and the external circuit (PCB, Printed Circuit Board).

[0003] The QFN (Quad Flat No-lead) package is a square surface-mount package with no exposed leads on all four sides and an exposed pad array on the bottom, offering strong heat dissipation, electrical performance, and reliability. However, existing QFN package structures are prone to warping and deformation during high-temperature heating due to the mismatch in thermal expansion coefficients between the package frame, the chip, and the molding compound. This results in poor pin coplanarity, affecting the yield of subsequent surface mount technology (SMT) applications. Summary of the Invention

[0004] In view of this, the purpose of this application is to propose a chip packaging structure and an aging test method for the test chip, which can reduce the warpage of the chip packaging structure.

[0005] To achieve the above objectives, this application provides a chip packaging structure, comprising:

[0006] chip; A frame, the surface of which includes a base island area and a pin area; the chip is mounted on the base island area; the pin area is arranged around the base island area, and the pin area is provided with pins for electrical connection to the chip via bonding wires; a groove is provided in the base island area, and the groove is at least partially arranged around the chip; A molding compound is disposed on the frame, and the molding compound covers the base island area, the pin area and the chip.

[0007] Furthermore, the grooves are provided in multiple locations, and the multiple grooves are arranged at intervals around the chip.

[0008] Furthermore, the depth of the groove is greater than or equal to 0.05 mm and less than or equal to 0.15 mm.

[0009] Furthermore, a roughened portion is provided between the frame and the encapsulation portion, which is formed by micro-etching on the surface of the frame.

[0010] Furthermore, the encapsulation portion includes a material with high filler content, low shrinkage, and low water absorption; the chip is mounted to the base island region using a die adhesive, which has a low modulus and a low coefficient of thermal expansion.

[0011] This application also provides a high-temperature curing method for a chip packaging structure, applied to the aforementioned chip packaging structure, comprising: The chip packaging structure is placed in an oven, and the oven is heated to a first preset temperature using a stepped heating method. The oven is controlled to perform high-temperature curing of the chip packaging structure at the first preset temperature and the first pressure, and the curing is maintained for the first preset time. The oven temperature is controlled to decrease to a first preset temperature, where the second preset temperature is lower than the first preset temperature. The chip package structure is removed from the oven and then molded.

[0012] Furthermore, the stepped heating method includes: The chip packaging structure is heated within a first temperature range for a first time. The chip packaging structure is heated for a second time within a second temperature range; The chip packaging structure is heated for a third time within a third temperature range, causing the chip packaging structure to heat up to a first preset temperature.

[0013] Furthermore, the first temperature range is greater than or equal to 130°C and less than or equal to 150°C; the first time is greater than or equal to 35s and less than or equal to 40s; the second temperature range is greater than or equal to 150°C and less than or equal to 165°C; the second time is greater than or equal to 25s and less than or equal to 30s; the third temperature range is greater than or equal to 165°C and less than or equal to 175°C; the third time is greater than or equal to 30s and less than or equal to 40s.

[0014] Furthermore, controlling the oven to slowly lower its temperature to a second preset temperature includes: Starting from the first preset temperature, the chip packaging structure is cooled to the second preset temperature at a preset cooling rate and a preset cooling time.

[0015] Furthermore, placing the chip packaging structure in the oven includes: Physical pressure is applied to the chip packaging structure.

[0016] Compared with the prior art, the chip packaging structure provided in this application reduces the impact of high temperature on the warpage of the chip packaging structure by arranging the chip in the center and setting grooves on the frame to form reverse stress compensation. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the chip packaging structure provided in the embodiments of this application; Figure 2 This is a schematic diagram of a chip packaging structure provided in another embodiment of this application; Figure 3 A flowchart illustrating the high-temperature curing method for the chip packaging structure provided in this application embodiment; Figure 4 A flowchart of a high-temperature curing method for a chip packaging structure provided in another embodiment of this application.

[0019] Figure label: 100. Chip packaging structure; 10. Frame; 11. Base island area; 12. Pin area; 13. Groove; 131. First groove; 132. Second groove; 200. Chip. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0021] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0022] Please refer to Figure 1As shown, a chip packaging structure 100 provided in this application is preferably a QFN packaging structure, including: a frame 10 and a molding compound.

[0023] The frame 10 has a square shape in its vertical projection. The surface of the frame 10 has a base island area 11 and a pin area 12. The base island area 11 is located at the center of the frame 10 and is used to mount the chip 200. The pin area 12 surrounds the base island area 11 and has multiple pins, which are electrically connected to the chip 200 via bonding wires. A recess 13 is provided within the base island area 11, at least partially surrounding the chip 200. A molding compound is disposed on the frame 10, covering the base island area 11, the pin area 12, and the chip 200, thereby isolating the base island area 11, the pin area 12, and the chip 200, preventing external moisture from entering the chip package structure 100 and causing chip 200 failure, thus enhancing the reliability of the chip package structure 100.

[0024] The chip packaging structure 100 provided in this application, by centrally arranging the chip 200, symmetrically distributing the base island and pins, and setting a groove 13 on the frame 10 to form a reverse stress supplement, can reduce the impact of high temperature on the warpage of the chip packaging structure 100, and avoid problems such as poor soldering, misalignment, and poor bonding of the chip packaging structure 100 caused by warpage.

[0025] Meanwhile, the chip packaging structure 100 provided in this application only requires adjustments to the internal layout and local structure of the frame 10 through optimized stress structural design, without increasing or decreasing the overall material and external dimensions of the chip packaging structure 100, thus not changing the overall thickness of the chip packaging structure 100. It can perfectly adapt to existing standard surface mount stations, PCB board mounting space and conventional SMT (Surface Mount Technology) production processes, without requiring mold modification or assembly process adjustment, and has strong versatility.

[0026] In some embodiments, the orthographic projection of the groove 13 in the vertical direction is a continuous square and is disposed around the chip 200.

[0027] In some implementation methods, please refer to Figure 2 As shown, there are multiple grooves 13, which are spaced apart around the chip 200 within the base island area 11.

[0028] The chip packaging structure 100 provided in this application can uniformly release and offset the thermal expansion stress generated during the high temperature process by symmetrically arranging multiple sets of grooves 13 in the base island area 11 relative to the chip 200, thereby achieving stress balance in the entire frame 10 and avoiding stress concentration on one side of the frame 10, which would cause warping or displacement deformation of the chip packaging structure 100 on one side.

[0029] Meanwhile, the chip packaging structure 100 provided in this application forms a regular stress release channel by symmetrically arranging multiple grooves 13, which can directionally supplement reverse stress, accurately constrain the overall deformation trend of the chip packaging structure 100, greatly reduce the overall warpage, and ensure the flatness of the chip packaging structure 100.

[0030] In some embodiments, the island region 11 has a square shape when projected vertically, and the groove 13 includes a plurality of first grooves 131 and a plurality of second grooves 132. The plurality of first grooves 131 are respectively disposed at the four bottom corners of the island region 11, and the plurality of second grooves 132 are respectively disposed between adjacent first grooves 131.

[0031] The chip packaging structure 100 provided in this application has first grooves 131 arranged at the four bottom corners of the base island area 11. Under high temperature, the chip packaging structure 100 can preferentially release the thermal stress concentrated at the corners of the base island area 11, alleviating the warping and lifting problems that are prone to occur at the four corners. At the same time, a second groove 132 is arranged between two adjacent first grooves 131, thereby filling in the stress release points on the side of the chip packaging structure 100, realizing uniform stress distribution throughout the base island area 11, and eliminating stress release blind spots.

[0032] Meanwhile, in the chip packaging structure 100 provided in this application, the orthographic projection of the base island area 11 in the vertical direction is a square, and the first groove 131 and the second groove 132 are arranged regularly along the outline of the square. The overall structure is highly symmetrical, so that when the chip packaging structure 100 is deformed by heat, the deformation trend in each direction is consistent, which can efficiently form reverse stress to cancel each other out, and suppress the overall deformation of the chip packaging structure 100 such as diagonal warping and side bending to the greatest extent.

[0033] Finally, the chip packaging structure 100 provided in this application forms a gradient stress compensation structure by setting first grooves 131 at the four corners of the base island area 11 to bear the main stress relief function, and setting second grooves 132 between two adjacent first grooves 131 to assist in balancing the residual stress during transition. This structure can not only offset the thermal stress generated by the chip packaging structure 100 at high temperature, but also significantly reduce the overall warpage of the chip packaging structure 100.

[0034] For example, four first grooves 131 are provided, and four or eight second grooves 132 are provided accordingly, etc. This application does not limit this.

[0035] In some embodiments, the first groove 131 is curved in the vertical direction, so that it can be adapted to the four corners of the base island area 11 and can be perfectly embedded in the bottom corner of the base island. The groove 13 is arranged in a neat manner without crowding the chip 200 arrangement area in the center of the base island area 11.

[0036] In some embodiments, the depth of the groove 13 is greater than or equal to 0.05 mm and less than or equal to 0.15 mm.

[0037] The chip packaging structure 100 provided in this application has a groove 13 depth limited to a range of greater than or equal to 0.05 mm and less than or equal to 0.15 mm. This not only forms sufficient deformation space and stress compensation margin, effectively relieving the internal stress generated by high-temperature curing and reflow soldering, and significantly reducing package warpage, but also avoids insufficient stress release due to the groove 13 being too shallow, thus preventing the warpage control effect from failing to meet expectations.

[0038] Furthermore, the chip packaging structure 100 provided in this application, by setting the depth of the groove 13 to no more than 0.15mm, avoids excessive reduction of the physical thickness and load-bearing cross-sectional area of ​​the frame 10 due to excessively deep grooves, and can perfectly preserve the mechanical support performance of the frame 10, preventing the frame 10 from bending, breaking, deforming and breaking during stamping, packaging process and temperature cycling.

[0039] For example, the depth of the groove 13 can be 0.05, 0.07, 0.09, 0.11, 0.13, 0.15 mm, etc., and this application does not limit it.

[0040] In some embodiments, a roughened portion is provided between the frame 10 and the molding portion, which is formed by micro-etching on the surface of the frame 10.

[0041] The chip packaging structure 100 provided in this application increases the actual contact area between the frame 10 and the molding compound by forming a roughened portion with unevenness and roughness on the surface of the frame 10 through micro-etching. This allows the molding compound to be fully embedded in the roughened portion, forming a mechanical interlocking structure. As a result, the molding compound and the frame 10 are firmly bonded together and not easily separated, thereby reducing the warpage of the chip packaging structure 100 caused by high temperature.

[0042] In some embodiments, the encapsulated portion is made of a high-fill, low-shrinkage, and low-absorption material.

[0043] The chip packaging structure 100 provided in this application effectively reduces the overall thermal expansion coefficient of the molding compound by using a high-filling molding compound material. This makes its thermal expansion and contraction deformation degree close to that of the frame 10 and the chip 200, significantly alleviating the interfacial thermal stress caused by temperature changes in the chip packaging structure 100 and reducing the causes of warpage in the chip packaging structure 100 from the source. At the same time, the low-shrinkage material reduces the volume shrinkage during the high-temperature curing process of the chip packaging structure 100, which can prevent the molding compound from shrinking and pulling the frame 10 and the chip 200, reducing the residual internal stress in the molding compound. Combined with the stress relief structure of the groove 13, it reduces the overall warpage deformation of the chip packaging structure 100. The low water absorption material can significantly reduce the penetration of moisture into the interior of the chip packaging structure 100, which not only avoids the delamination, bulging, and board bursting problems caused by moisture expansion at high temperatures during reflow soldering, but also can isolate the internal bonding wires and chip 200 circuits of the chip packaging structure 100 for a long time, improving the weather resistance of the chip packaging structure 100.

[0044] Optionally, the encapsulated part can be made of Sumitomo EME-E670 type resin material, or it can be made of other materials with high filling, low shrinkage and low water absorption. This application does not limit this.

[0045] In some embodiments, the chip 200 is mounted to the base island using a die adhesive having a low modulus and a low coefficient of thermal expansion.

[0046] The chip packaging structure 100 provided in this application uses a low-modulus adhesive. The low-modulus adhesive is soft and elastic, and can act as an elastic buffer layer to effectively absorb and release the tensile and shear stress generated between the chip 200 and the base island, avoiding the stress from acting directly on the chip 200. At the same time, the adhesive has a lower coefficient of thermal expansion, and its thermal expansion and contraction deformation is closer to that of the chip 200, which greatly reduces the deformation difference between the chip 200 and the base island, thereby reducing the interface stress generated during temperature cycling, high-temperature curing, and reflow soldering from the source.

[0047] Optionally, the modulus of the adhesive sheet is less than or equal to 5 GPa.

[0048] For example, the modulus of the adhesive can be 5, 4, 3, 2, or 1 GPa, and this application does not limit it.

[0049] Since the adhesive has different coefficients of thermal expansion at low and high temperatures, the coefficient of thermal expansion of the adhesive at low temperature is A1, which can be less than or equal to 20ppm / ℃; the coefficient of thermal expansion of the adhesive at high temperature is A2, which can be less than or equal to 60ppm / ℃.

[0050] For example, the coefficient of thermal expansion A1 can be 20, 18, 16, 14, 12, 10 ppm / ℃, etc., and the coefficient of thermal expansion A2 can be 60, 58, 56, 54, 52, 50 ppm / ℃, etc., and this application does not limit it.

[0051] Please refer to Figures 3 to 4 As shown, this application also provides a high-temperature curing method for a chip package structure 100, applied to the aforementioned chip package structure 100. The high-temperature curing method for the chip package structure 100 comprises the following steps: Step S10: Place the chip packaging structure 100 in an oven and heat the oven to the first preset temperature in a stepped heating manner. Step S20: Control the oven to perform high-temperature curing on the chip packaging structure 100 at a first preset temperature and a first preset pressure, and maintain it for a first preset time; Step S30: Control the oven temperature to decrease to the second preset temperature, which is lower than the first preset temperature; Step S40: Remove the chip package structure 100 from the oven and open the mold.

[0052] The high-temperature curing method for the chip packaging structure 100 provided in this application heats the chip packaging structure 100 to a preset temperature through a gradient heating method in step S10. This allows the chip 200, adhesive, frame 10, and molding compound to gradually adapt to temperature changes, preventing drastic thermal expansion and contraction caused by excessive instantaneous temperature differences. This avoids problems such as chip 200 cracking, adhesive blistering, and instantaneous detachment of the bonding interface, ensuring a smooth transition to the curing condition. Simultaneously, through constant temperature and pressure curing in step S20, the molding compound fully completes the cross-linking reaction, resulting in consistent curing degree and uniform overall density. This suppresses deformation of the chip packaging structure 100 and, in conjunction with the groove 13 on the frame 10, further suppresses warping, improving the overall flatness of the chip packaging structure 100. Finally, through the slow cooling method in step S30, all components of the chip packaging structure 100 shrink synchronously and uniformly, gradually releasing residual stress accumulated during the curing process. This prevents stress rebound, local deformation, and corner warping caused by rapid cooling, stabilizing the overall shape after molding.

[0053] In some implementations, the first preset temperature is greater than or equal to 170°C and less than or equal to 180°C.

[0054] For example, the first preset temperature can be 170, 171, 173, 175, 177, 179, 180°C, etc., and this application does not limit it.

[0055] In some implementations, the first pressure is greater than or equal to 120 bar and less than or equal to 130 bar.

[0056] For example, the first pressure can be 120, 122, 124, 126, 128, 130 bar, etc., and this application does not limit it.

[0057] In some implementations, the first preset time is greater than or equal to 6 minutes and less than or equal to 7 minutes.

[0058] For example, the first preset time can be 6, 6.2, 6.4, 6.6, 6.8, 7 minutes, etc., and this application does not limit it.

[0059] In some implementations, the stepped heating method proceeds as follows: Step S11: Heat the chip package structure 100 within the first temperature range for a first time; Step S12: Heat the chip package structure 100 within the second temperature range for a second time; Step S13: Heat the chip package structure 100 within the third temperature range for a third time, so that the chip package structure 100 is heated to the first preset temperature.

[0060] The high-temperature curing method for the chip packaging structure 100 provided in this application involves heating in three temperature ranges sequentially, so that the chip packaging structure 100 is heated from a low temperature to a high temperature, avoiding strong thermal shock caused by a single large temperature increase. This allows the chip 200, die adhesive, frame 10, molding compound and other materials to be heated slowly and synchronously. At the same time, the different temperature ranges are kept at a constant temperature, which can gradually release the initial temperature difference stress between the surface and the interior of each structure, buffer the difference in thermal expansion rate between materials in advance, and suppress the initial warping trend such as local bulges and corner lifting in the early stage.

[0061] In some embodiments, step S11 is a preheating melting section, wherein the first temperature range is greater than or equal to 130°C and less than or equal to 150°C, and the first time is greater than or equal to 35s and less than or equal to 40s.

[0062] In some embodiments, step S12 is the cavity filling section, with a second temperature range greater than or equal to 150°C and less than or equal to 165°C. The second time is greater than or equal to 25s and less than or equal to 30s.

[0063] In some embodiments, step S13 is a curing and pressure holding stage, with a third temperature range greater than or equal to 165°C and less than or equal to 175°C. The third time is greater than or equal to 30 seconds and less than or equal to 40 seconds.

[0064] In some implementations, the oven temperature is controlled to decrease to a second preset temperature, specifically as follows: Starting from the first preset temperature, the chip package structure 100 is cooled to the second preset temperature at a preset cooling rate and a preset cooling time.

[0065] The high-temperature curing method for the chip packaging structure 100 provided in this application uses a fixed cooling rate and cooling time for uniform cooling, which allows the chip 200, die adhesive, frame 10, and molding compound to shrink slowly and synchronously. This avoids shrinkage differences caused by different materials cooling at different rates, effectively balancing the overall deformation. During the gradual cooling process, the internal stress accumulated during the high-temperature curing stage can be gradually dissipated, preventing rapid stress accumulation and rebound caused by rapid cooling. This reduces packaging warpage and distortion from the source. At the same time, the chip packaging structure 100 is removed from the mold after it has been cooled to a suitable low temperature. The mechanical properties and shape of the chip packaging structure 100 are completely stable, and it is not easy to be bumped, deformed, or damaged during the removal and transportation process, which facilitates the smooth progress of subsequent processes.

[0066] In some implementations, the preset cooling rate is greater than or equal to 1.5°C / min and less than or equal to 2°C / min.

[0067] For example, the preset cooling rate can be 1.5, 1.7, 1.9, 2.0 °C / min, etc., and this application does not limit it.

[0068] In some implementations, the preset cooling time is greater than or equal to 40 minutes and less than or equal to 50 minutes.

[0069] For example, the preset cooling time can be 40, 42, 44, 46, 48, 50 minutes, etc., and this application does not limit it.

[0070] In some implementations, the second preset temperature is greater than or equal to 75°C and less than or equal to 85°C.

[0071] For example, the second preset temperature can be 75, 77, 79, 80, 82, 84, 85°C, etc., and this application does not limit it.

[0072] In some embodiments, placing the chip package structure 100 in an oven includes: physically pressurizing the chip package structure 100 to prevent the frame 10 from shrinking during cooling, thereby reducing the warpage of the chip package structure 100.

[0073] In some implementations, physical pressure can be applied to the chip package structure 100 by placing a pressure block on the chip package structure 100.

[0074] Optionally, the briquette can be made of steel and have a hard chrome plated surface, making the briquette wear-resistant, non-stick, and non-deformable.

[0075] In some embodiments, the length of the pressing block is consistent with the effective length of the mold cavity in the oven, and the width covers the area of ​​the entire chip packaging structure 100, with a margin of greater than or equal to 2 mm and less than or equal to 3 mm reserved on one side.

[0076] In some implementations, the pressure per unit area of ​​the briquette is greater than or equal to 0.15 N / mm². 2 And less than or equal to 0.2 N / mm 2 .

[0077] For example, the pressure per unit area of ​​the briquette can be 0.15, 0.16, 0.17, 0.18, 0.19, or 0.2 N / mm. 2 This application does not impose any restrictions on this.

[0078] In some implementations, the weight of the briquette is greater than or equal to 1.3 kg and less than or equal to 1.7 kg.

[0079] For example, the weight of the briquette can be 1.3, 1.4, 1.5, 1.6, 1.7 kg, etc., and this application does not limit it.

[0080] Please refer to Figures 1 to 4 As shown, this application provides a chip packaging structure 100 and a high-temperature curing method for the chip packaging structure 100. Without changing the overall thickness or the external dimensions of the chip packaging structure 100, the method works synergistically from four dimensions: structural design, interface treatment, material selection, and curing process. This significantly reduces the warpage of the chip packaging structure 100 under conditions such as high-temperature curing and SMT reflow soldering, improves product flatness, soldering yield, and long-term reliability, and is fully compatible with existing SMT surface mount processes and general assembly spaces, demonstrating excellent versatility and mass production capability.

[0081] The specific improvement methods are as follows: By centrally arranging the chip 200 and symmetrically distributing the base island area 11 and pin area 12, the layout ensures balanced stress distribution during thermal deformation of the chip package structure 100. A groove 13 is formed within the base island area 11, consisting of a first groove 131 with four corner bends and a second groove 132 positioned between adjacent first grooves 131, thus creating a symmetrical arrangement around the chip 200 and forming channels for reverse stress compensation and gradient stress release. Furthermore, by limiting the groove depth to a shallow groove range of 0.05mm to 0.15mm, grooves are only created on the local surface of the base island area 11. This avoids reducing the overall thickness of the chip package structure 100 or altering its external dimensions. This releases concentrated thermal stress at the corners and sides of the frame 10, offsetting stress caused by differences in thermal expansion between different materials, while preserving the structural strength of the frame 10 and preventing structural breakage.

[0082] Meanwhile, the chip packaging structure 100 provided in this application forms a roughened part by chemical micro-etching at the interface between the frame 10 and the molding part, thereby increasing the contact area between the two and improving the bonding strength by mechanical interlocking. Under high temperature environment, it is not easy for interface delamination and debonding to occur, and avoids the exacerbation of packaging warping deformation due to interface debonding.

[0083] Furthermore, by selecting a die-attach adhesive with low modulus and low coefficient of thermal expansion, it is sandwiched between the chip 200 and the frame 10 to act as a flexible buffer layer, absorbing the shear and tensile stress caused by temperature changes, reducing the difference in thermal expansion deformation between the chip 200 and the frame 10, preventing the chip 200 from cracking under stress, and buffering and suppressing warping from the inside.

[0084] At the same time, high-filling, low-shrinkage, and low-water-absorption epoxy molding compound is used to reduce the overall coefficient of thermal expansion, narrow the deformation gap with frame 10 and chip 200, and reduce the internal stress of curing by relying on low shrinkage characteristics. The low water absorption rate eliminates the problem of moisture bulging and delamination caused by damp heat and reflow soldering, thus stabilizing the packaging form from the outside.

[0085] Finally, at the process level, a three-stage stepped heating method is adopted, which gradually increases the temperature of the chip packaging structure 100 in three temperature zones: preheating and melting, cavity filling, and curing and holding pressure. This avoids thermal shock caused by sudden high temperature, allows various materials to complete the thermal transformation smoothly, and relieves the initial stress in advance.

[0086] Among them, the chip packaging structure 100 is cured under constant temperature and pressure at 170℃~180℃ and 120bar~130bar to ensure that the plastic encapsulation part is fully cross-linked and molded, and deformed by pressure. The temperature is slowly and uniformly reduced to 75℃~85℃ at a rate of 1.5℃ / min~2℃ / min, releasing the overall residual internal stress simultaneously to prevent stress rebound warping caused by rapid cooling. Throughout the process of solidifying the chip packaging structure, physical pressure is applied using steel pressure blocks to further constrain the shrinkage and deformation of the frame 10. The entire process only optimizes the temperature and pressure and the heating and cooling rhythm, without needing to change the thickness and external dimensions of the packaging structure.

[0087] Therefore, the chip packaging structure 100 provided in this application can make the warpage less than or equal to 30μm while maintaining the overall thickness unchanged.

[0088] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; many substitutions, modifications and variations of these embodiments will be apparent to those skilled in the art based on the foregoing description, and for the sake of brevity they are not provided in the details.

[0089] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A chip packaging structure, characterized in that, include: chip; A frame, the surface of which includes a base island area and a pin area; the chip is mounted on the base island area; the pin area is arranged around the base island area, and the pin area is provided with pins for electrical connection to the chip via bonding wires; a groove is provided in the base island area, and the groove is at least partially arranged around the chip; A molding compound is disposed on the frame, and the molding compound covers the base island area, the pin area and the chip.

2. The chip packaging structure according to claim 1, characterized in that, The groove is provided in multiple places, and the multiple grooves are arranged at intervals around the chip.

3. The chip packaging structure according to claim 1, characterized in that, The depth of the groove is greater than or equal to 0.05 mm and less than or equal to 0.15 mm.

4. The chip packaging structure according to claim 1, characterized in that, A roughened section is provided between the frame and the encapsulation part, and the roughened section is formed by micro-etching on the surface of the frame.

5. The chip packaging structure according to claim 1, characterized in that, The encapsulation portion includes a high-filling, low-shrinkage, and low-water-absorption material; the chip is mounted on the base island region using a die-attach adhesive, which has a low modulus and a low coefficient of thermal expansion.

6. A high-temperature curing method for a chip packaging structure, applied to the chip packaging structure as described in any one of claims 1-5, characterized in that, include: The chip packaging structure is placed in an oven, and the oven is heated to a first preset temperature using a stepped heating method. The oven is controlled to perform high-temperature curing of the chip packaging structure at the first preset temperature and the first pressure, and the curing is maintained for the first preset time. The oven temperature is controlled to decrease to a second preset temperature, which is lower than the first preset temperature. The chip package structure is removed from the oven and then molded.

7. The high-temperature curing method for the chip packaging structure according to claim 6, characterized in that, The stepped heating method includes: The chip packaging structure is heated within a first temperature range for a first time. The chip packaging structure is heated for a second time within a second temperature range; The chip packaging structure is heated for a third time within a third temperature range, causing the chip packaging structure to heat up to a first preset temperature.

8. The high-temperature curing method for the chip packaging structure according to claim 7, characterized in that, The first temperature range is greater than or equal to 130°C and less than or equal to 150°C; the first time is greater than or equal to 35s and less than or equal to 40s. The second temperature range is greater than or equal to 150°C and less than or equal to 165°C; the second time is greater than or equal to 25s and less than or equal to 30s. The third temperature range is greater than or equal to 165°C and less than or equal to 175°C; the third time is greater than or equal to 30s and less than or equal to 40s.

9. The high-temperature curing method for the chip packaging structure according to claim 6, characterized in that, The control of the oven to lower its temperature to a second preset temperature includes: Starting from the first preset temperature, the chip packaging structure is cooled to the second preset temperature at a preset cooling rate and a preset cooling time.

10. The high-temperature curing method for the chip packaging structure according to claim 6, characterized in that, The step of placing the chip packaging structure in the oven includes: Physical pressure is applied to the chip packaging structure.

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