Bonding apparatus, bonding method, storage medium, and method for manufacturing an article

Abstract

The present disclosure provides a bonding apparatus, a bonding method, a storage medium, and a method for manufacturing an article. The bonding apparatus configured to bond a chip to a corresponding bonding target region among a plurality of bonding target regions on a wafer, the bonding apparatus including a bonding head group including a plurality of bonding heads configured to hold the chip, a holding unit configured to hold the wafer, and a control unit configured to control a relative position between the bonding head group and the holding unit, wherein the control unit controls the bonding based on a combination of the bonding head and the bonding target region according to an amount of relative movement between the bonding head group and the holding unit in a plane parallel to a surface of the wafer having the plurality of bonding target regions, such that the plurality of bonding heads included in the bonding head group bond the chip to the corresponding bonding target region among the plurality of bonding target regions.

Description

Technical Field

[0001] This disclosure relates to bonding apparatus, bonding method, storage medium, and method for manufacturing articles. Background Technology

[0002] Japanese Patent Application Publication No. 2023-77928 discloses a bonding apparatus for bonding a chip held by a bonding head to a wafer.

[0003] When multiple bonding heads perform bonding at different timings, the combination of the bonding heads and the bonding target areas on the wafer can affect throughput. Summary of the Invention

[0004] This disclosure aims to provide a bonding device that is advantageous in terms of throughput.

[0005] According to one aspect of this disclosure, a bonding apparatus is provided, configured to bond a chip to a corresponding bonding target region among a plurality of bonding target regions on a wafer. The bonding apparatus includes a bonding head assembly, a holding unit, and a control unit. The bonding head assembly includes a plurality of bonding heads configured to hold the chip, the holding unit is configured to hold the wafer, and the control unit is configured to control the relative position between the bonding head assembly and the holding unit. The control unit controls the bonding based on a combination of bonding heads and bonding target regions, according to the amount of relative movement between the bonding head assembly and the holding unit in a plane parallel to the surface of the wafer having the plurality of bonding target regions, such that the plurality of bonding heads included in the bonding head assembly bond the chip to a corresponding bonding target region among the plurality of bonding target regions.

[0006] The features of this disclosure will become apparent from the following description of embodiments with reference to the accompanying drawings. The following description of the embodiments is given by way of example. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of the bonding device.

[0008] Figure 2A This is a schematic diagram of a head that is configured to hold the chip.

[0009] Figure 2B This is a schematic diagram of a head that is configured to hold the chip.

[0010] Figure 3 This is a schematic diagram of a wafer stage.

[0011] Figure 4 This is a flowchart of the bonding method.

[0012] Figure 5 This is a diagram showing a wafer that has undergone partial bonding.

[0013] Figure 6 This is a diagram showing an example of the bonding head retracting from the wafer in the Z-axis direction.

[0014] Figure 7 This is a diagram showing an example of the bonding head retracting from the wafer along the XY plane.

[0015] Figure 8 This is a diagram illustrating an example of the bonding sequence of the bonding target regions on a wafer.

[0016] Figure 9 This is a schematic diagram showing the bonding target area on the wafer W and the first and second bonding heads disposed above the chip measurement unit for measuring the chip.

[0017] Figure 10 This is a flowchart of a method for manufacturing items. Detailed Implementation

[0018] Embodiments of this disclosure will be described below with reference to the accompanying drawings. It should be understood that the following embodiments are not intended to limit the disclosure set forth in the claims. Although multiple features are described in the embodiments, not all of these features are essential to this disclosure, and the embodiments may be appropriately combined. In the drawings, identical or similar parts are indicated by the same reference numerals, and repeated descriptions are omitted.

[0019] In this specification and accompanying drawings, directions are indicated by the XYZ coordinate system, in which the X, Y, and Z axes are orthogonal to each other. In this coordinate system, the vertical direction is defined as the Z-axis direction, and the horizontal plane perpendicular to the vertical direction is defined as the XY plane. However, when the XYZ coordinate system is shown in the accompanying drawings, this coordinate system is preferred.

[0020] In each embodiment, a specific construction will be described.

[0021] First Embodiment In the following description, a wafer on which semiconductor devices are formed is described as a bonding target object, and a monolithic chip including semiconductor devices is described as a bonding object. However, the bonding target object and the bonding object are not limited thereto, and various modifications can be made within the scope of this disclosure.

[0022] Examples of bonding target objects include, but are not limited to, silicon wafers, silicon wafers with wiring formed, glass wafers, glass panels with wiring formed, printed wiring boards (PWBs) with wiring formed, printed circuit boards (PCBs) with mounted electronic components, and metal panels. Alternatively, the bonding target object can be a wafer to which a chip with semiconductor devices formed is bonded. Alternatively, the bonding target object may not be a wafer, but a chip with semiconductor devices formed.

[0023] For example, bonding objects can include, but are not limited to, a single monolithic chip, a stack of multiple monolithic chips, small pieces of material, optical components, microelectromechanical systems (MEMS), or other structures. Chips are monolithized through a chip dicing process (cutting process).

[0024] Bonding methods are not limited to any particular method. Examples of bonding methods include, but are not limited to, adhesive bonding, temporary bonding using temporary adhesives, hybrid bonding, atomic diffusion bonding, vacuum bonding, and bump bonding. A variety of temporary and permanent bonding methods can be used.

[0025] Hybrid bonding (also known as direct bonding) is a bonding method that directly bonds the bonding object and the bonding target object without using wires, adhesives, etc. A simplified example of hybrid bonding will be described below. First, the bonding surfaces of both the bonding object and the bonding target object are cleaned, and then, for example, through plasma treatment, the bonding surfaces are made hydrophilic and activated. Then, the activated bonding surfaces of the bonding object and the activated bonding surfaces of the bonding target object are brought into contact with each other and temporarily bonded together. Subsequently, the bonding object and the bonding target object are permanently bonded by, for example, heat treatment. Hybrid bonding is advantageous in improving electrical properties and performance. For example, hybrid bonding can increase the data transfer speed between semiconductor devices, thereby significantly improving the overall device performance. Another advantage of hybrid bonding is that it allows for the stacking of chips, thus making efficient use of space. This enables the manufacture of compact, high-performance devices.

[0026] Figure 1 This is a schematic diagram of the bonding device BD. (Example) Figure 1 As shown, the bonding device BD may include a pickup unit 3 and a bonding unit 4 arranged on a base 1, and the base 1 is damped by a support 2. Although Figure 1 An example is shown where the pickup unit 3 and bonding unit 4 are mounted on a single base 1, but the pickup unit 3 and bonding unit 4 can be mounted separately on separate bases. The bonding device BD can be configured to position and bond the chip D to a bonding target portion of the wafer W, which serves as the bonding target object. The chip D can be provided in a state where it is held by a dicing tape attached to the dicing frame 33. The bonding device BD may also include a control unit CNT, which is configured to control the pickup unit 3 and bonding unit 4. The control unit CNT can be implemented by, for example, a programmable logic device (PLD) (such as a field-programmable gate array (FPGA)), an application-specific integrated circuit (ASIC), a general-purpose or special-purpose computer containing a program, or any combination thereof.

[0027] The pickup unit 3 may include a pickup head 31 and a release head 32.

[0028] Pick-up unit 3 separates the chip D to be bonded to wafer W from the dicing tape using release head 32 and holds the chip D by suction using pick-up head 31. Pick-up head 31 rotates the chip D, for example, 180 degrees and transfers the chip D to bonding head 422 of bonding unit 4.

[0029] The bonding apparatus BD of this embodiment includes multiple pickup heads 31a and 31b, multiple release heads 32a and 32b, and multiple bonding heads 422a and 422b. The multiple bonding heads are collectively referred to as the bonding head group.

[0030] In other words, a bond head assembly comprises multiple bond heads. Figure 1 The example shown provides two pick heads, two release heads, and two bond heads. However, the number of pick heads, release heads, and bond heads can differ from each other, and each can have three or more. Therefore, by providing multiple pick heads, release heads, and bond heads, the time required for bonding processing can be reduced. Here, the number of pick heads is, for example, equal to or greater than the number of bond heads.

[0031] The pick-up head 31 contacts the bonding surface of the chip D. Therefore, in applications where bonding is performed after surface activation (such as hybrid bonding), the pick-up head 31 preferably has a highly stable surface. Having a highly stable surface means, for example, that the surface of the pick-up head 31 in contact with the bonding surface of the chip D is coated with diamond-like carbon (DLC), a fluorine-based coating, etc. Alternatively, in applications where bonding is performed after surface activation (such as hybrid bonding), it is preferable to reduce the contact area by employing a shape with a small contact area (such as a high-density pin). Alternatively, in applications where bonding is performed after surface activation (such as hybrid bonding), it is preferable that the pick-up head 31 employs a non-contact processing method, such as a Bernoulli chuck. Alternatively, in applications where bonding is performed after surface activation (such as hybrid bonding), the pick-up head 31 may be configured to hold a side surface or edge portion of the chip D, thereby avoiding contact with the bonding surface of the chip D.

[0032] The bonding unit 4 may include a surface plate 41 and a support portion 42. The wafer stage 43 may be disposed above the surface plate 41. The wafer stage 43 may be driven by a drive mechanism 435, such as a linear motor, in the X-axis direction (first direction) and the Y-axis direction (second direction).

[0033] The drive mechanism 435 can also be configured to rotate the wafer stage 43 about an axis parallel to the Z-axis (third direction). Instead of rotating the wafer stage 43 about an axis parallel to the Z-axis, the bonding head 422 can rotate the chip D about an axis parallel to the Z-axis. The drive mechanism 435 serves as a positioning mechanism for changing the relative position between the wafer chuck 432 (or wafer W) and the bonding head 422 (or chip D).

[0034] A chip measurement unit 431 is disposed on a wafer stage 43. The chip measurement unit 431 may be, for example, an image capturing unit (camera) and is configured to detect the position of feature portions of the chip D held by the bonding head 422 by imaging. The wafer stage 43 may be equipped with a bar mirror 433. The bar mirror 433 can serve as a target for an interferometer 434. The wafer stage 43 may include a wafer chuck 432 mounted thereon. The wafer chuck 432 holds the wafer W, which serves as the bonding target. The wafer stage 43 serves as a support portion configured to support the wafer chuck 432 and the chip measurement unit 431.

[0035] The wafer measurement unit 421 is mounted on the support portion 42. The wafer measurement unit 421 is, for example, an image capturing unit (camera). The wafer measurement unit 421 detects the position of the feature portion of the wafer W, which is used as a bonding target object and is held by the wafer chuck 432, by imaging.

[0036] The control unit CNT can be configured to specify or calculate the positions of multiple bonding target portions on the wafer W based on the positions of feature portions of the wafer W detected by the wafer measurement unit 421. The support portion 42 may also include an interferometer 434 configured to measure the position of the wafer stage 43 using a bar mirror 433. The support portion 42 may also include a bonding head 422 configured to receive and hold a chip D conveyed from the pick-up head 31 and bond the chip D to the bonding target portions of the wafer W. The support portion 42 serves as a support for supporting the bonding head 422 and the wafer measurement unit 421.

[0037] exist Figure 1In the example, the pick-up head 31 rotates the chip D by 180 degrees and transfers the chip D to the bonding head 422. Alternatively, a first chip holding unit and a second chip holding unit can be provided, and the chip D can be transferred from the pick-up head 31 to the first chip holding unit, then from the first chip holding unit to the second chip holding unit, and subsequently from the second chip holding unit to the bonding head 422. Alternatively, a drive mechanism can be provided to drive the bonding head 422 to receive the chip D. Alternatively, the pick-up head 31 can place the chip D on an intermediate stage disposed on the wafer stage 43, and the bonding head 422 can hold the chip D on the intermediate stage by operating the drive mechanism included in the wafer stage 43 or by operating the bonding head 422 itself. In this case, while placing the chip D on the intermediate stage, the wafer measurement unit 421 can detect the position of the feature portion of the chip D.

[0038] Figure 2A and Figure 2B This is a schematic diagram of the head holding chip D. In Figure 2A and Figure 2B In the example shown, the pickup head 31 is illustrated as an example; however, the bonding head 422 may have a similar construction. The head configured to hold the chip D includes a collet holder 312 configured to hold a collet 311 and a body 313 configured to hold the collet holder 312. The collet holder 312 holds the collet 311, which is a clamp that contacts the chip D. Figure 2A The collet 311, collet retainer 312, and body 313 are shown in an unintegrated state. Figure 2B The image shows the integrated state of the collet 311, collet retainer 312, and body 313. During the bonding process, the collet 311, collet retainer 312, and body 313 are as follows... Figure 2B The integration shown.

[0039] For example, the holding of the body 313 to the collet retainer 312 and the holding of the collet retainer 312 to the collet 311 can be achieved by using a vacuum source 314 to expel gas from the space between the holding member and the held member. The holding of the body 313 to the collet retainer 312 and the holding of the collet retainer 312 to the collet 311 can be achieved by mechanical holding using claws or other mechanisms, or by magnetic holding using magnets.

[0040] The collet 311 holds the chip D using a holding surface 311a. Examples of materials used for the collet include, but are not limited to, fluororubber, polyetheretherketone (PEEK), and stainless steel (SUS). Holding the chip D using the collet 311 is achieved, for example, by venting gas from the space between the holding surface 311a and the chip D.

[0041] The collet holder 312 is always held by the body 313. In contrast, the collet 311 can be replaced depending on the type of chip D. Alternatively, the collet 311 can be replaced depending on damage, wear, or contamination that occurs during the bonding of multiple chips D.

[0042] For example, when the collet 311 is replaced due to damage or contamination, the used collet is discarded into a collet processing unit (not shown), and a new collet supplied from a collet supply unit (not shown) is installed on the collet holder 312. At this time, the collet 311 is removed and installed using, for example, a collet changing hand (not shown). The collet 311 can be cleaned appropriately, and the bonding device BD may include a unit for cleaning the collet 311.

[0043] Figure 3 This is a schematic diagram of wafer stage 43. The wafer W is held by a wafer chuck 432. The wafer W or wafer stage 43 can be positioned relative to rotation about an axis parallel to the X-axis (first direction) and an axis parallel to the Y-axis (second direction), and about an axis parallel to the Z-axis (third direction) orthogonal to the X-axis and Y-axis, which are orthogonal to orthogonal to each other. For this purpose, wafer stage 43 may be equipped with strip mirrors 433, more specifically, strip mirrors 433a and 433b.

[0044] Bar mirror 433a serves as the target for interferometers 434a and 434c. The control unit CNT is configured to detect the position of the wafer stage 43 in the X-axis direction based on the output from interferometer 434a, and to detect the rotation of the wafer stage 43 about an axis parallel to the Z-axis direction based on the outputs from interferometers 434a and 434c. Bar mirror 433b serves as the target for interferometer 434b. The control unit CNT is configured to detect the position of the wafer stage 43 in the Y-axis direction based on the output from interferometer 434b. The control unit CNT can be configured to perform feedback control of the position of the wafer W or the wafer stage 43 relative to the rotation about axes parallel to the X-axis and Y-axis, and about an axis parallel to the Z-axis orthogonal to the X-axis and Y-axis, based on the outputs from interferometers 434a, 434b, and 434c. Interferometer 434a and control unit CNT can be considered components of the aforementioned positioning mechanism.

[0045] A reference plate 436 can be disposed on the upper surface of the wafer stage 43. Multiple marks 436a, 436b, and 436c can be arranged on the reference plate 436. The reference plate 436 can be formed of a material with a low coefficient of thermal expansion, thereby allowing the marks to be formed with high positional accuracy. In one example, the reference plate 436 can be constructed by forming the marks on a quartz substrate using a semiconductor photolithography process. The reference plate 436 can have a surface at substantially the same height as the surface of the wafer W and can be observed using the wafer measurement unit 421; however, a separate camera can also be provided for observing the reference plate 436. The wafer stage 43 has a configuration that combines a coarse-motion stage driven over a large area and a fine-motion stage driven with high precision over a small area. In this configuration, the chip measurement unit 431, the bar mirrors 433a and 433b, the wafer chuck 432, and the reference plate 436 can be disposed on the fine-motion stage to achieve high-precision positioning.

[0046] The following describes a method for ensuring the origin, magnification, X-axis and Y-axis orientations (rotation), and orthogonality of the wafer stage 43 using a reference plate 436. Mark 436a is observed through the wafer measurement unit 421, and the output value of the interferometer is defined as the origin of the wafer stage 43 when mark 436a is located at the center of the output image of the wafer measurement unit 421. Next, mark 436b is observed through the wafer measurement unit 421, and the Y-axis orientation (rotation) and magnification in the Y-axis direction of the wafer stage 43 are determined based on the output value of the interferometer when mark 436b is located at the center of the output image of the wafer measurement unit 421. Next, mark 436c is observed through the wafer measurement unit 421, and the X-axis orientation (rotation) and magnification in the X-axis direction of the wafer stage 43 are determined based on the output value of the interferometer when mark 436c is located at the center of the output image of the wafer measurement unit 421. Therefore, axial orientation and orthogonality can be calibrated by defining the direction from mark 436b to mark 436a on the reference plate 436 as the Y-axis of the bonding device BD, and defining the direction from mark 436c to mark 436a as the X-axis of the bonding device BD. Furthermore, calibration can be performed by using the spacing between marks 436b and 436a as the scale reference for the Y-axis of the bonding device BD, and using the spacing between marks 436c and 436a as the scale reference for the X-axis of the bonding device BD. Since the refractive index of the interferometer's optical path changes due to atmospheric pressure variations or temperature fluctuations, the interferometer's measurements may fluctuate. Therefore, calibration is preferably performed at all times to ensure the origin position, magnification, rotation, and orthogonality of the wafer stage 43. To reduce fluctuations in the interferometer's measurements, it is preferable to enclose the space where the wafer stage 43 is located within a temperature-controlled chamber, thereby controlling the temperature inside the temperature-controlled chamber.

[0047] Although an example of calibration using a reference plate has been described, the calibration method is not limited to this example. For example, calibration can be performed by abutting a reference surface, or high-precision positioning can be achieved using a position measuring device with an absolute reference, such as a white light interferometer.

[0048] The position of wafer stage 43 can be measured using an encoder. Specifically, an encoder scale and encoder head can be used instead of an interferometer and a bar mirror. The encoder scale is preferably formed of a material with a low coefficient of thermal expansion. In one example, the encoder scale can be produced by forming the scale on a quartz substrate using a semiconductor photolithography process. Alternatively, multiple encoder heads can be arranged, and the encoder head to be used can be switched according to the position of the bonding target portion. Alternatively, a pair of encoder heads can be arranged symmetrically with respect to the bonding target portion, which is beneficial for improving position measurement accuracy.

[0049] exist Figure 1 In the example shown, the wafer stage 43 moves in the XY plane; alternatively, the bonding head 422 can move in the XY plane, or both the wafer stage 43 and the bonding head 422 can move in the XY plane. When the bonding head 422 moves, a measuring mechanism (interferometer or encoder) is preferably provided for measuring the position of the bonding head 422. In this embodiment, the XY plane is a plane parallel to the surface of the wafer W, which includes the bonding target region.

[0050] When using multiple bonding heads 422 for bonding processing, it may be undesirable for multiple bonding heads 422 to perform bonding processing simultaneously. Figure 5 This diagram shows a wafer W that has undergone partial bonding. The black area on wafer W is the bonding completion area W1, where chip D has been bonded, and the white area on wafer W is the bonding target area W2 (W2A, W2B, W2C, and W2D), where chip D has not yet been bonded. Now consider a configuration where the next bonding target area is W2A, and the first bonding head (first holding unit) and the second bonding head (second holding unit) are arranged side-by-side in the Y-axis direction. In this case, only one of the first and second bonding heads can face the bonding target area, while the other cannot. In other words, the first holding unit and the second holding unit cannot perform bonding processing simultaneously. If chip D held by one holding unit is bonded to the bonding target area W2A, then chip D held by the other holding unit comes into contact with wafer W or wafer chuck 432. Then, chip D that has come into contact with wafer W or wafer chuck 432 is damaged.

[0051] Furthermore, the first chip held by bonding head 422a (first holding unit) and the second chip held by bonding head 422b (second holding unit) may have different thicknesses. In this case, when the first holding unit and the second holding unit perform bonding simultaneously, the contact time between the bonding target object and the first chip is different from the contact time between the bonding target object and the second chip, which may lead to inappropriate bonding of at least one of the first chip and the second chip. Alternatively, the height of the first bonding target area to which the first chip on wafer W is to be bonded may be different from the height of the second bonding target area to which the second chip on wafer W is to be bonded. In this case, when the first holding unit and the second holding unit perform bonding simultaneously, the contact time between the first bonding target object and the first chip is different from the contact time between the second bonding target object and the second chip, which may lead to inappropriate bonding of at least one of the first chip and the second chip. Furthermore, the type and grade (quality) of the chip held by the first holding unit may be suitable for the first bonding target area, while the type and grade (quality) of the chip held by the second holding unit may not be suitable for the second bonding target area. In this situation, when bonding is performed simultaneously through the first holding unit and the second holding unit, an unsuitable chip may be bonded to the second bonding target area.

[0052] In the above-described situation, it is preferable to control the bonding process so that multiple bonding heads perform bonding simultaneously, and to control the process so that one bonding head retracts while another bonding head performs bonding. The control that allows multiple bonding heads to bond simultaneously refers to a control such that the time during which the first chip held by the first holding unit contacts the bonding target object and the time during which the second chip held by the second holding unit contacts the bonding target object at least partially overlap. In other words, the bonding apparatus according to this embodiment switches between a first control and a second control during the bonding process. The first control controls the bonding such that the time during which the first chip held by the first bonding head contacts the wafer W and the time during which the second chip held by the second bonding head contacts the wafer W at least partially overlap. The second control controls the bonding such that the first chip held by the first bonding head does not contact the wafer W, while the second chip held by the second bonding head contacts the wafer W. In the first control, the timing when the first chip held by the first bonding head and the second chip held by the second bonding head begin to contact the wafer W can be the same.

[0053] When multiple bonding heads perform bonding at different timings, the combination of the bonding heads and the bonding target areas on the wafer W will affect the throughput.

[0054] This disclosure provides a bonding apparatus that is advantageous in terms of throughput. Specifically, the combination of the bonding head and the bonding target region is determined with consideration of throughput. For example, the travel distance of the wafer stage 43 when the first bonding head performs bonding processing on the first bonding target region and the second bonding head performs bonding processing on the second bonding target region is defined as a first travel distance. The travel distance of the wafer stage 43 when the second bonding head performs bonding processing on the first bonding target region and the first bonding head performs bonding processing on the second bonding target region is defined as a second travel distance. Since a shorter travel distance of the wafer stage 43 is more advantageous in terms of throughput during the bonding process, it is advantageous in terms of throughput to use a method corresponding to the second travel distance when the second travel distance is shorter than the first travel distance. In other words, it is advantageous for the second bonding head to perform bonding processing on the first bonding target region and the first bonding head to perform bonding processing on the second bonding target region. In this case, the combination of the bonding head and the bonding target region on the wafer W is determined such that the second bonding head performs bonding on the first bonding target region, and the first bonding head performs bonding on the second bonding target region. Although the moving distance of the wafer stage 43 has been described above, the combination can be determined based on the relative movement between the bonding head group 422 and the wafer stage 43 (rather than based on the moving distance of the wafer stage 43).

[0055] Figure 4 This is a flowchart of the bonding method. This bonding method is controlled by the control unit CNT. Figure 4 The bonding method shown in the flowchart is performed by the control unit CNT according to the program stored therein. In step S1001, the wafer W, which serves as the bonding target, is loaded into the bonding apparatus BD and held by the wafer chuck 432. Since foreign matter adhering to the bonding surface may cause bonding defects, the interior of the bonding apparatus BD can be constructed as a space with high cleanliness (e.g., Class 1). To maintain high cleanliness, the wafer W can be housed in a container with high hermeticity and maintained at high cleanliness (such as a front-opening wafer transfer cassette (FOUP)) and can be loaded from the container into the bonding apparatus BD. To further improve cleanliness, the wafer W can be cleaned in the bonding apparatus BD after being loaded into it. In addition, bonding pretreatment can be performed. Examples of pretreatment may include, but are not limited to, cleaning of the wafer W and the chip D, applying adhesive to the wafer W in the case of adhesive bonding, and activating the surface of the wafer W in the case of mixed bonding. The wafer W is roughly positioned by a pre-aligner (not shown) based on a notch or orientation flat and the outer contour of the wafer, and then the wafer W is transferred to and held by the wafer chuck 432 on the wafer stage 43.

[0056] In step S1002, the wafer measurement unit 421 measures the position of the feature portion (measurement target portion) of wafer W, and determines the position of the bonding target portion based on this. Here, the positional relationship (relative position) between the feature portion (measurement target portion) of wafer W and the bonding target portion is known. Focus adjustment for capturing images of the feature portion of wafer W using the wafer measurement unit 421 can be performed by a focus adjustment mechanism disposed in the wafer measurement unit 421. Alternatively, focus adjustment can be performed by a Z-axis drive mechanism disposed in the wafer stage 43, which drives wafer W in the Z-axis direction. Alignment marks are usually formed on wafer W; however, when no alignment marks are formed, the feature portion whose position can be specified can be measured. The control unit CNT can cause the wafer measurement unit 421 to capture images of the feature portion of wafer W, and can detect the relative position of the image of the feature portion with respect to the center of the output image of the wafer measurement unit 421 as the position of the feature portion (measurement target portion).

[0057] An offset can be predetermined to enable high-precision measurement of the relative position of the mark with respect to the reference point of the bonding apparatus BD. This process may include driving the wafer stage 43 such that the mark on the reference plate 436 is within the field of view of the wafer measurement unit 421, and using the wafer measurement unit 421 to measure the position of the mark. The offset relative to the position measured using the wafer measurement unit 421 can be determined based on the driving position of the wafer stage 43 and the position of the mark measured using the wafer measurement unit 421. Here, although the reference point of the bonding apparatus BD is typically set at a specific mark location on the reference plate 436, any other location can also be used as the reference location.

[0058] Because the measurement range of the rotational orientation of the interferometer or encoder is limited, the amount of rotation that the wafer stage 43 can correct is relatively small. Therefore, when the rotation of wafer W is large, it is preferable to correct the rotation and reposition wafer W. When repositioning wafer W, the position of wafer W needs to be measured again. The surface position (surface height) of the bonding surface of wafer W is measured during the autofocus operation performed when measuring the marks on wafer W or by using a first height measuring unit (not shown). Because of the thickness variation of wafer W, it is advantageous to measure the surface position of wafer W to accurately manage the gap between wafer W and chip D during the bonding operation. Here, the measurement result of the surface height of the bonding surface of wafer W is stored in a storage unit (not shown) included in the control unit CNT.

[0059] Since the origin position, magnification, X-axis and Y-axis directions (rotation), and orthogonality of the wafer stage 43 are ensured by using the reference plate 436, the position of the feature portion (measurement target portion) of the wafer W can be measured by referring to the origin position and the X-axis and Y-axis of the wafer stage 43. The wafer W includes bonding target portions (or semiconductor devices used as bonding targets) arranged at a predetermined pitch.

[0060] Because these bonding target portions (semiconductor devices) are manufactured by a semiconductor manufacturing apparatus with multilayer high-precision positioning, the bonding target portions (semiconductor devices) are repeatedly arranged with a spacing of nanometer-level precision. Therefore, wafer alignment in step S1002 may not require measuring the position of the feature portions corresponding to all bonding target portions (semiconductor devices). Therefore, the control unit CNT can be configured to determine the position of multiple bonding target portions by measuring the position of fewer than the number of bonding target portions and performing statistical processing on the measurement results (first measurement step). Here, multiple measurement target portions can be determined based on the arrangement information of the semiconductor devices. To determine the position of multiple bonding target portions, the control unit CNT calculates the origin position of the repeated arrangement of multiple bonding target portions, the rotation amount in the X-axis and Y-axis directions, the orthogonality between the X-axis and Y-axis, and the magnification error of the repetition spacing based on the measurement results of the multiple measurement target portions.

[0061] The wafer chuck 432 preferably has a temperature control function for adjusting the temperature of the wafer W. This is because the coefficient of thermal expansion of a silicon wafer is 3 ppm / °C, and in the case of a 300 mm diameter wafer, when the temperature increases by 1°C, the outermost periphery of the wafer may shift by 150 mm × 0.000003 = 0.00045 mm, or 450 nm. If the bonding position shifts after wafer alignment, bonding with high positional accuracy cannot be achieved; therefore, the wafer temperature is preferably kept stable within 0.1°C.

[0062] The movement of the chip to be bonded, parallel to or following the loading and alignment of the wafer used as the bonding target, will be described below. In step S2001, a dicing frame 33, in which the chip D, monolithized by a dicing machine, is arranged on a dicing tape, is transferred to the bonding apparatus BD. Since foreign matter adhering to the bonding surface may cause bonding defects, a container with high airtightness and maintained at a high level of cleanliness can be used to transfer the dicing frame 33. To improve cleanliness, the chip D on the dicing frame 33 can be cleaned in the bonding apparatus BD. The dicing frame 33 can be approximately positioned in its rotational direction and offset position based on the shape reference of the dicing frame 33 using a pre-aligner (not shown).

[0063] Furthermore, chip D can be classified as a preprocessing step. In this classification, chip D can be categorized, for example, by type or quality (grade). Classification is based on the arrangement information of the bonding target areas of wafer W or the quality information of chip D.

[0064] In step S2002, chip D is picked up by a plurality of pick-up heads 31. In other words, each of the plurality of pick-up heads 31 holds a corresponding chip D. Specifically, the pick-up head 31 and the release head 32 can be positioned at the location of the chip D to be picked up. Then, while the chip D to be picked up is held by the pick-up head 31, the dicing tape is peeled off the chip D by the release head 32, thereby the chip D is held by the pick-up head 31. The chip D to be picked up can be determined based, for example, known good die (KGD) information sent online to the bonding device BD. Normally, only known good dies are picked up; however, when a known bad die (KBD) is to be bonded to a defective device portion of the wafer W, a known bad die is picked up.

[0065] The pick-up operation can be performed based on the type information of chip D. For example, when multiple types of chips D are held on the dicing frame 33, the type of chip D to be bonded to the bonding target region of wafer W is picked up. Alternatively, the pick-up operation can be performed based on the quality information of chip D. For example, the quality of chip D suitable for the bonding target region of wafer W is picked up. For example, when chip D is to be bonded to the bonding target region of a high-quality wafer W, a pick-up operation is performed to bond high-quality chip D.

[0066] In step S2003, multiple chips D picked up by multiple pick-up heads 31 are transferred to multiple bonding heads 422, and each chip D is held by its corresponding bonding head 422. When a chip D is picked up by a pick-up head 31, the semiconductor device surface faces the pick-up head 31. In contrast, when a chip D is transferred to a bonding head 422, the surface opposite to the semiconductor device surface faces the bonding head 422. Transferring the chip D to the bonding head 422 can be done directly by the pick-up head 31 or via multiple chip holding units. Pre-treatment for bonding can be performed while the chip D is being transferred. Examples of pre-treatment may include, but are not limited to, cleaning the chip D, applying adhesive in the case of adhesive bonding, and surface activation in the case of mixed bonding. If the surface activation becomes ineffective while the chip D is being transferred to the bonding head 422, it is preferable to use an atmospheric pressure plasma activation unit to activate the bonding surface after the bonding head 422 holds the chip D.

[0067] In this way, the wafer W and chip D, which are used as bonding targets, are held by their respective holding units. This is the state of each holding chip D in the multiple bonding heads 422.

[0068] In step S1003, the position of the chip D held by the bonding head 422 can be measured. Specifically, the wafer stage 43 can be driven by the driving mechanism 435, so that the feature portion of the chip D enters the field of view of the chip measurement unit 431. Focus adjustment can be provided by a focus adjustment mechanism disposed in the chip measurement unit 431, or by a Z-axis driving mechanism disposed in the bonding head 422, which drives the chip D along the Z-axis. Alternatively, focus adjustment can be provided by a Z-axis driving mechanism disposed on the wafer stage 43 on which the chip measurement unit 431 is disposed, which drives the chip measurement unit 431 in the Z-axis direction.

[0069] The scribe lines on which alignment marks used in semiconductor manufacturing processes are formed can be removed by cutting. Therefore, chip D typically does not have alignment marks. Thus, the position can be measured using the ends of pads or bumps arranged on chip D, regions with non-periodic arrangements whose positions can be specified, or the external shape of chip D as feature portions. The control unit CNT causes the chip measurement unit 431 to capture an image of chip D and determines the position of the feature portion based on the position of the image of the feature portion relative to the center of the output image of the chip measurement unit 431. Although it is necessary to manage the offset used when positioning chip D at the bonding portion based on the position of chip D measured using the chip measurement unit 431, the method will be described later.

[0070] When measuring the position of chip D, it is preferable to measure the positions of multiple feature portions within chip D, and also to measure the rotation of chip D. To measure the positions of multiple feature portions, the wafer stage 43 can be driven during each measurement of the feature portion positions, or the field of view of the chip measurement unit 431 can be designed to allow observation of multiple feature portions simultaneously. During bonding, chip D can be rotated by rotating the wafer stage 43. However, because the interferometer 434 has a small measurement range for the rotation direction, it is preferable to correct the rotation and reposition chip D when the rotation of chip D is large. When chip D is repositioned, its position needs to be measured again. During the autofocus operation when measuring the position of chip D, or using a second height measurement unit (not shown), the surface position (surface height) of the bonding surface of each chip D is measured. Because the thickness of chip D varies, it is advantageous to measure the surface position of chip D to accurately manage the gap between wafer W and chip D during the bonding operation. Here, the measurement results of the surface height of the bonding surface of chip D are stored in a storage unit (not shown) included in the control unit CNT. The height of chip D can be measured at multiple locations, and the orientation of chip D or wafer W can be adjusted during bonding via a tilting mechanism (not shown). This tilting mechanism can be incorporated into wafer stage 43, wafer chuck 432, or bonding head 422.

[0071] In step S1004, the control unit CNT determines whether simultaneous bonding can be performed using multiple bonding heads 422 (determination step). This is also the step of determining which of the first and second controls described above should be performed. In other words, during the bonding step, one of the first and second controls is performed. The first control controls the bonding such that the time during which the first chip held by the first holding unit is in contact with the bonding target object and the time during which the second chip held by the second holding unit is in contact with the bonding target object at least partially overlap. The second control controls the bonding such that the first chip held by the first holding unit is not in contact with the bonding target object, while the second chip held by the second holding unit is in contact with the bonding target object. The determination in step S1004 is based on at least one of the following: information about the arrangement of the bonding target area of ​​the wafer W, information about the circuit pattern formed in the bonding target area, information about the type of chip D, information about quality, information about thickness, and information about bonding history. Information about quality includes information about the quality of at least one of the wafer W and the chip D. Information about thickness includes information about the thickness of at least one of the wafer W and the chip D.

[0072] For example, based on the arrangement information of the bonding target regions on wafer W (such as... Figure 5 (As shown in the information), the control unit CNT determines whether bonding can be performed simultaneously by multiple bonding heads, that is, whether the bonding target region exists directly below the multiple bonding heads. When the bonding target region exists directly below the multiple bonding heads, the control unit CNT determines that simultaneous bonding can be performed by the multiple bonding heads 422. When there is no bonding target region directly below any of the multiple bonding heads during the bonding process, the control unit CNT determines that simultaneous bonding cannot be performed by the multiple bonding heads 422. In other words, when there is no bonding target region on the wafer W corresponding to the first chip held by the first bonding head, and there is a bonding target region on the wafer W corresponding to the second chip held by the second bonding head, the control unit CNT performs the second control.

[0073] In another example, based on information about the circuit pattern formed in the bonding target region or information about the type of chip D, the control unit CNT determines whether multiple bonding heads can perform bonding simultaneously. In other words, the control unit CNT determines whether each bonding head holds a chip D of a type suitable for the bonding target region. When all chips D held by multiple bonding heads are of the type to be bonded to the corresponding bonding target region, the control unit CNT determines that simultaneous bonding can be performed by multiple bonding heads 422. When any chip D held by multiple bonding heads is not of the type to be bonded to the corresponding bonding target region, the control unit CNT determines that simultaneous bonding cannot be performed by multiple bonding heads 422. Figure 5The example shown describes the case where two bonding heads can simultaneously bond to bonding target regions W2B and W2C. Assume a chip of type A is to be bonded to bonding target region W2B, and a chip of type B is to be bonded to bonding target region W2C. In this case, if both bonding heads hold a chip of type B, the desired type of chip cannot be bonded to bonding target region W2B. In this situation, the control unit CNT determines that simultaneous bonding by multiple bonding heads is not possible. In other words, when the first chip is not of the type corresponding to the first bonding target region on wafer W and the second chip is of the type corresponding to the second bonding target region on wafer W, the control unit CNT performs a second control. The first chip is held by the first bonding head, and the second chip is held by the second bonding head. Additionally, the bonding target regions of the unbonded chips at this time can be determined. For example, consider the case where a chip has not yet been bonded to bonding target region W2A and a chip of type B is to be bonded to bonding target region W2A. In this scenario, the control unit CNT determines that one of the type B chips held by the two bonding heads is to be bonded to bonding target region W2C, while the other is to be bonded to bonding target region W2A. Information regarding the circuit patterns formed in the bonding target regions includes a table or mapping that includes information about the name of the circuit patterns formed in the bonding target regions or the symbols assigned to the bonding target regions. Information regarding the type of chip D includes a table or mapping that includes information about the name of chip D or the symbols assigned to chip D. Here, the type of chip D is classified based on, for example, the type of circuit patterns included in chip D or the size of chip D.

[0074] In another example, based on information about the quality of the bonding target region on wafer W or the quality of chip D, the control unit CNT determines whether multiple bonding heads can perform simultaneous bonding; that is, whether the bonding heads hold chips with suitable quality for the bonding target region. When each chip D held by the multiple bonding heads has suitable quality for bonding to the corresponding bonding target region, the control unit CNT determines that simultaneous bonding can be performed by the multiple bonding heads 422. When any chip D held by the multiple bonding heads has quality unsuitable for bonding to the corresponding bonding target region, the control unit CNT determines that simultaneous bonding cannot be performed by the multiple bonding heads 422. Figure 5The example shown describes the case where it is determined whether two bonding heads can simultaneously bond to bonding target regions W2B and W2C. Assume a chip of quality grade A is bonded to bonding target region W2B, and a chip of quality grade B is bonded to bonding target region W2C. In this case, if both bonding heads hold the grade B chip, the chip of the desired grade cannot be bonded to bonding target region W2B. In this case, the control unit CNT determines that simultaneous bonding by multiple bonding heads is not possible. Additionally, the bonding target region for the unbonded chip can be determined. For example, consider the case where a chip has not yet been bonded to bonding target region W2A and a grade B chip is to be bonded to bonding target region W2A. In this case, the control unit CNT determines that one of the grade B chips held by the two bonding heads should be bonded to bonding target region W2C, and the other should be bonded to bonding target region W2A. Information regarding the quality of the bonding target region on wafer W or the quality of chip D includes a table or mapping information, which includes information about the name of the bonding target region or chip D, or the symbol assigned to the bonding target region or chip D. In other words, when the quality of the first chip does not correspond to the first bonding target region on wafer W, and the quality of the second chip corresponds to the second bonding target region on wafer W, the control unit CNT performs a second control. The first chip is a chip held by the first bonding head, and the second chip is a chip held by the second bonding head.

[0075] In another example, based on information about the thickness of wafer W or chip D, the control unit CNT determines whether multiple bonding heads can be bonded simultaneously. The thickness information can be obtained by acquiring information measured by another device, or it can be obtained using the aforementioned height measuring unit. For example, the thickness of the first chip held by bonding head 422a, which serves as the first holding unit, and the thickness of the second chip held by bonding head 422b, which serves as the second holding unit, can be different from each other. When the thicknesses are different, if the first holding unit and the second holding unit bond simultaneously, the time during which the bonding target object (wafer W) is in contact with the first chip is different from the time during which the bonding target object is in contact with the second chip, and as a result, bonding of at least one of the first and second chips may not be possible. In this case, the control unit CNT determines that multiple bonding heads cannot bond simultaneously. Furthermore, the thicknesses of the first bonding target region to be bonded by the first holding unit and the second bonding target region to be bonded by the second holding unit can be different from each other. When the thicknesses are different, if the first holding unit and the second holding unit bond simultaneously, the contact time between the bonding target (wafer W) and the first chip differs from the contact time between the bonding target and the second chip. As a result, bonding of at least one of the first and second chips may not be possible. In this case, the control unit CNT determines that multiple bonding heads cannot bond simultaneously. The control unit CNT may make this determination based on whether the thickness of the wafer W or the thickness of the chip D falls within a predetermined allowable range. In other words, when at least one of the thickness of the first bonding target area and the thickness of the first chip is outside the allowable range, and at least one of the thickness of the second bonding target area and the thickness of the second chip is within the allowable range, the control unit CNT performs a second control.

[0076] In another example, based on information about the bonding history, the control unit CNT determines whether multiple bonding heads can bond simultaneously. For example, in Figure 5 The example shown describes a situation where chip D has not yet been bonded to bonding target region W2B, chip D has been bonded to bonding target region W2C, and a chip D is to be bonded to each of the bonding target regions W2B and W2C.

[0077] In this scenario, bonding target regions W2B and W2C have different heights. Therefore, when both bonding heads perform bonding simultaneously, the contact time between bonding target regions W2B and W2C and chip D differs. As a result, bonding to at least one of bonding target regions W2B and W2C may not be performed correctly. In this case, the control unit CNT determines that simultaneous bonding by multiple bonding heads is not possible. In other words, the control unit CNT obtains information about the number of chips D already bonded to the first bonding target region, to which the first chip held by the first bonding head is to be bonded. Furthermore, the control unit CNT obtains information about the number of chips D already bonded to the second bonding target region, to which the second chip held by the second bonding head is to be bonded. When the number of chips already bonded to the first bonding target region differs from the number of chips already bonded to the second bonding target region, the control unit CNT performs a second control operation.

[0078] If it is determined in step S1004 that simultaneous bonding can be performed by multiple bonding heads 422, the process proceeds to step S1005. In step S1005, the wafer stage 43 is driven by the drive mechanism 435, such that the chip D is positioned in the bonding target region (bonding target portion) of the wafer W, which serves as the bonding target object. At this time, the control unit CNT controls the drive mechanism 435 to provide feedback control of the position of the wafer stage 43 based on the measurement results from the interferometer 434. At this time, the control unit CNT determines the target position of the wafer stage 43 based on the position and rotation of the wafer W measured in step S1002, the position and rotation of the chip D measured in step S1003, and the offset. When an offset occurs due to the bonding operation, as will be described later, the control unit CNT treats the offset as an offset amount. As described above, step S1005 can be performed by driving the bonding heads 422 to position the chip D in the bonding target region (bonding target portion) of the wafer W, which serves as the bonding target object.

[0079] In step S1006, multiple chips D are bonded to the bonding target area of ​​wafer W (bonding step). As a bonding operation, the bonding head 422 can move up and down, or the wafer stage 43 or wafer chuck 432 can move up and down. In other words, the driving mechanism can be driven to change the relative position (spacing) between the chip D held by the bonding head 422 and the wafer W held by the wafer chuck 432. In the bonding step of step S1006, by changing the relative position between the multiple bonding heads 422 and the wafer W, the multiple chips D held by the multiple bonding heads 422 are bonded to multiple bonding target areas of wafer W. In other words, the control performed in step S1006 is a first control. The first control controls the bonding such that the time during which the first chip held by the first bonding head contacts the wafer W and the time during which the second chip held by the second bonding head contacts the wafer W at least partially overlap.

[0080] In the bonding operation, various types of chips D can be bonded to a single wafer W, different chips D can be bonded to the corresponding bonding target areas on the wafer W, or different numbers of chips D can be bonded to the corresponding bonding target areas on the wafer W.

[0081] In step S1007, the control unit CNT determines whether the bonding of chip D to wafer W has been completed. This means determining whether the bonding of all chips D to be bonded to wafer W has been completed. For example, consider the case where, after bonding chip D to one bonding target region of wafer W, another chip D is further bonded to the already bonded chip D. In this case, if the second bonding of chip D to the same bonding target region has not yet been completed, it is determined in step S1007 that the bonding process has not yet been completed. If the bonding process has not been completed, the process returns to the chip D pick-up operation in step S2002. Figure 4 In the example shown, the determination in step S1007 is performed after the bonding operation in step S1006, and then the chip D pickup operation is performed in step S2002. However, the chip pickup operation in step S2002 can be performed in parallel during the time period from the measurement of chip D in step S1003 to the bonding operation in step S1006.

[0082] Once bonding of chip D to all the multiple bonding target portions of wafer W is complete, wafer W is unloaded from bonding apparatus BD in step S1008. Wafer W can be returned to the FOUP that holds it, or it can be returned to another container. However, bonding typically alters the thickness of wafer W, thus necessitating an increase in the spacing between wafers W compared to before bonding; therefore, wafer W is returned to another container.

[0083] If it is determined in step S1004 that simultaneous bonding cannot be performed using multiple bonding heads 422, the control unit CNT selects a bonding head (the chip D to be bonded) to be used for bonding. In other words, the control unit CNT selects a bonding head to be retracted. This selection is based on at least one of the following: arrangement information of the bonding target area of ​​the wafer W, information about the circuit pattern formed in the bonding target area, information about the type of chip D, information about quality, information about thickness, and information about bonding history. Information about quality includes information about the quality of at least one of the wafer W and the chip D. Information about thickness includes information about the thickness of at least one of the wafer W and the chip D. For example, when two of the three bonding heads can perform simultaneous bonding, but one bonding head cannot, only the bonding head that cannot perform simultaneous bonding will be retracted. Or, when only one of the two bonding heads can perform bonding, the other bonding head will be retracted. Or, as... Figure 5 As shown, when bonding is performed only on a single bonding target area (W2A), the bonding heads other than the one used for bonding will retract.

[0084] In this embodiment, the combination of the bonding head and the bonding target region on the wafer W is determined in step S3001. Details of step S3001 will be described later. After step S3001, the bonding order (sequence determination step) is determined in step S3002. Details of step S3002 will also be described later. Here, the determination of the combination in step S3001 and the determination of the bonding order in step S3002 are performed during the second control period.

[0085] Next, the control unit CNT retracts the selected bonding head (hereinafter referred to as "bonding head") based on the selection result (S1009). The bonding head retracts such that, for example, the bonding head to be retracted is driven in the +Z direction to prevent the chip D held by the retracted bonding head from contacting other components during the bonding process performed by the bonding head used for bonding. In other words, the bonding head to be retracted moves in a direction perpendicular to the bonding target surface on the wafer W (Z-axis direction) and away from the wafer W (+Z direction). The amount of movement at this time is, for example, a distance equal to or greater than the sum of the thickness of the first chip held by the first bonding head and the thickness of the wafer W. Alternatively, when the bonding head moves in the -Z direction for bonding, only the bonding head used for bonding moves in the -Z direction, while the bonding head to be retracted does not move in the -Z direction, thus achieving retraction. In other words, the bonding head to be retracted is maintained at a position farther from the wafer W than the bonding head used for bonding. The bonding head for bonding moves in a direction perpendicular to the bonding target surface on wafer W (Z-axis direction) and in a direction closer to wafer W (-Z direction). Alternatively, the bonding head to be retracted can move in the XY plane to prevent the chip D held by the retracted bonding head from contacting other components during the bonding process performed by the bonding head for bonding. In other words, the bonding head to be retracted can move in a direction parallel to the bonding target surface on wafer W (in the XY plane direction). When the bonding head is retracted by movement, a drive mechanism for moving the bonding head can be provided. For example, movement of the bonding head in the XY plane direction can involve moving the first bonding head to a position where, when viewed in a direction perpendicular to the bonding target surface on wafer W (Z-axis direction), the first bonding head does not overlap with wafer W. In step S1009, the retractable bonding head can move in multiple directions, including directions perpendicular to the bonding target surface of the bonding target object (Z-axis direction, +Z direction) and directions parallel to the bonding target surface of the bonding target object (directions in the XY plane).

[0086] When the wafer W is moved in the +Z direction by driving the wafer stage 43 for bonding processing, the distance in the Z-axis direction between the chip D held by the corresponding bonding head and the wafer W (wafer stage 43) changes according to the amount of movement of the wafer stage 43. This is the case where the wafer stage 43, which serves as the third holding unit, is moved to bring the wafer W closer to the chip D. Therefore, when the wafer W is moved in the +Z direction by driving the wafer stage 43 for bonding processing, the method of moving the bonding head is advantageous. Specifically, the method of retracting the bonding head by moving the bonding head in the +Z direction and the method of retracting the bonding head by moving the bonding head along the XY plane are both advantageous. Figure 6This diagram illustrates an example of the bonding head retracting from the wafer W in the Z-axis direction. This retraction method can be achieved by driving the bonding head to be retracted in the +Z direction or by driving only the bonding head used for bonding in the -Z direction for the bonding process. Figure 7 This diagram illustrates an example of the bonding head retracting from wafer W along the XY plane. The retraction method is achieved by moving the bonding head along the XY plane to retract it. The XY plane is a plane parallel to the plane on which the bonding target area is located on wafer W (the bonding target object), and the Z-axis direction is perpendicular to the XY plane.

[0087] Next, the wafer stage 43 is driven by the driving mechanism 435, so that the chip D is located in the bonding target area (bonding target portion) on the wafer W (S1010). Step S1010 can be performed by driving the bonding head.

[0088] Next, chip D is bonded to the bonding target area on wafer W (S1011, bonding step). As part of the bonding operation, the bonding head 422 can move up and down, or the wafer stage 43 or wafer chuck 432 can move up and down. In other words, a drive mechanism can be driven to change the relative position (spacing) between chip D held by the bonding head 422 and wafer W held by the wafer chuck 432. In the bonding step of S1006, by changing the relative position between the multiple bonding heads 422 and wafer W, multiple chips D held by the multiple bonding heads 422 are bonded to multiple bonding target areas on wafer W. In contrast, in step S1011, the retracted bonding head from step S1009 is in the retracted position; therefore, during the bonding operation in step S1011, the retracted bonding head and the chip D held by it do not contact (interfere with) other components. In other words, the control performed in step S1011 (and step S1009) is the second control.

[0089] The second control controls the bonding process so that the first chip held by the first bonding head does not contact the wafer W, while the second chip held by the second bonding head contacts the wafer W. The control unit CNT performs the second control so that, based on the relative movement between the bonding head group 422 and the wafer stage 43, the chip D is bonded to the corresponding bonding target area using a combination of bonding heads and bonding target areas.

[0090] Next, the control unit CNT determines whether any one of the multiple bonding heads holds chip D (S1012). If no bonding head among the multiple bonding heads holds chip D, the process proceeds to step S1007. If any one of the multiple bonding heads holds chip D, the process proceeds to step S1013. In step S1013, the control unit CNT determines whether the bonding heads need to be retracted. For example, when only one of the multiple bonding heads holds chip D, and bonding can be performed correctly without retracting the bonding head that does not hold chip D, the control unit CNT determines that retraction is not required. Alternatively, when the control unit CNT determines that all of the multiple bonding heads hold chip D and that these bonding heads can be bonded simultaneously, the control unit CNT determines that retraction is not required. This determination is the same as the determination in step S1004.

[0091] If it is determined in step S1013 that retraction is necessary, the process proceeds to step S1009. If it is determined in step S1013 that retraction is not necessary, the process proceeds to step S1010.

[0092] Next, the process of determining the combination of the bonding head and the bonding target region on the wafer W in step S3001 will be described. Figure 8 This is a diagram illustrating an example of the bonding sequence of the bonding target regions on wafer W. Figure 8 In the example shown, the bonding target regions arranged in the -X and -Y directions are bonded first, in the order indicated by the arrows.

[0093] The control unit CNT can obtain layout information by receiving information about the layout of the bonding target area from another information processing device. The layout information can be pre-stored in a storage unit, or it can be obtained by receiving input from the operator.

[0094] Figure 9 This is a schematic diagram showing the bonding target area on the wafer W and the first bonding head 422a and the second bonding head 422b disposed above the chip measurement unit 431 for measuring chip D. The first bonding head 422a and the second bonding head 422b each hold chip D. In this state, the chip measurement step in step S1003 has been completed, and the first bonding head 422a and the second bonding head 422b are positioned above the chip measurement unit 431. Figure 9 In the example shown, a single chip measurement unit 431 measures a first chip held by a first bonding head 422a and a second chip held by a second bonding head 422b. However, two chip measurement units can be configured, each measuring a chip D held by a corresponding bonding head.

[0095] Figure 9The black area on wafer W represents the bonding target area (bonding completed area) where chip D has been bonded. The white area on wafer W represents the bonding target area (bonding to be completed area) where chip D has not yet been bonded. When chip D is sequentially bonded to the bonding target area, as... Figure 8 As shown, the next bonding process is performed on the first bonding target region 71 and the second bonding target region 72, and bonding is performed on these bonding target regions 71 and 72 by the first bonding head 422a and the second bonding head 422b, respectively. In this arrangement of bonding target regions, when the allowable driving range of the bonding head 422 in the XY plane is small, it is determined in step S1004 that simultaneous bonding cannot be performed by multiple bonding heads 422. In other words, when multiple bonding heads used for bonding cannot be simultaneously positioned on the corresponding bonding target regions, it is determined that simultaneous bonding cannot be performed. Furthermore, even when multiple bonding heads can be simultaneously positioned on multiple bonding target regions, it can still be determined in step S1004 that simultaneous bonding cannot be performed, as described above.

[0096] The bonding target regions to be bonded by multiple bonding heads are determined in the same manner as in step S1004. In other words, in Figure 9 In the example shown, based on the same criteria used in step S1004, the target regions to be bonded are determined from among a plurality of bonding target regions on wafer W as the first bonding target region 71 and the second bonding target region 72. Specifically, the target regions to be bonded are determined based on at least one of the following: information about the arrangement of the bonding target regions on wafer W, information about the circuit pattern formed in the bonding target regions, information about the type of chip D, information about quality, information about thickness, and information about bonding history. Information about quality includes information about the quality of at least one of wafer W and chip D. Information about thickness includes information about the thickness of at least one of wafer W and chip D.

[0097] Here, consider the case where the first chip held by the first bonding head 422a and the second chip held by the second bonding head 422b are of the same type, and either the first chip or the second chip can be bonded to the first bonding target region and the second bonding target region. Since it is determined in step S1004 that simultaneous bonding is not possible, the first bonding head 422a and the second bonding head 422b perform bonding operations at different timings. In this case, a first combination is conceivable, wherein the first chip held by the first bonding head 422a is bonded to the first bonding target region 71, and the second chip held by the second bonding head 422b is bonded to the second bonding target region 72. As another combination, a second combination is conceivable, wherein the first chip held by the first bonding head 422a is bonded to the second bonding target region 72, and the second chip held by the second bonding head 422b is bonded to the first bonding target region 71. In this embodiment, when multiple bonding heads are used to bond chip D to multiple bonding target regions, the combination of bonding heads and bonding target regions is determined based on the relative movement between the bonding head group 422 and the wafer stage 43.

[0098] exist Figure 9 In the diagram, PA represents the center coordinates of the first bonding head 422a, PB represents the center coordinates of the second bonding head 422b, Qn represents the center coordinates of the first bonding target region 71, and Qn+1 represents the center coordinates of the second bonding target region 72. These center coordinates represent the corresponding center position of the target object in the XY plane. Although center coordinates are used as an example in this embodiment, coordinates of any specific location can be used; for example, coordinates of the ends can be used.

[0099] When the first bonding head 422a and the second bonding head 422b perform bonding on the first bonding target region 71 and the second bonding target region 72, the shorter relative movement between the bonding head assembly 422 and the wafer stage 43 is advantageous in terms of throughput. Here, the relative movement between the bonding head assembly 422 and the wafer stage 43 refers to the movement in the XY plane. In this embodiment, the combination of bonding heads and bonding target regions is determined by the following method.

[0100] In the first combination, the relative movement between the bonding head group 422 and the wafer stage 43 when the first bonding head 422a performs bonding on the first bonding target region 71 is defined as ||PA - Q n When the second bonding head 422b performs bonding on the second bonding target region 72, the relative movement between the bonding head group 422 and the wafer stage 43 is defined as ||PB - Q. n+1 ||.

[0101] In the second combination, the relative movement between the bonding head group 422 and the wafer stage 43 when the first bonding head 422a performs bonding on the second bonding target region 72 is defined as ||PA - Q n+1 When the second bonding head 422b performs bonding on the first bonding target region 71, the relative movement between the bonding head group 422 and the wafer stage 43 is defined as ||PB - Q. n These relative displacements in the XY plane are obtained, for example, from the corresponding center coordinates of the target object in the XY plane.

[0102] At this point, the evaluation value of the first combination is represented by equation (1), and the evaluation value of the second combination is represented by equation (2). These evaluation values ​​are obtained by squaring the relative movement amount when each bonding head performs bonding processing on the corresponding bonding target region, and then summing the squared relative movement amounts of all bonding heads. Although this embodiment describes an example of calculating evaluation values ​​and determining the combination of bonding heads and bonding target regions for a bonding head group 422 including two bonding heads, the number of bonding heads can be three or more. By using the least squares method, the differences between evaluation values ​​can be amplified for evaluation. When the differences can be evaluated without squaring, the sum of the relative movement amounts can be used.

[0103] Formula 1 Equation (1) Formula 2 Equation (2) The combination of bonding head and bonding target region with the lowest evaluation value among these evaluation values ​​is selected. By using this combination of bonding head and bonding target region, the relative movement between bonding head group 422 and wafer stage 43 during the bonding process can be reduced, thereby increasing throughput.

[0104] exist Figure 9 In the example shown, based on the above evaluation value, it is determined that the first bonding head 422a performs bonding on the second bonding target region 72, and the second bonding head 422b performs bonding on the first bonding target region 71.

[0105] Next, the determination of the bonding sequence in step S3002 will be described. In addition to determining the combination of the bonding head group 422 and multiple bonding target regions based on the relative movement between the bonding head group 422 and the wafer stage 43 in the XY plane, the bonding sequence is also determined to further improve throughput.

[0106] When determining the bonding sequence, if the bonding process is performed using the combination of bonding heads and bonding target regions determined in step S3001, the bonding time is calculated for each possible bonding sequence. Here, the bonding time is, for example, the drive time required for the relative movement between the bonding head group 422 and the wafer stage 43. Figure 9 In the example shown, in step S3001, it is determined that the first bonding head 422a performs bonding on the second bonding target region 72, and the second bonding head 422b performs bonding on the first bonding target region 71. In this case, there are two possible bonding sequences: a first bonding sequence and a second bonding sequence. In the first bonding sequence, the first bonding head 422a performs bonding on the second bonding target region 72, and then the second bonding head 422b performs bonding on the first bonding target region 71.

[0107] In the second bonding sequence, the second bonding head 422b performs bonding on the first bonding target region 71, and then the first bonding head 422a performs bonding on the second bonding target region 72. The possible number of bonding sequences is cPc = c! (c factorial), where c is the number of bonding heads. Therefore, the bonding time is calculated for each of the c! bonding sequences. The bonding start time is, for example, the time when the relative position between the bonding head group 422 and the wafer stage 43 changes from the state when the bonding head group 422 is positioned at a predetermined start reference position (e.g., above the chip measurement unit 431). The bonding end time is, for example, the time when the multiple bonding heads have completed bonding the chip D to the multiple bonding target regions. This is the time until the bonding of the chip D held by the multiple bonding heads with the multiple bonding target regions is completed. Alternatively, the bonding end time is the time when the bonding head group 422 has completed moving to a predetermined end reference position (e.g., a predetermined position above the chip measurement unit 431 or pick-up unit 3).

[0108] For example, the bonding time is calculated based on at least one of the dimensions of the chip D to be bonded, the dimensions of the bonding head, the moving speed of the wafer stage 43, and the moving speed of the bonding head. Here, the moving speed of the wafer stage 43 and the moving speed of the bonding head are collectively referred to as the relative moving speed between the bonding head group 422 and the wafer stage 43 (holding cell). Here, the dimensions of the chip D and the bonding head refer to the corresponding areas of the chip D and the bonding head in the XY plane. The larger the chip D and the bonding head, the longer the time required to position the chip D directly above the bonding target area (that is, the greater the relative movement between the wafer stage 43 and the bonding head group 422). When the chip D is large, the amount of movement required for the bonding head to retract increases, thus the bonding time becomes longer. In other words, calculating the bonding time based on the dimensions of the chip D includes calculating the bonding time based on the retraction time of the bonding head. Furthermore, as the moving speed of the wafer stage 43 and the bonding head increases, the bonding time can be reduced. The bonding time is calculated using calculation formulas, prediction models, or simulations.

[0109] After calculating the bonding time for each possible bonding sequence, the bonding sequence with the shortest bonding time is determined as the bonding sequence to be used in the bonding process.

[0110] Reference Figure 9 Example description. When bonding is performed in the first bonding sequence, the first bonding head 422a first bonds on the second bonding target region 72. At this time, the relative movement between the bonding head group 422 and the wafer stage 43 is determined by ||PA - Q. n+1|| indicates. In this case, since there is no bonding target region directly below the second bonding head 422b and there is no risk of interference, the second bonding head 422b does not need to be retracted during the bonding process performed by the first bonding head 422a. In other words, the retraction time of the second bonding head 422b can be reduced. Next, for the bonding process performed by the second bonding head 422b, the wafer stage 43 and the bonding head group 422 move one column relative to each other in the X-axis direction, such that the first bonding target region 71 is located directly below the second bonding head 422b. While the second bonding head 422b is bonding on the first bonding target region 71, the bonding target region to which the chip D has already been bonded exists directly below the first bonding head 422a. In this case, based on the thickness of the bonded chip D and / or the bonding history, it is determined whether the first bonding head 422a interferes with the wafer W during the bonding process performed by the second bonding head 422b. When the first bonding head 422a interferes, it needs to retract; when it does not interfere, it does not need to retract. In other words, in the first bonding sequence, the retraction time of the second bonding head 422b and the first bonding head 422a can be eliminated. The relative movement of the bonding target area is calculated by adding the movement corresponding to a column in the X-axis direction to ||PA - Q. n+1 || Obtained from above.

[0111] When bonding is performed in the second bonding sequence, the second bonding head 422b first bonds on the first bonding target region 71. At this time, the relative movement between the bonding head assembly 422 and the wafer stage 43 is determined by ||PB - Q. n The || symbol indicates that the bonding target area is located directly below the first bonding head 422a, and the first bonding head 422a itself holds the chip D; therefore, there is a risk of interference. Therefore, the first bonding head 422a needs to be retracted during the bonding process performed by the second bonding head 422b.

[0112] In other words, the retraction time of the first bonding head 422a is required. Next, for the bonding process performed by the first bonding head 422a, the wafer stage 43 and the bonding head group 422 move one column relative to each other in the X-axis direction, such that the second bonding target region 72 is located directly below the first bonding head 422a. While the first bonding head 422a is bonding on the second bonding target region 72, there is no bonding target region directly below the first bonding head 422a; therefore, there is no risk of interference. Therefore, the second bonding head 422b does not need to retract during the bonding process performed by the first bonding head 422a. In other words, the retraction time of the second bonding head 422b can be reduced. Therefore, in the second bonding sequence, the retraction time of the first bonding head 422a is required, and the retraction time of the second bonding head 422b can be eliminated. The relative movement of the bonding target regions is calculated by adding the movement corresponding to one column in the X-axis direction to ||PB - Q. n || Obtained from above.

[0113] Therefore, from the perspective of retraction time, the first bonding sequence is more advantageous than the second bonding sequence. The relative movement in the first bonding sequence is calculated by adding the movement corresponding to one column in the X-axis direction to ||PA - Q. n+1 The relative shift in the second bonding sequence is obtained by adding the shift corresponding to a column in the X-axis direction to ||PB-Q. n This is obtained from the above. In other words, in the second bonding sequence, reciprocating movement occurs in the X-axis direction, thus increasing the amount of movement in the X-axis direction and resulting in a longer movement time. Therefore, from the perspective of the amount of movement, the first bonding sequence is also more advantageous than the second bonding sequence. From these perspectives, in Figure 9 In the example shown, the control unit CNT determines to perform bonding in the first bonding sequence.

[0114] The method of this embodiment is not limited to the example described above. Alternatively, the bonding target region can be divided into several sections according to the number of bonding heads included in the bonding head group 422, and the combination of bonding target region and bonding head can be determined for each section. Furthermore, the bonding order can be determined based on the combination of bonding target region and bonding head determined for each section.

[0115] Second Embodiment This embodiment relates to a method for manufacturing articles using the above-described bonding apparatus BD.

[0116] Figure 10This is a flowchart illustrating a method for manufacturing an article according to this embodiment. First, each of the plurality of bonding heads included in the bonding head assembly 422 holds the chip D (S4001, holding step). Next, the chip D is bonded to a corresponding bonding target region among a plurality of bonding target regions on the wafer W (S4002, bonding step). Then, the wafer W to which the chip D has been bonded in the bonding step is processed (S4003, processing step).

[0117] During the bonding step, as multiple bonding heads bond chip D to multiple bonding target regions, bonding is performed using a combination of bonding heads and bonding target regions based on the relative movement between the bonding head group 422 and the holding unit holding the wafer W. Here, the relative movement refers to the movement within a plane (XY plane) parallel to the surface of the wafer W having multiple bonding target regions.

[0118] Examples of articles manufactured using this method include, but are not limited to, semiconductor integrated circuit (IC) devices, liquid crystal display elements, color filters, MEMS, light-emitting devices (LEDs), sensors, and optical devices. The article manufacturing method according to this embodiment can improve throughput.

[0119] It should be understood that this disclosure is not limited to the above embodiments, and various changes and modifications can be made without departing from the spirit and scope of this disclosure. Therefore, the appended claims are used to define the scope of this disclosure.

[0120] According to this disclosure, a bonding device that is advantageous in terms of throughput can be provided.

[0121] Other embodiments The embodiments disclosed herein can also be implemented by a computer of a system or apparatus and by a method executed by the computer of the system or apparatus, wherein the computer of the system or apparatus reads and executes computer-executable instructions (e.g., one or more programs) recorded on a storage medium (which may also be more fully referred to as a "non-transitory computer-readable storage medium") to perform one or more functions of the above embodiments, and / or the computer of the system or apparatus includes one or more circuits (e.g., application-specific integrated circuits (ASICs)) for performing one or more functions of the above embodiments, the method being performed by the computer of the system or apparatus, for example by reading and executing computer-executable instructions from the storage medium to perform one or more functions of the above embodiments, and / or controlling one or more circuits to perform one or more functions of the above embodiments. The computer may include one or more processors (e.g., a central processing unit (CPU), a microprocessor unit (MPU)) and may include a network of separate computers or separate processors to read and execute computer-executable instructions. The computer-executable instructions may be provided to the computer, for example, from a network or storage medium. The storage medium may include, for example, a hard disk, random access memory (RAM), read-only memory (ROM), storage devices for distributed computing systems, optical discs (such as optical discs (CD), digital versatile optical discs (DVD), or Blu-ray discs (BD)). TM One or more of the following: flash memory devices, memory cards, etc.

[0122] Although this disclosure has been described with reference to embodiments, it should be understood that this disclosure is not limited to the disclosed embodiments. The scope of the appended claims should be given the broadest interpretation to cover all such variations and equivalent structures and functions.

Claims

1. A bonding apparatus configured to bond a chip to a corresponding bonding target region among a plurality of bonding target regions on a wafer, the bonding apparatus comprising: A bonding head assembly, comprising a plurality of bonding heads configured to hold the chip; A holding unit, configured to hold the wafer; as well as A control unit is configured to control the relative position between the bonding head assembly and the holding unit. The control unit controls bonding based on the relative movement between the bonding head group and the holding unit in a plane parallel to the surface of the wafer having the plurality of bonding target regions, and based on the combination of bonding heads and bonding target regions, so that the plurality of bonding heads included in the bonding head group bond the chip to the corresponding bonding target region among the plurality of bonding target regions.

2. The bonding apparatus according to claim 1, in, The plurality of bonding target regions includes a first bonding target region and a second bonding target region. The bonding head assembly includes a first bonding head and a second bonding head, and The control unit controls the bonding such that when a first relative movement is less than a second relative movement, the first bonding head bonds on the first bonding target region and the second bonding head bonds on the second bonding target region. The first relative movement is the relative movement when the first bonding head bonds on the first bonding target region and the second bonding head bonds on the second bonding target region, and the second relative movement is the relative movement when the first bonding head bonds on the second bonding target region and the second bonding head bonds on the first bonding target region.

3. The bonding apparatus according to claim 2, in, The first relative movement is the sum of the relative movement when the first bonding head moves to a position above the first bonding target area and the relative movement when the second bonding head moves to a position above the second bonding target area. The second relative movement is the sum of the relative movement when the first bonding head moves to a position above the second bonding target area and the relative movement when the second bonding head moves to a position above the first bonding target area.

4. The bonding apparatus according to claim 2, in, The first relative movement is the sum of the squared relative movement when the first bonding head moves to a position above the first bonding target region and the squared relative movement when the second bonding head moves to a position above the second bonding target region. The second relative movement amount is the sum of the value obtained by squaring the relative movement amount when the first bonding head moves to a position above the second bonding target area and the value obtained by squaring the relative movement amount when the second bonding head moves to a position above the first bonding target area.

5. The bonding apparatus according to claim 1, wherein, The bonding target region to which the chip is to be bonded by the bonding head group is determined based on at least one of the following: the arrangement information of the plurality of bonding target regions, the information about the circuit pattern formed in the bonding target regions, the chip type information, the quality information of the bonding target regions, the chip quality information, the wafer thickness information, the chip thickness information, and the bonding history information.

6. The bonding apparatus according to claim 1, wherein, The control unit determines, based on the combination, the bonding sequence for bonding the chip to the plurality of bonding target regions using the plurality of bonding heads included in the bonding head group.

7. The bonding apparatus according to claim 1, wherein, The control unit determines the bonding sequence based on the time required to bond the chip to the corresponding bonding target region among the plurality of bonding target regions using the plurality of bonding heads included in the bonding head group.

8. The bonding apparatus according to claim 7, wherein, The time period is the time from the start of the relative movement between the bonding head group and the holding unit when the bonding head group is positioned at a predetermined starting reference position to the time when the chip held by the plurality of bonding heads is bonded to the plurality of bonding target regions.

9. The bonding apparatus according to claim 7, wherein, The time period is the time from the start of the relative movement between the bonding head assembly and the holding unit when the bonding head assembly is positioned at a predetermined starting reference position to the time when the bonding head assembly has completed moving to a predetermined ending reference position.

10. The bonding apparatus according to claim 7, wherein, The time is calculated based on at least one of the following: the size information of the chip held by the plurality of bonding heads, the size information of the plurality of bonding heads, and the relative movement speed between the bonding head group and the holding unit.

11. The bonding apparatus according to claim 7, wherein, The time is calculated based on the time it takes for the bonding head to retract.

12. The bonding apparatus according to claim 7, wherein, The control unit calculates the time for each of the multiple bonding sequences and controls the bonding process to proceed in the bonding sequence with the shortest computation time.

13. The bonding apparatus according to claim 1, in, The bonding head assembly includes a first bonding head and a second bonding head, and The control unit is configured to switch between a first control and a second control. The first control is configured to control bonding such that the time period during which the first chip held by the first bonding head contacts the bonding target region and the time period during which the second chip held by the second bonding head contacts the bonding target region at least partially overlap. The second control is configured to control bonding such that while the second chip held by the second bonding head contacts the bonding target region, it prevents the first chip held by the first bonding head from contacting the bonding target region. In the second control, the control unit controls the bonding process based on the relative movement between the bonding head group and the holding unit, and on the combination of the bonding head and the bonding target region, so that the chip is bonded to the corresponding bonding target region among the plurality of bonding target regions.

14. A bonding method for bonding a chip to corresponding bonding target regions among a plurality of bonding target regions on a wafer, the bonding method comprising: The chip is held in place by using the corresponding bonding head from among the multiple bonding heads included in the bonding head group; as well as The chip is bonded to a corresponding bonding target region among the plurality of bonding target regions. In the bonding process, the plurality of bonding heads bond the chip to a corresponding bonding target region among the plurality of bonding target regions based on the relative movement between the bonding head group and the holding unit holding the wafer in a plane parallel to the surface of the wafer having the plurality of bonding target regions, and based on the combination of bonding heads and bonding target regions.

15. The bonding method according to claim 14, further comprising: The bonding target region to which the chip is to be bonded by the bonding head group is determined based on at least one of the following: the arrangement information of the plurality of bonding target regions, the information about the circuit pattern formed in the bonding target regions, the chip type information, the quality information of the bonding target regions, the chip quality information, the wafer thickness information, the chip thickness information, and the bonding history information.

16. The bonding method according to claim 14, further comprising: The bonding order is determined based on the time required to bond the chip to the corresponding bonding target region among the plurality of bonding target regions using the plurality of bonding heads.

17. A non-transitory computer-readable storage medium storing a program for causing a computer to perform the bonding method according to claim 14.

18. A method for manufacturing an article, the method comprising: The chip is held in place by using the corresponding bonding head from among the multiple bonding heads included in the bonding head group; The chip is bonded to a corresponding bonding target region among multiple bonding target regions on the wafer; as well as The chip is bonded to the wafer through the bonding process. In the bonding process, the plurality of bonding heads bond the chip to a corresponding bonding target region among the plurality of bonding target regions based on the relative movement between the bonding head group and the holding unit holding the wafer in a plane parallel to the surface of the wafer having the plurality of bonding target regions, and based on the combination of bonding heads and bonding target regions.

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