Wafer level three-dimensional stacked system-on-chip and method of manufacturing the same

Abstract

The present application relates to the field of semiconductor manufacturing, and particularly relates to a wafer-level three-dimensional stacked system chip and a manufacturing method thereof. The method comprises: providing a first wafer, a first core particle array is formed on the upper surface of the first wafer, and the first core particle array comprises at least one first defective core particle; and providing a second wafer, a second core particle array is formed on the upper surface of the second wafer, and the second core particle array corresponds to the first core particle array one by one. The present application also provides a system chip manufactured by the above method. Through a three-stage process of "wafer-level selective bonding, then removing defective core particles, and finally chip-level repairing", the present application realizes the precision of point-by-point repairing at the level of chip-to-wafer bonding while retaining the high production efficiency of wafer-to-wafer bonding, and effectively solves the technical problem that yield and efficiency are difficult to be balanced in the manufacturing of three-dimensional stacked system chips.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more specifically to a wafer-level three-dimensional stacked system chip and its manufacturing method. Background Technology

[0002] As Moore's Law slows down, 3D integration technology, especially 3D stacked system-on-chips, has become an important way to maintain and improve chip performance. By stacking and interconnecting different functional chips such as logic, memory, and analog chips in the vertical direction, higher integration density, shorter interconnect latency, and lower power consumption can be achieved.

[0003] Currently, the mainstream 3D stacking manufacturing methods are mainly divided into two categories: Wafer-to-Wafer (W2W) bonding technology: This method involves directly bonding two manufactured wafers face-to-face, then dicing the entire assembly into individual stacked chips. The significant advantage of the W2W process lies in its extremely high production efficiency, allowing the connection of tens of thousands of stacked cells in a single bonding process. However, its inherent limitations are also prominent: yield issues. Since both wafers may contain known-good dies (KGD), if even one defective die exists in a pair of matched dies, the entire stacked cell will fail, leading to an exponential increase in yield loss. This is especially problematic as wafer size increases and process nodes shrink, causing a sharp rise in cost.

[0004] Die-to-Wafer (D2W) bonding technology: This method first dices a wafer into individual chips, then filters out defective chips, and finally bonds them one by one to the corresponding positions on another wafer. The advantage of the D2W process is that it effectively avoids the yield problems of the W2W process by stacking only defective chips, thus ensuring the yield of the final product. However, its disadvantages are equally obvious: low production efficiency. The process of picking up and bonding chips one by one is extremely time-consuming, and the throughput (UPH) is much lower than that of the W2W process, leading to a significant increase in manufacturing costs.

[0005] To overcome the shortcomings of the two methods mentioned above, the industry has proposed some hybrid solutions, such as performing D2W stacking first and then wafer-level molding. However, these solutions have complex processes and are difficult to achieve high-density wafer-level interconnects.

[0006] Therefore, there is an urgent need for a new wafer-level 3D stacking method that can achieve the high efficiency of W2W process, solve its yield bottleneck, and avoid the low throughput problem of pure D2W process. Summary of the Invention

[0007] The present invention aims to overcome the problems of exponential decline in yield due to defective chips in existing wafer-to-wafer bonding processes, low production efficiency of chip-to-wafer bonding processes, and the complexity of existing hybrid solutions and the difficulty in achieving high-density wafer-level interconnects, and provides a wafer-level three-dimensional stacked system chip and its manufacturing method.

[0008] To address the above problems, this invention provides a method for manufacturing a wafer-level three-dimensional stacked system-on-a-chip, the method comprising the following steps: A first wafer is provided, and a first die array is formed on the upper surface of the first wafer, the first die array including at least one first die to be removed; A second wafer is provided, and a second chip array is formed on the upper surface of the second wafer, wherein the second chip array corresponds one-to-one with the first chip array; A first permanent bond is formed on the upper surface of the first wafer, excluding the first core region to be removed, or a second permanent bond is formed on the surface of the second wafer corresponding to the region excluding the first core region to be removed. The upper surface of the first wafer is bonded to the upper surface of the second wafer; From the back side of the second wafer, the first core to be removed is selectively cut and separated from the adjacent first core; The first core to be removed is selectively removed to expose the upper surface of the second wafer and form a vacancy. A third core is provided and the third core is bonded to the upper surface of the second core exposed at the vacant position; An electrical interconnect structure is formed between the first core and the corresponding second core, and between the third core and the corresponding second core.

[0009] Optionally, before bonding the third core to the upper surface of the second core exposed at the vacant location, the method further includes: A first partially permanent bonding sheet is formed on the lower surface of the third core particle, and the third core particle is bonded to the upper surface of the second core particle exposed at the vacant position through the first partially permanent bonding sheet; or, A second partially permanent bonding sheet is formed on the upper surface of the second core exposed at the vacant location, and the third core is bonded to the upper surface of the second core exposed at the vacant location through the second partially permanent bonding sheet.

[0010] Optionally, before bonding the upper surface of the first wafer to the upper surface of the second wafer, a temporary bonding sheet may be formed on the upper surface of the first wafer outside the region of the first core to be removed, or on the upper surface of the second wafer corresponding to the region of the first core to be removed.

[0011] Optionally, the interconnection structure includes: A first bump array formed on the surface of the first die, and a first pad array formed on the upper surface of the second wafer and corresponding to the first bump array; or A second bump array formed on the surface of the second core, and a second pad array formed on the upper surface of the first wafer and corresponding to the second bump array.

[0012] Optionally, before cutting and separating the first core particle to be removed, the method further includes: Remove the first bump array on the first core to be removed; or Remove the second bump array on the second core corresponding to the first core to be removed from the upper surface of the second wafer.

[0013] Optionally, the third core chip includes a third bump array or a third pad array.

[0014] Optionally, the method for forming the permanent bonded sheet includes: An organic photosensitive adhesive film is coated on the upper surface of the first wafer or the upper surface of the second wafer; The organic photosensitive adhesive film is patterned to remove the adhesive film corresponding to the first core particle area to be removed.

[0015] Optionally, a first metal interconnect array is embedded in the first permanent bond sheet, the first metal interconnects extending through the first permanent bond sheet, with their lower ends electrically connected to the pads of the first core and their upper ends exposed on the surface of the first permanent bond sheet; A second metal interconnect array is embedded in the second permanent bond sheet. The second metal interconnect extends through the second permanent bond sheet, with its lower end electrically connected to the pad of the second core and its upper end exposed on the surface of the second permanent bond sheet. In the step of forming the interconnect structure, annealing is used to form metal-metal bonds between the first metal interconnect sheet and the second metal interconnect sheet, which are arranged in a one-to-one manner, so that the first core and the second core are electrically interconnected.

[0016] Optionally, before bonding the third core to the vacant site, the method further includes: A third permanent bonding sheet is formed on the bonding surface of the third core, and a third metal interconnect array is embedded in the third permanent bonding sheet; The third metal interconnect extends through the third permanent bond sheet, with its lower end electrically connected to the pad of the third core and its upper end exposed on the surface of the third permanent bond sheet. The third metal interconnect piece makes one-to-one contact with the second metal interconnect piece exposed at the vacant position, and metal-to-metal bonding is formed by annealing, so that the third core piece and the corresponding second core piece are electrically interconnected.

[0017] Optionally, before bonding the third core to the upper surface of the second core exposed at the vacant location, the method further includes: Along the boundary of the vacant site, a focused ion beam etching or argon ion beam etching process is used to locally thin and etch the area of ​​the first permanent bonded sheet located at the edge of the vacant site, so that the first permanent bonded sheet forms a depression between the vacant site and the adjacent permanent bonded area.

[0018] Optionally, after bonding the third core to the upper surface of the second core exposed at the vacant location, the method further includes: The first chip contains some or all of the I / O pads, which correspond one-to-one with the second chip containing some or all of the I / O pads. The bonded overall structure is cut and separated into individual stacked units, and a vertical interconnect pillar array is formed between the corresponding I / O pads through a selective metal growth process. Dielectric isolation material is filled into the gaps in the vertical interconnect pillar array.

[0019] Optionally, the vertical interconnect pillars are made of any single metal or alloy selected from copper, aluminum, gold, silver, tin, nickel, cobalt, and tantalum.

[0020] Optionally, the first wafer and the second wafer are bonded using any one of van der Waals bonding, chemical adhesive bonding, or metal welding bonding.

[0021] Optionally, the first core particle to be removed can be cut and separated from the other first core particles by any one of mechanical cutting, laser cutting, or plasma cutting.

[0022] The present invention has at least the following beneficial effects: 1. This solution identifies defective cores before bonding and selectively avoids defective core areas during the formation of the permanent bond wafer. After W2W bonding is completed, the defective cores are cut, separated, and removed from the back side of the second wafer. The vacant positions are then repaired with a third core using the D2W method. This process solves the yield problem of stacking cell failure caused by defective cores while maintaining the high production efficiency of W2W whole-wafer bonding.

[0023] 2. This solution uses W2W batch bonding as the main process to complete the stacking of most cores, and only performs D2W repair on defective cores. This avoids the inefficient operation of picking up and bonding all cores one by one, thus retaining the high output efficiency of W2W and giving full play to the point repair capability of D2W.

[0024] 3. This solution employs a three-stage process flow: W2W selective bonding, defective die removal, and D2W repair. This process achieves D2W-level pinpoint repair accuracy while maintaining the mass production efficiency of W2W. It solves the yield bottleneck of traditional W2W and the efficiency bottleneck of pure D2W at extremely low marginal cost. At the same time, it provides a variety of optional interconnect solutions to adapt to different density and cost requirements, providing a complete solution for the mass production of 3D stacked system chips that combines high efficiency, high yield, high reliability, and high process compatibility. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of the first wafer in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the structure of the second wafer in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the bonding structure between the first wafer and the second wafer in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the structure for cutting the first core particle to be removed in Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the structure for removing the first core particle in Embodiment 1 of the present invention; Figure 6 This is a schematic diagram of the structure in Embodiment 1 of the present invention, in which the first core to be removed is replaced with a good third core. Figure 7 This is a schematic diagram of the structure of a complete three-dimensional stacked system chip in Embodiment 1 of the present invention; Figure 8 This is a schematic diagram of the structure for forming a metal interconnect sheet in Embodiment 2 of the present invention; Figure 9 This is a schematic diagram of the structure forming vertical interconnect pillars in Embodiment 3 of the present invention; Icon labels: 10-First wafer; 11-First chip array; 12-First chip to be removed; 13-Bonding wafer; 20-Second wafer; 22-Bonding wafer body; 30-Micro bump; 40-Metal interconnect wafer; 50-Vertical interconnect pillar; 60-Third chip. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] This invention can be widely applied to various semiconductor chip manufacturing fields that require high-density, high-reliability three-dimensional integration, and is especially suitable for application scenarios such as logic-memory chip stacking, processor-cache chip stacking, and heterogeneous integrated system-in-package (SiP).

[0028] Example 1

[0029] This embodiment provides a method for manufacturing a wafer-level three-dimensional stacked system-on-a-chip, the method comprising the following steps: A first wafer 10 is provided, and a first chip array 11 is formed on the upper surface of the first wafer 10. The first chip array 11 includes at least one first chip 12 to be removed. like Figure 1 As shown, a first wafer 10 with completed front-end processing is provided. The first wafer 10 is a silicon wafer containing logic chips. Below the upper surface of the first wafer 10, a plurality of regularly arranged first dies are formed through photolithography and etching processes. Each first die contains a complete device layer and interconnect layer, and the upper surface of each first die exposes pads. Defective dies in the first die array 11 are identified through wafer testing and marked as first dies to be removed 12.

[0030] A second wafer 20 is provided, and a second chip array is formed on the upper surface of the second wafer 20. The second chip array corresponds one-to-one with the first chip array 11. like Figure 2 As shown, a second wafer 20 is provided. The second wafer 20 is a silicon wafer containing memory chips, and its dimensions are the same as those of the first wafer 10. A second chip array is formed below the upper surface of the second wafer 20. Each second chip in the second chip array contains a complete device layer and interconnect layer, and the upper surface of each second chip exposes pads. The arrangement and spacing of the second chips correspond exactly to those of the first chips.

[0031] Optical alignment marks are formed at the edge regions of the first wafer 10 and the second wafer 20 using photolithography and etching processes, respectively, for subsequent high-precision bonding.

[0032] A first permanent bond is formed on the upper surface of the first wafer 10, excluding the region of the first core to be removed 12, or a second permanent bond is formed on the surface of the second wafer 20, corresponding to the region excluding the region of the first core to be removed 12. refer to Figure 3 As shown, specifically, this step uses a combination of spin coating and photolithography patterning to form a permanent bonding sheet. In this embodiment, the first permanent bonding sheet is formed on the upper surface of the first wafer 10.

[0033] First, an organic photosensitive adhesive film is uniformly coated onto the entire upper surface of the first wafer 10 using a spin coater. This adhesive film is made of benzocyclobutene resin, which combines good adhesion, low dielectric constant, and excellent thermal stability. After spin coating, a uniform film with a thickness of 20 μm is obtained. This provides sufficient bonding strength to support subsequent wafer-level processes while ensuring sufficient step coverage to fill the tiny gaps between the die particles.

[0034] A soft baking process is then performed to remove the organic solvents from the benzocyclobutene resin, allowing the film to partially cure and enhancing its adhesion to the wafer surface.

[0035] Next, a photolithography machine is used to project the designed mask pattern onto the surface of the benzocyclobutene film. The mask is designed to ensure that all other areas on the first wafer 10 are exposed, except for the area where the first core 12 to be removed is located (including a 20μm wide buffer zone around the core).

[0036] After exposure, a specialized benzocyclobutene developer is used for development. During development, the benzocyclobutene in the exposed areas undergoes a cross-linking reaction and becomes insoluble in the developer, thus remaining in the solution; while the benzocyclobutene in the unexposed core areas to be removed is completely dissolved and removed by the developer, exposing the inorganic passivation layer (made of silicon nitride) on the surface of the first core below that area. After development, the core is rinsed with deionized water and then spun dry.

[0037] Finally, the patterned first wafer 10 is hard-baked. The temperature is increased to 250°C at a rate of 5°C / min and held for 60 minutes. During this process, the benzocyclobutene in the retained regions undergoes complete cross-linking, forming a chemically stable and mechanically strong first permanent bond sheet. This permanent bond sheet will serve as the permanent connection medium between all good cores, except for defective areas, during subsequent wafer-to-wafer bonding.

[0038] In other embodiments, instead of processing the first wafer 10, the same spin coating, exposure, development and curing process can be used to form a second permanent bonding sheet on the upper surface of the second wafer 20, the coverage area of ​​which corresponds to all areas other than the area of ​​the first core 12 to be removed.

[0039] In some embodiments of this example, to further facilitate subsequent removal operations and prevent interface contamination, a temporary bonding sheet is formed between the first core particle to be removed 12 and the corresponding second core particle. The method for forming this temporary bonding sheet includes, but is not limited to, the following two approaches: Method 1 (Modification Method): After forming the first permanent bonded sheet (BCB film) in step 3, ultraviolet light (UV) is used to selectively irradiate the first core particle 12 region to be removed through a mask. The irradiation dose is 1000mJ / cm² to 3000mJ / cm², causing the BCB material in this region to undergo partial photolysis reaction, reducing the degree of crosslinking, and decreasing its adhesion strength from >10MPa at the permanent bonding level to <1MPa at the temporary bonding level, thereby transforming it from a permanent bonded sheet into a temporary bonded sheet.

[0040] Method 2 (Coating Method): After the permanent bonded sheet in the first core particle 12 region to be removed is patterned and removed, a layer of thermoplastic temporary adhesive material (such as polyimide precursor or thermoplastic polyester) with a thickness of 1μm to 5μm is coated only in the first core particle 12 region to be removed using microneedle jetting or screen printing. This material is viscous at room temperature to assist pre-bonding, and decomposes and volatilizes when heated to above 200°C and does not participate in permanent bonding.

[0041] The upper surface of the first wafer 10 is bonded to the upper surface of the second wafer 20; refer to Figure 3 As shown, specifically, the first wafer 10, with its permanent bonding pattern already completed, is pre-aligned and bonded to the uncoated second wafer 20. This embodiment employs a chemical adhesive bonding method. At room temperature, pre-alignment and fixation are first performed using van der Waals forces, followed by heating and pressurization to cause cross-linking and curing of the BCB permanent bonding sheets, forming a permanent chemical bond.

[0042] At room temperature, an initial pressure of 5 kN is first applied to the two wafers to bring their upper surfaces together. At this point, the permanent benzocyclobutene bond on the first wafer 10 and the SiO2 / Si3N4 passivation layer on the upper surface of the second wafer 20 are initially adsorbed by intermolecular van der Waals forces and capillary forces, and the two wafers are temporarily fixed together.

[0043] Subsequently, the bonding chamber was evacuated to 10. -3The pressure is increased by 10 kN / min to remove air and moisture from the interface, preventing bubble defects after bonding. Next, the chamber temperature is raised to 250°C, and the bonding pressure is increased to 30 kN, at a rate of 5 kN / min. Under these conditions, the viscosity of the benzocyclobutene resin further decreases, allowing it to flow and fill the tiny gaps between the two wafers. Simultaneously, the benzocyclobutene undergoes its final cross-linking and curing reaction, firmly bonding the two wafers together.

[0044] It is important to note that, since the benzocyclobutene in the first core particle 12 region to be removed has been completely removed in step three, there is no permanent chemical bonding medium in this region between the first wafer 10 and the second wafer 20. Only extremely weak physical contact exists between the lower surface of the first core particle 12 and the corresponding upper surface of the second core particle. This region will not form a strong connection during the bonding process, but rather a predetermined "weak connection region" or "fracture layer," facilitating subsequent selective removal operations.

[0045] In other embodiments, van der Waals bonding can also be used, which is suitable for dielectric layer pre-bonding in hybrid bonding processes. It does not require heating and pressure, and relies solely on the intermolecular forces after surface activation for bonding. The bonding strength is then enhanced by low-temperature annealing. Alternatively, metal welding bonding can be used, in which a low-melting-point solder, such as an AuSn eutectic alloy, is prepared on the wafer surface in advance. When heated to above the eutectic temperature, the solder melts and wets the opposite metal pads. After cooling, a strong metal bond is formed.

[0046] Before cutting and separating, since the first core particle 12 to be removed has an array of microbumps 30, it is necessary to use wet etching (using a mixed solution of nitric acid and hydrofluoric acid) or mechanical grinding process to remove all the microbumps 30 array on the first core particle 12 to be removed, so as to prevent metal debris from splashing and contaminating adjacent good core particles during subsequent cutting.

[0047] Specifically, in this embodiment, before laser cutting from the back side of the second wafer 20, a wet etching process (using a mixed solution of nitric acid and hydrofluoric acid) or a mechanical polishing process is used to remove all the microbumps 30 array on the first core 12 to be removed. The purpose of removing the bumps in the bad core area is to prevent the bump material (such as Cu / SnAg alloy) from generating metal spatter due to high-temperature melting during subsequent laser cutting, which would contaminate the surface of adjacent good cores or bonding interfaces, thereby avoiding additional yield loss.

[0048] In other embodiments (e.g., where the microbump 30 array is formed on the surface of the second die of the second wafer 20), the microbump 30 array on the second die corresponding to the first die to be removed on the upper surface of the second wafer 20 is removed accordingly. The removal method is the same as above.

[0049] From the back side of the second wafer 20, the first core to be removed 12 is selectively cut and separated from the adjacent first core; Laser cutting is used to completely separate the silicon material between the first core 12 to be removed and its adjacent first cores.

[0050] refer to Figure 4 As shown, specifically, by setting up laser cutting, the focused laser beam scans along the rectangular boundary of the core to be removed, and the depth of the cutting trench just penetrates the entire silicon layer thickness of the first wafer 10 and terminates at the bonding interface.

[0051] The etching endpoint is determined by real-time monitoring of the plasma spectral signal during the cutting process to detect the presence of characteristic peaks of the back surface material of the second wafer 20. This allows the cutting endpoint to be precisely controlled at the bonding interface, thereby forming a complete annular isolation trench around the defective core while preventing the second core below from being damaged by the cutting process.

[0052] In other embodiments, mechanical cutting or plasma cutting may also be used.

[0053] The first core 12 to be removed is selectively removed to expose the upper surface of the second wafer 20 and form a vacancy. refer to Figure 5 As shown, specifically, the first die 12 to be removed is removed using a high-precision vacuum nozzle and force feedback control system equipped on the pick-up stage. Since this area did not form a permanent bond during bonding, and the cutting groove has completely separated the die from its surroundings, the first die 12 is easily separated from the second die below under an upward pulling force and is removed completely without damage. After removal, the area originally covered by the defective die exposes the upper surface of the second wafer 20 below, forming a geometrically regular vacant space. The depth of this vacant space is 775 μm, and its bottom is the complete upper surface of the second die (including its passivation layer and input / output pads). This vacant space provides precise mounting space for subsequent replacement dies.

[0054] A third core 60 is provided and the third core 60 is bonded to the upper surface of the second core exposed at the vacant position.

[0055] refer to Figure 6As shown, specifically, after removing defective core particles, the exposed surface of the second core particle at the vacant location is cleaned and activated. An oxygen plasma cleaning process is used to remove organic contaminants and introduce active groups such as hydroxyl groups onto the surface to enhance the adhesion of subsequent bonding.

[0056] Provide a known good core that has been fully pre-tested as the third core 60. The function, size, and input / output pad layout of this third core must be completely consistent with the removed defective core to ensure compatibility with the second core.

[0057] Before final mounting, a localized permanent bonding sheet is precisely coated onto the center area of ​​the lower surface of the third core using an adhesive dipping process. This localized permanent bonding sheet is also made of benzocyclobutene resin, with a thickness of only 5 μm, and the coating area is the same size as that of the second core.

[0058] In other embodiments, a second locally permanent bonded sheet can also be formed on the upper surface of the second core exposed at the vacant location using microneedle jetting technology.

[0059] Then, using a high-precision flip-chip bonding machine, the third core particle is placed in the empty position with a placement accuracy of ±1μm. A pressure of 15N is applied to the placement head, and the placement head temperature is raised to 250°C and held for 10s to pre-cure the local benzocyclobutene, thus initially fixing the third core particle 60 in the empty position.

[0060] Subsequently, the entire wafer assembly was placed in a nitrogen oven and post-cured at 250°C for 60 minutes to fully cross-link the localized benzocyclobutene, forming permanent mechanical and electrical connections. This completed the replacement of the defective core, and all stacked cells on the entire wafer were now in known good condition.

[0061] An electrical interconnect structure is formed between the first core and the corresponding second core, and between the third core and the corresponding second core.

[0062] Specifically, in this embodiment, the electrical interconnect structure is formed by the following thermo-press bonding method: refer to Figure 7 As shown, before the first wafer 10 and the second wafer 20 are bonded, a Cu / SnAg microbump array 30 is formed at the pad opening of each first core of the first wafer 10 by seed layer sputtering and electroplating. Correspondingly, a copper pad array is formed at the pad opening of each second core of the second wafer 20 by sputtering and electroplating. The copper pad array is set away from the area of ​​the first core 12 to be removed.

[0063] After the first wafer 10 and the second wafer 20 are mechanically aligned and pre-fixed using BCB permanent bonding sheets, the entire bonding wafer assembly is placed in a thermosetting bonding machine, heated to 300°C, and simultaneously subjected to a bonding pressure of 30 kN for 60 seconds. During this process, the Cu / SnAg microbumps 30 and the copper pads achieve electrical connection under the combined action of heat and pressure: the SnAg solder cap melts, the molten solder flows and wets the surface of the opposite copper pad, and an interfacial reaction occurs with the copper pad to generate intermetallic compounds. After cooling, a reliable metallurgical bond is formed, realizing signal transmission and power supply between the first core and the corresponding second core.

[0064] For the third core, a third microbump array 30 is pre-prepared on its lower surface. After the third core is placed in the vacant position, the same thermo-press bonding process is used to form a metallurgical bond between the third microbump array 30 and the copper pad array on the exposed upper surface of the second core at the vacant position, thereby achieving electrical conductivity between the third core and the corresponding second core.

[0065] At this point, except for the first chip region 12 to be removed, all normally matched first chips and their corresponding second chips, as well as the third chip and its corresponding second chip, have established complete electrical interconnection channels, resulting in a complete three-dimensional stacked system chip that can be powered on.

[0066] The present invention also provides a wafer-level three-dimensional stacked system chip, the specific structure of which is as follows: A first wafer 10 is provided with a first chip array 11, the first chip array 11 including at least one vacant position; The second wafer 20 is provided with a second chip array that corresponds one-to-one with the first chip array 11. A permanent bonding sheet 13 is disposed between the remaining first particles (excluding the vacant positions) and the corresponding second particles in the first particle array 11, for bonding the remaining first particles to the corresponding second particles; The third core 60 is bonded to the upper surface of the second core exposed at the vacant position; An interconnection structure is disposed between the first core and the corresponding second core, and between the third core and the corresponding second core, for realizing signal transmission and / or power supply between the first core and the corresponding second core, and between the third core and the corresponding second core.

[0067] Example 2

[0068] refer to Figure 8As shown, the difference between this embodiment and Embodiment 1 is that the material of the permanent bonding sheet is a dielectric thin film containing silicon and / or carbon, and an array of metal interconnect sheets 40 is embedded therein to achieve electrical interconnection.

[0069] The differences between this embodiment and Embodiment 1 are as follows: Forming a permanent bonded sheet containing embedded metal interconnects 40; A silicon carbonitride thin film was deposited on the upper surface of the first wafer 10, excluding the area of ​​the first core 12 to be removed, using a plasma-enhanced chemical vapor deposition (PECVD) apparatus, as the first permanent bonding layer. The deposition thickness was strictly controlled to 1.0 μm.

[0070] Then, an array of first metal interconnects 40 is embedded using a damascene process. First, photoresist is coated onto a silicon carbonitride thin film, and the groove pattern (groove width 1 μm) for vertical interconnects is exposed and developed. Reactive ion etching (RIE) is performed using a carbon tetrafluoride / argon mixture (flow rate ratio 1:2) to etch grooves 0.8 μm deep in SiCN. Subsequently, a tantalum / tantalum nitride barrier layer with a thickness of 10 nm and a copper seed layer with a thickness of 100 nm are sputtered and deposited. Next, copper is used to completely fill the grooves using an electroplating process. Finally, chemical mechanical polishing (CMP) is used to remove excess copper and planarize the surface. In other embodiments, the metal interconnects can also be made of a copper alloy.

[0071] After chemical mechanical polishing (CMP), a controlled protrusion is formed on the top of the first metal interconnect 40 relative to the surface of the first permanent bond, with a protrusion height of 5 nm to 15 nm. This protrusion height is achieved by controlling the CMP polishing endpoint and polishing rate to ensure that the metal interconnects preferentially contact and diffuse bonding occur during subsequent annealing.

[0072] Using the exact same method, a second permanent bonding sheet with an array of second metal interconnect sheets 40 embedded in the corresponding region on the upper surface of the second wafer 20 is formed, with the first metal interconnect sheet 40 and the second metal interconnect sheet 40 arranged in a one-to-one correspondence.

[0073] On the bonding surface (lower surface) of the third core, a SiCN thin film of the same material and thickness is deposited by PECVD, and an array of multiple third metal interconnects 40 is embedded using the same copper damascene process as described above to form a third permanent bonding sheet. The positional distribution of the third metal interconnects 40 perfectly matches the array of second metal interconnects 40 exposed on the upper surface of the second core at the vacant positions.

[0074] After removing the defective core and exposing the vacant sites, but before performing D2W repair on the third core, the first permanent bond sheet is locally etched in the region of the first core to be removed 12, creating a depression between the first permanent bond sheet and the surrounding area. Specifically, a focused ion beam (FIB) or argon ion beam etching device is used to locally thin and etch the first permanent bond sheet around the vacant sites, forming a recessed trench structure with a depth of 20 nm. This recessed trench structure serves to buffer the shear stress caused by the mismatch in thermal expansion coefficients during subsequent thermal cycling, preventing cracks from propagating to the surrounding good product areas.

[0075] In a clean vacuum environment at room temperature (25°C), the third core 60 is placed in an empty position, and pre-bonding is performed by the van der Waals forces generated by the dangling bonds on the surface of the SiCN dielectric layer. At this time, only a very small pressure (<5N) is required to bond the two surfaces together.

[0076] The material is then annealed at a heating rate of 2°C / min to 300°C, with a preferred temperature range of 200°C-350°C, and held at that temperature for 2 hours. During this process, the protruding end faces of the first metal interconnect 40 and the second metal interconnect 40 come into contact with each other under pressure and undergo atomic interdiffusion, forming a reliable copper-copper metal bond; simultaneously, a dehydration condensation reaction occurs between the SiCN dielectric layers, forming a covalent bond fusion interface.

[0077] All other steps in this embodiment are the same as in Embodiment 1, and will not be repeated here.

[0078] Example 3

[0079] refer to Figure 9 As shown, the difference between this embodiment and Embodiment 1 is that after stacking and repair, a vertical interconnect pillar 50 array is formed between the corresponding pads in the air gap using a selective metal growth process.

[0080] The differences between this embodiment and Embodiment 1 are as follows: When the entire bonding wafer assembly contains the repaired third core, some or all of the pads in the first core correspond one-to-one with some or all of the pads in the second core.

[0081] A dicing machine is used to perform a full cut along the wafer dicing path. After dicing, each 3D stacking cell is separated independently.

[0082] A vertical interconnect pillar array 50 is formed between the corresponding I / O pads using a selective metal growth process. The cut individual stacked cells are immersed in an electroplating bath. The electroplating bath composition is: 200 g / L copper sulfate pentahydrate, 60 g / L sulfuric acid, 50 mg / L chloride ions, and appropriate additives. Using the copper pads exposed at the end faces of the first and second cores as cathodes, a selective electroplating process is employed, applying a current density of 5 ASD (amperes per square decimeter). Under the influence of the electric field, copper ions are deposited only on the surface of the exposed metal pads and gradually grow upwards / downwards, eventually bridging between the oppositely spaced pads to form vertical pillars, i.e., the vertical interconnect pillar array 50.

[0083] In this embodiment, the vertical interconnect post 50 is made of copper. In other embodiments, the interconnect post may be made of any single metal selected from aluminum, gold, silver, tin, nickel, cobalt, tantalum, or an alloy thereof.

[0084] The voids in the vertical interconnect pillar 50 array are filled with dielectric isolation material. A spin-coated glass (SOG) filling process is used, where liquid siloxane is drop-coated onto the chip surface at 1000 rpm for 30 seconds, followed by curing at 350°C for 60 minutes to allow the SOG to reflow and fill to the bottom of the voids. For high-density voids with an aspect ratio greater than 2:1, high-density plasma-chemical vapor deposition (HDP-CVD) with SiO2 is used for filling. After filling, CMP smoothing is performed to expose the tops of the interconnect pillars.

[0085] The other steps in this embodiment (providing the first wafer 10 and the second wafer 20, selectively forming the permanent bonding wafer, W2W bonding, laser cutting and removal, bonding of the third core, etc.) are the same as in Embodiment 1, and will not be repeated here.

[0086] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for manufacturing a wafer-level three-dimensional stacked system-on-a-chip, characterized in that, The method includes the following steps: A first wafer is provided, and a first die array is formed on the upper surface of the first wafer, the first die array including at least one first die to be removed; A second wafer is provided, and a second chip array is formed on the upper surface of the second wafer, wherein the second chip array corresponds one-to-one with the first chip array; A first permanent bond sheet is formed on the upper surface of the first wafer, excluding the first core region to be removed, or a second permanent bond sheet is formed on the surface of the second wafer corresponding to the region excluding the first core region to be removed. The upper surface of the first wafer is bonded to the upper surface of the second wafer; From the back side of the second wafer, the first core to be removed is selectively cut and separated from the adjacent first core; The first core to be removed is selectively removed to expose the upper surface of the second wafer and form a vacancy. A third core is provided and the third core is bonded to the upper surface of the second core exposed at the vacant position; An electrical interconnect structure is formed between the first core and the corresponding second core, and between the third core and the corresponding second core.

2. The manufacturing method according to claim 1, characterized in that, Before bonding the third core to the upper surface of the second core exposed at the vacant location, the method further includes: A first partially permanent bonding sheet is formed on the lower surface of the third core particle, and the third core particle is bonded to the upper surface of the second core particle exposed at the vacant position through the first partially permanent bonding sheet; or, A second partially permanent bonding sheet is formed on the upper surface of the second core exposed at the vacant location, and the third core is bonded to the upper surface of the second core exposed at the vacant location through the second partially permanent bonding sheet.

3. The manufacturing method according to claim 1, characterized in that, Before bonding the upper surface of the first wafer to the upper surface of the second wafer, a temporary bonding sheet is formed on the upper surface of the first wafer outside the region of the first core to be removed, or on the upper surface of the second wafer corresponding to the region of the first core to be removed.

4. The manufacturing method according to claim 1, characterized in that, The interconnection structure includes: A first bump array formed on the surface of the first die, and a first pad array formed on the upper surface of the second wafer and corresponding to the first bump array; or A second bump array formed on the surface of the second core, and a second pad array formed on the upper surface of the first wafer and corresponding to the second bump array.

5. The manufacturing method according to claim 4, characterized in that, Before cutting and separating the first core particle to be removed, the process further includes: Remove the first bump array on the first core to be removed; or Remove the second bump array on the second core corresponding to the first core to be removed from the upper surface of the second wafer.

6. The manufacturing method according to claim 4, characterized in that, The third core chip includes a third bump array or a third pad array.

7. The manufacturing method according to claim 1, characterized in that, The method for forming the permanent bonded sheet includes: An organic photosensitive adhesive film is coated on the upper surface of the first wafer or the upper surface of the second wafer; The organic photosensitive adhesive film is patterned to remove the adhesive film corresponding to the first core particle area to be removed.

8. The manufacturing method according to claim 1, characterized in that, An array of first metal interconnects is embedded in the first permanent bonded sheet. The first metal interconnects penetrate the first permanent bonded sheet, with their lower ends electrically connected to the pads of the first core and their upper ends exposed on the surface of the first permanent bonded sheet. A second metal interconnect array is embedded in the second permanent bond sheet. The second metal interconnect extends through the second permanent bond sheet, with its lower end electrically connected to the pad of the second core and its upper end exposed on the surface of the second permanent bond sheet. In the step of forming the interconnect structure, annealing is used to form a metal-metal bond between the first metal interconnect and the second metal interconnect, which are arranged in a one-to-one correspondence, so as to electrically interconnect the first core and the second core.

9. The manufacturing method according to claim 8, characterized in that, Before bonding the third core to the vacant site, the method further includes: A third permanent bonding sheet is formed on the bonding surface of the third core, and a third metal interconnect array is embedded in the third permanent bonding sheet; The third metal interconnect extends through the third permanent bond sheet, with its lower end electrically connected to the pad of the third core and its upper end exposed on the surface of the third permanent bond sheet; The third metal interconnect piece makes one-to-one contact with the second metal interconnect piece exposed at the vacant position, and metal-to-metal bonding is formed by annealing, so that the third core piece and the corresponding second core piece are electrically interconnected.

10. The manufacturing method according to claim 8, characterized in that, Before bonding the third core to the upper surface of the second core exposed at the vacant location, the method further includes: Along the boundary of the vacant site, a focused ion beam etching or argon ion beam etching process is used to locally thin and etch the area of ​​the first permanent bonded sheet located at the edge of the vacant site, so that the first permanent bonded sheet forms a depression between the vacant site and the adjacent permanent bonded area.

11. The manufacturing method according to claim 1, characterized in that, After bonding the third core to the upper surface of the second core exposed at the vacant location, the process further includes: The pads of the first chip are partially or completely corresponding to the pads of the second chip in a one-to-one manner. The bonded overall structure is cut and separated into individual stacked units, and a vertical interconnect pillar array is formed between the corresponding pads of the gap using a selective metal growth process. Dielectric isolation material is filled into the gaps in the vertical interconnect pillar array.

12. The manufacturing method according to claim 11, characterized in that, The vertical interconnect pillars are made of any single metal or alloy thereof selected from copper, aluminum, gold, silver, tin, nickel, cobalt, and tantalum.

13. The manufacturing method according to claim 1, characterized in that, The first wafer and the second wafer are bonded using any one of the following methods: van der Waals bonding, chemical adhesive bonding, or metal welding bonding.

14. The manufacturing method according to claim 1, characterized in that, The first core particle to be removed is cut and separated from the other first core particles by any one of mechanical cutting, laser cutting or plasma cutting.

Images