3D stacked chip structure based on elastic microsphere stress buffering and preparation method thereof

Abstract

The application provides a 3D stacked chip structure based on elastic microsphere stress buffering and a preparation method thereof, relates to the technical field of semiconductors, and comprises a first chip and a second chip, the surface of the first chip is provided with electric interconnection circuit one, the second chip is internally provided with electric interconnection circuit two, the electric interconnection circuit one and the electric interconnection circuit two are both provided with functional conductive pads, the surfaces of the non-signal transmission areas of the first chip and the second chip where the functional conductive pads are located are provided with dummy metal pads, the first chip and the second chip are both provided with insulating UV glue, the insulating UV glue is provided with elastic microspheres, and the functional conductive pads on the first chip and the functional conductive pads on the second chip are bonded through a copper bonding curing layer; the application is prepared based on the existing semiconductor lithography, electroplating and bonding processes, the process is standardized, no special equipment needs to be added, and the operation reliability under the conditions of extreme temperature change and high load large current and the AEC-Q100 vehicle standard requirements are met.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a 3D stacked chip structure based on elastic microsphere stress buffer and its fabrication method. Background Technology

[0002] Electric vehicle onboard control and power conversion chips must strictly comply with AEC-Q100 Grade 0 / 1 automotive standards. During high-speed fast charging and instantaneous high-power acceleration, the onboard chips experience short-term and drastic temperature rises, and under normal operating conditions, they continuously operate in a wide temperature range of -40℃ to 150℃.

[0003] In existing technologies, the top-level logic chip in 3D stacked chips and microbump integrated architectures uses silicon substrate, which has a coefficient of thermal expansion of 2.6 × 10⁻⁶. -6 / K, the thermal expansion coefficients of the materials used in the bottom high-voltage driver chip and the interposer layer are significantly different from those of the silicon substrate. CTE mismatch causes uneven expansion and contraction of the materials in each layer during repeated thermal cycling, and generates a large amount of shear stress and concentrated thermal stress at the hybrid bonding interface. When automotive power chips are subjected to ultra-high current density, the micron-level traditional rigid conductive bonding points generate current crowding effect when large currents are passed through them, which in turn triggers electron migration. Metal atoms are displaced by electron wind and form microscopic voids at the edge of the bonding points. Furthermore, under the combined effect of thermal stress shear and electron migration voids, the hybrid bonding points are prone to fatigue cracking and a sudden increase in contact resistance. In severe cases, this can cause chip delamination and circuit breakage, threatening the operational safety of the electric vehicle's power system.

[0004] Conventional mitigation solutions involve thickening the bottom filler and adding external reinforcement structures. These methods encroach on the packaging space and reduce signal transmission bandwidth, and cannot fundamentally eliminate the electron migration problem caused by high current. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the existing technology and to propose a 3D stacked chip structure based on elastic microsphere stress buffer and its fabrication method.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: a 3D stacked chip structure based on elastic microsphere stress buffering, comprising: a first chip and a second chip, wherein the surface of the first chip is provided with an electrical interconnection line one, and the second chip is provided with an electrical interconnection line two, both the electrical interconnection line one and the electrical interconnection line two are provided with functional conductive pads, and the surfaces of the non-signal transmission areas of the first chip and the second chip where the functional conductive pads are located are provided with dummy metal pads, and insulating UV adhesive is provided on the first chip and the second chip between two adjacent functional conductive pads and between the dummy metal pads and the functional conductive pads, insulating UV adhesive is provided on the second chip corresponding to the dummy metal pads on the first chip, and insulating UV adhesive is provided on the first chip corresponding to the dummy metal pads on the second chip, wherein elastic microspheres are provided on the insulating UV adhesive, and the functional conductive pads on the first chip and the functional conductive pads on the second chip are bonded together by a copper bonding curing layer.

[0007] Furthermore, the surfaces of the first and second chips, in addition to the functional conductive pad and the dummy metal pad, are covered with a silicon dioxide dielectric layer; the tops of the functional conductive pad, the dummy metal pad, and the insulating UV adhesive are exposed and protrude from the silicon dioxide dielectric layer.

[0008] Furthermore, both the first and second electrical interconnects are connected to grounding pins via grounding lines. The grounding lines connected to the first and second electrical interconnects are respectively located within the first and second chips. The two grounding pins are respectively located on the sides of the first and second chips. The second electrical interconnect is connected to an electrical interconnect pin located within the second chip.

[0009] Furthermore, the gap edge between the first chip and the second chip is filled with sealant, and the electrical interconnect pins extending out of the second chip are sealed with sealant. The first chip and the second chip, together with the structures connected thereto, are encapsulated in an epoxy molding layer, and the ends of the electrical interconnect pins and the ground pins extend out of the epoxy molding layer.

[0010] The fabrication method of a 3D stacked chip structure based on elastic microsphere stress buffering includes the following steps: S1. Provide a first chip and a second chip, and prepare electrical interconnect lines and functional conductive pads on the bonding surfaces of the first chip and the second chip respectively, and arrange dummy metal pads in the non-signal transmission area. S2. Deposit a silicon dioxide dielectric layer on the surface of the first chip and the second chip, such that the tops of the functional conductive pad, the dummy metal pad and the insulating UV adhesive all protrude from the surface of the silicon dioxide dielectric layer. S3. Provide pre-made elastic microspheres and precisely place them on the insulating UV adhesive coated on the dummy metal pad, and use the UV adhesive to initially fix the elastic microspheres. S4. Align the first chip and the second chip vertically, and use bonding and pre-bonding processes to initially bond them together. At the same time, align the functional conductive pads of the two chips together and guide the elastic microspheres to fall between the corresponding virtual metal pads. S5. The first chip and the second chip that are initially bonded are subjected to thermo-press bonding and high-temperature annealing treatment, thereby forming a copper bonding and curing layer between the corresponding functional conductive pads, and driving the upper and lower end faces of the elastic microspheres to achieve eutectic welding with the corresponding dummy metal pads to obtain a 3D stacked chip structure.

[0011] Furthermore, the elastic microsphere has an elastic core and a conductive shell that completely covers the outer surface of the elastic core; the material of the elastic core of the elastic microsphere is selected from any one or more combinations of polyimide, polyphthalamide, and polysiloxane, and the shear modulus of the elastic core of the elastic microsphere is less than the shear modulus of the silicon substrate of the first chip and the second chip; the conductive shell of the elastic microsphere is a nickel-gold double-layer composite metal structure, with an inner layer of nickel and an outer layer of gold, and the total thickness of the shell is 120nm~150nm, and the diameter of the elastic microsphere is 1μm~5μm.

[0012] Furthermore, the elastic microspheres are arranged in an asymmetric gradient density layout on the hybrid bonding interface. The density of elastic microspheres in the high stress concentration region at the outer edge of the first chip and the second chip is greater than the density in the low stress region at the center. Specifically, the elastic microspheres in the high stress concentration region at the outer edge of the first chip and the second chip are arranged in a honeycomb array, and the area of ​​the arrangement area accounts for 35% to 50%, while the area of ​​the arrangement area in the low stress region at the center of the first chip and the second chip accounts for 10%.

[0013] Furthermore, in step S2, a silicon dioxide dielectric layer is deposited on the surfaces of the first chip and the second chip using a PECVD process; wherein, the cavity temperature of the PECVD process is 300℃, the deposition pressure is 80Pa, and the thickness of the deposited silicon dioxide dielectric layer is 1.5μm±0.05μm; and, the surface of the functional conductive pad, the dummy metal pad, and the elastic microspheres are all provided with the silicon dioxide dielectric layer, and the tops of the functional conductive pad, the dummy metal pad, and the insulating UV adhesive all protrude from the surface covered by the silicon dioxide dielectric layer.

[0014] Furthermore, after step S5, an encapsulation step is included: filling the gap edge between the first chip and the second chip with sealant, and using an epoxy molding compound to completely cover both chips and the bonding connection structure between them, with the ends of the electrical interconnect pins and ground pins in the second chip extending out of the epoxy molding compound.

[0015] Compared with the prior art, the advantages and positive effects of the present invention are as follows: In this invention, the first and second chips generate shear thermal stress due to a mismatch in their coefficients of thermal expansion. The elastic core absorbs the concentrated thermal stress at the interface through shear deformation, preventing cracking of the copper bonding and curing layer at the functional conductive pad. This gives the stacked structure high tolerance to high and low temperature cycling environments ranging from -40℃ to 150℃. The conductive outer shell forms an independent current shunt channel, diluting the local current density of the functional conductive pad, reducing the current density value from 1.2 × 10⁻⁶ in the traditional structure. 6 A / cm 2 Reduced to 4.5×10 5 A / cm 2 This invention eliminates current crowding effects and suppresses the generation of voids in metal atom displacement and micro-electron migration. The elastic microspheres in the high-stress concentration area on the outer edge are arranged in a honeycomb array with an area ratio of 35% to 50%, while the low-stress area in the center has an asymmetric gradient layout with an area ratio of 10%. This effectively strengthens high-stress protection on the outer edge without occupying additional packaging space and is compatible with high-bandwidth signal transmission. The invention is fabricated based on existing semiconductor lithography, electroplating, and bonding processes. The process is standardized and requires no additional specialized equipment, achieving operational reliability under extreme temperature changes and high-load, high-current conditions, meeting the requirements of the AEC-Q100 automotive standard. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating the fabrication method of the 3D stacked chip structure based on elastic microsphere stress buffering according to the present invention. Figure 2 This is a schematic diagram of the 3D stacked chip structure based on elastic microsphere stress buffering of the present invention. Figure 3 This is a schematic diagram illustrating the electrical interconnection between the first chip and the second chip in the fabrication method of the 3D stacked chip structure based on elastic microsphere stress buffer of the present invention. Figure 4 This is a schematic diagram of the first chip and the second chip, which are semi-finished products of the fabrication method of the 3D stacked chip structure based on elastic microsphere stress buffer of the present invention. Figure 5 This is a schematic diagram of the bonding between the first chip and the second chip in the fabrication method of the 3D stacked chip structure based on elastic microsphere stress buffer of the present invention.

[0017] Figure label: 1. First chip; 2. Electrical interconnection line one; 3. Second chip; 4. Electrical interconnection line two; 5. Grounding line; 6. Grounding pin; 7. Electrical interconnection pin; 8. Functional conductive pad; 9. Copper bonding and curing layer; 10. Dummy metal pad; 11. Insulating UV adhesive; 12. Elastic microspheres; 13. Silicon dioxide dielectric layer; 14. Sealant; 15. Epoxy encapsulation layer. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Example 1

[0019] like Figures 2 to 5 As shown, the present invention provides a technical solution: a 3D stacked chip structure based on elastic microsphere stress buffer and its fabrication method, comprising: a first chip 1 and a second chip 3, wherein the first chip 1 is an AI logic chip, and the second chip 3 is a high-voltage driving chip with an interposer layer function. Electrical interconnection lines 1-2 are provided on the surface of the first chip 1, and electrical interconnection lines 2-4 are provided inside the second chip 3. Functional conductive pads 8 are provided on both electrical interconnection lines 1-2 and 2-4. Dummy metal pads 10 are provided on the surface of the non-signal transmission areas of the first chip 1 and the second chip 3 where the functional conductive pads 8 are located. Insulating UV adhesive 11 is provided between two adjacent functional conductive pads 8 and between the dummy metal pad 10 and the functional conductive pad 8 on both the first chip 1 and the second chip 3. The dummy metal pad 10 on the first chip 3 corresponds to the second chip 3, which is provided with insulating UV adhesive 11. The dummy metal pad 10 on the second chip 3 corresponds to the first chip 1, which is also provided with insulating UV adhesive 11. Elastic microspheres 12 are provided on the insulating UV adhesive 11. The functional conductive pads 8 on the first chip 1 and the functional conductive pads 8 on the second chip 3 are bonded together by a copper bonding and curing layer 9. In this design, the interconnect line 1 2 on the surface of the first chip 1 and the interconnect line 2 4 inside the second chip 3 jointly carry the electrical signal and power transmission between the chips, forming a vertical electrical link. The first chip 1 is a silicon-based automotive high-performance logic chip fabricated using a 3nm process, and the second chip 3 is a silicon carbide automotive high-voltage drive interposer. Both have a thickness of 2.6 × 10⁻⁻⁶. 6 / K and 4.0×10⁻ 6The coefficient of thermal expansion of / K leads to a significant mismatch in the coefficient of thermal expansion under drastic temperature changes from -40℃ to 150℃. The functional conductive pads 8 on the electrical interconnects 1 and 2 and the dummy metal pads 10 on the non-signal transmission area of ​​the hybrid bonding interface respectively serve the functions of signal transmission and stress buffering and anchoring. Insulating UV adhesive 11 is applied to the surfaces of the first chip 1 and the second chip 3 between adjacent functional conductive pads 8 and between the dummy metal pads 10 and functional conductive pads 8. The insulating UV adhesive 11 is applied at corresponding positions on the top and bottom to provide a physical fixing medium for the fixed placement of the elastic microspheres 12. The elastic microspheres 12 themselves contain an elastic core with a low shear modulus and a nickel-gold double-layer composite metal conductive shell that completely covers the elastic core. The inner layer of the nickel-gold double-layer structure is a nickel layer and the outer layer is a gold layer, with a total thickness of 150nm and an elastic microsphere diameter of 2μm. The shear modulus of the elastic core is between 3.1 and 3.5 GPa, which is much smaller than that of the silicon substrate 68. With a shear modulus of GPa, the elastic core of the elastic microsphere 12 actively absorbs over 75% of the concentrated thermal stress at the interface through shear deformation when CTE mismatch shear stress is induced by temperature cycling. This prevents high stress from transferring to the conductive bonding points and avoids thermal fatigue cracking of the copper bonding solidification layer 9. Meanwhile, the nickel-gold conductive shell forms an independent shunt channel when a large driving current of 5A is applied, resulting in an internal density of up to 1.2 × 10⁻⁶ g / L. 6 The current congestion condition was significantly diluted to 4.5 × 10 A / cm². 5 A / cm 2 This fundamentally reduces the current crowding effect, thereby suppressing the displacement of metal atoms and the formation of micro-voids under the action of electron wind. At the same time, the elastic microspheres 12 on the virtual metal pad 10 in the non-signal transmission area are arranged in an asymmetric gradient density layout within the hybrid bonding interface. The high stress concentration area at the outer edge is arranged in a honeycomb array with an area ratio of 35% to 50%, while the low stress area at the center is sparsely arranged with an area ratio of 10%. This specifically strengthens the protection of the chip's outer edge where thermal stress and mechanical vibration are superimposed. After the structure based on the synergistic effect of the low shear modulus elastic core and the nickel-gold conductive shell is completed, the functional conductive pad 8 between the first chip 1 and the second chip 3 is formed into a copper bonding solidification layer 9 through hot pressing bonding and high-temperature annealing at 350°C. This achieves bumpless copper-copper direct bonding with a contact spacing of less than 10μm. This integrated metal bonding layer and the eutectic solder joints of the microspheres together constitute a dual-path electrical connection and stress buffering system within the hybrid bonding interface.

[0020] like Figures 2 to 5As shown, both electrical interconnection line 1 (2) and electrical interconnection line 2 (4) are connected to grounding pins (6) via grounding lines (5). The grounding lines (5) connecting electrical interconnection line 1 (2) and electrical interconnection line 2 (4) are respectively located inside the first chip 1 and the second chip 3. The two grounding pins (6) are respectively located on the sides of the first chip 1 and the second chip 3. Electrical interconnection line 2 (4) is connected to an electrical interconnection pin (7) located inside the second chip 3. In this design, electrical interconnection line 1 (2) and electrical interconnection line 2 (4) are connected to grounding pins (6) via grounding lines (5). The two grounding lines (5) provide independent current discharge paths for the first chip 1 and the second chip 3. The grounding pins (6) on the side of the first chip 1 and the second chip 3 form a unified external grounding terminal after the first chip 1 and the second chip 3 are bonded together. Electrical interconnection line 2 (4) is connected to an electrical interconnection pin (7) located inside the second chip 3. The electrical interconnection pin (7) is led out from inside the second chip 3. The grounding lines (5) and grounding pins (6) release the static electricity and surge current inside the first chip 1 and the second chip 3 to the outside. The electrical interconnection pin (7) realizes the electrical connection between electrical interconnection line 2 (4) inside the second chip 3 and the external circuit.

[0021] like Figures 2 to 5 As shown, the surfaces of the first chip 1 and the second chip 3, excluding the functional conductive pad 8 and the dummy metal pad 10, are covered with a silicon dioxide dielectric layer 13; the tops of the functional conductive pad 8, the dummy metal pad 10, and the insulating UV adhesive 11 are exposed and protrude beyond the silicon dioxide dielectric layer 13; in this design, the silicon dioxide dielectric layer 13 covers the surfaces of the first chip 1 and the second chip 3, excluding the functional conductive pad 8 and the dummy metal pad 10, and the tops of the functional conductive pad 8, the dummy metal pad 10, and the insulating UV adhesive 11 are exposed and protrude beyond the silicon dioxide dielectric layer 13, which covers... In the padless areas of the first chip 1 and the second chip 3, the non-conductive areas between adjacent conductive pads are physically isolated. The tops of the functional conductive pad 8 and the dummy metal pad 10 protrude from the surface of the dielectric layer, forming a vertical height difference between the top of the pad and the upper plane of the dielectric layer. The top of the insulating UV adhesive 11 also protrudes from the silicon dioxide dielectric layer 13, so that the upper surface of the insulating UV adhesive 11 extends beyond the plane of the dielectric layer. The configuration of the top being exposed and protruding from the silicon dioxide dielectric layer 13 ensures that the direct physical surfaces of the functional conductive pad 8, the dummy metal pad 10 and the insulating UV adhesive 11 are not covered or constrained by the dielectric layer material.

[0022] like Figure 2As shown, the gap edge between the first chip 1 and the second chip 3 is filled with sealant 14, and the electrical interconnect pin 7 extending from the second chip 3 is sealed with sealant 14. The first chip 1 and the second chip 3, along with the structures connected thereto, are encapsulated within an epoxy molding compound 15, with the ends of the electrical interconnect pin 7 and the ground pin 6 extending out of the epoxy molding compound 15. In this design, sealant 14 fills the gap edge between the first chip 1 and the second chip 3 and seals the electrical interconnect pin 7 extending from the second chip 3. This physically prevents external environmental media from entering the internal gap between the two chips and eliminates the exposed area at the root of the electrical interconnect pin 7, preventing contaminants from entering and short-circuiting at the pin root. The epoxy molding compound 15 encapsulates the first chip 1 and the second chip 3. The entire package, including the 3 and its connection structure, provides rigid environmental isolation and mechanical protection for the stacked structure, maintaining the physical stability of the internal hybrid bonding interface. The ends of the electrical interconnect pins 7 and ground pins 6 extend out of the epoxy molding layer 15, enabling the internal electrical interconnect lines and ground lines to establish electrical connections with external circuits through the pin ends. At the same time, the extended pin ends form the physical contact surfaces between the package and the external circuit board. The sealant 14 and the epoxy molding layer 15 together form a multi-level protection structure. The sealant 14 seals the internal gaps and fixes the pin roots, while the epoxy molding layer 15 isolates the external environment and fixes the overall stacked structure. The pin ends extending out of the epoxy molding layer 15 ensure the interconnectivity of external circuits while maintaining the integrity of the overall package. Example 2

[0023] like Figures 1 to 5 As shown, the method for fabricating a 3D stacked chip structure based on elastic microsphere stress buffering, used to fabricate the 3D stacked chip structure based on elastic microsphere stress buffering proposed in Example 1, includes the following steps: S1. A first chip 1 and a second chip 3 are provided, and electrical interconnects and functional conductive pads 8 are fabricated on the bonding surfaces of the first chip 1 and the second chip 3, respectively. Dummy metal pads 10 are arranged in the non-signal transmission area. In this design, the first chip 1 is made of silicon substrate and the process technology is 3nm, and the second chip 3 is made of silicon carbide material. The coefficients of thermal expansion of the two are 2.6×10⁻⁶ and 2.6×10⁻⁶, respectively. -6 / K and 4.0×10 -6 / K, the difference in thermal expansion coefficient is established at room temperature and becomes the physical source of interfacial shear stress under subsequent harsh temperature change conditions. The electrical interconnection lines and functional conductive pads 8 on the bonding surfaces of the first chip 1 and the second chip 3 are formed into a precisely patterned copper metal pad structure based on photolithography, sputtering and electroplating processes. The dummy metal pads 10, which are synchronously deployed in the non-signal transmission area, are set independently of the signal transmission path of the functional conductive pads 8. The planar configuration of the dummy metal pads 10 provides a fixed anchor point for the subsequent positioning of the elastic microspheres 12 in the interface. The coexistence of the functional conductive pads 8 and the dummy metal pads 10 constitutes a regional independent pad layer system for electrical signal transmission and microsphere stress buffering and anchoring.

[0024] S2. A silicon dioxide dielectric layer 13 is deposited on the surfaces of the first chip 1 and the second chip 3, such that the tips of the functional conductive pad 8, the dummy metal pad 10, and the insulating UV adhesive 11 all protrude from the surface of the silicon dioxide dielectric layer 13; wherein: The silicon dioxide dielectric layer 13 is deposited on the surfaces of the first chip 1 and the second chip 3 using a PECVD process. The PECVD process is performed at a chamber temperature of 300°C and a deposition pressure of 80 Pa, resulting in a silicon dioxide dielectric layer 13 with a thickness of 1.5 μm ± 0.05 μm. Furthermore, the functional conductive pad 8, the dummy metal pad 10, and the elastic microspheres 12 are all covered with the silicon dioxide dielectric layer 13, and the tips of the functional conductive pad 8, the dummy metal pad 10, and the insulating UV adhesive 11 protrude from the surface covered by the silicon dioxide dielectric layer 13. In this design, the silicon dioxide dielectric layer 13 is deposited on the surfaces of the first chip 1 and the second chip 3 using a PECVD process at a chamber temperature of 300°C and a deposition pressure of 80 Pa. The resulting silicon dioxide dielectric layer 13 has a thickness of 1.5 μm ± 0.05 μm, and its distribution extends to the functional conductive pad 8, the dummy metal pad 10, and the elastic microspheres 12. The surfaces of pad 10 and elastic microspheres 12, as well as the tops of functional conductive pad 8, dummy metal pad 10, and insulating UV adhesive 11, form physical morphological structures protruding from the surface covered by silicon dioxide dielectric layer 13. The controlled cavity temperature and deposition pressure in the PECVD process ensure the film quality and overall thickness uniformity of the dielectric layer under low-temperature conditions of the chip. The complete coverage of the non-conductive area of ​​silicon dioxide dielectric layer 13 between adjacent conductive pads creates a continuous physical barrier layer, thereby preventing electrical short circuits. The morphology of each pad layer and the top of insulating UV adhesive 11 protruding from the surface of silicon dioxide dielectric layer 13 directly defines the spatial height difference. This height difference provides the basic positioning and pressure conditions for the physical contact and thermo-pressing bonding of the interface in the subsequent vertical stacking process. The property of the surface of elastic microspheres 12 being covered by silicon dioxide dielectric layer 13 gives its insulating coating state a physical constraint effect before the final metal eutectic bonding occurs.

[0025] S3. Provide pre-fabricated elastic microspheres 12 and precisely place them on insulating UV adhesive 11 coated on the dummy metal pad 10, and use the UV adhesive to initially fix the elastic microspheres 12; wherein: The elastic microsphere 12 has an elastic core and a conductive shell that completely covers the outer surface of the elastic core. The material of the elastic core of the elastic microsphere 12 is selected from any one or more combinations of polyimide, polyphthalamide, and polysiloxane, and the shear modulus of the elastic core of the elastic microsphere 12 is less than the shear modulus of the silicon substrate of the first chip 1 and the second chip 3. The conductive shell of the elastic microsphere 12 is a nickel-gold double-layer composite metal structure, with an inner nickel layer and an outer gold layer, and the total thickness of the shell is 120nm~150nm. The diameter of the elastic microsphere 12 is 1μm to 5μm. In this design, the elastic microsphere 12 has an elastic core and a conductive shell that completely covers the outer surface of the elastic core. The elastic core is composed of a single type or a combination of polyimide, polyphthalamide, and polysiloxane. The shear modulus of the elastic core is 3.0GPa to 3.5GPa, which is less than the shear modulus of 68GPa of the silicon substrate of the first chip 1 and the second chip 3. The difference in shear modulus allows the elastic core to withstand the stress at the hybrid bonding interface. When shear stress is caused by a mismatch in the thermal expansion coefficients of the same material, the reversible displacement and deformation of the internal molecular chain segments can absorb the concentrated thermal stress at the interface. The conductive shell adopts a nickel-gold double-layer composite metal structure, with a nickel layer as the inner layer and a gold layer as the outer layer. During the eutectic welding process, the nickel layer provides an adhesion transition and anti-diffusion barrier between the conductive shell and the metal pad. The gold layer provides low contact resistance and surface anti-oxidation protection for the conductive connection interface. The total thickness of the conductive shell ranges from 120nm to 150nm, and the diameter of the elastic microspheres 12 ranges from 1μm to 5μm. The size limitation of the total thickness and diameter ensures that the conductive shell maintains the continuity and physical integrity of the metal shell structure itself when the elastic core deforms. At the same time, the conductive shell provides a conduction path for the current in the mixed bonding interface that is independent of the functional conductive pad 8. The arrangement of the conduction path provides a bypass channel for the local concentrated current when the functional conductive pad 8 is crowded due to a large current load. The shunt channel inhibits the directional migration of metal atoms under the action of electron wind and eliminates the conditions for the formation of micro voids. The elastic microspheres 12 are arranged in an asymmetric gradient density pattern on the hybrid bonding interface. The density of elastic microspheres 12 in the high-stress concentration areas at the outer edges of the first chip 1 and the second chip 3 is greater than that in the central low-stress area. Specifically, the elastic microspheres 12 in the high-stress concentration areas at the outer edges of the first chip 1 and the second chip 3 are arranged in a honeycomb array, and the area of ​​the arrangement is 35%~50%, while the area of ​​the arrangement in the central low-stress area of ​​the first chip 1 and the second chip 3 is 10%. In this design, the difference in shear stress distribution at the interface between the first chip 1 and the second chip 3 is obtained based on the results of thermomechanical stress tensor simulation. The shear stress level in the outer edge area, which is more than 2.5 mm from the geometric center, is higher than that in the central area. The elastic microspheres 12 are arranged in an asymmetric gradient density pattern at the hybrid bonding interface with a higher density in the outer edge area than in the central area. The elastic microspheres 12 in the outer region are arranged in a honeycomb array and cover the area by 35% to 50%, while the central region is sparsely distributed with an area of ​​10%. The high-density arrangement of the honeycomb array in the outer region increases the total number of elastic microspheres 12 per unit area. The concentrated shear stress in the region is dispersed and absorbed by the shear deformation of more elastic cores. The lower area of ​​the central region protects the low-stress area and reduces the space occupied at the interface. The spatially differentiated density arrangement between the outer and central regions constitutes a zoned protection mechanism based on the actual stress distribution at the interface. The zoned protection mechanism inhibits the fatigue cracking of the copper bonding curing layer 9 of the functional conductive pad 8 in the outer region, inhibits the delamination of the hybrid bonding interface under mechanical vibration conditions, maintains the conductivity integrity of the hybrid bonding interface under combined mechanical vibration and thermal shock conditions greater than 50G, and meets the requirements for AEC-Q100 automotive use.

[0026] S4. The first chip 1 and the second chip 3 are vertically aligned, and they are initially bonded together through bonding and pre-bonding processes. Simultaneously, the functional conductive pads 8 of both chips are aligned, and the elastic microspheres 12 are guided to fall between the corresponding dummy metal pads 10. In this design, during the vertical alignment of the first chip 1 and the second chip 3, the planar alignment accuracy between them is controlled to be less than or equal to 0.2 μm. Under a pre-bonding pressure of 0.1 MPa and a holding time of 20 seconds, the bonding and pre-bonding processes achieve the initial bonding of the first chip 1 and the second chip 3. The mutual alignment of the functional conductive pads 8 ensures a bump-free copper-copper direct connection with a micron-level contact distance of less than 10 μm. Before subsequent thermo-bonding, the bonding points establish the correct spatial coordinate relationship, avoiding electrical short circuits and bonding defects caused by horizontal misalignment. Under the guidance mechanism, the elastic microsphere 12 falls between the corresponding upper and lower dummy metal pads 10. This physical positioning process directly constructs the initial contact space between the nickel-gold conductive shell on the surface of the elastic microsphere 12 and the upper and lower dummy metal pads 10. The structural adhesive force generated by the pre-bonding process maintains the first chip 1 and the second chip 3 at a fixed relative distance and planar orientation, providing preliminary mechanical fixing conditions for thermo-bonding and high-temperature annealing processes. At the same time, it eliminates the potential risk of the elastic microsphere 12 shifting laterally or rolling away from the effective contact area before subsequent high-temperature treatment.

[0027] S5. The first chip 1 and the second chip 3, which are initially bonded, are subjected to thermo-press bonding and high-temperature annealing to form a copper bonding and curing layer 9 between the corresponding functional conductive pads 8. The upper and lower end faces of the elastic microspheres 12 are driven to achieve eutectic bonding with the corresponding dummy metal pads 10 to obtain a 3D stacked chip structure. In this design, the first chip 1 and the second chip 3, which are initially bonded, are subjected to thermo-press bonding and high-temperature annealing. The bonding pressure in the thermo-pressing stage is set to 0.6MPa to 0.8MPa, the bonding temperature is set to 220℃, and the bonding time is controlled to 40min. The maximum temperature in the high-temperature annealing stage is increased to 350℃, and the holding time of the maximum temperature is set to 60min. The entire thermo-pressing and annealing process is carried out in a high-purity nitrogen atmosphere with a volume fraction of 99.999%. The cooling rate after annealing is controlled to be 3℃ / m. until the temperature returns to room temperature; the corresponding functional conductive pad 8 forms a copper bonding solidification layer 9 through copper atom interface diffusion during hot pressing and annealing. The contact spacing of the copper bonding solidification layer 9 is less than 10μm. The nickel-gold conductive shell of the elastic microsphere 12 completes eutectic welding with the corresponding dummy metal pads 10 during hot pressing and high-temperature annealing. Eutectic welding establishes an electrical connection between the upper and lower end faces of the elastic microsphere 12 and the dummy metal pads 10. The elastic core of the elastic microsphere 12 absorbs the interface thermal stress through shear deformation during the hot pressing stage. The controlled cooling rate after high-temperature annealing causes the stacked structure to release the internal thermal stress caused by CTE mismatch and inhibits the generation of interface cracks and voids. Finally, a hybrid bonding system is formed at the interface by the eutectic solder joints of the copper bonding solidification layer 9 and the elastic microsphere 12, thus obtaining a 3D stacked chip structure.

[0028] Furthermore, after step S5, an encapsulation step is included: filling the gap edge between the first chip 1 and the second chip 3 with sealant 14, and using an epoxy molding compound 15 to completely encapsulate both chips and the bonding connection structure between them, with the ends of the electrical interconnect pins 7 and ground pins 6 in the second chip 3 extending out of the epoxy molding compound 15; in this design, the gap edge between the first chip 1 and the second chip 3 is filled with sealant 14, and the first chip 1, the second chip 3, and the bonding connection structure formed between the first chip 1 and the second chip 3 are completely encapsulated using an epoxy molding compound 15. The epoxy molding compound 15 is made using a low-loss epoxy molding compound through an injection molding process, with an injection temperature of 175°C, a holding pressure of 80 kg, a holding time of 90 s, and a thickness of 0.6 mm to 1.2 mm after molding. The insulation resistance of the molding compound used is greater than 10 Ω·cm. 14After injection molding is completed and the mold is held under pressure and cooled, the mold is opened and the part is removed. Then, the plastic encapsulation flash burrs generated during the encapsulation process are removed. The ends of the electrical interconnect pins 7 and ground pins 6 located in the second chip 3 extend outward through the coverage of the epoxy encapsulation layer 15. The sealant 14 physically seals the gaps at the edges of the stacked structure, thus blocking the external environmental medium. The epoxy encapsulation layer 15 provides rigid mechanical protection for the internal stacked structure and the hybrid bonding interface, and physically isolates it from external mechanical impact and chemical corrosion environment. The ends of the electrical interconnect pins 7 and ground pins 6 extending out of the epoxy encapsulation layer 15 provide exposed electrical contact areas for electrical interconnection between the package and the external circuit board, enabling the internal chip to establish signal and potential connections with external devices through external lines.

[0029] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments that can be applied to other fields. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A 3D stacked chip structure based on elastic microsphere stress buffering, characterized in that, include: A first chip (1) and a second chip (3) are provided. The surface of the first chip (1) is provided with an electrical interconnect line 1 (2), and the second chip (3) is provided with an electrical interconnect line 2 (4). Both the electrical interconnect line 1 (2) and the electrical interconnect line 2 (4) are provided with functional conductive pads (8). The surface of the non-signal transmission area of ​​the first chip (1) and the second chip (3) where the functional conductive pads (8) are located is provided with dummy metal pads (10). The first [missing information] between two adjacent functional conductive pads (8) and between the dummy metal pads (10) and the functional conductive pads (8) is [missing information]. Both chip (1) and chip (3) are provided with insulating UV adhesive (11). The second chip (3) corresponding to the dummy metal pad (10) on the first chip (1) is provided with insulating UV adhesive (11). The first chip (1) corresponding to the dummy metal pad (10) on the second chip (3) is provided with insulating UV adhesive (11). The insulating UV adhesive (11) is provided with elastic microspheres (12). The functional conductive pad (8) on the first chip (1) and the functional conductive pad (8) on the second chip (3) are bonded together by a copper bonding curing layer (9).

2. The 3D stacked chip structure based on elastic microsphere stress buffering according to claim 1, characterized in that: The surfaces of the first chip (1) and the second chip (3), excluding the functional conductive pad (8) and the dummy metal pad (10), are covered with a silicon dioxide dielectric layer (13); the tops of the functional conductive pad (8), the dummy metal pad (10) and the insulating UV adhesive (11) are exposed and protrude from the silicon dioxide dielectric layer (13).

3. The 3D stacked chip structure based on elastic microsphere stress buffering according to claim 1, characterized in that: Both the first electrical interconnection line (2) and the second electrical interconnection line (4) are connected to grounding pins (6) via grounding lines (5). The grounding lines (5) connected to the first electrical interconnection line (2) and the second electrical interconnection line (4) are respectively located in the first chip (1) and the second chip (3). The two grounding pins (6) are respectively located on the sides of the first chip (1) and the second chip (3). The second electrical interconnection line (4) is connected to an electrical interconnection pin (7) located in the second chip (3).

4. The 3D stacked chip structure based on elastic microsphere stress buffering according to claim 1, characterized in that: The gap edge between the first chip (1) and the second chip (3) is filled with sealant (14), and the electrical interconnect pin (7) extending out of the second chip (3) is sealed with sealant (14). The first chip (1) and the second chip (3) together with the structure connected thereto are encapsulated in an epoxy molding layer (15), and the ends of the electrical interconnect pin (7) and the ground pin (6) extend out of the epoxy molding layer (15).

5. A method for fabricating a 3D stacked chip structure based on elastic microsphere stress buffering, as described in any one of claims 1 to 4, characterized in that: Includes the following steps: S1. Provide a first chip (1) and a second chip (3), and prepare electrical interconnects and functional conductive pads (8) on the bonding surfaces of the first chip (1) and the second chip (3) respectively, and lay out dummy metal pads (10) in the non-signal transmission area. S2. A silicon dioxide dielectric layer (13) is deposited on the surface of the first chip (1) and the second chip (3), and the tops of the functional conductive pad (8), the dummy metal pad (10) and the insulating UV adhesive (11) protrude from the surface of the silicon dioxide dielectric layer (13). S3. Provide pre-made elastic microspheres (12) and accurately place them on the insulating UV adhesive (11) coated on the dummy metal pad (10) to initially fix the elastic microspheres (12) with UV adhesive; S4. Align the first chip (1) and the second chip (3) vertically, and make them initially bonded by bonding and pre-bonding processes. At the same time, align the functional conductive pads (8) of the two chips and guide the elastic microspheres (12) to fall between the corresponding virtual metal pads (10). S5. The first chip (1) and the second chip (3) that are initially bonded are subjected to hot pressing and high-temperature annealing treatment, thereby forming a copper bonding curing layer (9) between the opposite functional conductive pads (8), and driving the upper and lower end faces of the elastic microspheres (12) to achieve eutectic welding with the corresponding dummy metal pads (10) to obtain a 3D stacked chip structure.

6. The method for fabricating a 3D stacked chip structure based on elastic microsphere stress buffering according to claim 5, characterized in that: The elastic microsphere (12) is provided with an elastic core and a conductive shell that completely covers the outer surface of the elastic core; the material of the elastic core of the elastic microsphere (12) is selected from any one or more combinations of polyimide, polyphthalamide, and polysiloxane, and the shear modulus of the elastic core of the elastic microsphere (12) is less than the shear modulus of the silicon substrate of the first chip (1) and the second chip (3); the conductive shell of the elastic microsphere (12) is a nickel-gold double-layer composite metal structure, with an inner layer of nickel and an outer layer of gold, and the total thickness of the shell is 120nm~150nm, and the diameter of the elastic microsphere (12) is 1μm~5μm.

7. The method for fabricating a 3D stacked chip structure based on elastic microsphere stress buffering according to claim 5, characterized in that: The elastic microspheres (12) are arranged in an asymmetric gradient density layout on the hybrid bonding interface. The density of elastic microspheres (12) in the high stress concentration area on the outer edge of the first chip (1) and the second chip (3) is greater than that in the low stress area in the center. The elastic microspheres (12) in the high stress concentration area on the outer edge of the first chip (1) and the second chip (3) are arranged in a honeycomb array and the area of ​​the arrangement area is 35% to 50%. The area of ​​the arrangement area in the low stress area in the center of the first chip (1) and the second chip (3) is 10%.

8. The method for fabricating a 3D stacked chip structure based on elastic microsphere stress buffering according to claim 5, characterized in that: In step S2, a silicon dioxide dielectric layer (13) is deposited on the surfaces of the first chip (1) and the second chip (3) using a PECVD process; wherein, the cavity temperature of the PECVD process is 300℃, the deposition pressure is 80Pa, and the thickness of the deposited silicon dioxide dielectric layer (13) is 1.5μm±0.05μm; and, the surface of the functional conductive pad (8), the dummy metal pad (10) and the elastic microsphere (12) is provided with the silicon dioxide dielectric layer (13), and the top of the functional conductive pad (8), the dummy metal pad (10) and the insulating UV adhesive (11) protrudes from the surface covered by the silicon dioxide dielectric layer (13).

9. The method for fabricating a 3D stacked chip structure based on elastic microsphere stress buffering according to claim 5, characterized in that: After step S5, an encapsulation step is also included: filling the gap edge between the first chip (1) and the second chip (3) with sealant (14), and using an epoxy encapsulation layer (15) to completely cover the two and the bonding connection structure between them, and making the ends of the electrical interconnect pins (7) and ground pins (6) in the second chip (3) extend out of the epoxy encapsulation layer (15).

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