Semiconductor package including power capacitor

Abstract

A semiconductor package includes a first semiconductor chip, a plurality of second semiconductor chips stacked on the first semiconductor chip in a first direction perpendicular to an upper surface of the first semiconductor chip, an upper semiconductor chip stacked on an uppermost second semiconductor chip of the plurality of second semiconductor chips, and a dummy semiconductor chip stacked on the upper semiconductor chip and including a capacitor. The upper semiconductor chip includes an upper via hole passing through at least a portion of the upper semiconductor chip and electrically connected with the capacitor.

Description

Cross-reference to related applications

[0001] This application claims the benefit of Korean Patent Application No. 10-2025-0043691, filed with the Korean Intellectual Property Office on April 3, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The example embodiment relates to a semiconductor package. Background Technology

[0003] To meet the demands for smaller size and higher capacity, semiconductor packaging technology continues to evolve. In recent years, various methods have been developed for manufacturing stacked semiconductor packages with reduced size, increased capacity, and improved mounting efficiency.

[0004] Additionally, three-dimensional stacking technology for multiple semiconductor chips has been developed. Through-silicon via (TSV) technology has also been developed, which allows connections between semiconductor packaged components via short interconnects through a silicon substrate.

[0005] In three-dimensional stacked structures, thermal resistance can increase with the number of stacked layers, potentially leading to power supply issues. When powered through the bottom substrate chip, the power path within the substrate chip is under significant stress, which can reduce the efficiency of powering the upward-facing semiconductor chips. To address these issues, technologies capable of providing a stable power supply to the stacked semiconductor chips are needed. Summary of the Invention

[0006] One aspect is the provision of a semiconductor package for improving power efficiency.

[0007] On the other hand, a semiconductor package for enhancing thermal properties by reducing thermal resistance is also provided.

[0008] However, the objectives to be achieved by the exemplary embodiments of this disclosure are not limited to the above-described objectives, and other objectives can be clearly understood by those skilled in the art through the following description.

[0009] According to one aspect, a semiconductor package is provided, comprising: a first semiconductor chip; a plurality of second semiconductor chips stacked on the first semiconductor chip along a first direction perpendicular to the upper surface of the first semiconductor chip; an upper semiconductor chip stacked on the uppermost of the plurality of second semiconductor chips; and a dummy semiconductor chip stacked on the upper semiconductor chip, and including a capacitor. The upper semiconductor chip includes an upper through-hole electrically connected to the capacitor.

[0010] According to another aspect, a semiconductor package is provided, comprising: a first semiconductor chip; a plurality of second semiconductor chips stacked on the first semiconductor chip along a first direction perpendicular to the upper surface of the first semiconductor chip; a connection terminal disposed on the lower surface of the first semiconductor chip; an upper semiconductor chip stacked on the uppermost of the plurality of second semiconductor chips; a dummy semiconductor chip stacked on the upper semiconductor chip and including a capacitor; and a molding layer surrounding the plurality of second semiconductor chips, the upper semiconductor chip, and the dummy semiconductor chip. Each of the plurality of second semiconductor chips includes a plurality of second vias, the plurality of second vias including power / ground vias configured to transmit a power supply voltage or a ground voltage between the first semiconductor chip and the plurality of second semiconductor chips, the upper semiconductor chip including an upper semiconductor substrate and an upper via, the upper via being electrically connected to the power / ground via and disposed in the upper semiconductor substrate, and the capacitor being electrically connected to the upper via.

[0011] According to another aspect, a semiconductor package is also provided, comprising: a first semiconductor chip; connection terminals disposed on a lower surface of the first semiconductor chip; a plurality of second semiconductor chips stacked on the first semiconductor chip along a first direction perpendicular to the upper surface of the first semiconductor chip; an upper semiconductor chip stacked on the uppermost of the plurality of second semiconductor chips; a dummy semiconductor chip comprising: a dummy semiconductor substrate stacked on the upper semiconductor chip; a dummy bonding layer; and a capacitor disposed between the dummy semiconductor substrate and the dummy bonding layer and connected to the upper semiconductor chip; and a molding layer surrounding the plurality of second semiconductor chips, the upper semiconductor chip, and the dummy semiconductor chip. The first semiconductor chip includes: a first semiconductor substrate; a first bonding layer on the lower surface of the first semiconductor substrate; a second bonding layer on the upper surface of the first semiconductor substrate; and a plurality of first vias disposed in the first semiconductor substrate. Each of the plurality of second semiconductor chips includes: a second semiconductor substrate; a second chip wiring layer; a plurality of second vias disposed in the second semiconductor substrate; a third bonding layer on the lower surface of the semiconductor chip; and a fourth bonding layer on the upper surface of the semiconductor chip. The plurality of second vias include: power / ground vias configured to transmit power supply voltage or ground voltage between the first semiconductor chip and the plurality of second semiconductor chips; and signal vias configured to transmit information. The upper semiconductor chip includes: an upper semiconductor substrate; a first upper bonding layer contacting the uppermost of the plurality of second semiconductor chips; a second upper bonding layer contacting a dummy semiconductor chip; and an upper via disposed in the upper semiconductor substrate and electrically connected to a capacitor and the power / ground via of each of the plurality of second semiconductor chips.

[0012] According to another aspect, a method for manufacturing a semiconductor package is provided, the method comprising: forming a first semiconductor chip; stacking a plurality of second semiconductor chips on the first semiconductor chip, each of the plurality of second semiconductor chips including a second semiconductor substrate and a plurality of second vias disposed in the second semiconductor substrate; stacking a semiconductor chip on the uppermost of the plurality of second semiconductor chips, the upper semiconductor chip including an upper semiconductor substrate and an upper via disposed in the upper semiconductor substrate; and stacking a dummy semiconductor chip including a capacitor on the upper semiconductor chip. The plurality of second vias include power / ground vias for transmitting power supply voltage or ground voltage and signal vias for transmitting information, and the capacitor is connected to the power / ground via through the upper via.

[0013] According to another aspect, a method of manufacturing a semiconductor package may further include: forming a first upper bonding layer disposed on a lower surface of an upper semiconductor substrate; forming a second upper bonding layer disposed on an upper surface of the upper semiconductor substrate and in contact with a dummy semiconductor chip; forming a second upper bonding pad surrounded by the second upper bonding layer; and forming a dummy bonding layer disposed below a capacitor and a fifth bonding pad surrounded by the dummy bonding layer, wherein the capacitor is connected to an upper via through the fifth bonding pad and the second upper bonding pad.

[0014] According to another aspect, a method of manufacturing a semiconductor package may further include: forming a molding layer surrounding a first semiconductor chip, a plurality of second semiconductor chips and a dummy semiconductor chip, wherein the upper surface of the dummy semiconductor chip is configured to be coplanar with the upper surface of the molding layer.

[0015] Detailed descriptions of other example embodiments are included in the detailed description and accompanying drawings.

[0016] The effects that can be obtained through this disclosure are not limited to those described above, and other effects will be apparent to those skilled in the art from the following description. Attached Figure Description

[0017] These and / or other aspects, features, and advantages of the present invention will become apparent and more readily understood from the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0018] Figure 1 This is a cross-sectional view of a semiconductor package according to an example embodiment;

[0019] Figure 2 yes Figure 1 A magnified view of the middle part P;

[0020] Figure 3 This is a cross-sectional view of a semiconductor package according to an example embodiment;

[0021] Figure 4 This is a cross-sectional view of a semiconductor package according to an example embodiment;

[0022] Figure 5 It is a cross-sectional view of a semiconductor package according to an example embodiment; and

[0023] Figures 6 to 11 This is a diagram illustrating the manufacturing process of a semiconductor package according to an example embodiment. Detailed Implementation

[0024] The present disclosure will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments described herein. It should also be emphasized that the present disclosure provides details of alternative examples, but such enumeration of alternatives is not exhaustive. Furthermore, any consistency in detail between the various examples should not be construed as requiring such detail. The terms and words used in this disclosure and the appended claims are not limited to their general or dictionary definitions, and are to be interpreted in accordance with the principle that the inventor may appropriately define the concepts of the terms in order to best describe his invention.

[0025] In the following description, the singular form of the item identifier does not limit the item to a single instance; multiple instances of the item may exist, and the description of the item may apply to all instances unless the context explicitly states otherwise. Terms such as “include” or “comprising” indicate the presence of a feature, number, operation, action, element, component, or combination thereof, but it should be understood that one or more other features, numbers, operations, actions, elements, components, or combinations thereof may be present or added.

[0026] Throughout this disclosure, ordinal numbers such as “first” and “second” may be used to describe various elements. However, elements described without the use of “first”, “second”, etc., in the specification may still be referred to as “first” or “second” in the claims. Furthermore, elements referenced with a specific ordinal number (e.g., “first” in a particular claim) may be referenced elsewhere without an ordinal number or with a different ordinal number (e.g., “second” in the specification or another claim).

[0027] In the following description, it should be noted that expressions such as upper side, upper surface, lower side, lower surface, side surface, front surface, or rear surface are based on the orientation shown in the accompanying drawings, and these expressions may change when the relative orientation of the respective objects changes. For clarity or emphasis, the shape and size of elements in the accompanying drawings may be exaggerated. Similar reference numerals are used throughout the text to denote similar elements.

[0028] The terms used herein, such as “identical,” “equal,” “plane,” “coplanar,” “parallel,” and “perpendicular,” cover identical or nearly identical, including variations that may occur due to conventional manufacturing processes. Unless the context or other statement otherwise indicates, the term “substantially” may be used herein to emphasize that meaning.

[0029] The various pads of the device described herein can be conductive terminals connected to the internal wiring of the device and can transmit signals and / or power supply voltages between the internal wiring and / or internal circuitry of the device and external sources. Various pads can be disposed on or near the outer surface of the device, and their planar dimensions can be larger than the wiring (e.g., the XY horizontal dimensions of the pad are both larger than the width of the internal wiring to which it is connected) to facilitate electrical connections to another terminal (e.g., a bump or solder ball) and / or external wiring.

[0030] As used herein, the term "dummy" refers to a component that has the same or similar shape and / or structure as a component with the same name but without the "dummy" descriptor, but does not have the same substantive function (e.g., signal transmission). In some cases, a "dummy" element may be electrically floating or may be connected to various voltage sources, but does not provide the same functionality as the non-dummy element it represents. For example, a dummy pad may not be electrically connected to wiring, or a dummy chip may not include active semiconductor devices.

[0031] It will be understood that when referring to an element as "connected" or "coupled" to another element or "on top of" another element, the element may be directly connected or coupled to the other element or directly on top of the other element, or there may be an intermediate element. In contrast, when referring to an element as "directly connected" or "directly coupled" to another element or "in contact" with another element (or in any form that uses the word "in contact"), there is no intermediate element at the point of contact.

[0032] As used herein, components described as "electrically connected" are configured such that electrical signals can be transmitted from one component to another (although the strength of such signals may be attenuated and they may be selectively transmitted during transmission). Furthermore, components with "direct electrical connections" form a common electrical node through electrical connections of one or more conductors (e.g., wires, pads, internal wiring, vias, etc.). Therefore, directly electrically connected components do not include components electrically connected via active elements (e.g., transistors or diodes).

[0033] In the following description, exemplary embodiments based on the technical concept of this disclosure will be described with reference to the accompanying drawings.

[0034] Figure 1 A semiconductor package 10 according to an example embodiment is shown, and Figure 2 yes Figure 1 A magnified view of the middle part P.

[0035] refer to Figure 1 and Figure 2 The semiconductor package 10 according to the example embodiment may include a first semiconductor chip 100, a connection terminal 150, a plurality of second semiconductor chips 201 to 207, an upper semiconductor chip 208, a dummy semiconductor chip 400, and a molding layer 450.

[0036] According to the example embodiment, the first direction D1 can refer to the direction intersecting with the upper surface of the first semiconductor chip 100, and is the direction in which the first semiconductor chip 100, the chip stack 200, and the dummy semiconductor chip 400 are stacked on top of each other. For example, the first direction D1 can be a direction perpendicular to the upper surface of the first semiconductor chip 100. The second direction D2 can refer to a direction parallel to the upper surface of the first semiconductor chip 100 and intersecting with the first direction D1. The third direction D3 can refer to a direction intersecting with the first direction D1 and the second direction D2. The first direction D1 and the second direction D2, the second direction D2 and the third direction D3, and the first direction D1 and the third direction D3 can each be perpendicular to each other.

[0037] The first semiconductor chip 100 may include a first semiconductor substrate 110, a first via 111, a first chip wiring layer 120, a first bonding layer 130, and a second bonding layer 140.

[0038] The first semiconductor substrate 110 may include an upper surface and a lower surface opposite to each other. The upper surface of the first semiconductor substrate 110 may be an upper surface in a first direction D1, and the lower surface of the first semiconductor substrate 110 may be a lower surface in the first direction D1. The upper surface of the first semiconductor substrate 110 may be a surface facing the chip stack 200. The lower surface of the first semiconductor substrate 110 may be a surface on which the first chip wiring layer 120 is formed.

[0039] The first semiconductor substrate 110 may include silicon (Si). However, the material of the first semiconductor substrate 110 is not limited to this. For example, the first semiconductor substrate 110 may include other semiconductor materials, such as germanium (Ge), germanium silicon (Ge-Si), or group III-V compounds such as gallium phosphide (GaP), gallium arsenide (GaAs), and gallium antimonide (GaSb). For example, the first semiconductor substrate 110 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0040] A first via 111 may be disposed in a first semiconductor substrate 110. The first via 111 may pass through the first semiconductor substrate 110 and be connected to a first chip wiring layer 120. For example, the first via 111 may be connected to the first chip wiring layer 120 and a second bonding pad 141. For example, the upper portion of each first via 111 may be connected to a corresponding one of the second bonding pads 141, and the lower portion of each first via 111 may be connected to the first chip wiring layer 120.

[0041] The first via 111 may be cylindrical. For example, the first via 111 may be formed as a through-silicon via (TSV) in the first semiconductor chip 100. For example, the first via 111 may include copper (Cu), aluminum (Al) or tungsten (W), but these are just examples.

[0042] The first chip wiring layer 120 may include a semiconductor device and has a circuit structure electrically connected to the semiconductor device. Although not shown in detail, the first chip wiring layer 120 may have a multi-layer wiring structure, which includes multiple wiring patterns and multiple wiring vias located at different heights.

[0043] The first chip wiring layer 120 may include various types of electronic devices. For example, the first chip wiring layer 120 may include metal-oxide-semiconductor field-effect transistors (MOSFETs) (e.g., complementary metal-oxide-semiconductor (CMOS) transistors), system-scale integrated circuits (LSI), flash memory, dynamic random access memory (DRAM), static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), phase-change random access memory (PRAM), magnetic random access memory (MRAM) or resistive RAM (RERAM), image sensors (e.g., CMOS image sensors (CIS)), microelectromechanical systems (MEMS), active devices, passive devices, etc.

[0044] The first bonding layer 130 may be disposed below the first semiconductor substrate 110 and on the lower surface of the first chip wiring layer 120. The first bonding layer 130 may be disposed below the first chip wiring layer 120. The first bonding layer 130 may surround the first bonding pad 131 connected to a corresponding one of the connection terminals 150.

[0045] The first bonding layer 130 may surround the first bonding pad 131. Each of the first bonding pads 131 may be electrically connected to a corresponding first via 111. The first bonding pads 131 may be a plurality of bonding pads spaced apart from each other in a second direction D2 or a third direction D3.

[0046] The second bonding layer 140 may be disposed on the upper surface of the first semiconductor substrate 110. The second bonding layer 140 may surround the second bonding pad 141. Each of the second bonding pads 141 may be electrically connected to a corresponding first via 111. The second bonding pads 141 may be connected to the lowermost second semiconductor chip 201 among a plurality of second semiconductor chips 201 to 207. The second bonding pads 141 may include a plurality of bonding pads spaced apart from each other in a second direction D2 or a third direction D3.

[0047] The first bonding layer 130 and the second bonding layer 140 may include materials comprising at least one of the following: silicon monoxide (SiO), silicon nitride (SiN), silicon carbonitride (SiCN), silicon carbon monoxide (SiCO), and polymers. The first bonding pad 131 and the second bonding pad 141 may include conductive materials such as copper (Cu), aluminum (Al), or tungsten (W), but these are merely examples.

[0048] Connection terminals 150 may be disposed on the lower surface of the first semiconductor chip 100. Connection terminals 150 may be disposed below the first bonding pad 131. Each connection terminal 150 may be electrically connected to a corresponding one of the first bonding pads 131. The semiconductor package 10 may be electrically connected to external components via the connection terminals 150. For example, the connection terminals 150 may be electrically connected to an external voltage source and supply power to the chip stack 200 through the first bonding pad 131, the first chip wiring layer 120, the first via 111, and the second bonding pad 141.

[0049] The connection terminal 150 may include at least one of solder balls, bumps, under-bump metallization (UBM), etc., but this is just an example.

[0050] The chip stack 200 may include a plurality of second semiconductor chips 201 to 207 and an upper semiconductor chip 208. The number of semiconductor chips included in the chip stack 200 shown and described in this disclosure is for illustrative purposes only and should not be construed as limiting.

[0051] Multiple second semiconductor chips 201 to 207 may be stacked on the first semiconductor chip 100 along a first direction D1 intersecting the upper surface of the first semiconductor chip 100. The thickness of each of the multiple second semiconductor chips 201 to 207 in the first direction D1 may be the same as the thickness of the upper semiconductor chip 208 in the first direction D1. Each of the multiple second semiconductor chips 201 to 207 may include a second semiconductor substrate 210, a second via 211, a second chip wiring layer 220, a third bonding layer 230, and a fourth bonding layer 240.

[0052] The second semiconductor substrate 210 may include an upper surface and a lower surface opposite to each other. The upper surface of the second semiconductor substrate 210 may be an upper surface in the first direction D1, and the lower surface of the second semiconductor substrate 210 may be a lower surface in the first direction D1. The upper surface of the second semiconductor substrate 210 may be a surface facing the dummy semiconductor chip 400. The lower surface of the second semiconductor substrate 210 may be a surface on which the second chip wiring layer 220 is formed.

[0053] The second semiconductor substrate 210 may include silicon (Si). However, the material of the second semiconductor substrate 210 is not limited to this. For example, the second semiconductor substrate 210 may include other semiconductor materials, such as germanium (Ge), germanium silicon (Ge-Si), or group III-V compounds such as gallium phosphide (GaP), gallium arsenide (GaAs), and gallium antimonide (GaSb). For example, the second semiconductor substrate 210 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0054] A second via 211 may be disposed in the second semiconductor substrate 210. The second via 211 may pass through the second semiconductor substrate 210 and connect to the second chip wiring layer 220. For example, the second via 211 may connect to the second chip wiring layer 220 and the fourth bonding pad 241. For example, the upper portion of each second via 211 may connect to a corresponding one of the fourth bonding pads 241, and the lower portion of each second via 211 may connect to the second chip wiring layer 220.

[0055] The second via 211 may be cylindrical. For example, the second via 211 may be formed as a through-silicon via (TSV) in the second semiconductor chips 201 to 207. For example, the second via 211 may include a conductive material such as copper (Cu), aluminum (Al) or tungsten (W), but these are just examples.

[0056] The second via 211 may include a signal via 211a and a power / ground via 211b. The signal via 211a can transmit data information (e.g., data), address, and / or control / command information between the first semiconductor chip 100 and the chip stack 200. The power / ground via 211b can transmit power supply voltage or ground voltage between the first semiconductor chip 100 and the chip stack 200. For example, the power / ground via 211b can be connected to a voltage source or internal voltage regulator of the semiconductor package.

[0057] At least one second via 211 can be connected to a corresponding one of the upper via 311 and the capacitor 421. For example, a power / ground via 211b can be connected to a corresponding one of the upper via 311 and the capacitor 421. Additionally, at least one first via 111 and a corresponding connection terminal 150 can be connected to the capacitor 421 through the power / ground via 211b. Accordingly, the power efficiency of the semiconductor package 10 can be improved. Furthermore, the thermal characteristics can be enhanced by reducing the resistance of the semiconductor package 10.

[0058] The second chip wiring layer 220 may include various types of electronic devices. For example, the second chip wiring layer 220 may include metal-oxide-semiconductor field-effect transistors (MOSFETs) (e.g., complementary metal-oxide-semiconductor (CMOS) transistors), system-scale integrated circuits (LSI), flash memory, dynamic random access memory (DRAM), static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), phase-change random access memory (PRAM), magnetic random access memory (MRAM) or resistive RAM (RERAM), image sensors (e.g., CMOS image sensors (CIS)), microelectromechanical systems (MEMS), active devices, passive devices, etc.

[0059] The third bonding layer 230 can be disposed below the second semiconductor substrate 210 on the lower surface of the second chip wiring layer 220.

[0060] The third bonding layer 230 may surround the third bonding pad 231. The third bonding pad 231 may be electrically connected to the second via 211. For example, each third bonding pad in the third bonding pad 231 may be electrically connected to a corresponding one in the second via 211. The third bonding pad 231 may include a plurality of bonding pads spaced apart from each other in the second direction D2 or the third direction D3.

[0061] A fourth bonding layer 240 may be disposed on the upper surface of the second semiconductor substrate 210. The fourth bonding layer 240 may surround a fourth bonding pad 241. The fourth bonding pad 241 may be electrically connected to a second via 211. For example, each fourth bonding pad 241 may be electrically connected to a corresponding second via 211. The fourth bonding pad 241 may include a plurality of bonding pads spaced apart from each other in a second direction D2 or a third direction D3.

[0062] The third bonding layer 230 and the fourth bonding layer 240 may comprise at least one of the following materials: silicon monoxide (SiO), silicon nitride (SiN), silicon carbonitride (SiCN), silicon carbon monoxide (SiCO), and polymers. For example, the third bonding pad 231 and the fourth bonding pad 241 may comprise copper (Cu), aluminum (Al), or tungsten (W), but these are merely examples.

[0063] Multiple second semiconductor chips 201 to 207 can be bonded to each other. Adjacent third bonding layers 230 and fourth bonding layers 240 within the chip stack 200 can contact and bond together. Multiple second semiconductor chips 201 to 207 adjacent to each other in the first direction D1 can be electrically connected through third bonding pads 231 and fourth bonding pads 241.

[0064] The upper semiconductor chip 208 can be disposed on the uppermost second semiconductor chip 207 among a plurality of second semiconductor chips 201 to 207. The upper semiconductor chip 208 may include an upper semiconductor substrate 310, an upper via 311, a first upper bonding layer 330 and a second upper bonding layer 340.

[0065] A dummy semiconductor chip 400 may be disposed on the upper surface of the upper semiconductor substrate 310, and a plurality of second semiconductor chips 201 to 207 may be disposed on the lower surface of the upper semiconductor substrate 310. The upper semiconductor substrate 310 may include silicon (Si). However, the material of the upper semiconductor substrate 310 is not limited thereto. For example, the upper semiconductor substrate 310 may include other semiconductor materials, such as germanium (Ge), germanium silicon (Ge-Si), or group III-V compounds such as gallium phosphide (GaP), gallium arsenide (GaAs), and gallium antimonide (GaSb). For example, the upper semiconductor substrate 310 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0066] An upper via 311 may be disposed in the upper semiconductor substrate 310. The upper via 311 may pass through at least a portion of the upper semiconductor chip 208. The upper via 311 may be connected to a corresponding second via 211. For example, the upper via 311 may be connected to a power / ground via 211b in the second via 211. When the upper via 311 is connected to a signal via 211a, the data signal transmitted through the signal via 211a may be lost due to the stub effect. Therefore, the upper via 311 may not be connected to the signal via 211a, but this is merely an example.

[0067] Each upper via 311 can overlap with a corresponding power / ground via 211b in the first direction D1. The upper via 311 can be formed to correspond to one of the second vias 211 of the uppermost second semiconductor chip 207 among a plurality of second semiconductor chips 201 to 207. The upper semiconductor substrate 310 can be disposed in a region of the upper semiconductor chip 208 corresponding to at least one second via 211, where no corresponding upper via 311 is formed. For example, the upper semiconductor substrate 310 can be configured to overlap with at least one signal via 211a.

[0068] The upper via 311 can be cylindrical. For example, the upper via 311 can be formed as a through-silicon via (TSV) in the upper semiconductor chip 208. For example, the upper via 311 can include a conductive material such as copper (Cu), aluminum (Al) or tungsten (W), but these are just examples.

[0069] The first upper bonding layer 330 may be disposed below the upper semiconductor substrate 310 on the lower surface of the upper chip wiring layer 320. The first upper bonding layer 330 may surround the first upper bonding pad 331.

[0070] The first upper bonding pad 331 may include a plurality of bonding pads spaced apart from each other in the second direction D2 or the third direction D3. As an example, the first upper bonding pad 331 may overlap with a corresponding second via 211 in the first direction D1. As another example, the first upper bonding pad 331 may overlap with a corresponding third bonding pad 231 and a corresponding fourth bonding pad 241 in the first direction D1. For example, each first upper bonding pad 331 may be connected to the fourth bonding pad 241 of the uppermost second semiconductor chip 207 among a plurality of second semiconductor chips 201 to 207.

[0071] The second upper bonding layer 340 may be disposed on the upper surface of the upper semiconductor substrate 310. The second upper bonding layer 340 may surround the second upper bonding pad 341. The second upper bonding pad 341 may include a plurality of bonding pads spaced apart from each other in the second direction D2 or the third direction D3. The second upper bonding pad 341 may be formed to overlap with a corresponding first upper bonding pad 331 in the first direction D1. The second upper bonding pad 341 may be connected to at least one first upper bonding pad 331 through a corresponding upper via 311. The second upper bonding pad 341 may be connected to a power / ground via 211b, at least one first via 111, and at least one connection terminal 150 through the upper via 311.

[0072] The dummy semiconductor chip 400 can be disposed on the upper semiconductor chip 208. For example, the width of the dummy semiconductor chip 400 in the second direction D2 can be the same as the width of the chip stack 200 in the second direction D2. The dummy semiconductor chip 400 may include a dummy semiconductor substrate 410, an upper wiring layer 420, and a dummy bonding layer 430.

[0073] The dummy semiconductor substrate 410 may be formed to be thicker than the second semiconductor substrate 210 and the upper semiconductor substrate 310 in the first direction D1. The upper surface of the dummy semiconductor substrate 410 may be disposed on the same plane as the upper surface of the molding layer 450 (e.g., they may be coplanar). Heat generated inside the semiconductor package 10 may be released to the outside of the semiconductor package 10 through the dummy semiconductor substrate 410.

[0074] The upper wiring layer 420 may be disposed between the dummy semiconductor substrate 410 and the upper semiconductor chip 208. When power is supplied to the chip stack 200 via the connection terminal 150, it may be difficult to supply power to the upper part of the chip stack 200. The upper wiring layer 420 may include a capacitor 421 disposed below the dummy semiconductor substrate 410 to improve power supply to the upper part of the chip stack 200.

[0075] Capacitor 421 can be connected to a fifth bonding pad 431 of a dummy bonding layer 430, which is disposed below the upper wiring layer 420. The fifth bonding pad 431 can be configured to overlap with one of the second upper bonding pads 341 in a first direction and be positioned corresponding to the second upper bonding pad 341. The fifth bonding pad 431 can be electrically connected between capacitor 421 and the second upper bonding pad 341. Capacitor 421 can power a semiconductor chip disposed on the upper part of the chip stack 200.

[0076] A molding layer 450 may be disposed on the first semiconductor chip 100. The molding layer 450 may cover a portion of the upper surface of the first semiconductor chip 100. The molding layer 450 may surround the side surfaces of the chip stack 200 and the dummy semiconductor chip 400. The upper surface of the molding layer 450 may be disposed on the same plane as the upper surface of the dummy semiconductor chip 400. For example, the molding layer 450 may include an epoxy molding compound (EMC), but this is merely an example.

[0077] Figures 3 to 5 It shows a difference Figure 1 The semiconductor package shown is a semiconductor package according to an example embodiment. Elements that are the same as, substantially the same as, or similar to those previously described may be identified using the same reference numerals, and the description of these elements may be omitted or limited, provided that the previous description still applies. Figures 3 to 5 The relevant descriptions will mainly focus on... Figure 1The differences between the example embodiments shown.

[0078] refer to Figure 3 The second upper bonding layer 340 includes a first dummy bonding pad 341a. The first dummy bonding pad 341a may correspond to the first upper bonding pad 331 and may be located in areas of the second upper bonding layer 340 where the second upper bonding pad 341 is not located. For example, the first dummy bonding pad 341a may overlap with each of the first upper bonding pads 331 that do not correspond to the second upper bonding pad 341 in the first direction D1.

[0079] The bonding pads 341 and 341a of the second upper bonding layer 340 can be formed in the region that overlaps with the fourth bonding pad 241 of the fourth bonding layer 240 in the first direction D1.

[0080] refer to Figure 4 The second dummy bonding pad 431a can also be disposed in the dummy bonding layer 430. The second dummy bonding pad 431a can be disposed in a region corresponding to the first upper bonding pad 331, and no fifth bonding pad 431 is disposed in this region. For example, the second dummy pad 431a can overlap with each of the first upper bonding pads 331 that do not correspond to the fifth bonding pad 431 in the first direction D1.

[0081] refer to Figure 5 The semiconductor package 10 may further include a first support layer 30, a first solder ball 31, a second support layer 40, and a second solder ball 41. The first support layer 30 may be disposed between the first semiconductor chip 100 and the second semiconductor chip 201, between adjacent second semiconductor chips 201 to 207, and between the second semiconductor chip 207 and the upper semiconductor chip 208. As an example, the first support layer 30 may be disposed between the second bonding layer 140 and the third bonding layer 230 of the lowermost second semiconductor chip 201 among the plurality of second semiconductor chips 201 to 207. As another example, between adjacent second semiconductor chips 201 to 207, the first support layer 30 may be disposed between the fourth bonding layer 240 of the lower second semiconductor chip and the third bonding layer 230 of the upper second semiconductor chip. As another example, the first support layer 30 may be disposed between the fourth bonding layer 240 of the second semiconductor chip 207 and the first upper bonding layer 330. For example, the first support layer 30 may include a non-conductive film (NCF).

[0082] The first solder ball 31 can be electrically connected between the first semiconductor chip 100 and a plurality of second semiconductor chips 201 to 207. As an example, each of the first solder balls 31 can be disposed between a corresponding second bonding pad 141 and a corresponding third bonding pad 231 of the second semiconductor chip 201. As another example, between adjacent second semiconductor chips 201 to 207, the first solder ball 31 can each be disposed between a corresponding fourth bonding pad 241 of the lower second semiconductor chip and a corresponding third bonding pad 231 of the upper second semiconductor chip. As yet another example, the first solder ball 31 can each be disposed between a corresponding fourth bonding pad 241 and a corresponding first upper bonding pad 331 of the second semiconductor chip 207.

[0083] The second support layer 40 can be disposed between the upper semiconductor chip 208 and the dummy semiconductor chip 400. For example, the second support layer 40 can be disposed between the second upper bonding layer 340 and the dummy bonding layer 430.

[0084] The second solder ball 41 can be disposed between the second upper bonding pad 341 and the fifth bonding pad 431. The second solder ball 41 can be electrically connected to the capacitor 421 through the fifth bonding pad 431.

[0085] Figures 6 to 11 This is an example diagram illustrating the manufacturing process of a semiconductor package 10 according to an example embodiment.

[0086] refer to Figure 6 After attaching the first release film 521 to the upper surface of the first support substrate 511, the first semiconductor chip 100 can be attached to the first release film 521. The first semiconductor chip 100 can be attached to the first release film 521, so that the first chip wiring layer 120 faces the first support substrate 511.

[0087] The bottommost second semiconductor chip 201 can be disposed on the first semiconductor chip 100. The second bonding pad 141 of the first semiconductor chip 100 and the third bonding pad 231 of the second semiconductor chip 201 can be bonded together by heat and pressure.

[0088] refer to Figure 7 Multiple second semiconductor chips 201 to 207 can be stacked sequentially on the first semiconductor chip 100. Among the adjacent second semiconductor chips 201 to 207, during stacking, the fourth bonding pad 241 of the lower second semiconductor chip can be bonded to the third bonding pad 231 of the upper second semiconductor chip by heating and pressurizing.

[0089] The upper semiconductor chip 208 can be disposed on the uppermost second semiconductor chip 207. The first upper bonding pad 331 and the fourth bonding pad 241 of the uppermost second semiconductor chip 207 can be bonded together by heat and pressure.

[0090] refer to Figure 8 The dummy semiconductor chip 400 can be stacked on the upper semiconductor chip 208. The fifth bonding pad 431 of the dummy semiconductor chip 400 and the fourth bonding pad 341 of the upper semiconductor chip 208 can be bonded together by heat and pressure.

[0091] refer to Figure 9 A molding layer 450 can be formed to cover the upper surface of the first semiconductor chip 100 and surround the side surfaces of the chip stack 200 and the dummy semiconductor chip 400. The molding layer 450 and the upper surface of the dummy semiconductor chip 400 can be aligned on the same plane because their upper portions can be partially removed by a polishing process (e.g., chemical mechanical polishing (CMP)). After the molding layer 450 is formed, the first support substrate 511 and the first release film 521 can be separated from the first chip wiring layer 120.

[0092] refer to Figure 10 It can Figure 9 The structure is reversed, attached to the second release film 522, and bonded to the second support substrate 512. The upper surfaces of the dummy semiconductor substrate 410 and the molding layer 450 can be bonded to the second release film 522.

[0093] refer to Figure 11 A first bonding layer 130, a first bonding pad 131, and a connection terminal 150 can be formed above the first chip wiring layer 120. The second support substrate 512 and the second release film 522 can be separated from the dummy semiconductor substrate 410 and the molding layer 450, and when the structure is reversed, a [structure / structure] can be formed. Figure 1 The semiconductor package 10 shown.

[0094] Although this disclosure has been described in detail with reference to the foregoing exemplary embodiments, its scope is not limited thereto, and those skilled in the art will understand that this disclosure is intended to cover various modifications and equivalent arrangements within the spirit and scope of the appended claims. Furthermore, the foregoing exemplary embodiments can be implemented by removing some of their elements, and each exemplary embodiment can be implemented.

Claims

1. A semiconductor package, comprising: First semiconductor chip; Multiple second semiconductor chips are stacked on the first semiconductor chip along a first direction perpendicular to the upper surface of the first semiconductor chip; The upper semiconductor chip is stacked on the topmost of the plurality of second semiconductor chips; as well as A dummy semiconductor chip is stacked on top of the semiconductor chip and includes a capacitor. The upper semiconductor chip includes an upper through-hole electrically connected to the capacitor.

2. The semiconductor package according to claim 1, wherein, Each of the plurality of second semiconductor chips includes: Second semiconductor substrate; Second chip wiring layer; and Multiple second vias are disposed in the second semiconductor substrate.

3. The semiconductor package according to claim 2, wherein, In each of the plurality of second semiconductor chips: The plurality of second vias include power / ground second vias configured to transmit power supply voltage or ground voltage, and The upper through hole and the capacitor are electrically connected to the power / ground second through hole.

4. The semiconductor package according to claim 3, wherein, In each of the plurality of second semiconductor chips, the plurality of second vias further include signal second vias configured to transmit information.

5. The semiconductor package according to claim 3, in, The first semiconductor chip includes: First semiconductor substrate; A first bonding layer is formed on the lower surface of the first semiconductor substrate; A second bonding layer is formed on the upper surface of the first semiconductor substrate; and Multiple first through-holes are disposed in the first semiconductor substrate, and Among them, the first through hole in the plurality of first through holes is the first power supply through hole that is electrically connected to the capacitor through the second power supply / grounding through hole.

6. The semiconductor package according to claim 5, further comprising: A connection terminal is disposed on the lower surface of the first bonding layer of the first semiconductor chip. The connection terminal is electrically connected to the capacitor through the first power supply through hole, the second power supply / grounding through hole, and the upper through hole.

7. The semiconductor package according to claim 6, in, The first semiconductor chip also includes: A first bonding pad is bonded to the connection terminal; and The second bonding pad is bonded to the lowest of the plurality of second semiconductor chips, and Each of the plurality of second semiconductor chips further includes: A third bonding layer is formed on the lower surface of the second semiconductor chip; A fourth bonding layer is formed on the upper surface of the second semiconductor chip; The third bonding pad is bonded to a corresponding second through-hole among the plurality of second through-holes; and The fourth bonding pad is bonded to the corresponding second through hole.

8. The semiconductor package according to claim 7, wherein, The semiconductor chip also includes: Upper semiconductor substrate, surrounding the upper via; The first upper bonding layer is in contact with the uppermost second semiconductor chip among the plurality of second semiconductor chips; The second upper bonding layer is in contact with the dummy semiconductor chip; A first upper bonding pad, bonded to the fourth bonding pad of the uppermost of the plurality of second semiconductor chips; and The second upper bonding pad overlaps with the upper via in the first direction.

9. The semiconductor package according to claim 2, wherein, The semiconductor chip also includes: Upper semiconductor substrate, surrounding the upper via; The first upper bonding layer is in contact with the uppermost second semiconductor chip among the plurality of second semiconductor chips; The second upper bonding layer is in contact with the dummy semiconductor chip; A plurality of first upper bonding pads, each of the plurality of first upper bonding pads overlapping with a corresponding second via in the plurality of second vias in the first direction; Multiple second upper bonding pads are disposed between the upper via and the capacitor; and The first dummy bonding pad corresponds to a corresponding first upper bonding pad among the plurality of first upper bonding pads between two adjacent second upper bonding pads.

10. The semiconductor package according to claim 9, wherein, The virtual semiconductor chip also includes: A virtual semiconductor substrate is disposed above the upper semiconductor chip; An upper wiring layer is disposed below the dummy semiconductor substrate, and the capacitor is disposed in the upper wiring layer; A dummy bonding layer is provided below the upper wiring layer; The fifth bonding pad overlaps with a corresponding second upper bonding pad among the plurality of second upper bonding pads in the first direction; and The second dummy bonding pad overlaps with the corresponding first dummy bonding pad in the first direction.

11. The semiconductor package according to claim 1, further comprising: A molding layer surrounds the plurality of second semiconductor chips, the upper semiconductor chip, and the dummy semiconductor chip.

12. The semiconductor package according to claim 1, wherein, Each of the plurality of second semiconductor chips has the same thickness in the first direction.

13. The semiconductor package according to claim 12, wherein, The thickness of the upper semiconductor chip in the first direction is the same as the thickness of each of the plurality of second semiconductor chips in the first direction.

14. A semiconductor package, comprising: First semiconductor chip; Multiple second semiconductor chips are stacked on the first semiconductor chip along a first direction perpendicular to the upper surface of the first semiconductor chip; A connection terminal is disposed on the lower surface of the first semiconductor chip; The upper semiconductor chip is stacked on the topmost of the plurality of second semiconductor chips; A dummy semiconductor chip is stacked on top of the semiconductor chip and includes a capacitor; and A molding layer surrounds the plurality of second semiconductor chips, the upper semiconductor chip, and the dummy semiconductor chip. Each of the plurality of second semiconductor chips includes a plurality of second vias, the plurality of second vias including power / ground vias configured to transmit power supply voltage or ground voltage between the first semiconductor chip and the plurality of second semiconductor chips, and The upper semiconductor chip includes an upper semiconductor substrate and an upper via. The upper via is electrically connected to the power / ground via and is disposed in the upper semiconductor substrate. The capacitor is electrically connected to the upper through hole.

15. The semiconductor package of claim 14, wherein, In each of the plurality of second semiconductor chips, the plurality of second vias further include signal vias configured to transmit information.

16. The semiconductor package of claim 14, wherein, The first semiconductor chip includes: A first bonding layer includes a first bonding pad bonded to the connection terminal; and The second bonding layer includes a second bonding pad bonded to the lowermost second semiconductor chip among the plurality of second semiconductor chips that contacts the first semiconductor chip, and Each of the plurality of second semiconductor chips further includes: A third bonding layer is formed on the lower surface of the second semiconductor chip; A fourth bonding layer is formed on the upper surface of the second semiconductor chip; A third bonding pad is connected to a corresponding second through-hole among the plurality of second through-holes; and The fourth bonding pad is connected to the corresponding second through hole among the plurality of second through holes.

17. The semiconductor package of claim 14, wherein, The upper surface of the dummy semiconductor chip is coplanar with the upper surface of the molding layer.

18. The semiconductor package of claim 17, wherein, The semiconductor chip also includes: A first upper bonding layer is in contact with the uppermost second semiconductor chip among the plurality of second semiconductor chips, and is disposed on the lower surface of the upper semiconductor chip; A second upper bonding layer is disposed on the upper surface of the upper semiconductor chip; First upper bonding pads, each overlapping in the first direction with a corresponding second via of the plurality of second vias in each of the plurality of second semiconductor chips; and The second upper bonding pad connects the dummy semiconductor chip and the upper semiconductor chip.

19. The semiconductor package of claim 14, wherein, Each of the plurality of second semiconductor chips has the same thickness in the first direction.

20. A semiconductor package, comprising: First semiconductor chip; A connection terminal is disposed on the lower surface of the first semiconductor chip; Multiple second semiconductor chips are stacked on the first semiconductor chip along a first direction perpendicular to the upper surface of the first semiconductor chip; The upper semiconductor chip is stacked on the topmost of the plurality of second semiconductor chips; A dummy semiconductor chip includes a dummy semiconductor substrate stacked on the upper semiconductor chip, a dummy bonding layer, and a capacitor disposed between the dummy semiconductor substrate and the dummy bonding layer and connected to the upper semiconductor chip; as well as A molding layer surrounds the plurality of second semiconductor chips, the upper semiconductor chip, and the dummy semiconductor chip. The first semiconductor chip includes: First semiconductor substrate; A first bonding layer is formed on the lower surface of the first semiconductor substrate; A second bonding layer is formed on the upper surface of the first semiconductor substrate; and Multiple first vias are disposed in the first semiconductor substrate. Each of the plurality of second semiconductor chips includes: Second semiconductor substrate; Second chip wiring layer; Multiple second through holes are disposed in the second semiconductor substrate; A third bonding layer is formed on the lower surface of the second semiconductor chip; and A fourth bonding layer is formed on the upper surface of the second semiconductor chip; The plurality of second through holes include: A power / ground via is configured to transmit power voltage or ground voltage between the first semiconductor chip and the plurality of second semiconductor chips; and Signal vias are configured to transmit information, and The upper semiconductor chip includes: On semiconductor substrate; The first upper bonding layer is in contact with the uppermost second semiconductor chip among the plurality of second semiconductor chips; The second upper bonding layer is in contact with the dummy semiconductor chip; and An upper via is disposed in the upper semiconductor substrate, and the upper via is electrically connected to the capacitor and the power / ground via of each of the plurality of second semiconductor chips.

Images