Semiconductor package

Abstract

A semiconductor package includes a package substrate, at least one first semiconductor chip stacked offset in a first direction on the package substrate, first semiconductor chip pads on a top surface of each of the at least one first semiconductor chip, at least one second semiconductor chip stacked offset in the first direction on a first semiconductor chip of the at least one first semiconductor chip disposed at an uppermost end, second semiconductor chip pads on a top surface of each of the at least one second semiconductor chip, and a plurality of substrate pads arranged in two rows on the package substrate, wherein a second semiconductor chip disposed at a lowermost end of the at least one second semiconductor chip is stacked offset in the first direction and a second direction on the first semiconductor chip disposed at the uppermost end.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2025-0044928, filed on April 7, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor packages. Background Technology

[0003] Due to the rapid development of the electronics industry and user demands, electronic devices are becoming more compact and lightweight. As a result, high integration and large capacity are expected in semiconductor devices, which are the core components of electronic devices. However, the high integration of semiconductor devices is reaching its limits. Therefore, semiconductor packages that include multiple semiconductor chips have been developed to achieve high capacity. Summary of the Invention

[0004] With the increasing demand for high-capacity semiconductor devices, semiconductor packages that include multiple semiconductor chips stacked within the package can be developed. Methods for stacking multiple semiconductor chips within the package and connecting the stacked chips to the package substrate via wiring formed by wire bonding or patterning between the multiple semiconductor chips and the package substrate are also considered.

[0005] According to embodiments of this disclosure, a semiconductor package with improved signal characteristics is provided.

[0006] Furthermore, the implementation methods are not limited to the tasks described above, and other tasks can be clearly understood by those skilled in the art through the following description.

[0007] One aspect of this disclosure provides a semiconductor package comprising: a package substrate; at least one first semiconductor chip offset and stacked on the package substrate in a first direction; first semiconductor chip pads arranged to be spaced apart from each other in a second direction on the top surface of each of the at least one first semiconductor chip; at least one second semiconductor chip offset and stacked on the first semiconductor chip disposed at the uppermost end of the at least one first semiconductor chip in the first direction; second semiconductor chip pads arranged to be spaced apart from each other in a second direction on the top surface of each of the at least one second semiconductor chip; and a plurality of substrate pads arranged in two rows on the package substrate, wherein the second semiconductor chip disposed at the lowermost end of the at least one second semiconductor chip is offset and stacked on the first semiconductor chip disposed at the uppermost end in both the first and second directions.

[0008] Another aspect of this disclosure provides a semiconductor package, the semiconductor package comprising: a package substrate; a first chip stack structure including a plurality of first semiconductor chips offset and stacked on the package substrate in a first direction; first semiconductor chip pads arranged to be parallel to and spaced apart from each other in a second direction on the top surface of each of the plurality of first semiconductor chips; a second chip stack structure offset and stacked in a first direction and a second direction on the top surface of the first semiconductor chip disposed at the uppermost end of the plurality of first semiconductor chips, the second chip stack structure including a plurality of second semiconductor chips offset and stacked in the first direction; and second semiconductor chip pads arranged to be parallel to and spaced apart from each other in the plurality of second semiconductor chips. The top surfaces of the substrates are spaced apart from each other in a second direction; a plurality of substrate pads are arranged in a first row and a second row on the package substrate; conductive patterns connect a first semiconductor chip pad to a substrate pad and a second semiconductor chip pad to a substrate pad; and insulating patterns are disposed between the conductive patterns facing each other in a vertical direction, wherein the substrate pads are divided into ground / power substrate pads and signal substrate pads, and the plurality of substrate pads disposed in each of the first and second rows include alternating ground / power substrate pads and signal substrate pads, wherein when viewed from above in a vertical direction, the ground / power substrate pads face each other diagonally, and the signal substrate pads face each other diagonally when viewed from above in a vertical direction.

[0009] Another aspect of this disclosure provides a semiconductor package comprising: a package substrate; a first chip stack structure including a plurality of first semiconductor chips offset and stacked on the package substrate in a first direction; first semiconductor chip pads arranged parallel to and spaced apart from each other in a second direction on the top surface of each of the plurality of first semiconductor chips; a second chip stack structure offset and stacked in a first direction and a second direction on the top surface of the first semiconductor chip disposed at the uppermost end of the plurality of first semiconductor chips, the second chip stack structure including a plurality of second semiconductor chips offset and stacked in the first direction; second semiconductor chip pads arranged spaced apart from each other in a second direction on the top surface of each of the plurality of second semiconductor chips; a substrate pad arranged in a first row and a second row on the package substrate; and a conductive pattern connecting the first semiconductor chip pads to the substrate pads and connecting the second semiconductor chips... A pad is connected to a substrate pad; and an insulating pattern is disposed between conductive patterns facing each other in a vertical direction, wherein the substrate pad is divided into a ground / power substrate pad and a signal substrate pad, and a plurality of substrate pads disposed in each of the first and second rows include alternating ground / power substrate pads and signal substrate pads, wherein the ground / power substrate pads face each other diagonally when viewed from above in a vertical direction, and the signal substrate pads face each other diagonally when viewed from above in a vertical direction, and the conductive pattern includes alternating ground / power conductive patterns and signal conductive patterns, wherein the substrate pads disposed in the first row are superimposed on a first semiconductor chip pad in a first direction, the substrate pads disposed in the second row are superimposed on a second semiconductor chip pad in a first direction, and at least one of the substrate pads disposed in the first row is not superimposed on at least one of the substrate pads disposed in the second row in a first direction. Attached Figure Description

[0010] Figure 1 This is a perspective view that schematically illustrates an example of a semiconductor package.

[0011] Figure 2 It is shown schematically. Figure 1 A plan view of a semiconductor package.

[0012] Figure 3 It is shown schematically. Figure 1 A schematic diagram of the first and second substrate pads of a semiconductor package.

[0013] Figure 4 It is along Figure 2 The sectional view taken by line A1-A1'.

[0014] Figure 5 It is along Figure 2 The sectional view taken by line A2-A2'.

[0015] Figure 6 This is a plan view schematically showing an example of a semiconductor package.

[0016] Figure 7 It is along Figure 6 The sectional view taken by line B1-B1'.

[0017] Figure 8 It is along Figure 6 The sectional view taken by line B2-B2'.

[0018] Figure 9 This is a plan view schematically showing an example of a semiconductor package.

[0019] Figure 10 It is shown schematically. Figure 9 A side view of a semiconductor package.

[0020] Figure 11 This is a plan view schematically showing an example of a semiconductor package.

[0021] Figures 12 to 17 This is a plan view illustrating an example method of manufacturing a semiconductor package. Detailed Implementation

[0022] In the following description, embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions will be omitted.

[0023] Figure 1 This is a perspective view schematically showing a semiconductor package according to some embodiments. Figure 2 It is shown schematically. Figure 1 A plan view of a semiconductor package. Figure 3 It is shown schematically. Figure 1 A schematic diagram of the first and second substrate pads of a semiconductor package. Figure 4 It is along Figure 2 The sectional view taken by line A1-A1'. Figure 5 It is along Figure 2 The sectional view taken by line A2-A2'.

[0024] Reference Figures 1 to 5 The semiconductor package 10 may include a package substrate 100, a plurality of substrate pads 110_S and 110_G / P, a first chip stack structure 200, a second chip stack structure 300, and conductive patterns G / P_L and S_L.

[0025] The package substrate 100 may be disposed beneath the first chip stack structure 200 and electrically connected to each of the first chip stack structure 200 and the second chip stack structure 300. According to some embodiments, the package substrate 100 may be formed based on, for example, a ceramic substrate, a printed circuit board (PCB), an organic substrate, an intermediate substrate, etc. Furthermore, in some embodiments, the package substrate 100 may include a redistribution structure. In some embodiments, the package substrate 100 may include a body portion and wiring. Some portions of the wiring may be exposed on the bottom surface of the package substrate 100 to serve as bump pads for mounting external connection terminals thereon.

[0026] In the accompanying drawings, the X-axis and Y-axis directions indicate directions parallel to the top or bottom surface of the package substrate 100, and the X-axis and Y-axis directions may be perpendicular to each other. The Z-axis direction may indicate a direction perpendicular to the top or bottom surface of the package substrate 100. In other words, the Z-axis direction may be a direction perpendicular to the XY plane.

[0027] Furthermore, in the following figures, the first horizontal direction, the second horizontal direction, and the vertical direction can be understood as follows: the first horizontal direction can be understood as the X-axis direction, the second horizontal direction can be understood as the Y-axis direction, and the vertical direction can be understood as the Z-axis direction.

[0028] External connection terminals may be disposed on the lower surface of the package substrate 100. A first external connection terminal may be electrically connected to an external device (e.g., a motherboard, PCB, package substrate, etc.). The first external connection terminal may be electrically connected to a wiring pattern formed in the package substrate 100 via a bump pad attached to the bottom surface of the package substrate 100.

[0029] External connection terminals may include solder balls. However, according to some embodiments, external connection terminals may have a structure including posts and solder. External connection terminals may include at least one of copper (Cu), silver (Ag), gold (Au), and tin (Sb).

[0030] Substrate pads 110_S and 110_G / P may be disposed on the top surface of the package substrate 100. A plurality of substrate pads 110_S and 110_G / P may be provided, and in some embodiments, the plurality of substrate pads 110_S and 110_G / P may be arranged side-by-side in two rows on the package substrate 100. For example, the plurality of substrate pads 110_S and 110_G / P may be arranged in a first row and a second row. The first row may include substrate pads 110_S and 110_G / P adjacent to the first chip stack structure 200 and spaced apart from each other in a first horizontal direction X, and the second row may include substrate pads 110_S and 110_G / P spaced apart from the first row in a second horizontal direction Y and spaced apart from each other in the first horizontal direction X. The second row may be spaced apart from the first chip stack structure 200 in the second horizontal direction Y, with the first row positioned between the second row and the first chip stack structure 200.

[0031] According to some embodiments, the base pads 110_S and 110_G / P disposed in the first row may be spaced apart from each other by a first interval in the first horizontal direction X. The base pads 110_S and 110_G / P disposed in the second row may also be spaced apart from each other by a first interval in the first horizontal direction X.

[0032] According to some embodiments, the base pads 110_S and 110_G / P disposed in the first row and the base pads 110_S and 110_G / P disposed in the second row can be arranged to be staggered by a first interval, respectively. The base pads 110_S and 110_G / P disposed in the second row can be offset by a first interval relative to the base pads 110_S and 110_G / P disposed in the first row in a first horizontal direction X. Therefore, at least one of the base pads 110_S and 110_G / P disposed in the first row can be non-overlapping with the base pads 110_S and 110_G / P disposed in the second horizontal direction Y. Furthermore, at least one of the base pads 110_S and 110_G / P disposed in the second row can be non-overlapping with the base pads 110_S and 110_G / P disposed in the second horizontal direction Y.

[0033] According to some embodiments, among the base pads 110_S and 110_G / P disposed in the first row, the base pad 110_S and 110_G / P disposed at the outermost position in the first horizontal direction (e.g., +X direction) may not overlap with the base pads 110_S and 110_G / P disposed in the second horizontal direction Y. Among the base pads 110_S and 110_G / P disposed in the first row, each of the base pads 110_S and 110_G / P other than the base pad 110_S and 110_G / P disposed at the outermost position according to the positive first horizontal direction +X may overlap with a corresponding one of the base pads 110_S and 110_G / P disposed in the second horizontal direction Y.

[0034] According to some embodiments, among the base pads 110_S and 110_G / P disposed in the second row, the base pads 110_S and 110_G / P disposed on the outermost side in the negative first horizontal direction (e.g., -X direction) may not overlap with the base pads 110_S and 110_G / P disposed in the first row in the second horizontal direction Y. Among the base pads 110_S and 110_G / P disposed in the second row, each of the base pads 110_S and 110_G / P except for the base pads 110_S and 110_G / P disposed on the outermost side according to the negative first horizontal direction -X may overlap with a corresponding base pad 110_S and 110_G / P disposed in the first row in the second horizontal direction Y. Here, the positive first horizontal direction and the negative first horizontal direction can be understood as opposite directions. Furthermore, the first horizontal direction may represent the direction along which the base pads 110_S and 110_G / P in each of the first and second rows are arranged spaced apart from each other, and the second horizontal direction may represent the direction along which the first and second rows are spaced apart from each other.

[0035] According to some implementations, the substrate pads 110_S and 110_G / P can be divided into a ground / power substrate pad 110_G / P and a signal substrate pad 110_S. However, the substrate pads 110_S and 110_G / P can also include other types of substrate pads in addition to being divided into a ground / power substrate pad 110_G / P and a signal substrate pad 110_S.

[0036] According to some embodiments, the base pads 110_S and 110_G / P disposed in the first row may include alternating ground / power base pads 110_G / P and signal base pads 110_S. For example, as Figure 1 and Figure 2As shown, when the base pad located at the outermost position in the positive first horizontal direction +X in the first row is the ground / power base pad 110_G / P, the base pad adjacent to the ground / power base pad 110_G / P in the negative first horizontal direction -X in the first row can be the signal base pad 110_S.

[0037] According to some implementations, the base pads 110_S and 110_G / P disposed in the second row may include alternating ground / power base pads 110_G / P and signal base pads 110_S.

[0038] For example, such as Figure 1 and Figure 2 As shown, when the base pad located at the outermost position in the positive first horizontal direction +X in the second row is the ground / power base pad 110_G / P, the base pad adjacent to the ground / power base pad 110_G / P in the negative first horizontal direction -X in the second row can be the signal base pad 110_S.

[0039] According to some embodiments, the "base pads 110_S and 110_G / P disposed in the first row" and the "base pads 110_S and 110_G / P disposed in the second row" stacked on top of each other in the second horizontal direction Y can be different types of base pads 110_S and 110_G / P. For example, when either of the base pads 110_S and 110_G / P disposed in the first row is a ground / power base pad 110_G / P, the base pad disposed in the second row that is stacked with the base pad 110_G / P in the second horizontal direction Y can be a signal base pad 110_S.

[0040] According to some embodiments, one of the base pads 110_S and 110_G / P disposed in each of the first and second rows can be a base pad of a different type from the base pads 110_S and 110_G / P adjacent in at least one of the first horizontal direction X and the second horizontal direction Y. For example, when referring to Figure 2 When the base pad 110_S and 110_G / P on line A1-A1' is a ground / power base pad 110_G / P in the second row, the base pads set on both sides of the ground / power base pad 110_G / P in the first horizontal direction X and the base pads set on the first row that are superimposed on the ground / power base pad 110_G / P in the second horizontal direction Y can all be signal base pads 110_S.

[0041] According to some implementations, in the base pads 110_S and 110_G / P, such as Figure 3As shown, the signal substrate pad 110_S and the ground / power substrate pad 110_G / P can be arranged alternately in the first horizontal direction X and the second horizontal direction Y. The ground / power substrate pad 110_G / P can be arranged to surround the signal substrate pad 110_S, and the signal substrate pad 110_S can be arranged to surround the ground / power substrate pad 110_G / P.

[0042] Signal substrate pads 110_S can be disposed between ground / power substrate pads 110_G / P, and ground / power substrate pads 110_G / P can be disposed between signal substrate pads 110_S. When viewed from above in the vertical direction Z, ground / power substrate pads 110_G / P can face each other diagonally, and signal substrate pads 110_S can face each other diagonally. That is, when viewed from above in the vertical direction Z, the ground / power substrate pads 110_G / P disposed in the first row and the ground / power substrate pads 110_G / P disposed in the second row can face each other diagonally, and the signal substrate pads 110_S disposed in the first row and the signal substrate pads 110_S disposed in the second row can face each other diagonally.

[0043] In some embodiments, the ground / power substrate pads 110_G / P may not overlap each other in the first direction. Furthermore, the signal substrate pads 110_S may not overlap each other in the first direction.

[0044] A first chip stack structure 200 may be disposed on a package substrate 100. The first chip stack structure 200 may be positioned on the package substrate 100 at a predetermined distance from the substrate pads 110_S and 110_G / P. According to some embodiments, the first chip stack structure 200 may be spaced apart from the substrate pads 110_S and 110_G / P disposed in a second row in a second horizontal direction Y, with the substrate pads 110_S and 110_G / P disposed in the first row positioned between the first chip stack structure 200 and the substrate pads 110_S and 110_G / P disposed in the second row.

[0045] The first chip stack structure 200 may include a first semiconductor chip 210 and a first semiconductor chip pad 220. The first chip stack structure 200 may include at least one first semiconductor chip 210. According to some embodiments, the first chip stack structure 200 may include multiple first semiconductor chips 210. For example, as... Figure 1As shown, the first chip stack structure 200 may include two first semiconductor chips 210. However, the number of first semiconductor chips 210 is not limited to this. Multiple first semiconductor chips 210 may be stacked offset in a first direction. Therefore, the first chip stack structure 200 may have a structure in which multiple first semiconductor chips 210 are stacked offset in a first direction. In other words, the first chip stack structure 200 may be a structure in which multiple first semiconductor chips 210 are stacked in a cascade type (i.e., stepped type) in a first direction. Here, the first direction may be the same as the direction along which the first row and the second row are spaced apart from each other. For example, the first direction may be the same as the second horizontal direction Y. However, the first direction is not limited to this, and the first direction may be various directions such as the first horizontal direction X.

[0046] According to some embodiments, each of the first semiconductor chips 210 may be arranged such that a surface adjacent to the passive surface of the semiconductor substrate faces the package substrate 100. That is, the bottom surface of each of the first semiconductor chips 210 may be a surface close to the passive surface of the semiconductor substrate, and the top surface of each of the first semiconductor chips 210 may be a surface close to the active surface of the semiconductor substrate.

[0047] An adhesive layer 150 may be disposed on the bottom surface of each of the first semiconductor chips 210. The adhesive layer 150 may be a film having its own adhesive properties. For example, the adhesive layer 150 may be a double-sided adhesive film. In some embodiments, the adhesive layer 150 may be a strip material layer, a liquid-phase coated curable material layer, or a combination thereof. Furthermore, the adhesive layer 150 may include a thermosetting structure, a thermoplastic structure, a UV-curable material, or a combination thereof. The adhesive layer 150 may be referred to as a die-attach film (DAF) or a non-conductive film (NCF).

[0048] Because the first semiconductor chips 210 of the first chip stack structure 200 are stacked in a stepped manner in the first direction, a portion of the top surface of each of the first semiconductor chips 210 is exposed. That is, each of the first semiconductor chips 210 may have a portion of its top surface that is not covered by another first semiconductor chip 210 directly stacked on its top surface. When the first semiconductor chips 210 are stacked in a stepped manner in the first direction, the portion of the top surface of the first semiconductor chip 210 in the direction opposite to the first direction may be exposed upwards.

[0049] A first semiconductor chip pad 220 may be disposed on the top surface of each of the first semiconductor chips 210. According to some embodiments, the first semiconductor chip pad 220 may be disposed on an area where a portion of the top surface of each of the first semiconductor chips 210 is exposed upwards. According to some embodiments, a plurality of first semiconductor chip pads 220 may be provided. Each of the first semiconductor chip pads 220 may be disposed on the exposed upwardly surface of the top surface of each of the plurality of first semiconductor chips 210. According to some embodiments, a plurality of first semiconductor chip pads 220 may be disposed on the top surface of the first semiconductor chip 210, respectively. According to some embodiments, the first semiconductor chip pads 220 may be arranged side-by-side on the top surface of the first semiconductor chip 210 in a first horizontal direction X. According to some embodiments, the first semiconductor chip pads 220 may be spaced apart from each other by a first interval.

[0050] According to some embodiments, a first semiconductor chip pad 220 (e.g., the vertical projection of the first semiconductor chip pad 220) can be stacked in the second horizontal direction Y with substrate pads 110_S and 110_G / P (e.g., the vertical projections of substrate pads 110_S and 110_G / P in the first row) disposed in the first row. In some embodiments, a first semiconductor chip pad 220 disposed on a first semiconductor chip 210 can correspond one-to-one with substrate pads 110_S and 110_G / P disposed in the first row, and the corresponding first semiconductor chip pad 220 and substrate pads 110_S and 110_G / P (e.g., the vertical projections of the corresponding first semiconductor chip pad 220 and substrate pads 110_S and 110_G / P) can be stacked on top of each other in the second horizontal direction Y.

[0051] At least one of the first semiconductor chip pads 220 (e.g., the vertical projection of at least one of the first semiconductor chip pads 220) may not overlap with all of the base pads 110_S and 110_G / P disposed in the second row (e.g., the vertical projection of all of the base pads 110_S and 110_G / P disposed in the second row) in the second horizontal direction Y.

[0052] According to some embodiments, a first semiconductor chip 210 included in the first chip stack structure 200 may form a first channel. Furthermore, a second semiconductor chip 310 included in the second chip stack structure 300 may form a second channel. The first channel and the second channel can operate independently.

[0053] According to some embodiments, the first semiconductor chip 210 may be a memory chip or a logic chip. The memory chip may be, for example, a volatile memory chip (such as dynamic random access memory (DRAM) or static random access memory (SRAM)), or a non-volatile memory chip (such as phase-change RAM (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FeRAM), or resistive RAM (RRAM)). Furthermore, the logic chip may be, for example, a microprocessor (such as a central processing unit (CPU), graphics processing unit (GPU), or application processor (AP)), an analog device, or a digital signal processor.

[0054] In some implementations, the first semiconductor chip 210 may be a NAND flash memory chip. In this case, the first chip stack structure 200 can be understood as a structure in which multiple NAND flash memory chips are stacked offset in a first direction.

[0055] The second chip stack structure 300 may be stacked on the first chip stack structure 200. The second chip stack structure 300 may be stacked on the first chip stack structure 200 with an upward offset in each of the first and second directions.

[0056] Specifically, the second chip stack structure 300 may be stacked on the top surface of the first semiconductor chip 210 disposed at the uppermost end of the first chip stack structure 200. The second chip stack structure 300 may include at least one second semiconductor chip 310. According to some embodiments, the second chip stack structure 300 may include multiple second semiconductor chips 310. Figure 1 As shown, the second chip stack structure 300 may include two second semiconductor chips 310. However, the number of second semiconductor chips 310 is not limited to this.

[0057] The second semiconductor chip 310, located at the bottommost end, can be offset and stacked on the top surface of the first chip stack structure 200 in each of a first direction and a second direction. Here, the first direction can be the direction along which the first semiconductor chip 210 is offset and stacked, and the second direction can be a direction perpendicular to the first direction. According to some embodiments, the second direction can be a negative first horizontal direction -X.

[0058] Multiple second semiconductor chips 310 may be stacked offset in the first direction. In other words, multiple second semiconductor chips 310 may be stacked in a cascaded (i.e., stepped) manner in the first direction.

[0059] The second semiconductor chip 310 disposed at the bottom of the second chip stack structure 300 can be offset and stacked on the first semiconductor chip 210 disposed at the top of the first chip stack structure 200 in a first direction and a second direction, and the second semiconductor chip 310 disposed on the bottom of the second semiconductor chip 310 in the second chip stack structure 300 can be offset and stacked on the bottommost second semiconductor chip 310 in a first direction.

[0060] Because the second semiconductor chips 310 of the second chip stack structure 300 are stacked in a stepped manner in the first direction, a portion of the top surface of each of the second semiconductor chips 310 is exposed. That is, each of the second semiconductor chips 310 may have a portion of its top surface that is not covered by another second semiconductor chip 310 directly stacked on its top surface. When the second semiconductor chips 310 are stacked in a stepped manner in the first direction, the portion of the top surface of the second semiconductor chip 310 in the direction opposite to the first direction may be exposed upwards.

[0061] The adhesive layer 150 may be disposed on the bottom surface of each of the second semiconductor chips 310. The adhesive layer 150 may be substantially the same as the adhesive layer 150 disposed on the bottom surface of each of the first semiconductor chips 210.

[0062] A second semiconductor chip pad 320 may be disposed on the top surface of each of the second semiconductor chips 310. According to some embodiments, the second semiconductor chip pad 320 may be disposed on an upwardly exposed portion of the top surface of each of the second semiconductor chips 310. According to some embodiments, a plurality of second semiconductor chip pads 320 may be provided. Each of the second semiconductor chip pads 320 may be disposed on an upwardly exposed portion of the top surface of each of the plurality of second semiconductor chips 310. According to some embodiments, a plurality of second semiconductor chip pads 320 may be disposed on the top surface of the second semiconductor chip 310 respectively. According to some embodiments, the second semiconductor chip pads 320 may be arranged side-by-side on the top surface of the second semiconductor chip 310 in a first horizontal direction X. According to some embodiments, the second semiconductor chip pads 320 may be spaced apart from each other by a first interval.

[0063] According to some embodiments, the second semiconductor chip pad 320 (e.g., the vertical projection of the second semiconductor chip pad 320) can be stacked in the second horizontal direction Y with the base pads 110_S and 110_G / P (e.g., the vertical projections of the base pads 110_S and 110_G / P in the second row) disposed in the second row. In some embodiments, the second semiconductor chip pad 320 disposed on a second semiconductor chip 310 can correspond one-to-one with the base pads 110_S and 110_G / P disposed in the second row, and the corresponding second semiconductor chip pad 320 and the base pads 110_S and 110_G / P (e.g., the vertical projections of the corresponding second semiconductor chip pad 320 and the base pads 110_S and 110_G / P) can be stacked on top of each other in the second horizontal direction Y.

[0064] Therefore, the first semiconductor chip pad 220 arranged in a row on the first semiconductor chip 210 can correspond to the substrate pads 110_S and 110_G / P disposed in the first row in the second horizontal direction Y, and the second semiconductor chip pad 320 arranged in a row on the second semiconductor chip 310 can correspond to the substrate pads 110_S and 110_G / P disposed in the second row in the second horizontal direction Y.

[0065] At least one of the second semiconductor chip pads 320 (e.g., the vertical projection of at least one of the second semiconductor chip pads 320) may not overlap with all of the base pads 110_S and 110_G / P disposed in the first row (e.g., the vertical projection of all of the base pads 110_S and 110_G / P disposed in the first row) in the second horizontal direction Y.

[0066] According to some embodiments, a second semiconductor chip 310 included in the second chip stack structure 300 may form a second channel. The second channel may operate independently of the first channel.

[0067] According to some embodiments, the second semiconductor chip 310 may be a memory chip or a logic chip. The memory chip may be, for example, a volatile memory chip (such as dynamic random access memory (DRAM) or static random access memory (SRAM)), or a non-volatile memory chip (such as phase-change RAM (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FeRAM), or resistive RAM (RRAM)). Furthermore, the logic chip may be, for example, a microprocessor (such as a central processing unit (CPU), graphics processing unit (GPU), or application processor (AP)), an analog device, or a digital signal processor.

[0068] In some implementations, the second semiconductor chip 310 may be a NAND flash memory chip. In this case, the second chip stack structure 300 can be understood as a structure in which multiple NAND flash memory chips are stacked offset in a first direction.

[0069] According to some implementations, the second semiconductor chip 310 may be a chip of the same type as the first semiconductor chip 210, but is not limited thereto, and the second semiconductor chip 310 and the first semiconductor chip 210 may be chips of different types.

[0070] The conductive patterns G / P_L and S_L can be configured to electrically connect the first semiconductor chip pad 220 to the substrate pads 110_S and 110_G / P, and to electrically connect the second semiconductor chip pad 320 to the substrate pads 110_S and 110_G / P. According to some embodiments, the conductive patterns G / P_L and S_L connecting the first semiconductor chip pad 220 to the substrate pads 110_S and 110_G / P can be formed on the insulating block 170. Furthermore, portions of the conductive patterns G / P_L and S_L connecting the second semiconductor chip pad 320 to the substrate pads 110_S and 110_G / P that do not overlap with the insulating pattern I_L in the vertical direction can be provided on the insulating block 170.

[0071] The insulating block 170 can have a right-angled triangular shape in its cross-section on the YZ plane. The conductive patterns G / P_L and S_L can have a tilted but not bent shape in their cross-section on the YZ plane through the insulating block 170. Furthermore, the lengths of the conductive patterns G / P_L and S_L can be reduced through the insulating block 170.

[0072] The conductive pattern can be divided into a ground / power conductive pattern G / P_L and a signal conductive pattern S_L. The ground / power conductive pattern G / P_L electrically connects the ground / power substrate 110_G / P to the first semiconductor chip pad 220 and to the second semiconductor chip pad 320. The signal conductive pattern S_L electrically connects the signal substrate 110_S to the first semiconductor chip pad 220 and to the second semiconductor chip pad 320.

[0073] According to some embodiments, when viewed from above in the vertical Z direction, the conductive patterns G / P_L and S_L may extend in the first direction. Furthermore, the conductive patterns G / P_L and S_L may have a stepped shape in a cross-section on the YZ plane.

[0074] The conductive patterns G / P_L and S_L connecting the first semiconductor chip pad 220 to the substrate pads 110_S and 110_G / P can cover at least some portions of the top surface of the first semiconductor chip 210 and at least some portions of the top surface of the package substrate 100.

[0075] The conductive patterns G / P_L and S_L connecting the second semiconductor chip pad 320 to the substrate pads 110_S and 110_G / P can cover at least some portions of the top surface of the second semiconductor chip 310, the insulating pattern I_L, and at least a portion of the top surface of the package substrate 100.

[0076] The insulating pattern I_L can be configured to insulate between the conductive patterns G / P_L and S_L connecting the first semiconductor chip pad 220 to the substrate pads 110_S and 110_G / P, and the conductive patterns G / P_L and S_L connecting the second semiconductor chip pad 320 to the substrate pads 110_S and 110_G / P. The conductive patterns G / P_L and S_L, spaced apart from each other in the vertical direction Z and with the insulating pattern I_L positioned between them, can be different types of conductive patterns G / P_L and S_L. For example, one of the conductive patterns G / P_L and S_L, spaced apart in the vertical direction Z and with the insulating pattern I_L positioned between them, can be a ground / power supply conductive pattern G / P_L, and the other can be a signal conductive pattern S_L.

[0077] Multiple conductive patterns G / P_L and S_L, as well as multiple insulating patterns I_L, can be configured. For example, as... Figure 1 As shown, when the conductive patterns G / P_L and S_L, the insulating pattern I_L, and the pattern formed by the accumulation of conductive patterns G / P_L and S_L in the vertical direction Z are defined as a bundle pattern, multiple bundle patterns are arranged, and these bundle patterns can be arranged to be spaced apart from each other in a second direction. The second direction can be perpendicular to the first direction, and according to some embodiments, the second direction can be a first horizontal direction X. The structures of adjacent bundle patterns can be different from each other. For example, any bundle pattern can have a structure in which the ground / power conductive pattern G / P_L, the insulating pattern I_L, and the signal conductive pattern S_L are sequentially stacked in the vertical direction Z, and another bundle pattern adjacent to this bundle pattern can have a structure in which the signal conductive pattern S_L, the insulating pattern I_L, and the ground / power conductive pattern G / P_L are sequentially stacked in the vertical direction Z.

[0078] The first semiconductor chip pad 220 can be electrically connected to the substrate pads 110_S and 110_G / P disposed in the first row via conductive patterns G / P_L and S_L. Specifically, among the first semiconductor chip pads 220, the first semiconductor chip pad 220 connected to the ground / power substrate pad 110_G / P can be electrically connected to the ground / power conductive pattern G / P_L. The ground / power conductive pattern G / P_L can be electrically connected to the first semiconductor chip pad 220 that is superimposed on the ground / power substrate pad 110_G / P in the second horizontal direction Y. Furthermore, among the first semiconductor chip pads 220, the first semiconductor chip pad 220 connected to the signal substrate pad 110_S can be electrically connected to the signal conductive pattern S_L. The signal conductive pattern S_L can be electrically connected to the first semiconductor chip pad 220 that is superimposed on the signal substrate pad 110_S in the second horizontal direction Y.

[0079] Since the substrate pads 110_S and 110_G / P in the first row are arranged such that the ground / power substrate pad 110_G / P and the signal substrate pad 110_S are alternately arranged at a first interval in the second direction, the conductive patterns G / P_L and S_L that connect the first semiconductor chip pad 220 to the substrate pads 110_S and 110_G / P in the first row can also be arranged alternately, while the ground / power conductive pattern G / P_L and the signal conductive pattern S_L are spaced apart from each other at a first interval in the second direction.

[0080] The second semiconductor chip pad 320 can be electrically connected to the substrate pads 110_S and 110_G / P disposed in the second row via conductive patterns G / P_L and S_L. Specifically, among the second semiconductor chip pads 320, the second semiconductor chip pad 320 connected to the ground / power substrate pad 110_G / P can be electrically connected to the ground / power conductive pattern G / P_L. The ground / power conductive pattern G / P_L can be electrically connected to the second semiconductor chip pad 320 that overlaps with the ground / power substrate pad 110_G / P in the second horizontal direction Y. Furthermore, among the second semiconductor chip pads 320, the second semiconductor chip pad 320 connected to the signal substrate pad 110_S can be electrically connected to the signal conductive pattern S_L. The signal conductive pattern S_L can be electrically connected to the second semiconductor chip pad 320 that overlaps with the signal substrate pad 110_S in the second horizontal direction Y.

[0081] Since the substrate pads 110_S and 110_G / P in the second row are arranged such that the ground / power substrate pad 110_G / P and the signal substrate pad 110_S are alternately arranged at a first interval in the second direction, the conductive patterns G / P_L and S_L that connect the second semiconductor chip pad 320 to the substrate pads 110_S and 110_G / P in the second row can also be arranged alternately, while the ground / power conductive pattern G / P_L and the signal conductive pattern S_L are spaced apart from each other at a first interval in the second direction.

[0082] Therefore, the grounding / power supply conductive pattern G / P_L can be disposed on both sides of the signal conductive pattern S_L in the first horizontal direction X and on the side of the signal conductive pattern S_L in the vertical direction Z, and the signal conductive pattern S_L can be disposed on both sides of the grounding / power supply conductive pattern G / P_L in the first horizontal direction X and on the side of the grounding / power supply conductive pattern G / P_L in the vertical direction Z.

[0083] In the semiconductor package 10 according to the inventive concept, a ground / power substrate 110_G / P may surround a signal substrate 110_S, and a ground / power conductive pattern G / P_L may surround a signal conductive pattern S_L. Therefore, signal interference between the signal substrates 110_S and / or between the signal conductive patterns S_L can be minimized, and the signal return path can be more robustly formed at a closer distance, thereby reducing loop inductance. As a result, noise or distortion that may occur during signal transmission between the signal substrates 110_S and the signal conductive patterns S_L can be reduced, and thus signal integrity can be improved even in high-speed signals.

[0084] Figure 6 This is a schematic plan view of a semiconductor package according to some embodiments. Figure 7 It is along Figure 6 The sectional view taken by line B1-B1'. Figure 8 It is along Figure 6 The sectional view taken along line B2-B2'. In the following text, references are omitted. Figures 1 to 5 The descriptions contain redundant and overlapping content, and primarily focus on the differences.

[0085] Reference Figures 6 to 8 The semiconductor package 20 may include a package substrate 100, a first chip stack structure 201, a second chip stack structure 301, and conductive patterns G / P_L and S_L.

[0086] The packaging substrate 100 may be disposed below the first chip stack structure 201 and may be electrically connected to each of the first chip stack structure 201 and the second chip stack structure 301.

[0087] Substrate pads 110_S and 110_G / P may be disposed on the top surface of the package substrate 100. A plurality of substrate pads 110_S and 110_G / P may be disposed, and in some embodiments, the plurality of substrate pads 110_S and 110_G / P may be arranged side by side in two rows on the package substrate 100.

[0088] For example, multiple substrate pads 110_S and 110_G / P may be arranged in a first row and a second row. The first row may include substrate pads 110_S and 110_G / P that are adjacent to the first chip stack structure 201 and spaced apart from each other in a first horizontal direction X, and the second row may include substrate pads 110_S and 110_G / P that are spaced apart from the first row in a second horizontal direction Y and spaced apart from each other in the first horizontal direction X. The second row may be spaced apart from the first chip stack structure 201 in the second horizontal direction Y, with the first row positioned between the second row and the first chip stack structure 201.

[0089] According to some embodiments, the base pads 110_S and 110_G / P disposed in the first row may be spaced apart from each other by a first interval in the first horizontal direction X. The base pads 110_S and 110_G / P disposed in the second row may also be spaced apart from each other by a first interval in the first horizontal direction X.

[0090] According to some embodiments, the base pads 110_S and 110_G / P disposed in the first row and the base pads 110_S and 110_G / P disposed in the second row can be arranged to be staggered by a first interval, respectively. The base pads 110_S and 110_G / P disposed in the second row can be offset by a first interval relative to the base pads 110_S and 110_G / P disposed in the first row in a first horizontal direction X.

[0091] According to some embodiments, among the base pads 110_S and 110_G / P disposed in the first row, the base pad 110_S and 110_G / P disposed at the outermost position in the first horizontal direction (e.g., +X direction) may not overlap with the base pads 110_S and 110_G / P disposed in the second horizontal direction Y. Among the base pads 110_S and 110_G / P disposed in the first row, each of the base pads 110_S and 110_G / P other than the base pad 110_S and 110_G / P disposed at the outermost position according to the positive first horizontal direction +X may overlap with a corresponding one of the base pads 110_S and 110_G / P disposed in the second horizontal direction Y.

[0092] According to some embodiments, the base pads 110_S and 110_G / P may be divided into a ground / power base pad 110_G / P and a signal base pad 110_S. According to some embodiments, the base pads 110_S and 110_G / P disposed in the first row may include alternating ground / power base pads 110_G / P and signal base pads 110_S.

[0093] According to some embodiments, the "base pads 110_S and 110_G / P disposed in the first row" and "base pads 110_S and 110_G / P disposed in the second row" stacked on top of each other in the second horizontal direction Y can be base pads 110_S and 110_G / P of different types. For example, when any one of the base pads 110_S and 110_G / P disposed in the first row is a ground / power base pad 110_G / P, the base pad disposed in the second row that is stacked with the base pad 110_G / P in the second horizontal direction Y can be a signal base pad 110_S. According to some embodiments, one of the base pads 110_S and 110_G / P disposed in each of the first and second rows can be a base pad of a different type from the base pads 110_S and 110_G / P adjacent to at least one of the base pads 110_S and 110_G / P in at least one of the first horizontal direction X and the second horizontal direction Y.

[0094] A first chip stack structure 201 may be disposed on a package substrate 100. The first chip stack structure 201 may be positioned on the package substrate 100 at a predetermined distance from the substrate pads 110_S and 110_G / P. According to some embodiments, the first chip stack structure 201 may be spaced apart from the substrate pads 110_S and 110_G / P disposed in a second row in a second horizontal direction Y, with the substrate pads 110_S and 110_G / P disposed in the first row positioned between the first chip stack structure 201 and the substrate pads 110_S and 110_G / P disposed in the second row.

[0095] The first chip stack structure 201 may include a first semiconductor chip 210 and a first semiconductor chip pad 220. The first chip stack structure 201 may include four first semiconductor chips 210. The four first semiconductor chips 210 may be stacked offset in a first direction, and the first semiconductor chip pad 220 may be disposed on the top surface of each of the four first semiconductor chips 210. An adhesive layer 150 may be disposed on the bottom surface of each of the first semiconductor chips 210.

[0096] The second semiconductor chip 310 disposed at the bottom of the second chip stack structure 301 can be offset and stacked on the first semiconductor chip 210 disposed at the top of the first chip stack structure 201 in a first direction and a second direction. Furthermore, another second semiconductor chip 310 disposed on the second semiconductor chip 310 disposed at the bottom of the second chip stack structure 301 can be offset and stacked on the second semiconductor chip 210 disposed at the bottom of the second chip stack structure 301 in a first direction.

[0097] Because the second semiconductor chips 310 of the second chip stack structure 301 are stacked in a stepped manner in the first direction, a portion of the top surface of each of the second semiconductor chips 310 is exposed. That is, each of the second semiconductor chips 310 may have a portion of its top surface that is not covered by another second semiconductor chip 310 directly stacked on its top surface. When the second semiconductor chips 310 are stacked in a stepped manner in the first direction, the portion of the top surface of the second semiconductor chip 310 in the direction opposite to the first direction may be exposed upwards.

[0098] The second chip stack structure 301 may include four second semiconductor chips 310. An adhesive layer 150 may be disposed on the bottom surface of each of the second semiconductor chips 310. The adhesive layer 150 may be substantially the same as the adhesive layer 150 disposed on the bottom surface of each of the first semiconductor chips 210.

[0099] The second semiconductor chip pad 320 may be disposed on the top surface of each of the second semiconductor chips 310. According to some embodiments, the second semiconductor chip pad 320 may be disposed on an area in which a portion of the top surface of each of the second semiconductor chips 310 is exposed upward.

[0100] Conductive patterns G / P_L and S_L can be configured to electrically connect the first semiconductor chip pad 220 to the substrate pads 110_S and 110_G / P, and to electrically connect the second semiconductor chip pad 320 to the substrate pads 110_S and 110_G / P. The conductive patterns can be divided into a ground / power conductive pattern G / P_L and a signal conductive pattern S_L. The ground / power conductive pattern G / P_L electrically connects the ground / power substrate pad 110_G / P to the first semiconductor chip pad 220, and also electrically connects the ground / power substrate pad 110_G / P to the second semiconductor chip pad 320. The signal conductive pattern S_L electrically connects the signal substrate pad 110_S to the first semiconductor chip pad 220, and also electrically connects the signal substrate pad 110_S to the second semiconductor chip pad 320.

[0101] According to some embodiments, when viewed from above in the vertical Z direction, the conductive patterns G / P_L and S_L may extend in the first direction. Furthermore, the conductive patterns G / P_L and S_L may have a stepped shape in a cross-section on the YZ plane.

[0102] The conductive patterns G / P_L and S_L connecting the first semiconductor chip pad 220 to the substrate pads 110_S and 110_G / P can cover at least some portions of the top surface of the first semiconductor chip 210 and at least some portions of the top surface of the package substrate 100.

[0103] The conductive patterns G / P_L and S_L connecting the second semiconductor chip pad 320 to the substrate pads 110_S and 110_G / P can cover at least some portions of the top surface of the second semiconductor chip 310, the insulating pattern I_L, and at least a portion of the top surface of the package substrate 100.

[0104] The insulating pattern I_L can be configured to insulate between the conductive patterns G / P_L and S_L connecting the first semiconductor chip pad 220 to the substrate pads 110_S and 110_G / P, and the conductive patterns G / P_L and S_L connecting the second semiconductor chip pad 320 to the substrate pads 110_S and 110_G / P. The conductive patterns G / P_L and S_L, spaced apart from each other in the vertical direction Z and with the insulating pattern I_L positioned between them, can be different types of conductive patterns G / P_L and S_L. For example, one of the conductive patterns G / P_L and S_L, spaced apart in the vertical direction Z and with the insulating pattern I_L positioned between them, can be a ground / power supply conductive pattern G / P_L, and the other can be a signal conductive pattern S_L.

[0105] Multiple conductive patterns G / P_L and S_L, as well as multiple insulating patterns I_L, can be configured. For example, as... Figures 6 to 8 As shown, when the conductive patterns G / P_L and S_L, the insulating pattern I_L, and the pattern formed by the accumulation of conductive patterns G / P_L and S_L in the vertical direction Z are defined as a bundle pattern, multiple bundle patterns are arranged, and the multiple bundle patterns can be arranged to be spaced apart from each other in a second direction. The second direction can be perpendicular to the first direction, and according to some embodiments, the second direction can be a first horizontal direction X. The structures of adjacent bundle patterns can be different from each other. For example, any bundle pattern can have a structure in which the ground / power conductive pattern G / P_L, the insulating pattern I_L, and the signal conductive pattern S_L are sequentially stacked in the vertical direction Z, and another bundle pattern adjacent to this bundle pattern can have a structure in which the signal conductive pattern S_L, the insulating pattern I_L, and the ground / power conductive pattern G / P_L are sequentially stacked in the vertical direction Z.

[0106] The grounding / power supply conductive pattern G / P_L can be disposed on both sides of the signal conductive pattern S_L in the first horizontal direction X and on the side of the signal conductive pattern S_L in the vertical direction Z, and the signal conductive pattern S_L can be disposed on both sides of the grounding / power supply conductive pattern G / P_L in the first horizontal direction X and on the side of the grounding / power supply conductive pattern G / P_L in the vertical direction Z.

[0107] Figure 9 This is a schematic plan view of a semiconductor package according to some embodiments. Figure 10 It is shown schematically. Figure 9 A side view of a semiconductor package. (In the following text, references are omitted.) Figures 1 to 8 The descriptions overlap, but the main focus is on the differences.

[0108] Reference Figure 9 and Figure 10 The semiconductor package 11 may include a package substrate 100, a first chip stack structure 200, a second chip stack structure 300, and conductive patterns G / P_L and S_L.

[0109] The packaging substrate 100 may be disposed below the first chip stack structure 200 and may be electrically connected to each of the first chip stack structure 200 and the second chip stack structure 300.

[0110] Substrate pads 110_S and 110_G / P may be disposed on the top surface of the package substrate 100. A plurality of substrate pads 110_S and 110_G / P may be disposed, and in some embodiments, the plurality of substrate pads 110_S and 110_G / P may be arranged side by side in two rows on the package substrate 100.

[0111] A first chip stack structure 200 may be disposed on a package substrate 100. The first chip stack structure 200 may be positioned on the package substrate 100 at a predetermined distance from the substrate pads 110_S and 110_G / P. According to some embodiments, the first chip stack structure 200 may be spaced apart from the substrate pads 110_S and 110_G / P disposed in a second row in a second horizontal direction Y, with the substrate pads 110_S and 110_G / P disposed in the first row positioned between the first chip stack structure 200 and the substrate pads 110_S and 110_G / P disposed in the second row.

[0112] The first chip stack structure 200 may include a first semiconductor chip 210 and a first semiconductor chip pad 220. According to some embodiments, a plurality of first semiconductor chips 210 may be disposed. The plurality of first semiconductor chips 210 may be offset and stacked in a first direction. The second semiconductor chip 310 disposed at the bottom of the second chip stack structure 300 may be offset and stacked on the first semiconductor chip 210 disposed at the top of the first chip stack structure 200 in a first and second direction, and another second semiconductor chip 310 disposed on the second semiconductor chip 310 disposed at the bottom of the second chip stack structure 300 may be offset and stacked on the second semiconductor chip 310 disposed at the bottom of the second chip stack structure 300 in a first direction.

[0113] Because the second semiconductor chips 310 of the second chip stack structure 300 are stacked in a stepped manner in the first direction, a portion of the top surface of each of the second semiconductor chips 310 is exposed. That is, each of the second semiconductor chips 310 may have a portion of its top surface that is not covered by another second semiconductor chip 310 directly stacked on its top surface. When the second semiconductor chips 310 are stacked in a stepped manner in the first direction, the portion of the top surface of the second semiconductor chip 310 in the direction opposite to the first direction may be exposed upwards.

[0114] The second chip stack structure 300 may include a plurality of second semiconductor chips 310. An adhesive layer 150 may be disposed on the bottom surface of each of the second semiconductor chips 310. The adhesive layer 150 may be substantially the same as the adhesive layer 150 disposed on the bottom surface of each of the first semiconductor chips 210.

[0115] The second semiconductor chip pad 320 may be disposed on the top surface of each of the second semiconductor chips 310. According to some embodiments, the second semiconductor chip pad 320 may be disposed on an area in which a portion of the top surface of each of the second semiconductor chips 310 is exposed upward.

[0116] According to some embodiments, a support member 400 may be disposed between the bottommost second semiconductor chip 310 and the package substrate 100. The support member 400 may be configured to support the bottommost second semiconductor chip 310 on the top surface of the package substrate 100. The support member 400 may be configured to support the surface exposed from the first semiconductor chip 210 on the bottom surface of the bottommost second semiconductor chip 310. The bottommost second semiconductor chip 310 may be offset from the topmost first semiconductor chip 210 in each of a first and second direction. In this case, the support member 400 may be disposed on the second direction side of the first semiconductor chip 210. When viewed from above in the vertical direction Z, the support member 400 may be completely covered by the second chip stack structure 300. In some embodiments, the support member 400 may include a silicon dummy. Since the support member 400 supports the bottom surface of the bottommost second semiconductor chip 310, the structural stability of the offset stacked second semiconductor chips 310 may be improved. Furthermore, since the support member 400 is shielded by the second chip stack structure 300, the dimensions of the semiconductor package 11 may be maintained.

[0117] Figure 11 This is a schematic plan view of a semiconductor package according to some embodiments. In the following text, references are omitted. Figures 1 to 10 The descriptions overlap, but the main focus is on the differences.

[0118] Reference Figure 11 The semiconductor package 12 may include a package substrate 100, a first chip stack structure 200, a second chip stack structure 300, and conductive patterns G / P_L and S_L.

[0119] The packaging substrate 100 may be disposed below the first chip stack structure 200 and may be electrically connected to each of the first chip stack structure 200 and the second chip stack structure 300.

[0120] Substrate pads 110_S and 110_G / P may be disposed on the top surface of the package substrate 100. A plurality of substrate pads 110_S and 110_G / P may be disposed, and in some embodiments, the plurality of substrate pads 110_S and 110_G / P may be arranged side by side in two rows on the package substrate 100.

[0121] A first chip stack structure 200 may be disposed on a package substrate 100. The first chip stack structure 200 may be positioned on the package substrate 100 at a predetermined distance from the substrate pads 110_S and 110_G / P. According to some embodiments, the first chip stack structure 200 may be spaced apart from the substrate pads 110_S and 110_G / P disposed in a second row in a second horizontal direction Y, with the substrate pads 110_S and 110_G / P disposed in the first row positioned between the first chip stack structure 200 and the substrate pads 110_S and 110_G / P disposed in the second row.

[0122] The first chip stack structure 200 may include a first semiconductor chip 210 and a first semiconductor chip pad 220. According to some embodiments, a plurality of first semiconductor chips 210 may be disposed. The plurality of first semiconductor chips 210 may be offset and stacked in a first direction. The second semiconductor chip 310 disposed at the bottom of the second chip stack structure 300 may be offset and stacked on the first semiconductor chip 210 disposed at the top of the first chip stack structure 200 in a first and second direction, and another second semiconductor chip 310 disposed on the second semiconductor chip 310 disposed at the bottom of the second chip stack structure 300 may be offset and stacked on the second semiconductor chip 310 disposed at the bottom of the second chip stack structure 300 in a first direction.

[0123] Because the second semiconductor chips 310 of the second chip stack structure 300 are stacked in a stepped manner in the first direction, a portion of the top surface of each of the second semiconductor chips 310 is exposed. That is, each of the second semiconductor chips 310 may have a portion of its top surface that is not covered by another second semiconductor chip 310 directly stacked on its top surface. When the second semiconductor chips 310 are stacked in a stepped manner in the first direction, the portion of the top surface of the second semiconductor chip 310 in the direction opposite to the first direction may be exposed upwards.

[0124] The second chip stack structure 300 may include a plurality of second semiconductor chips 310. An adhesive layer 150 may be disposed on the bottom surface of each of the second semiconductor chips 310. The adhesive layer 150 may be substantially the same as the adhesive layer 150 disposed on the bottom surface of each of the first semiconductor chips 210.

[0125] The second semiconductor chip pad 320 may be disposed on the top surface of each of the second semiconductor chips 310. According to some embodiments, the second semiconductor chip pad 320 may be disposed on an area in which a portion of the top surface of each of the second semiconductor chips 310 is exposed upward.

[0126] According to some embodiments, the support member 401 may be disposed between the lowermost second semiconductor chip 310 and the package substrate 100. The support member 401 may be configured to support the lowermost second semiconductor chip 310 on the top surface of the package substrate 100. The support member 401 may be configured to support the surface exposed from the first semiconductor chip 210 on the bottom surface of the lowermost second semiconductor chip 310.

[0127] According to some embodiments, the support member 401 may have a curved shape when viewed from above in the vertical direction Z. In some embodiments, the support member 401 may have a vertically curved shape when viewed from above in the vertical direction Z. In this case, the support member 401 may be configured to face the first semiconductor chip 210 in both the first and second directions. When viewed from above in the vertical direction Z, the support member 401 may be completely covered by the second chip stack structure 300. In some embodiments, the support member 401 may include a silicon dummy. Since the support member 401 supports the bottom surface of the bottommost second semiconductor chip 310, the structural stability of the offset stacked second semiconductor chips 310 can be improved. Furthermore, since the support member 401 is shielded by the second chip stack structure 300, the dimensions of the semiconductor package 12 can be maintained.

[0128] Figures 12 to 17 This is a plan view illustrating a method for manufacturing a semiconductor package according to some embodiments. In the following text, references are omitted. Figures 1 to 11 The descriptions overlap, but the main focus is on the differences.

[0129] Reference Figure 12 A packaging substrate 100 is provided, in which substrate pads 110_S and 110_G / P are arranged on the top surface of the packaging substrate 100. The substrate pads 110_S and 110_G / P may be arranged in two rows on the top surface of the packaging substrate 100. The first row and the second row may be spaced apart from each other in the second horizontal direction Y.

[0130] The base pads 110_S and 110_G / P in the first row can be configured such that the ground / power base pad 110_G / P and the signal base pad 110_S are alternately spaced apart from each other in the first horizontal direction X by a first interval. The base pads 110_S and 110_G / P in the second row can also be configured such that the ground / power base pad 110_G / P and the signal base pad 110_S are alternately spaced apart from each other in the first horizontal direction X by a first interval.

[0131] According to some embodiments, the base pads 110_S and 110_G / P disposed in the first row and the base pads 110_S and 110_G / P disposed in the second row can be arranged to be staggered by a first interval, respectively. The base pads 110_S and 110_G / P disposed in the second row can be offset by a first interval relative to the base pads 110_S and 110_G / P disposed in the first row in a first horizontal direction X.

[0132] Reference Figure 13 A first chip stack structure 200 is mounted on a packaging substrate 100. The first chip stack structure 200 may include a plurality of first semiconductor chips 210. The plurality of first semiconductor chips 210 may be offset and stacked in a first direction. The side surfaces of the plurality of first semiconductor chips 210 may be coplanar.

[0133] A plurality of first semiconductor chip pads 220 may be disposed on the top surface of each of the first semiconductor chips 210. The plurality of first semiconductor chip pads 220 may be arranged on an area in which a portion of the top surface of each of the first semiconductor chips 210 is exposed upward. According to some embodiments, the first semiconductor chip pads 220 (e.g., the vertical projection of the first semiconductor chip pads 220) may be stacked in a second horizontal direction Y with the substrate pads 110_S and 110_G / P disposed in the first row (e.g., the vertical projection of the substrate pads 110_S and 110_G / P disposed in the first row).

[0134] Reference Figure 14 A second chip stack structure 300 is mounted on the first chip stack structure 200. The second chip stack structure 300 may be offset and stacked on the first chip stack structure 200 in each of a first direction and a second direction. The second chip stack structure 300 may be stacked on the top surface of the first semiconductor chip 210 located at the uppermost end of the first chip stack structure 200.

[0135] The second chip stack structure 300 may include a plurality of second semiconductor chips 310. The second semiconductor chip 310 disposed at the bottom end may be offset and stacked on the top surface of the first chip stack structure 200 in each of the first and second directions.

[0136] A plurality of second semiconductor chip pads 320 may be disposed on the top surface of each of the second semiconductor chips 310. The plurality of second semiconductor chip pads 320 may be arranged on an area in which a portion of the top surface of each of the second semiconductor chips 310 is exposed upward. According to some embodiments, the second semiconductor chip pads 320 (e.g., the vertical projection of the second semiconductor chip pads 320) may be stacked in the second horizontal direction Y with the substrate pads 110_S and 110_G / P disposed in the second row (e.g., the vertical projection of the substrate pads 110_S and 110_G / P disposed in the second row).

[0137] Reference Figure 15 The first semiconductor chip pad 220 on the first semiconductor chip 210 is electrically connected to the substrate pads 110_S and 110_G / P disposed in the first row through conductive patterns G / P_L and S_L.

[0138] The conductive pattern can be divided into a ground / power conductive pattern G / P_L and a signal conductive pattern S_L. The ground / power conductive pattern G / P_L electrically connects the ground / power substrate 110_G / P to the first semiconductor chip pad 220. The signal conductive pattern S_L electrically connects the signal substrate 110_S to the first semiconductor chip pad 220. When viewed from above in the vertical Z direction, the conductive patterns G / P_L and S_L can extend in the first direction. Furthermore, the conductive patterns G / P_L and S_L can have a stepped shape in the cross-section on the YZ plane.

[0139] The conductive patterns G / P_L and S_L connecting the first semiconductor chip pad 220 to the substrate pads 110_S and 110_G / P can cover at least some portions of the top surface of the first semiconductor chip 210 and at least some portions of the top surface of the package substrate 100.

[0140] The conductive patterns G / P_L and S_L may cover at least a portion of the top surface of each of the first semiconductor chip pads 220. In some embodiments, the conductive patterns G / P_L and S_L may completely cover the top surface of the first semiconductor chip pad 220. In some embodiments, the conductive patterns G / P_L and S_L may completely cover both the top surface and side surfaces of the first semiconductor chip pad 220. In some embodiments, the conductive patterns G / P_L and S_L may only cover a portion of the top surface of the first semiconductor chip pad 220. In this specification, the conductive patterns G / P_L and S_L that connect the first semiconductor chip pad 220 to the substrate pads 110_S and 110_G / P may be referred to as the first conductive pattern.

[0141] Reference Figure 16An insulating pattern I_L is formed on the conductive patterns G / P_L and S_L that electrically connect the first semiconductor chip pad 220 to the substrate pads 110_S and 110_G / P in the first row. The insulating pattern I_L may be formed to cover the conductive patterns G / P_L and S_L that are superimposed on the second semiconductor chip 310 in the second horizontal direction Y. Alternatively, the insulating pattern I_L may not be formed on the conductive patterns G / P_L and S_L that are not superimposed on the second semiconductor chip 310 in the second horizontal direction Y.

[0142] An insulating pattern I_L may be formed around conductive patterns G / P_L and S_L. In some embodiments, the insulating pattern I_L may only cover the top surfaces of the conductive patterns G / P_L and S_L. In some embodiments, the insulating pattern I_L may completely cover the exposed surfaces of the conductive patterns G / P_L and S_L.

[0143] Reference Figure 17 Conductive patterns G / P_L and S_L are formed that electrically connect the second semiconductor chip pad 320 to the substrate pads 110_S and 110_G / P disposed in the second row.

[0144] Conductive patterns G / P_L and S_L can be formed on insulating pattern I_L (see...) Figure 16 In this case, among the conductive patterns G / P_L and S_L that electrically connect the second semiconductor chip pad 320 to the substrate pads 110_S and 110_G / P provided in the second row, the conductive pattern G / P_L that does not overlap with the first semiconductor chip 210 in the second horizontal direction Y may not be formed on the insulating pattern I_L. In this specification, the conductive patterns G / P_L and S_L that electrically connect the second semiconductor chip pad 320 to the substrate pads 110_S and 110_G / P provided in the second row may be referred to as the second conductive pattern.

[0145] In some aspects, this disclosure provides a method for manufacturing a semiconductor package. The method includes: providing a package substrate, the package substrate including substrate pads disposed in a first row and a second row on a top surface of the package substrate; mounting a first chip stack structure on the package substrate, the first chip stack structure including first semiconductor chips offset and stacked in a first direction; mounting a second chip stack structure on the first chip stack structure, the second chip stack structure including second semiconductor chips offset and stacked in a first direction and the second chip stack structure being offset and stacked in each of the first and second directions; forming a first conductive pattern, the first conductive pattern electrically connecting the first semiconductor chips to the substrate pads respectively; forming insulating patterns on the first conductive patterns stacked with the second semiconductor chips in the first direction respectively; and forming a second conductive pattern, the second conductive pattern electrically connecting the second semiconductor chips to the substrate pads respectively, wherein the substrate pads disposed in the first row are arranged offset from the substrate pads disposed in the second row by a first interval.

[0146] In some implementations, the substrate pad may be divided into a ground / power substrate pad and a signal substrate pad, and the substrate pads in each of the first and second rows may have alternating ground / power substrate pads and signal substrate pads.

[0147] In some implementations, the ground / power base pad may surround the signal base pad.

[0148] In some embodiments, the second conductive pattern, which is superimposed on the first semiconductor chip in the first direction, may be disposed on an insulating pattern.

[0149] In some implementations, each of the first conductive pattern and the second conductive pattern may be divided into a ground / power conductive pattern and a signal conductive pattern.

[0150] In some implementations, the ground / power conductive pattern and the signal conductive pattern may face each other in a second direction.

[0151] In some embodiments, a first semiconductor chip pad may be disposed on the top surface of each of the first semiconductor chips, and a second semiconductor chip pad may be disposed on the top surface of each of the second semiconductor chips.

[0152] In some implementations, the insulating pattern may cover the entire exposed surface of the first conductive pattern.

[0153] In some embodiments, after mounting a first chip stack structure comprising first semiconductor chips stacked offset in a first direction onto a package substrate, the method may further include forming supports that are laterally spaced from the first chip stack structure.

[0154] In some embodiments, the support may be disposed between the bottommost second semiconductor chip and the packaging substrate, and the support may be completely covered by the second chip stack structure when viewed from above in the vertical direction, and may be flexible.

[0155] Although the inventive concept has been specifically shown and described with reference to some embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0156] While this specification contains numerous specific details of implementation, these should not be construed as limiting the scope of any invention or the scope of claims, but rather as descriptions of features that may be implemented for specific embodiments of a particular invention. Certain features described in this specification within the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, while features may be described above as functioning in certain combinations, one or more features from a combination may be removed from that combination in some cases, and the combination may involve sub-combinations or variations thereof.

Claims

1. A semiconductor package, comprising: Packaging substrate; One or more first semiconductor chips are offset and stacked on a package substrate in a first direction; A plurality of first semiconductor chip pads are spaced apart from each other in a second direction on the upper surface of each of the one or more first semiconductor chips; One or more second semiconductor chips are stacked offset in a first direction on the uppermost first semiconductor chip of the one or more first semiconductor chips. A plurality of second semiconductor chip pads are spaced apart from each other in a second direction on the upper surface of each of the one or more second semiconductor chips; as well as Multiple substrate pads are arranged in the first and second rows on the encapsulation substrate. In this configuration, the lowermost second semiconductor chip in one or more second semiconductor chips is offset and stacked on the uppermost first semiconductor chip in a first direction and a second direction.

2. The semiconductor package according to claim 1, wherein, The plurality of base pads includes a plurality of ground / power base pads and a plurality of signal base pads. The plurality of grounding / power supply pads and the plurality of signal pads are alternately arranged in each of the first and second rows.

3. The semiconductor package according to claim 2, wherein, The plurality of ground / power base pads surround the plurality of signal base pads.

4. The semiconductor package according to claim 1, wherein, The first direction and the second direction form a right angle.

5. The semiconductor package according to claim 1, further comprising: Multiple conductive patterns are used to connect a corresponding base pad in a first row of the multiple base pads to a corresponding first semiconductor chip pad in the multiple first semiconductor chip pads, and to connect a corresponding base pad in a second row of the multiple base pads to a corresponding second semiconductor chip pad in the multiple second semiconductor chip pads. as well as Multiple insulating patterns are provided between a corresponding conductive pattern in the multiple conductive patterns that connects a corresponding base pad in the first row to a corresponding first semiconductor chip pad and a corresponding conductive pattern in the multiple conductive patterns that connects a corresponding base pad in the second row to a corresponding second semiconductor chip pad.

6. The semiconductor package according to claim 5, wherein, The plurality of conductive patterns includes one or more ground / power conductive patterns and one or more signal conductive patterns.

7. The semiconductor package according to claim 6, wherein, Among the plurality of conductive patterns, the conductive patterns that are spaced apart from each other in the vertical direction and in which the corresponding insulating pattern is placed are conductive patterns of different types.

8. The semiconductor package according to claim 6, wherein, The one or more ground / power conductive patterns and the one or more signal conductive patterns face each other in a second direction.

9. The semiconductor package according to claim 1, wherein, The one or more first semiconductor chips correspond to four first semiconductor chips, and Wherein, the one or more second semiconductor chips correspond to four second semiconductor chips.

10. The semiconductor package according to any one of claims 1 to 9, further comprising: The support is located between the packaging substrate and the bottommost second semiconductor chip.

11. The semiconductor package of claim 10, wherein, When viewed from above in a vertical direction, the support has a curved shape.

12. A semiconductor package, comprising: Packaging substrate; The first chip stacking structure includes a plurality of first semiconductor chips stacked offset in a first direction on a packaging substrate; A plurality of first semiconductor chip pads, each of which is parallel to and spaced apart from each other in a second direction on its upper surface; The second chip stack structure comprises a plurality of second semiconductor chips offset and stacked in a first direction and a second direction on the upper surface of the uppermost first semiconductor chip among the plurality of first semiconductor chips. A plurality of second semiconductor chip pads, each of which is spaced apart from each other in a second direction on its upper surface; Multiple base pads are arranged in the first and second rows on the encapsulation substrate; Multiple conductive patterns are used to connect one or more corresponding first semiconductor chip pads of the plurality of first semiconductor chip pads to one or more corresponding base pads of the plurality of base pads, and to connect one or more corresponding second semiconductor chip pads of the plurality of second semiconductor chip pads to one or more corresponding base pads of the plurality of base pads. as well as An insulating pattern is disposed between corresponding conductive patterns that face each other in the vertical direction among the plurality of conductive patterns. The plurality of base pads includes a plurality of grounding / power supply base pads and a plurality of signal base pads. The plurality of grounding / power supply pads and the plurality of signal pads are alternately arranged in each of the first and second rows. When viewed vertically from above, the plurality of grounding / power base pads face each other diagonally, and When viewed from above in a vertical direction, the plurality of signal base pads face each other diagonally.

13. The semiconductor package according to claim 12, wherein, The plurality of conductive patterns includes one or more ground / power conductive patterns and one or more signal conductive patterns.

14. The semiconductor package of claim 13, wherein, Among the plurality of conductive patterns, the corresponding conductive patterns facing each other in the vertical direction are conductive patterns of different types, and Among these, the corresponding conductive patterns that face each other laterally in the plurality of conductive patterns are conductive patterns of different types.

15. The semiconductor package according to claim 12, wherein, The vertical projection of one or more of the plurality of substrate pads in the first row is superimposed on the vertical projection of the plurality of first semiconductor chip pads in the first direction, and Wherein, the vertical projection of one or more of the plurality of base pads in the second row is superimposed on the vertical projection of the plurality of second semiconductor chip pads in the first direction.

16. The semiconductor package according to any one of claims 12 to 15, further comprising: A support is located between the packaging substrate and the lowest second semiconductor chip among the plurality of second semiconductor chips.

17. The semiconductor package of claim 16, wherein, When viewed from above in a vertical direction, the support is completely covered by the second chip stack structure.

18. A semiconductor package, comprising: Packaging substrate; The first chip stacking structure includes a plurality of first semiconductor chips stacked offset in a first direction on a packaging substrate; A plurality of first semiconductor chip pads, each of the plurality of first semiconductor chips having a surface on which they are parallel to each other and spaced apart in a second direction perpendicular to a first direction; The second chip stack structure is offset and stacked on the upper surface of the uppermost first semiconductor chip among the plurality of first semiconductor chips in each of a first direction and a second direction. The second chip stack structure includes a plurality of second semiconductor chips offset and stacked in the first direction. A plurality of second semiconductor chip pads, spaced apart from each other in a second direction on the top surface of each of the plurality of second semiconductor chips; Multiple base pads are arranged in the first and second rows on the encapsulation substrate; Multiple conductive patterns connect the multiple first semiconductor chip pads to the multiple substrate pads, and the multiple second semiconductor chip pads to the multiple substrate pads; as well as Insulating patterns, between corresponding conductive patterns that face each other in the vertical direction among the plurality of conductive patterns. The plurality of substrate pads includes a plurality of ground / power substrate pads and a plurality of signal substrate pads alternately arranged in each of the first and second rows. When viewed vertically from above, the plurality of grounding / power base pads face each other diagonally. When viewed vertically from above, the plurality of signal base pads face each other diagonally, and The plurality of conductive patterns include a plurality of ground / power conductive patterns and a plurality of signal conductive patterns arranged alternately.

19. The semiconductor package of claim 18, further comprising: A support member is located between the packaging substrate and the lowest second semiconductor chip among the plurality of second semiconductor chips. The support has a curved shape when viewed from above in a vertical direction.

20. The semiconductor package of claim 18, wherein, Among the plurality of conductive patterns, the corresponding conductive patterns that are spaced apart from each other in the vertical direction and in which the insulating pattern is placed are conductive patterns of different types.

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