Multi-step chemical mechanical polishing method for materials used in the semiconductor industry

Abstract

The present invention relates to a method (100) for polishing a planar substrate (Waf) using a planarization polisher comprising a support plate (Pl) arranged with a polishing pad (Pol.Pad), a conditioning head (Cond.Head) for conditioning the polishing pad and a head (Pol.Head) for holding the planar substrate (Waf) against the polishing pad, the method comprising a first step (110) of first conditioning the polishing pad (Pol.Pad) using the conditioning head (Cond.Head), wherein no polishing operation is performed on the planar substrate (Waf); a second step (120) of first polishing the planar substrate (Waf), wherein no conditioning operation is performed on the polishing pad; and a third step (130) wherein (i) a second polishing of the planar substrate (Waf) is performed, while (ii) a second conditioning of the polishing pad (Pol.Pad) is performed.

Description

Technical Field

[0001] This invention relates to an optimized chemical mechanical polishing method for reducing the formation of scratches on a substrate (e.g., a substrate of semiconductor material, referred to as a wafer). Background Technology

[0002] The field of semiconductor materials requires extremely smooth and uniform material surfaces, for example, for fabricating semiconductor wafers used in photolithography or direct contact bonding stages, or for processing the surface of donor wafers or layers separated from such wafers after a lift-off stage (possibly using Smart Cut™ technology). For these purposes, mechanical polishing or chemical mechanical polishing (CMP) operations are typically employed.

[0003] Chemical mechanical polishing (CMP) is a method that combines mechanical and chemical actions to smooth surfaces. In CMP operations on wafers, the wafer is pressed against a polishing pad and rubbed in the presence of a polishing slurry (often called a slurry). During CMP, the slurry is chemically neutral and does not chemically abrade the material being polished.

[0004] Polishing pads typically consist of flexible disks made of polymers, woven fabrics, or nonwoven fabrics, with a known roughness and a profile designed to grind the wafer surface. Polishing slurries consist of liquids capable of chemically etching the wafer (e.g., through oxidation), containing abrasive particles capable of mechanically etching the material.

[0005] While polishing the wafer, the polishing pad can be frictionally dressed by a dressing element, which is, for example, a metal disk with diamonds embedded on its surface.

[0006] Patent document US 2006 / 0183410 A1 relates to a system and method for diamond dressing of a soft polishing pad used for chemical mechanical planarization and polishing (CMP).

[0007] Patent document US 2011 / 0256812 A1 relates to closed-loop control for improving the profile of a polishing pad.

[0008] Patent document US 8562392 B2 relates to a polishing apparatus and a polishing method.

[0009] Patent document US 2003 / 0166383 A1 relates to a polishing apparatus.

[0010] Patent document US 2017 / 0008146 A1 relates to a chemical mechanical planarization trimmer.

[0011] Patent document US 5961373 A relates to a method for manufacturing a semiconductor device, the method comprising trimming a polishing pad.

[0012] A specific example requiring extremely fine surface fabrication is the preparation of silicon carbide (SiC) slabs, with the aim of providing atomically flat and damage-free substrates for high-quality epitaxy. These substrates are fundamental components in the fabrication of high-performance semiconductor devices for high-power applications.

[0013] CMP operations involve mechanical polishing, which generates debris that can exacerbate certain surface defects (such as scratches). To ensure the desired polishing quality, this debris may need to be removed. More typically, to avoid or reduce surface defects, CMP operations are usually performed while finely adjusting polishing parameters and carefully selecting the consumables used. Nevertheless, there is still room for improvement, which is desirable given the importance of substrate or layer surface quality in the semiconductor industry.

[0014] To address this, two-step CMP polishing methods have been developed, such as those described by Weilei Wang et al. in their paper "Two-Step Chemical Mechanical Polishing of 4H-SiC (0001) Wafer" (2021, ECS J. SolidState Sci. Technol., 10.074004). CMP operations involve complex interactions between the wafer surface and the consumables of the CMP equipment (polishing pads, slurry, and elements for dressing the polishing pads). The two-step approach involves using a first consumable combination in the first stage to achieve a first objective, such as a high rate of material removal from the surface of the wafer to be processed. In the second stage, a second consumable combination is employed to achieve a second objective, such as high surface quality of the wafer. The slurry / polishing pad pairing, on the other hand, varies between the first and second stages. This approach complicates consumable selection and increases the number of operations to be performed, whereas in industrial environments, the opposite is true: the goal is to simplify operations while maintaining the desired performance level. Summary of the Invention

[0015] The purpose of this invention is to provide a method for mechanical polishing or chemical mechanical polishing of substrates used in the semiconductor industry, which solves the above-mentioned problems.

[0016] To achieve these objectives, one aspect of the present invention is a method for polishing a planar substrate using a planarization polishing machine, the planarization polishing machine including a support plate, a replaceable trimming head and a polishing head, a replaceable polishing pad placed on the support plate, the replaceable trimming head being arranged for trimming the polishing pad, and the polishing head being arranged for holding the planar substrate against the replaceable polishing pad, the method comprising three stages: (1) a first stage in which a first polishing pad is trimmed for the first time by a first trimming head, and the planar substrate is not polished against the polishing pad in the first stage; (2) a second stage following the first stage in which a first polishing of the planar substrate is performed, the planar substrate is held against the first polishing pad by the polishing head, and the first polishing pad is not trimmed in the second stage; and (3) a third stage following the second stage in which (i) a second polishing of the planar substrate is performed by holding the planar substrate against a second polishing pad by means of the polishing head, and (ii) a second trimming of the second polishing pad is performed by the second trimming head.

[0017] The polishing method according to the present invention can reduce the presence of scratches on the surface of a flat substrate and also obtain a surface condition that matches subsequent operations (which have high requirements for the surface condition) (e.g., photolithography or epitaxial growth operations for manufacturing electronic circuits).

[0018] Furthermore, this simplifies the management of consumables (polishing pads, dressing heads, polishing fluid) used in the polishing process and reduces the number of loading and unloading operations involved by being able to use the same consumables throughout the polishing operation, without having to change these consumables between stages of the process.

[0019] According to additional non-limiting features of the invention, the following features can be considered individually or in any technically achievable combination: - The first polishing pad and the second polishing pad can be the same polishing pad; - The same polishing slurry can be directed onto the board in the first, second and third stages; - The first trimming head and the second trimming head can be the same trimming head; - In the second and third stages, the parameter representing the force applied by the polishing head to the flattened substrate can be the same; - In the second and third stages, the parameter representing the rotation applied to the flat substrate by the polishing head can be the same; - In the second and third stages, the parameter representing the rotation applied to the plate can be the same; and - The flat substrate may consist of a silicon carbide plate or include a silicon carbide layer that has been chemically and mechanically polished.

[0020] This invention relates to a method for manufacturing a composite substrate, the method comprising the following stages: preparing a surface of a donor substrate; preparing a surface of a receiver substrate; assembling the receiver substrate and the donor substrate by bringing the prepared surface of the donor substrate into direct contact with the prepared surface of the receiver substrate; peeling off the donor substrate to leave a transfer layer formed by the donor substrate of a certain thickness on the receiver substrate; and preparing a free surface of the transfer layer, wherein at least one of the stages of preparing the surface of the donor substrate, preparing the surface of the receiver substrate, and preparing the free surface of the transfer layer is performed by a polishing method according to the invention.

[0021] According to additional non-limiting features of the invention, the following features can be considered individually or in any technically achievable combination: - The donor substrate may be formed at least partially of SiC or GaN (each being a single-crystal structure), and / or the receiver substrate may be formed at least partially of SiC or AlN (each being a polycrystalline form); - The method for manufacturing a composite substrate may further include a stage of re-trimming the free surface of the donor substrate after the stripping stage, wherein the re-trimming stage is performed by a polishing method according to the invention.

[0022] The present invention relates to a method for manufacturing electronic devices, the method comprising a stage selected from the following performed on a flat substrate subjected to a polishing method according to the present invention: epitaxial layer growth, direct contact bonding stage, or photolithography operation. Attached Figure Description

[0023] Other features and advantages of the invention will become apparent from the following detailed description of the invention, taking into account the accompanying drawings, in which: [ Figure 1 ] Figure 1 The planarization polishing machine in use is shown; [ Figure 2 ] Figure 2 A chemical mechanical polishing method according to the present invention is shown; [ Figure 3 ] Figure 3 Test results of a chemical mechanical polishing method using "in-situ" finishing are shown; [ Figure 4 ] Figure 4 Test results of a chemical mechanical polishing method using "non-in-situ" finishing are shown; [ Figure 5 ] Figure 5 Test results of the three-stage chemical mechanical polishing method according to the present invention are shown; [ Figure 6 ] Figure 6 It shows the use of Figure 2 Polishing methods are used to manufacture composite substrates; [ Figure 7 ] Figure 7 It shows the manufacturing process. Figure 6 The method of composite substrates in the process. Detailed Implementation

[0024] Embodiments of the present invention Embodiments of the present invention are described in detail below, and are provided by Figures 1 to 5 As shown.

[0025] In the following sections of this specification, the invention will be described in examples of chemical mechanical polishing. However, it should be noted that the invention is also applicable to purely mechanical polishing operations.

[0026] Figure 1 A machine Mac for chemical mechanical polishing in use is shown, the machine Mac having a support plate P1, a replaceable dressing head Cond.Head and a polishing head Pol.Head, a replaceable polishing pad Pol.Pad placed on the support plate P1, the replaceable dressing head Cond.Head being arranged to dress the polishing pad Pad.Pol, and the polishing head Pol.Head being arranged to hold the substrate to be treated against the polishing pad.

[0027] The polishing operation on a flat substrate Waf (e.g., a wafer) is performed by holding the wafer against the polishing pad Pol.Pad via the polishing head Pol.Head by applying a force F1 oriented toward the plate Pl and a rotation ω2 about the vertical axis Ax2 centered on the polishing head. The rotation ω2 is transmitted to the wafer via the carrier element Car, which is in contact with the wafer.

[0028] The plate Pl also follows a rotation ω1 along the vertical axis Ax1 centered on the plate. The relative motion between the plate and the wafer allows for uniform polishing.

[0029] Although not shown here, the polishing machine Mac is equipped with a system for dispensing polishing slurry Sl, which serves to lubricate and chemically etch the surface of the wafer.

[0030] The polishing machine Mac is also equipped with a head, Cond.Head, for dressing the polishing pad Pol.Pad. Its function is to dress the surface of the pad, thereby maintaining its stable properties. The dressing head can consist of a rigid metal disc with diamond inlays on its surface. The disc exhibits a rotation ω3 about axis Ax3 centered on the dressing head, which is mounted at the end of an arm Sw.Ar, which exhibits an oscillating motion Sw about axis A4 centered at the other end of the arm Sw.Ar. A vertical force F2 oriented towards the plate Pl is applied to the dressing head.

[0031] Figure 3 , Figure 4 and Figure 5 Characterization results are shown for a flat substrate having at least one silicon carbide surface that has undergone polishing in the following ways: (1) polishing the wafer while trimming the polishing pad (referred to as polishing with “in-situ” trimming); (2) polishing the wafer after trimming the polishing pad without trimming the polishing (referred to as polishing with “non-in-situ” trimming); and (3) polishing the wafer for the first time after trimming the polishing pad without trimming the polishing (therefore, trimming is referred to as “non-in-situ”), and polishing the wafer for the second time while trimming the polishing pad (referred to as polishing with “in-situ” trimming).

[0032] The relevant parameters for the polishing operation mentioned in the previous paragraph are as follows.

[0033] The trimming pad can have a Shore A hardness between 90 and 100, compressibility between 0% and 6%, density between 0.95 and 1.11, and be driven to rotate ω1 at a speed between 90 rpm and 120 rpm.

[0034] The polishing head can apply pressure to the wafer between 3 psi and 9 psi (units commonly used by suppliers of such equipment in this field) (i.e., at 21000 N / m). 2 and 62000 N / m 2 The pressure between them), and it is driven to rotate ω2 at a speed between 70 rpm and 160 rpm.

[0035] The dressing head may consist of a diamond-coated metal disc having an aggression between 20 and 30, a flatness between 0 and 75, and a rotational speed ω3 between 10 rpm and 140 rpm. The dressing head may be configured to apply a force between 4 lbf and 8 lbf (pounds of force, a unit commonly used by suppliers of such equipment) to the polishing pad, assuming a standard diameter of 4.25 inches (a unit commonly used by suppliers of such equipment).

[0036] The characterization shown here was performed using the SICA88 device from Lasertec, which combines visible light Nomarski prism confocal microscopy with photoluminescence technology (as described in [1] T. Kimoto et al., “Fundamentals of Silicon Carbide Technology Growth Characterization Devices and Applications” (p. 126) or [2] D. Baierhofer et al., “Materials Science in Semiconductor Processing” (140 (2022), 106 414)) and is generally used to examine the surface of semiconductor substrates.

[0037] Figures 1 to 3 (A) depicts a defect diagram that shows the different types of defects on the surface being analyzed. Figures 1 to 3 The results of the roughness analysis are described in (B).

[0038] like Figure 3 As shown, conventional polishing operations involve trimming the polishing pad while polishing the wafer. However, this approach does not satisfactorily prevent the formation of surface defects such as scratches.

[0039] Figures 1 to 4 The explanation is as follows. The stage of polishing the wafer simultaneously with dressing the polishing pad results in a variable scratch rate between 10% and 30%, meaning that 10% to 30% of the wafers show scratches; see [link to documentation]. Figure 3 (A) Figure 3 The relevant roughness shown in (B) is in the range of 4 to 5 (any unit of SICA88 device), where regions R1 and R2 exhibit roughness of less than 4.6 and 5.1 (any unit of SICA88 device), respectively.

[0040] like Figure 4 As shown, the "non-in-situ" polishing operation can reduce the scratch rate to the range of 0% to 8%, with a roughness in the range of 5 to 7 (any unit of SICA88 equipment), and regions R1 and R2 exhibiting roughness of less than 5.7 and 6.3 (any unit of SICA88 equipment), respectively.

[0041] The cause has not been fully explained Figure 3 and Figure 4The mechanism of surface condition differences between polishing operation types. The lower roughness of polishing operations using "in-situ" dressing is likely due to the good surface condition of the polishing pad, which is continuously re-dressed. The increased roughness of polishing operations using "out-of-situ" dressing appears to be related to debris from the wafer, diamond particles from the dressing head, and / or abrasive particles from the polishing slurry. "Out-of-situ" dressing fails to optimize roughness but appears to be better able to remove scratch-causing particles or aggregates.

[0042] Based on this observation, a method 100 was proposed that employs a three-stage polishing process for a planar substrate (e.g., a wafer). This will be discussed below. Figure 5 The result of this method is shown.

[0043] In stage 110, the first polishing pad Pol.Pad is trimmed using the trimming head Cond.Head. Polishing slurry Sl is guided onto the first polishing pad. In this first stage, the flat substrate Waf is not subjected to polishing operations against the polishing pad Pol.Pad.

[0044] In the intermediate stage 115 following stage 110, the trimming head is moved away from the first polishing pad, and instead, the flattened substrate is brought into contact with the first polishing pad and pressed against the first polishing pad by the polishing head Pol.Head and the carrier element Car.

[0045] In the second stage 120 following the intermediate stage 115, the flat substrate Waf is polished by holding it against the first polishing pad Pad.Pol using a polishing head Pol.Head. Polishing slurry Sl is guided onto the polishing pad. In this second stage, no trimming operation is performed on the first polishing pad Pad.Pol. In other words, in the second stage 120 of polishing the flat substrate Waf, the trimming head is positioned at a distance from the polishing pad, maintaining a gap between the trimming head and the polishing pad; that is, the head is positioned not to apply any action, particularly mechanical action, to the polishing pad. Alternatively, the head can be moved from... Figure 2 Completely removed from the polishing system shown.

[0046] In the intermediate stage 125 following stage 120, the dressing head is brought into contact with the polishing pad and pressed against it.

[0047] In the third stage 130 following the intermediate stage 125, the flat substrate Waf is polished by holding it against the first or second polishing pad Pad.Pol using a polishing head Pol.Head, while the polishing pad Pol.Pad is trimmed using a trimming head Cond.Head. Polishing slurry Sl is guided onto the polishing pad.

[0048] The first polishing pad is used in stages 110 and 120. The same first polishing pad may be used in stage 130, or it may be replaced by a second polishing pad of the same or different type as the first polishing pad.

[0049] The same dressing head can be used for two or three of the three stages 110, 120 and 130, or three dressing heads of three different types can each be used for one of the corresponding stages of the three stages 110, 120 and 130.

[0050] The same polishing slurry can be used for two or three of the three stages 110, 120, and 130, or three different types of polishing slurries can each be used for a corresponding stage of the three stages 110, 120, and 130. As mentioned above, each polishing slurry (or solution) is preferably chemically neutral for the surface to be polished, or capable of chemically etching the surface to be polished, depending on the circumstances. For example, an embodiment in which either stage 120 or 130 is a chemical-mechanical polishing stage and the other is a mechanical polishing stage is conceivable.

[0051] The polishing parameters (such as the speeds of rotation ω1, ω2, ω3, and ω4, and the amounts representing the applied forces F1 and F2) can be identical for two or all three of the three stages 110, 120, and 130, or they can be different for each of the three stages 110, 120, and 130.

[0052] Selecting different consumables (polishing pads, dressing heads, polishing fluids) according to the stage can optimize each of these stages and thus achieve the best surface quality. On the other hand, in an industrial environment, this complicates the management of consumables, the use and maintenance of polishing systems (machines, consumable inventory and handling, etc.), and becomes a source of errors and additional costs.

[0053] Conversely, limiting the variation of consumables simplifies their management, simplifies the maintenance of the polishing system, and limits the number of loading and unloading operations required, thereby reducing sources of error and lowering costs.

[0054] Figure 5 The results of the three-stage polishing operation are shown, in which the consumables remain the same in the three stages 110, 120 and 130.

[0055] It is obvious that, with Figure 3 and Figure 4 Compared to the polishing operation shown, the number of scratches is reduced, and compared to Figure 4Compared to the polishing operation shown, the roughness level is reduced, with regions R1 and R2 exhibiting roughnesses of less than 5.1 and 5.7 (arbitrary units for the SICA88 device), respectively. Therefore, the number of surface defects (particularly scratches) and the roughness are matched to subsequent epitaxial, direct bonding, or photolithography operations. Compared to conventional methods, the three-stage polishing method according to the invention significantly reduces the number of surface defects.

[0056] In practice, stage 120 can be used to remove relatively large thicknesses of the flat substrate to be treated, such as between 180 nm (for a flat substrate consisting of a silicon carbide (SiC) layer) and 800 nm (for a single-crystal silicon carbide wafer). This stage, employing "non-in-situ" finishing, can prevent scratch formation but results in suboptimal roughness.

[0057] Stage 130 can be considered a finishing step, which, compared to Stage 120, uses "in-situ" finishing to remove a smaller thickness (e.g., about 50 nm) of the flat substrate to be processed. This stage can reduce the roughness of the flat substrate surface without introducing scratches.

[0058] After stages 110 to 130, the planarized substrate is prepared for additional operations 140 for fabricating semiconductor devices. These operations may include one or more of epitaxial thin-layer growth, direct contact bonding, or photolithography.

[0059] Epitaxial thin-layer growth can obtain semiconductor layers with high crystal quality that can be directly formed on polished layers of flat substrates.

[0060] Direct contact bonding enables the bonding of homogeneous or complex planar structures to planar substrates using known assembly methods (e.g., molecular bonding, bonding, or metal-to-metal bonding).

[0061] Photolithography can produce complex semiconductor devices on flat substrates.

[0062] Each of these operations benefits from the polishing quality achieved through methods with stages 110 to 130, which can increase the production yield of the final semiconductor device.

[0063] Application Examples Figure 6 and Figure 7Method 200 is illustrated, which is a specific embodiment of the above-described method and is particularly suitable for obtaining a composite semiconductor substrate comprising a thin layer of a first semiconductor material supported by a substrate of a second material. The thin layer is intended to form an active layer of a semiconductor device. The substrate is selected for its characteristics (which are complementary to the characteristics of the thin layer). Therefore, a composite substrate can be formed by a layer of SiC or GaN with a single-crystal structure supported by a substrate of SiC or AlN with a polycrystalline structure.

[0064] Method 200 begins by providing two substrates, Sub1 and Sub2, through two provisioning stages 210 and 220, respectively. In embodiments of the invention, substrate Sub1 is composed of SiC or GaN having a single-crystal structure and is intended to serve as a donor substrate for forming a thin single-crystal layer TrLay. Substrate Sub2 is composed of SiC or AlN having a polycrystalline structure and is intended to serve as a support substrate for the transfer layer TrLay.

[0065] In stage 230, where at least one optical entity is injected, a stage is performed where a substrate Sub1 is prepared to separate the layer TrLay formed by a portion of the thickness of the substrate Sub1 (in this embodiment, according to Smart Cut). TM technology).

[0066] Therefore, the substrate Sub1 must be fabricated by introducing at least one optical entity (e.g., hydrogen or helium) into the substrate. This introduction can correspond to hydrogen implantation, i.e., ion bombardment with hydrogen. In a manner known per se, such as... Figure 6 As shown, hydrogen ions H are injected + To form a weakening plane Frgl that defines the layer TrLay to be transferred, the layer TrLay corresponding to the surface Surf1 (H) of the substrate Sub1 at the weakening plane Frgl. + Ions are injected through the surface Surf1 into the volume between the substrate Sub1 and the surface Surf1.

[0067] The properties and dosage of the implanted entity, as well as the implantation energy, are selected based on the thickness of the layer to be transferred and the physicochemical properties of the substrate Sub1. In the case of a substrate Sub1 made of SiC, implantation at energy levels between 30 keV and 300 keV can be selected. 16 atoms / cm 2 and 5.10 17 atoms / cm 2 The hydrogen dosage is used to define the TrLay layer with a thickness of approximately 200 nm to 2000 nm.

[0068] In assembly stage 250, the two substrates Sub1 and Sub2 are assembled together by bringing layer TrLay into direct contact with one surface of substrate Sub2. The two layers adhere to each other via molecular bonding. In this way, an intermediate stack IntStck is formed, comprising two substrates Sub1 and Sub2 with a weakening layer Frgl.

[0069] The assembly stage requires the contact surfaces to be as flat and smooth as possible, ideally atomically flat. To this end, stages 210 and 220, which provide the substrate, each include implementing the polishing method described above, applying it at least to the surfaces of substrates Sub1 and Sub2 intended to contact each other in assembly stage 250.

[0070] In the separation stage S260 following the assembly stage 250, the substrate Sub1 is peeled into two parts at the weakening layer Frgl (in this embodiment, according to Smart Cut). TM (Process). Therefore, a portion of the substrate Sub1 is separated from the rest of its volume, thereby isolating the target layer (in this case, layer TrLay, which is separated from the rest of the substrate Sub1 by fracturing at the weakening plane Frgl). Layer TrLay is then transferred onto the support Sub2. The resulting assembly forms the composite substrate Comp.Sub.

[0071] This separation stage may include applying heat treatment to the stack IntStck at a temperature range of approximately 800°C to 1000°C, thereby enabling the separation of layer TrLay and thus completing the transfer of layer TrLay to substrate Sub2. Alternatively or supplementing the heat treatment, this stage may include applying a blade, a gas or liquid jet, or any other mechanical force at the weakening plane Frgl.

[0072] In an optional stage following the separation stage, a stabilization heat treatment can be applied to the composite substrate Comp.Sub. This stabilization heat treatment corrects crystal defects present in the TrLay layer. This heat treatment can be arranged by placing the composite substrate at a temperature between 1500°C and 1900°C for a duration between 30 minutes and 10 hours. This heat treatment is preferably performed by exposing the free surface of the TrLay layer to a neutral gas atmosphere.

[0073] After the layer TrLay separates from the rest of the substrate Sub1, its free surface Surf.Sep is not flat. In order to make it suitable for any operation commonly used in the semiconductor industry, the preparation of this surface Surf.Sep needs to be optimized, especially to reduce its roughness, ideally making it atomically flat and smooth.

[0074] Therefore, in surface preparation stage 270, planarization and polishing are applied to the surface Surf.Sep of layer TrLay. This can be achieved through the above process. Figure 2 The polishing process described.

[0075] After the stripping stage 260, the donor substrate Sub1 has a surface Surf1' formed by stripping the substrate at the weakened plane. In the Refurb stage, where the substrate Sub1 is refinished so that it can be used as a donor substrate again, the state of the surface Surf1' can be restored according to the same process as in stage 270.

[0076] In this application, the drawings are not necessarily drawn to scale. Some features and components may be depicted enlarged relative to other components, or in a schematic form, and for clarity and brevity, some details of conventional elements may not be shown.

[0077] Of course, the present invention is not limited to the described embodiments, and alternative embodiments may be introduced without departing from the scope of the invention as defined by the claims.

Claims

1. A method (100) for polishing a planar substrate (Waf) using a planarization polishing machine, the planarization polishing machine comprising a support plate (P1), a replaceable trimming head (Cond.Head), and a polishing head (Pol.Head), wherein a replaceable polishing pad (Pol.Pad) is disposed on the support plate (P1), the replaceable trimming head (Cond.Head) is arranged to trim the polishing pad (Pad.Pol), and the polishing head (Pol.Head) is arranged to hold the planar substrate (Waf) against the replaceable polishing pad, the method comprising three stages: - First stage (110), in which the first polishing pad (Pol.Pad) is first trimmed by the first trimming head (Cond.Head), and the flat substrate (Waf) is not polished against the polishing pad (Pol.Pad) in this first stage; - A second stage (120) following the first stage (110), wherein the first polishing of the planar substrate (Waf) is performed, and the planar substrate (Waf) is held against the first polishing pad (Pad.Pol) by a polishing head (Pol.Head), and no trimming operation is performed on the first polishing pad (Pad.Pol) in this second stage; and - The third stage (130) following the second stage (120) includes (i) a second polishing of the flat substrate (Waf) by means of a polishing head (Pol.Head) to keep the flat substrate (Waf) against the second polishing pad (Pad.Pol), and (ii) a second trimming of the second polishing pad (Pol.Pad) by means of a second trimming head (Cond.Head).

2. The method (100) according to claim 1, wherein, The first polishing pad and the second polishing pad are the same polishing pad (Pol.Pad).

3. The method (100) according to claim 1 or 2, wherein, In the first stage (110), the second stage (120) and the third stage (130), the same polishing slurry (Sl) is guided onto the board.

4. The method (100) according to any one of claims 1 to 3, wherein, The first dressing head and the second dressing head are the same dressing head (Cond.Head).

5. The method (100) according to any one of claims 1 to 4, wherein, In the second stage (120) and the third stage (130), the parameter representing the force (F1) applied by the polishing head to the flat substrate is the same.

6. The method (100) according to any one of claims 1 to 5, wherein, In the second and third stages, the parameter (ω2) representing the rotation applied to the flat substrate (Waf) by the polishing head (Pol.Head) is the same.

7. The method (100) according to any one of claims 1 to 6, wherein, In the second and third stages, the parameter representing the rotation (ω1) applied to the plate (Pl) is the same.

8. The method (100) according to any one of claims 1 to 7, wherein, The flat substrate is composed of a silicon carbide plate or includes a silicon carbide layer subjected to chemical mechanical polishing.

9. A method (200) for manufacturing a composite substrate (Comp.Sub), the method (200) comprising the following stages: - Prepare the surface (Surf1) of the (210) donor substrate (Sub1); - Prepare the surface (Surf2) of the (220) receiving substrate (Sub2); - The receiving substrate (Sub1) and the donor substrate (Sub2) are assembled by making the fabrication surface (Surf1) of the donor substrate and the fabrication surface (Surf2) of the receiving substrate directly contact each other. - Peel off (260) the donor substrate (Sub1) to leave a transfer layer (TrLay) of a certain thickness formed by the donor substrate (Sub1) on the receiving substrate (Sub2); and - Prepare the free surface (Surf.Sep) of the (270) transfer layer. in, At least one of the stages of preparing the surface of the donor substrate (Surf1), preparing the surface of the receiving substrate (Surf2), and preparing the free surface of the transfer layer (SepSurf) is performed by the method of any one of claims 1 to 8.

10. The method (200) according to claim 9, wherein, The donor substrate (Sub1) is at least partially formed of SiC or GaN, each being a single-crystal structure, and / or the receiver substrate (Sub2) is at least partially formed of SiC or AlN, each being a polycrystalline form.

11. The method (200) according to claim 9 or 10, wherein the method (200) further includes a refurbishment stage (Refurb) of the free surface (Surf1') of the donor substrate (Sub1) after the stripping stage (260), wherein, The re-adjustment stage is carried out by the method described in any one of claims 1 to 8.

12. A method for manufacturing an electronic device, the method comprising a stage (140) selected from epitaxial layer growth, direct contact bonding, or photolithography operation performed on a planar substrate subjected to the method of any one of claims 1 to 8.

Images