compare command

Abstract

An apparatus includes decoding circuitry to decode a compare-and-conditional-add command that identifies a target address, a comparison data value, and an addend data value. Processing circuitry, in response to the compare-and-conditional-add command, triggers a set of atomic operations to read a target data value from a storage location corresponding to the target address and selectively write an updated data value to the storage location depending on whether the comparison data value satisfies a comparison condition with respect to the target data value. The updated data value includes a result of an addition of the target data value and the addend data value performed in response to the compare-and-conditional-add command. A comparison condition result indication is provided that indicates whether the comparison data value satisfies the comparison condition. The comparison condition result indication includes at least one of the target data value and the updated data value.

Description

Background Technology Technical Field

[0001] This technology relates to the field of data processing. More specifically, this technology relates to commands for accessing memory systems. Technical Background

[0002] Data processing devices can provide shared data that can be accessed by multiple requesters. For example, a location in a memory system may be read and written by multiple requesters. As system size increases, the number of requesters contending for access to shared resources may increase, potentially leading to problems accessing those resources. It is desirable to allow multiple requesters (e.g., processors) to access and update shared values. This shared access will be permitted even as contention increases in systems with a large number of requesters. Summary of the Invention

[0003] At least some examples of this technology provide an apparatus comprising: a decoding circuit configured to decode a compare and conditionally add command identifying a target address, a comparison data value, and an addend data value; and a processing circuit that, in response to the compare and conditionally add command, triggers a set of atomic operations to: read a target data value from a storage location corresponding to the target address; and selectively write an updated data value to the storage location depending on whether the comparison data value satisfies a comparison condition relative to the target data value read from the storage location, wherein the updated data value includes the result of adding the target data value and the addend data value in response to the compare and conditionally add command; and the processing circuit is configured to provide a comparison condition result indication indicating whether the comparison data value satisfies the comparison condition, the comparison condition result indication including at least one of the target data value and the updated data value.

[0004] At least some examples provide computer-readable code for manufacturing the aforementioned apparatus. This code may be disposed on a computer-readable medium. This medium may be non-transitory.

[0005] At least some examples of this technology provide a method comprising: decoding a comparison and conditional addition command identifying a target address, a comparison data value, and an addend data value; and triggering a set of atomic operations in response to the comparison and conditional addition command, the set of atomic operations comprising: reading a target data value from a storage location corresponding to the target address; and selectively writing an updated data value to the storage location depending on whether the comparison data value satisfies a comparison condition relative to the target data value read from the storage location, wherein the updated data value includes the result of adding the target data value and the addend data value in response to the comparison and conditional addition command; and the method comprising providing a comparison condition result indication indicating whether the comparison data value satisfies the comparison condition, the comparison condition result indication including at least one of the target data value and the updated data value.

[0006] At least some examples provide a non-transitory storage medium for storing a computer program for controlling a host data processing device to provide an instruction execution environment. The computer program includes: decoding program logic configured to decode a compare-and-conditionally add command identifying a target address, a comparison data value, and an addend data value; and processing program logic that, in response to the compare-and-conditionally add command, triggers a set of atomic operations to: read a target data value from a storage location corresponding to the target address; and selectively write an updated data value to the storage location depending on whether the comparison data value satisfies a comparison condition relative to the target data value read from the storage location, wherein the updated data value includes the result of adding the target data value and the addend data value in response to the compare-and-conditionally add command; and the processing program logic is configured to provide a comparison condition result indication indicating whether the comparison data value satisfies the comparison condition, the comparison condition result indication including at least one of the target data value and the updated data value.

[0007] The computer program can be set on a computer-readable medium. The medium can be non-transitory.

[0008] Further aspects, features, and advantages of this technology will become apparent from the following description, which is taken in conjunction with the accompanying drawings. Attached Figure Description

[0009] Figure 1 An example of a data processing device is illustrated schematically;

[0010] Figure 2 An example of a processor that supports compare and conditionally add instructions is illustrated schematically;

[0011] Figure 3 An example of a data processing apparatus that supports comparison and conditional addition transactions is illustrated schematically;

[0012] Figure 4 This is a ladder diagram illustrating a process triggered by a compare and conditionally add command;

[0013] Figure 5 This is a flowchart illustrating a process triggered by a compare and conditionally add command;

[0014] Figure 6 It is a flowchart illustrating the process of responding to a compare and conditionally add instruction in a system in which the processor is arranged to perform a series of atomic operations;

[0015] Figures 7A and 7B are flowcharts illustrating the process of responding to a compare and conditionally add instruction in a system where memory system components are arranged to perform a series of atomic operations; and

[0016] Figure 8 A simulation example is shown. Detailed Implementation

[0017] An apparatus according to an example of the present technology includes decoding circuitry configured to decode a compare-and-conditionally-add command. As will be discussed below, the decoding circuitry may include an instruction decoder configured to decode compare-and-conditionally-add instructions, and / or may include circuitry within a memory system component configured to decode compare-and-conditionally-add memory system bus commands.

[0018] The compare-and-conditionally-add command identifies the target address, the compare data value, and the addend data value. The target address may identify a storage location within shared memory that can be accessed by several requesting parties (e.g., multiple processing elements). Each of the identified values ​​may be identified using a reference to a register or directly within the compare-and-conditionally-add command. For example, the command may identify a register storing the address operand, the compare data value, and the addend data value used to determine the target address. Alternatively, the command may specify one or more of these identified values ​​directly in the encoding of the command itself (e.g., as an immediate value). The target address may not be specified completely, and in some examples, an offset may be specified by the compare-and-conditionally-add command, which may be combined with a base address to provide the target address.

[0019] The processing circuitry responds to a compare and conditionally add command to trigger a set of atomic operations. This set of atomic operations is observed as an indivisible series of operations performed without interference from other requesters in the address space accessible to the target address. This means that the set of atomic operations should provide the same result as would occur if no access from any of the other requesters occurred between the start and end of the set of atomic operations (e.g., write access to the memory location associated with the target address could be denied by other requesters while the set of atomic operations are being executed, or a mechanism could be provided to detect such interfering write access and ensure that the set of atomic operations fails if such interfering access is detected).

[0020] This set of atomic operations includes reading a target data value from a storage location corresponding to a target address. The storage location can be a location in memory or a location in cache memory corresponding to the memory location identified by the target address. This set of atomic operations also includes selectively writing an updated data value to the storage location depending on whether a comparison data value satisfies a comparison condition relative to the target data value read from the storage location. For example, the target data value is compared with a comparison data value, and the comparison condition is evaluated to determine whether the storage location should be updated. The comparison condition is not particularly limited and may include, for example, determining whether the target data value is less than, equal to, or greater than the comparison data value.

[0021] The updated data value includes the result of adding the target data value to the addend data value, where the addition is performed in response to a compare and conditional add command. It should be understood that if one of the addends is negative, the addition includes subtraction.

[0022] Therefore, this technology provides a command for atomically comparing a target data value with a comparison value and selectively adding a value to the target data value depending on the result of the comparison. The comparison of the target data value and the subsequent selective writing of the updated data value provide a means of ensuring atomicity by ensuring that the write fails if the assumption tested by the comparison is not true (e.g., because another requester has updated the target data value).

[0023] Compare-and-conditionally-add commands can be particularly useful in processors with multiple requesters that can access a shared address space, where multiple requesters may attempt to access the same target data value. By providing architectural support for compare-and-conditionally-add commands, this provides system designers with architectural flexibility to implement microarchitectural design options that help reduce the duration of periods when atomic operations, such as those involving atomic updates to a value at a given target address using the sum of the value and the addend, are prone to failure due to external interference from another requester writing to the memory location associated with the target address. This can be particularly helpful for modern processors, which typically have a greater number of requesters and therefore contention for access to shared resources becomes a particular problem. Therefore, the inventors have recognized that the increasing number of requesters in modern processors makes it reasonable to introduce such commands into architectures supported by decoding circuitry, although system support for these commands requires additional complexity.

[0024] The processing circuitry responds to a compare-and-conditionally-add command by providing a comparison condition result indication that the compared data values ​​satisfy the comparison condition. For example, the comparison condition result indication can be provided in a software-visible manner. If the compare-and-conditionally-add command is a memory bus command issued by the requesting party, the comparison condition result indication can be returned to the requesting party.

[0025] The comparison condition result indication includes at least one of the target data value and the updated data value. This helps support more efficient circuit implementations compared to alternatives that set condition flags in the control register, because in practice, the circuit responsible for selectively writing the updated data value to memory in some implementations may not have a direct path to setting condition flags, and therefore setting condition flags may not be a particularly efficient or scalable way to provide a comparison condition result indication for the compare and conditionally add command.

[0026] Therefore, providing an indication of the comparison condition result includes returning at least one of the target data value and the updated data value. The target data value indicates whether the updated data has been written to memory, since it is the target data value (along with the comparison data value, which should be known to the entity that issued the comparison and conditional addition command) that determines whether the comparison condition is met. The target data value has been read as part of this set of atomic operations and is therefore generally available to the processing circuitry, so returning the target data value may require very little additional overhead. Similarly, the updated data value can also be used as an indication of the comparison condition result, since the updated data value (i.e., the result of adding the target data value and the addend, regardless of whether the updated data value was actually written to the memory location corresponding to the target address) is simply a value offset by the addend relative to the target data value, and therefore returning the updated data value will allow the target data value itself and the result of the comparison condition to be derived. The manner in which the target data value and / or the updated data value are returned depends on the specific implementation, but may involve sending the target data value or the updated data value to the requesting party via the memory bus, and / or storing the target data value or the updated data value in a register.

[0027] Therefore, in some examples, the comparison condition result indicator includes the target data value, regardless of whether the comparison data value satisfies the comparison condition. In this case, the comparison condition result indicator indicates the old value at the storage location corresponding to the target address before performing the comparison and conditional addition operation.

[0028] In other examples, the comparison condition result indicator includes the updated data value, regardless of whether the compared data value satisfies the comparison condition. In this case, the comparison condition result indicator indicates the value that would have been written to the storage location if the comparison condition had been met, even if the comparison condition was not actually met.

[0029] In some examples, the comparison condition result indicator includes both: the target data value and the updated data value, corresponding to the final value stored at the memory location associated with the target address after the completion of the set of atomic operations; and a comparison condition result indicator specifying whether the compared data value satisfies the comparison condition. In this example, the final value can be either the target data value (if the comparison condition is not met) or the updated data value (if the comparison condition is met). In some use cases, future processing may depend on the updated data value if the comparison condition is met and on the target data value if the comparison condition is not met. Therefore, for the entity issuing the compare and conditionally add command, returning the final value obtained from a conditionally selective write based on the comparison condition may be useful, as this reduces the amount of subsequent operations that need to be applied to generate the value required for future processing. However, just as in the case where the final value is the value of the updated data value, the final value itself does not distinguish whether the final value matches the expected value of the updated data value because the condition was successfully written after the comparison condition was met, or because there was external interference at the storage location and the comparison condition failed, but the target data value written by the external requester just happened to be the same as the expected value of the updated data value. In addition to returning one of the target data value and the updated data value corresponding to the final value, it can also return a separate indication of the comparison result (e.g., a pass / fail indicator).

[0030] The comparison conditions can be fixed. However, in some examples, several options for the comparison conditions may exist, and the encoding of the compare and conditionally add command can identify the comparison conditions. For example, different command variants may be provided for different comparison conditions, distinguished by command identifiers (e.g., the opcode of the instruction). In other examples, the compare and conditionally add command may provide a field indicating the comparison conditions. In either case, supporting several comparison conditions increases the versatility of the command. Such comparison conditions may include, for example, equal to (satisfied when the target data value equals the comparison data value), not equal to, greater than, less than, greater than or equal to, less than or equal to, etc., and in some implementations, signed and unsigned versions of the comparison conditions, such as greater than or less than, may be supported.

[0031] As described above, this series of atomic operations is observed indivisibly. This means that in a system with multiple requesters accessing the same address space, reads, comparisons, and selective writes should have the same result, as if no other requester had interfered with the memory location associated with the target address during the period between the read and write. In contrast, if the read and write are triggered by separate commands and are not atomic, a write access to the target address by another requester can be observed between the read and write. Supporting atomic commands can be helpful in situations where multiple requesters contend for the use of shared resources stored in a memory system.

[0032] In some examples, the decoding circuitry is provided by the instruction decoder, and the compare-and-conditionally-add command is a compare-and-conditionally-add instruction defined by the instruction set architecture supported by the instruction decoder. Support for compare-and-conditionally-add instructions allows software with access to a shared address space to conditionally add values ​​in that shared address space, regardless of contention from other requesters. This thus provides an improved instruction set architecture for use with systems experiencing contention between requesters. The instruction decoder may be located within the processor core, and the processing circuitry may be located within the same processor core and may perform the addition of the target data value and the addend data value within that processor core. Alternatively, the processing circuitry may be located within the processor core and, in response to the decoding of the compare-and-conditionally-add instruction, trigger a command or a series of commands to instruct circuitry outside the processor core to perform that set of atomic operations. For example, the processing circuitry may issue a compare-and-conditionally-add memory system bus command, as discussed below. In yet another example, the instruction decoder may be located within the processor core, but the processing circuitry may be located outside the processor core, such as within a memory system component. In this example, the processing circuitry can be more local to the storage location and better positioned for condition updates, while reducing data transfers (and associated overhead and latency) between the memory and the processor core.

[0033] In the example where the compare-and-conditionally-add instruction is an instruction, the processing circuitry can be configured to return a comparison condition result indication (e.g., the target data value or the updated data value) to a general-purpose register. This allows the comparison condition result indication to be available in software, making subsequent instructions following the compare-and-conditionally-add instruction dependent on the comparison result indication. Returning this indication to a general-purpose register is more efficient than setting a flag in a control register because there is no direct path to update the flag based on a load / store access to a memory location in the memory system. This means that updating the flag might require additional operations to compare the returned value to generate the flag.

[0034] In some examples, the compare-and-conditionally-add instruction can be configured to identify the schema registers associated with the compare data value and the addend data value. That is, the compare-and-conditionally-add instruction can specify a schema register identifier that allows the processor to identify the registers used to obtain the compare data value and the addend data value. Specifying the registers to obtain these values ​​provides a more compact encoding of the instruction. The target address can be identified in a similar manner.

[0035] In some examples, in response to a compare-and-conditionally-add instruction, the processing circuitry can be configured to return a target data value or an updated data value to the architecture register that specifies the addend data value. As described above, the target data value acts as a comparison condition result indicator that enables the software to determine whether the comparison condition is satisfied. The software may want to determine whether the comparison condition is satisfied by comparing the target data value (either explicitly returned or derived from the updated data value) with the comparison data value and evaluating the comparison condition. By returning the target data value or the updated data value to the addend register, the number of registers specified by the compare-and-conditionally-add instruction can be reduced by reusing the source register as the destination register, while still allowing the software to perform comparisons because the comparison data value is not overwritten. In subsequent comparison instructions, the same architecture register used as the source register for the compare-and-conditionally-add instruction can be used as the source register to evaluate the condition. This approach helps save coding space in the instruction set architecture compared to the non-destructive coding of separate architecture registers for each of the addend data value, the comparison data value, and the destination register to which the target data value or the updated data value is returned. Furthermore, while it would be possible to return the target / updated data value to the architecture register used for the comparison data value, it is anticipated that in most workloads, the addend data value is more likely to remain static across multiple iterations of a loop where each iteration requires a set of atomic operations than the comparison data value. Therefore, writing an overwrite to the addend register instead of the comparison data register reduces the number of additional instructions required to move values ​​between architecture registers for the purpose of preserving the overwrite value, thereby helping to support better average-case performance.

[0036] In some systems, the order in which memory access instructions are observed can be important for ensuring consistency. For example, a write instruction that appears in program order after a load instruction might need to be observed after the load instruction to ensure that the correct data is loaded without being overwritten. In some examples, barrier instructions can be used to impose ordering, preventing instructions appearing on one side of the barrier from being observed on the other side. Barrier instructions can be used in conjunction with specific types of memory access instructions, and therefore combining barriers with memory access instructions to reduce code size can be beneficial.

[0037] The compare-and-conditionally-add instruction acts as a load instruction because it causes the target data value to be read from the memory location corresponding to the target address. Providing a fetch variant of the load instruction can be useful, acting as a barrier to prevent later memory access instructions from being observed before the load instruction. Therefore, in some examples, the instruction decoder may control the processing circuitry in response to at least one variant of the compare-and-conditionally-add instruction to prevent memory access instructions that are later in program order than the compare-and-conditionally-add instruction from being observed before the compare-and-conditionally-add instruction. This instruction can act as a one-way barrier, and thus the processing circuitry may allow memory access instructions that are earlier in program order than the fetch variant of the compare-and-conditionally-add instruction to be observed after the compare-and-conditionally-add instruction.

[0038] The compare-and-conditionally-add instruction can also function as a store instruction, as it allows updated data to be written to the memory location associated with the target address. Providing a release variant of the store instruction can be useful, acting as a barrier to prevent earlier memory access instructions from being observed after the store instruction. Therefore, in some examples, the instruction decoder can control the processing circuitry in response to at least one variant of the compare-and-conditionally-add instruction to prevent memory access instructions that are program-orderly earlier than the compare-and-conditionally-add instruction from being observed later than the compare-and-conditionally-add instruction. This instruction can act as a one-way barrier, and thus the processing circuitry can allow memory access instructions that are program-orderly later than the release variant of the compare-and-conditionally-add instruction to be observed earlier than the compare-and-conditionally-add instruction.

[0039] In some examples, the decoding circuitry is provided by at least one memory component. If the processing circuitry is positioned closer to the memory location, the series of operations triggered by the compare and conditional add command can be performed with increased efficiency, for example, to shorten the distance that the target data must be sent to read. This reduces the amount of time that prevents the memory location associated with the target address from being accessed by other requesters. Therefore, in some examples, the decoding circuitry (and processing circuitry) can be located within components of the memory system, such as outside the processor core.

[0040] When the decoding circuitry is provided by the memory system component, commands can be issued from the processor to the memory system component via the memory system bus, thereby instructing the processing circuitry to perform the series of atomic operations. Therefore, in some examples, the compare-and-conditionally-add command includes a compare-and-conditionally-add memory system bus command that can be decoded by the decoding circuitry within the memory system component.

[0041] In some examples, in a device with multiple requesters, the target data value may be stored in a system cache accessible to several requesting devices (e.g., processing cores). The shared cache may be accessible, for example, via an interconnect used to maintain consistency among the requesting devices. In some examples, a compare-and-conditionally-add command may be issued by one of the requesters, and at least one instance of processing circuitry and decoding circuitry may be located in the interconnect.

[0042] In some examples, the target data value may be stored in memory. Therefore, in some examples, at least one instance of the processing circuitry and the decoding circuitry may be located in a memory controller provided to control access to the memory.

[0043] An example will now be described with reference to the accompanying drawings.

[0044] Figure 1 An apparatus for data processing is schematically illustrated. The apparatus includes a decoding circuit 100, a processing circuit 102, and a data storage 104. These will be described below, with specific reference to the diagram. Figure 2 and Figure 3 There are several different ways in which these components can be implemented. Generally speaking, the decoding circuit responds to a comparison and conditional addition command to trigger a series of atomic operations to read the target data value, and selectively updates the target data value by adding an addend to the target data value if the target data value satisfies the comparison condition.

[0045] The inventors have recognized that common idiomatic patterns in code involve reading data values ​​from a data store, comparing those data values ​​with comparison data values, and conditionally adding those data values ​​if a comparison condition is met. For example, one possible scenario for such a sequence of events is when a counter is stored in a storage location (e.g., memory) that tracks the number of times an event has occurred. The requester can check the value of the counter to determine if it meets a criterion (such as whether the counter has reached a threshold), and depending on the result, the counter can be updated to indicate another event. For example, a processor can use a counter to track the number of times a task has been completed. The counter can be checked to determine if the task needs to be executed, and if so, the counter can be incremented to indicate that the requester has executed the task another time.

[0046] One way this compare-and-add sequence of operations can be performed is by using a series of independent instructions that trigger a series of transactions on the memory system. For example, the instruction sequence may include: a load instruction for loading a target data value by triggering a load transaction; a comparison instruction for comparing the loaded value with a comparison value; an addition instruction for updating the loaded value; and an atomic compare-and-swap instruction for issuing a compare-and-swap transaction to commit the updated value to memory. The comparisons within the compare-and-swap transaction ensure that the loaded value to be updated remains the same as the value used in the comparison instruction before the updated value is committed.

[0047] The inventors have recognized that such a sequence of instructions is prone to interruption when the target data value to be accessed is a shared value accessible to other requesters. For example, the target data value could be a shared counter tracking the number of times a task has been completed among a set of processors capable of performing tasks independently, and thus accessible simultaneously by different requesters. Specifically, if a second requester loads the target data value from the same address before one requester can submit an updated value, this could invalidate the updated data value held by the first requester. Therefore, the complete sequence of operations cannot be completed and must be retried. This can lead to different processors simultaneously attempting to load and update the same value and interrupting each other, potentially resulting in a significant amount of wasted work.

[0048] The inventors have realized that race conditions can be avoided if the series of operations used to compare values ​​and conditionally add those values ​​can be performed in atomic sequences. From the perspective of a requester other than the one attempting to update the target data value, the atomic sequence of loading and conditional writing occurs at once, meaning that access from another requester cannot be observed between the loading and selective addition, and that the series of operations cannot be interrupted by contention from another requester.

[0049] Furthermore, when a compare-and-add operation is included within a broader sequence of operations that needs to be executed atomically as a whole (where the overall sequence of operations may be too complex to be executed in a single command), a typical architecture would typically use a compare-and-swap command to achieve this, where the sequence would terminate with the sum of the target data value and the addend data value being written to memory under the condition that no interference was detected in an earlier part of the sequence. This compare-and-swap command conditionally writes the swapped value to memory if the target data value at the target memory location satisfies a given comparison condition with the comparison operands. However, in such an architecture, implementing a method where the swapped value is the sum of the target data value and the addend data value would require executing an additional command before the compare-and-add command to read the target data value and perform the addition. Such an architecture would not provide the hardware with any hints regarding the addition and compare-and-swap, and therefore would not support, as referenced... Figure 4 The ladder diagram discussed in the section describes a more efficient hardware implementation for reducing latency during periods when the overall sequence is susceptible to external interference. This more efficient hardware implementation is enabled in response to conditional compare-and-add operations (such as using local addition circuitry on memory system components or performing the addition in the load / store unit of the processor core, rather than on the arithmetic / logic unit of the processor core, which would typically be slower, and if the architecture treats the addition as a separate instruction from compare-and-swap, making it appear as any ordinary addition to be scheduled on the arithmetic / logic unit, then performing the addition on the arithmetic / logic unit of the processor core may be the only option available to the hardware designer). By supporting implementation options that can reduce latency between reading the target data value and conditionally writing the updated data value depending on the addition, architectures supporting conditional compare-and-add commands can thus support system designs that reduce the performance costs of managing contention as the number of requesters increases in modern processing systems.

[0050] The inventors have recognized that there are therefore significant performance benefits that can be obtained by configuring the device to trigger a set of atomic operations for conditionally adding a target data value in response to a compare and conditionally add command. Providing dedicated commands for such operations may seem counterintuitive, but the inventors have realized that in scenarios with modern processors that can provide a large number of requesters and are therefore associated with significant contention, supporting dedicated compare and conditionally add commands to trigger a series of atomic operations provides significant performance benefits that outweigh the additional complexity required to support such commands.

[0051] Commands can be implemented in the device in several ways. As discussed below, the system's instruction decoder may support compare-and-conditionally-add instructions. These instructions can cause the processor itself to perform a series of atomic operations, or they can cause the processor to trigger a memory component to perform such a series of atomic operations, for example, by issuing a compare-and-conditionally-add transaction on the memory bus. The memory system component may be more local to the memory location associated with the target address, and this may therefore allow the atomic sequence to be performed in a more efficient manner. Therefore, the decoding circuit 100 and processing circuit 102 may be located in the processor core or in a memory system component (such as an interconnect or memory controller). The data repository 104 may be located in memory, or it may be a cache storing data associated with the target address in memory. In some examples, the data repository 104 may be a cache within the processor.

[0052] Figure 2 An example of a data processing device 2 that supports comparison and conditional addition instructions is illustrated schematically. In addition to memory 34, device 2 may be provided, for example, as a processor core as part of a multi-core processor. The data processing device has a processing pipeline 4 comprising multiple pipeline stages. In this example, the pipeline stages include: a fetch stage 6 for fetching instructions from instruction cache 8; a decode stage 10 for decoding the fetched program instructions to generate micro-operations to be processed by the remaining stages of the pipeline; an issue stage 12 for checking whether the operands required for the micro-operation are available in register file 14, and issuing the micro-operation for execution once the operands required for a given micro-operation are available; an execution stage 16 for performing the data processing operation corresponding to the micro-operation by processing the operands read from register file 14 to generate a result value; and a write-back stage 18 for writing the processed result back to register file 14. It should be understood that this is merely one example of a possible pipeline architecture, and other systems may have additional stages or different stage configurations. For example, in an out-of-order processor, an additional register renaming stage may be included, which maps the architecture registers specified by program instructions or micro-operations to physical register specifiers in the identifier register file 14.

[0053] Execution phase 16 includes multiple processing units for performing different categories of processing operations. For example, the execution units may include: an arithmetic / logic unit (ALU) 20 for performing arithmetic or logical operations; a floating-point unit 22 for performing operations on floating-point values; a branching unit 24 for evaluating the results of branching operations and adjusting the program counter representing the current execution point accordingly; and a load / store unit 28 for performing load / store operations to access data in memory systems 8, 30, 32, and 34. In this example, the memory system includes a Level 1 data cache 30, a Level 1 instruction cache 8, a Level 2 cache 32 shared between data and instructions, and main system memory 34. It should be understood that this is only one example of a possible memory hierarchy, and other cache arrangements may also be provided. The specific types of processing units 20 to 28 shown in execution phase 16 are only one example, and other specific implementations may have a different set of processing units or may include multiple instances of the same type of processing units, allowing multiple micro-operations of the same type to be processed in parallel. It should be understood that Figure 2 This is merely a simplified representation of some components of a possible processor pipeline architecture, and the processor may include many other elements not illustrated for the sake of brevity, such as branch prediction mechanisms, address translation, or memory management mechanisms.

[0054] The decoding stage 10 of processor 2 is configured to decode a compare-and-conditionally-add instruction and, in response to decoding the instruction, issue a control signal. The compare-and-conditionally-add instruction can identify the target address, the comparison data value, and the addend data value through identifier architecture registers, for which the corresponding physical registers are set in register file 14.

[0055] In some examples, in response to a compare and conditionally add instruction, decoder 10 may trigger a series of atomic operations, wherein: load / store unit 28 issues a load transaction to the memory system to load the target data value to be stored in register 14, ALU 20 evaluates the comparison condition by referring to the target data value and the comparison data value in register 14, ALU 20 calculates the updated data value based on the target data value and the addend value in register 14, and LSU 28 selectively writes the updated data value to the storage location depending on the result of the comparison.

[0056] In other examples, in response to a compare and conditionally add instruction, decoder 10 may cause one or more transactions to be issued via the memory system bus to one or more memory system components in the memory system, so that the series of atomic operations are performed by said memory system components, such as... Figure 3 exemplified.

[0057] Figure 3 An example of a data processing apparatus 40 is schematically illustrated, comprising multiple requesting devices 2, 41 sharing access to a memory system. In this example, the requesting devices include two central processing units (CPUs) 2 (e.g., such as...). Figure 2 As shown) and a graphics processing unit (GPU) 41, but it should be understood that other types of requesting devices, such as a network interface controller or a display controller, may also be provided. The CPU 2 and GPU 41 each have at least one cache 42 for caching data from the memory system (e.g., ...). Figure 2 (Examples are Level 1 caches 8 and 30 and Level 2 cache 32). The memory system is accessed via a coherence interconnect 50, which manages the coherence between the corresponding cache 42 in requesting devices 2 and 41 and any other caches in the system (e.g., system-level cache 52 coupled to an interconnect not assigned to any particular requester). When accessing data in its local cache 42, requesting devices 2 and 41 may transmit a coherence transaction to the coherence interconnect 50. In response to this transaction, if it is determined that those caches may be holding data from the corresponding address, the interconnect 50 sends a snoop request to the other caches to locate the latest copy of the required data and, if necessary, invalidate stale data or write modified data back to memory, depending on the requirements of the coherence protocol employed. Such snoop requests and invalidations may result in the interruption of a sequence of instructions executed to conditionally update the target data value. If data needs to be retrieved from main memory 34, the coherent interconnect 50 can trigger a read request to memory 34 via one or more memory controllers 48, and similarly, a write to main memory can be triggered by the coherent interconnect 50. Each requesting device has a transaction interface 44, which is responsible for generating transactions transmitted to the interconnect 50 via the memory system bus, receiving responses from the interconnect, and handling listen requests triggered by the interconnect in response to transactions issued by other requesting devices. Interface 44 can be considered as a transaction issuing circuit for generating transactions.

[0058] In addition to rule-based read or write transactions of a coherence protocol that allow data to be read into cache 42 or written to memory 34, the system can also support comparison-conditional addition atomic transactions processed by processing unit 46, which is closer to the location where the data is stored. In response to a comparison-conditional addition atomic transaction, the data access circuitry in processing unit 46 reads the target data value from the storage location identified by the target address in cache 52 or memory 34. The "far" arithmetic / logic unit (far ALU, unlike the "near" ALU in CPU 2) in processing unit 46 performs a comparison based on the read data value and a comparison operand provided by the requesting device. The far ALU performs an addition between the read data value and the addend provided by the requesting device, and the data access circuitry selectively writes the updated data value back to the addressed storage location based on the comparison result. A comparison condition result indicator (such as the target data value or the updated data value) is also returned to the requesting device. Reads, ALU operations, and writes occur atomically, making them a series of indivisible operations that cannot be partially completed or interleaved with other operations performed in memory or cache.

[0059] When the target data of an atomic transaction is stored in the system cache 52, the transaction can be processed using the processing unit 46 within the interconnect. When the target data is stored in the main memory 34, the atomic transaction can be processed by the processing unit 46 within the corresponding memory controller 48. It should be understood that the processing unit 46 for processing atomic transactions may also be located elsewhere in the system 40.

[0060] Figure 4 This is a ladder diagram illustrating the process in which the requesting device and memory system components respond to a compare and conditionally add command.

[0061] like Figure 3 As shown, the system includes as follows Figure 2 The illustrated processors each include an fetch stage 6, a decode stage 10, and an execution stage 16. At stage 400, a compare-and-conditionally add instruction is fetched by the fetch stage 6 of one of the processors and provided to the instruction decode stage 10 (an example of decoder circuitry 100), which decodes the compare-and-conditionally add instruction. In response to the compare-and-conditionally add instruction, at step 402, the decode stage 10 sends a control signal to the execution stage 16 of the pipeline. The compare-and-conditionally add instruction identifies the target address, comparison data value, and addend data value, for example, through a reference architecture register, and may also specify the comparison condition in its encoding. Figure 4In the example shown, the execution phase (e.g., load / store unit 28) responds to control signal 402 to trigger a Compare-and-Conditional Add (CCA) transaction to the memory system components via the memory bus. Execution phase 16 issues a CCA transaction specifying the same target address, comparison data value, and addend data value identified by the CCA instruction. In this way, the processor triggers this set of atomic operations to read the target address and selectively add to that target address.

[0062] The comparison and conditional addition transaction specifies the target address, comparison data value, and addend data value, and can further specify the comparison conditions. Memory system component 46 includes decoding circuitry 100. Figure 1 As shown, the decoding circuit is configured to decode the compare and conditionally add transaction and, in response, issue a load request 406 to load the target data value from the storage location corresponding to the target address into the data storage 104 (e.g., cache 52 or memory 34). The target data value is returned from the data storage 104 at 408, and the processing circuitry 102 within the memory system component 46 can use the target data value and the compare data value to evaluate the comparison condition. For example, the target data value can be subtracted from the compare data value to determine which value (if any) is larger by evaluating whether the result is positive, negative, or zero. The memory system component 46 can also use the target data value to calculate the updated data value by adding an addend. The memory system component can return a comparison condition result indication 410 to the processor that issued the compare and conditionally add transaction. The comparison condition indication indicates whether the comparison condition was met. The target data value itself can be provided as a comparison condition result indicator because it can be compared by the requesting party with the comparison data value (which the requesting party may already have access to, as this value was used to issue the compare and condition add transaction) to determine whether the condition is met. Alternatively, an updated data value can be returned to the requesting party. The updated data value is offset relative to the target data value by an addend known to the processor that issued the compare and condition add transaction, and is therefore used to derive the target data value, which can then be used to evaluate the comparison condition. Thus, both the target data value and the updated data value can serve as comparison condition result indicators.

[0063] In some examples, in addition to a comparison condition result indicator (which can be the target data value, the updated data value, or a comparison condition result indicator (e.g., a single bit flag indicating whether the comparison condition was met)), memory system component 46 may also return a final value corresponding to the memory location at the target address after this series of atomic operations. If the comparison condition is not met, this final value is equal to the target data value, and if the comparison condition is met, this final value is equal to the updated data value. The final value itself may not allow the result of the comparison condition to be evaluated, but it may be useful for software to use this final value for future processing.

[0064] In step 410, the target data value or the updated data value (which in either case serves as an indication of the comparison condition result) may be returned to the architecture register identified in the compare and condition add instruction for storing the addend data value.

[0065] The memory system components also selectively store updated data values ​​in the memory location associated with the target address. If the comparison condition is not met, the memory location is not updated, and the target data value continues to be stored. If the comparison condition is met, the memory location is updated to store the updated data value formed by adding the addend data value to the target data value.

[0066] It should be understood that instead of issuing a comparison and conditional addition transaction at stage 404, the processor can perform this series of atomic operations internally, and therefore can issue internal control signals to LSU 28 to atomically perform the calculation of loaded and updated data values, as well as selective write operations (e.g., using a local ALU located separately within load / store unit 28 from the ALU 20 set up for handling rule ALU instructions). In this case... Figure 4 The steps shown to be executed by the memory component can also be executed by the processor's execution phase 16. Therefore, the processor can also act as the processing circuit 102.

[0067] It should be understood that the comparison-conditional-add instructions supported in the instruction set architecture and / or the comparison-conditional-add bus commands supported in the interconnect bus architecture provide system designers with considerable flexibility to change the specific way the circuitry used to implement the comparison-conditional-add operation is provided. However, unlike architectures that do not support the comparison-conditional-add command, which would not support more efficient implementations such as performing the addition operation at the remote ALU logic at memory system component 46, since the addition would not be signaled as part of an atomic comparison operation, there is greater flexibility in implementation options by supporting the comparison-conditional-add command, as the comparison-conditional-add command informs the hardware that the addition operation will be included in a set of atomic operations involving read, compare, and conditional write. This helps support implementations that can reduce the duration of periods during which a series of atomic operations will be vulnerable to external interference, as architectures that do not support the comparison-conditional-add command may constrain system designers to implement such sequences using separate addition instructions processed on the ALU 20 of the processor core, which would tend to increase the latency of the period between the initial load at step 406 and the storage of the updated value depending on the addition at step 412. The longer the latency during this period, the greater the likelihood that the group of atomic operations will fail due to contention from another requester, which is particularly problematic in modern processors involving many processor cores 2,41. Therefore, architectural support for comparison and conditional addition commands is extremely beneficial in helping to support better software performance for highly parallel workloads, which involve contention for access to shared resources between processes executing on multi-core systems.

[0068] An example of a compare-and-conditionally-add instruction has the following encoding:

[0069]

[0070] Where Xs identifies the register storing the comparison data value, and Xt identifies the register storing the addend data value. The part in square brackets identifies the base address.<Xn|SP> The base address is identified by a register that immediately offsets by #0. The register storing the base address can be a general-purpose register Xn, or a special-purpose register that stores the stack pointer SP. The instruction also specifies the comparison condition cond.

[0071] Comparison conditions can be specified in various ways, such as by providing different variants of the CCAADD instruction (with different opcodes). Alternatively, a field including comparison condition specifiers can also be provided. Comparison conditions can be an "equal to" condition that is satisfied when the compared data value and the target data value are equal, a "greater than" or "less than" condition that is satisfied when the compared data value is greater than or less than the target data value, etc.

[0072] Variants of the instruction can operate on registers of different sizes. For example, a variant can be provided for operation on a 32-bit register, and a different variant can be provided for operation on a 64-bit register. Both variants can access the same physical register, but the 32-bit variant can, for example, cause the processor to ignore the high 32 bits of the register.

[0073] Instruction variants can also act as one-way barrier instructions. A fetch variant prevents a later memory access instruction (load and store instruction) in program sequence from being observed before a fetch variant of a compare-conditionally add instruction. A release variant prevents an earlier memory access instruction in program sequence from being observed after a fetch variant.

[0074] A code sequence may include comparison and conditional addition instructions and subsequent instructions to determine whether a comparison condition is met. Such a code sequence may look like this:

[0075]

[0076]

[0077] Therefore, comparison and branch instructions can be used after the CCAADD instruction to check the returned target data value to evaluate whether the condition is met (and thus write the updated data value to the memory location associated with the target address). The comparison instruction sets a condition flag in the control register, which can be checked by subsequent branch instructions to evaluate the condition. It should be understood that this comparison is separate from the evaluation of the comparison condition triggered by the compare and condition add command, and is used to inform the software of the result, not to determine whether the target location should be updated.

[0078] It should be understood that branch instructions can alternatively test whether a path is successful and branch to the successful path.

[0079] Figure 5 This is a flowchart illustrating a process triggered by a compare-and-conditionally-add command. At step 500, the compare-and-conditionally-add command is decoded by the decoding circuit 100, thereby specifying the target address, the addend data value, and the comparison data value. At step 502, the decoding circuit 100 triggers a series of atomic operations to be executed by the processing circuit 102.

[0080] At step 504, the target data value is read from a storage location in data storage 104, which corresponds to the target address.

[0081] At step 506, addition is performed between the target data value read from the storage location and the addend data value specified by the compare and conditionally add command. Step 506 is shown in a dashed box because in some examples this addition can be performed if the comparison condition is met. However, in other examples, this series of atomic operations can be completed more quickly if the addition is performed without waiting for the result of the comparison to be determined, and if it is subsequently found that the comparison is not met, the updated data value can simply be discarded.

[0082] At step 508, the comparison data value and the target data value are compared to determine whether the comparison condition is met.

[0083] If the comparison condition is met, then at step 510, the updated data value calculated at step 506 is written to the storage location associated with the target address.

[0084] If the comparison condition is not met, then at step 512, the data at the storage location associated with the target address is left unchanged.

[0085] In either case, at step 514, a comparison condition result indication is provided to indicate the result of the comparison condition. For example, the target data value or the updated data value may be provided to a register that can be accessed by software.

[0086] It should be understood that Figure 5 The steps shown can be performed in parallel or in a modified order. For example, step 514 is independent of steps 510 or 512 and can be performed directly after step 508. Similarly, step 506 can be performed after step 508 as discussed above.

[0087] Figure 6 This is a flowchart illustrating the process of responding to a compare and conditionally add instruction in a system where the processor is arranged to perform a series of atomic operations.

[0088] At step 600, the compare-and-conditionally-add instruction is decoded. In response, at step 602, the processor issues a command to load the target data value from the memory system (e.g., from a cache, which may be located within the processor) into a register. At step 604, the comparison condition indicated by the compare-and-conditionally-add instruction is evaluated within the processor (e.g., by the LSU) between the target data value and the comparison data value. At step 606, an updated data value is generated by adding the addend data value and the target data value, and at step 608, the updated data value is selectively written to the memory location associated with the target address. In some examples, steps 604 and 606 may be performed in reverse order (where step 606 occurs before step 604) or at least partially in parallel. At step 610, a comparison condition result indication is returned (e.g., returned to one or more general-purpose registers, such as the register that provides the addend data value). The comparison condition result indication specifies at least one of the target data value and the updated data value.

[0089] Figures 7A and 7B illustrate the process of responding to a compare and conditional add instruction in a system where memory system components are arranged to perform a series of atomic operations.

[0090] Figure 7A illustrates the steps taken by a processing element connected to memory via a memory bus. At step 700, the processing element decodes a compare-and-conditionally-add instruction, and in response to decoding the compare-and-conditionally-add instruction, at step 702, a compare-and-conditionally-add transaction is issued via the memory bus.

[0091] Figure 7B illustrates the steps taken by a memory system component connected to a memory bus. At step 710, the compare-and-conditionally-add transaction issued by the processing element is decoded. In response, at step 712, the memory system component reads a target data value from a storage location associated with the target address specified by the compare-and-conditionally-add transaction. At step 714, a comparison condition between the target data value and the comparison data value is evaluated. At step 716, an updated data value is generated by adding the target data value and the addend data value. At step 718, the updated data value is selectively stored in the storage location associated with the target address. At step 720, a comparison condition result indication is returned to the requester that issued the compare-and-conditionally-add transaction. The comparison condition result indication specifies at least one of the target data value and the updated data value. The comparison condition result indication can be returned to the requester on the same read data path used to provide read data in response to a memory read bus transaction.

[0092] The concepts described herein may be embodied in computer-readable code used to manufacture devices embodying the described concepts. For example, the computer-readable code may be used in one or more stages of the semiconductor design and manufacturing process, including the electronic design automation (EDA) stage, to manufacture integrated circuits including devices embodying these concepts. The aforementioned computer-readable code may additionally or alternatively enable the definition, modeling, simulation, verification, and / or testing of devices embodying the concepts described herein.

[0093] For example, computer-readable code for manufacturing a device embodying the concepts described herein may be embodied in code that defines the hardware description language (HDL) representation of these concepts. For instance, the code may define a register-transfer level (RTL) abstraction of one or more logic circuits for defining a device embodying these concepts. The code may define an HDL representation of one or more logic circuits embodying the device using Verilog, SystemVerilog, Chisel, or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language) and intermediate representations such as FIRRTL. Computer-readable code may provide definitions of the concepts or other behavioral representations of the concepts embodying the concepts using system-level modeling languages ​​such as SystemC and SystemVerilog, which can be interpreted by a computer to enable simulation, functional and / or formal verification and testing of the concepts.

[0094] Additionally or alternatively, computer-readable code may define a low-level description of an integrated circuit component embodying the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer-readable representations of the integrated circuit component may be generated by applying one or more logic synthesis processes to the RTL representation to generate a definition for manufacturing a device embodying the invention. Alternatively or additionally, one or more logic synthesis processes may generate a bitstream from the computer-readable code to be loaded into a field-programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purpose of verifying and testing the concepts prior to manufacturing integrated circuits, or the FPGA may be deployed directly in a product.

[0095] Computer-readable code may include a mixture of code representations for manufacturing apparatus, such as one or more of RTL representations, netlist representations, or other computer-readable definitions used in the semiconductor design and manufacturing process for manufacturing apparatus embodying the present invention. Alternatively or additionally, the concept may be defined in a combination of computer-readable definitions used in the semiconductor design and manufacturing process for manufacturing apparatus and computer-readable code defining instructions that will be executed by the defined apparatus once manufactured.

[0096] Such computer-readable code can be contained in any known transient computer-readable medium (such as wired or wireless transmission of code over a network) or non-transitory computer-readable medium such as semiconductors, magnetic disks, or optical disks. Integrated circuits made using computer-readable code may include components such as one or more of the following: a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or other components that embody the concept independently or collectively.

[0097] Figure 8 Examples of emulator implementations that can be used are illustrated. While the previously described embodiments implement the invention in terms of means and methods for operating specific processing hardware supporting the technologies involved, it is also possible to provide an instruction execution environment according to the embodiments described herein, which is implemented using a computer program. Such computer programs are generally referred to as emulators, in part because they provide a software-based implementation of a hardware architecture. Types of emulator computer programs include simulators, virtual machines, models, and binary converters, including dynamic binary converters. Typically, the emulator implementation can run on a host processor 806, which optionally runs a host operating system 804, thereby supporting the emulator program 802. In some arrangements, multiple emulation layers may exist between the hardware and the provided instruction execution environment and / or multiple different instruction execution environments provided on the same host processor. Historically, powerful processors were required to provide emulator implementations that execute at a reasonable speed, but such approaches may be reasonable in certain situations, such as when it is desirable to run code native to another processor for compatibility or reuse reasons. For example, the emulator implementation may provide additional functionality to the instruction execution environment that is not supported by the host processor hardware, or provide an instruction execution environment that is typically associated with a different hardware architecture. An overview of the simulation is given in the following literature: “Some Efficient Architecture Simulation Techniques”, Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0098] With respect to embodiments previously described with reference to specific hardware constructions or features, equivalent functionality may be provided in simulated embodiments by suitable software constructions or features. For example, specific circuitry may be implemented as computer program logic in simulated embodiments. Similarly, memory hardware such as registers or cache memory may be implemented as software data structures in simulated embodiments. Where one or more of the hardware elements referenced in the previously described embodiments are present in an arrangement on host hardware (e.g., host processor 806), some simulated embodiments may utilize the host hardware where appropriate.

[0099] The simulator program 802 can be stored on a computer-readable storage medium (which may be a non-transitory medium) and provides a program interface (instruction execution environment) to the target code 800 (which may include applications, operating systems, and management programs), the same as the interface of the hardware architecture modeled by the simulator program 802. Therefore, the simulator program 802 can be used to execute program instructions of the target code 800 (including compare and conditionally add instructions) from within the instruction execution environment, enabling a host computer 806, which does not actually possess the hardware features of device 2 discussed above, to emulate these features.

[0100] The simulator code may include, for example, decoding program logic 808 for causing the host computer 806 to perform the functions of decoding circuit 100, and processing program logic 810 for causing the host computer 806 to perform the functions of processing circuit 102.

[0101] In this application, the phrase "configured as..." is used to mean that the elements of the device are configured to perform the defined operations. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operations, or a processor or other processing device may be programmed to perform the function. "Configured as" does not imply that the elements of the device need to be changed in any way to provide the defined operations.

[0102] In this application, a list of features beginning with the phrase “at least one of” means that any one or more of those features can be provided independently or in combination. For example, “at least one of the following: A, B, and C” covers any of the following options: A only (without B or C), B only (without A or C), C only (without A or B), a combination of A and B (without C), a combination of A and C (without B), a combination of B and C (without A), or a combination of A, B, and C.

[0103] While exemplary embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments, and various changes and modifications can be made therein by those skilled in the art without departing from the scope of the invention as defined in the appended claims.

Claims

1. An apparatus, the apparatus comprising: A decoding circuit configured to decode a comparison and conditional addition command that identifies a target address, compares a data value, and adds a data value; and Processing circuitry, in response to the compare and conditionally add command, triggers a set of atomic operations to: Read the target data value from the storage location corresponding to the target address, and The updated data value is selectively written to the storage location depending on whether the compared data value satisfies the comparison condition relative to the target data value read from the storage location. The updated data value includes the result of adding the target data value and the addend data value in response to the comparison and conditional addition command; and The processing circuit is configured to provide a comparison condition result indication indicating whether the comparison data value satisfies the comparison condition, the comparison condition result indication including at least one of the target data value and the updated data value.

2. The apparatus of claim 1, wherein the comparison condition result indication includes the target data value, regardless of whether the comparison data value satisfies the comparison condition.

3. The apparatus of claim 1, wherein the comparison condition result indication includes the updated data value, regardless of whether the comparison data value satisfies the comparison condition.

4. The apparatus of claim 1, wherein the comparison condition result indication includes both of the following: The target data value and the updated data value correspond to one of the final values ​​stored at the storage location associated with the target address after the completion of the set of atomic operations; and A comparison condition result indicator that specifies whether the comparison data value satisfies the comparison condition.

5. The apparatus according to any of the preceding claims, wherein the encoding of the comparison and conditional addition command identifies the comparison condition.

6. The apparatus according to any of the preceding claims, wherein the set of atomic operations is a set of operations that are to be observed indivisibly.

7. The apparatus according to any preceding claim, the apparatus comprising an instruction decoder, the instruction decoder including the decoding circuitry, wherein the compare-and-conditionally-add command comprises a compare-and-conditionally-add instruction defined by an instruction set architecture.

8. The apparatus of claim 7, wherein the processing circuitry is configured to return the comparison condition result indication to a general-purpose register.

9. The apparatus of any one of claims 7 and 8, wherein the compare and conditionally add instruction is configured to identify a schema register associated with the compare data value and the addend data value.

10. The apparatus of claim 9, wherein in response to the compare and conditionally add instruction, the processing circuitry is configured to return the target data value or the updated data value to the architecture register associated with the addend data value.

11. The apparatus according to any one of claims 7 to 8, wherein the instruction decoder controls the processing circuitry in response to at least one variant of the compare-and-conditionally-add instruction to prevent a memory access instruction that is later in program order than the compare-and-conditionally-add instruction from being observed before the compare-and-conditionally-add instruction.

12. The apparatus according to any one of claims 7 to 11, wherein the instruction decoder controls the processing circuitry in response to at least one variant of the compare-and-conditionally-add instruction to prevent a memory access instruction preceding the compare-and-conditionally-add instruction in program sequence from being observed after the compare-and-conditionally-add instruction.

13. The apparatus according to any of the preceding claims, wherein at least one memory system component includes the decoding circuit, and the compare and conditionally add command includes a compare and conditionally add memory system bus command.

14. The apparatus of claim 13, wherein the memory system component is an interconnect for maintaining consistency between the requesting device and at least one other requesting device or cache.

15. The apparatus of claim 13, wherein the memory system component is a memory controller for controlling access to the memory.

16. A system comprising at least one memory system component and means according to any one of claims 7 to 12, wherein the at least one memory system component is configured to trigger a read of a target data value from the storage location corresponding to the target address in response to the compare and conditionally add instruction.

17. A system comprising at least one requesting device and means according to any one of claims 13 to 15, the at least one requesting device being configured to issue the compare and conditionally add memory system bus command.

18. A computer-readable medium for storing computer-readable code for manufacturing an apparatus according to any one of claims 1 to 17.

19. A method comprising: Decode the comparison and conditional addition command that identifies the target address, compares the data value, and adds the addend data value; as well as In response to the comparison and conditional addition command, a set of atomic operations is triggered, the set of atomic operations including: Read the target data value from the storage location corresponding to the target address, and The updated data value is selectively written to the storage location depending on whether the compared data value satisfies the comparison condition relative to the target data value read from the storage location. The updated data value includes the result of adding the target data value and the addend data value in response to the comparison and conditional addition command; and The method includes providing a comparison condition result indication that indicates whether the comparison data value satisfies the comparison condition, the comparison condition result indication including at least one of the target data value and the updated data value.

20. A computer program for controlling a host data processing device to provide an instruction execution environment, the computer program comprising: The decoding program logic is configured to decode the comparison and conditional addition command that identifies the target address, compares the data value, and adds the addend data value. and Processing logic, in response to the compare and conditionally add command, triggers a set of atomic operations to: Read the target data value from the storage location corresponding to the target address, and The updated data value is selectively written to the storage location depending on whether the compared data value satisfies the comparison condition relative to the target data value read from the storage location. The updated data value includes the result of adding the target data value and the addend data value in response to the comparison and conditional addition command; and The processing logic is configured to provide a comparison condition result indication that indicates whether the comparison data value satisfies the comparison condition, the comparison condition result indication including at least one of the target data value and the updated data value.

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