Stacked memory physical layer (PHY) floorplan

Abstract

A die (110) includes a first set of physical layer (PHY) blocks arranged in a first column (512), where the first column (512) extends along a side (510) of the die. The die also includes a second set of PHY blocks arranged in a second column (514) adjacent to the first column (512). The first set of PHY blocks includes a first PHY block, the second set of PHY blocks includes a second PHY block, and the first PHY block and the second PHY block share one or more clock resources.

Description

Cross-references to related applications

[0001] This application claims priority and benefit to non-provisional patent application serial number 18 / 608,440, filed on March 18, 2024, with the United States Patent and Trademark Office, the entire contents of which are as fully set forth herein and incorporated herein for all applicable purposes. Background Technology Technical Field

[0003] This disclosure relates in general to memory interfaces, and more specifically to memory physical layer (PHY) layout planning. Background Technology

[0005] A system may include one or more processors and one or more memory devices for storing data and / or instructions for the one or more processors. For example, the one or more memory devices may be implemented as Double Data Rate (DDR) memory, which increases the data transfer rate by transmitting data on both the rising and falling edges of a clock signal. The one or more processors may access the one or more memory devices using a memory controller that interfaces with the one or more memory devices via a memory interface. Summary of the Invention

[0006] The following is a simplified overview of one or more embodiments to provide a basic understanding of such embodiments. This overview is not an exhaustive summary of all anticipated embodiments, nor is it intended to identify key or essential elements of all embodiments, nor to depict the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed descriptions that follow.

[0007] A first aspect relates to a system including a die. The die includes a first set of physical layer (PHY) blocks arranged in a first column, wherein the first column extends along one side of the die. The die also includes a second set of PHY blocks arranged in a second column adjacent to the first column. The first set of PHY blocks includes a first PHY block, and the second set of PHY blocks includes a second PHY block, and the first PHY block and the second PHY block share one or more clock resources.

[0008] The second aspect relates to a system comprising a die. The die includes physical layer (PHY) blocks arranged in at least two columns, wherein a first column extends along one side of the die, and a second column is adjacent to the first column. The PHY blocks include a first PHY block in the first column and a second PHY block in the second column, and the first PHY block and the second PHY block share one or more clock resources. Attached Figure Description

[0009] Figure 1 Examples of memory devices and dies according to certain aspects of this disclosure are shown, the die including a processor, a memory controller, and a memory interface.

[0010] Figure 2 A side view of a bare die in a package according to certain aspects of this disclosure is shown.

[0011] Figure 3 An exemplary layout of a memory interface including a physical layer (PHY) block is shown according to certain aspects of this disclosure.

[0012] Figure 4A A block diagram of an exemplary PHY block according to certain aspects of this disclosure is shown.

[0013] Figure 4B It is shown that certain aspects of this disclosure are used for Figure 4A An exemplary layout of the bumps of the PHY block.

[0014] Figure 5 An exemplary layout of a memory interface according to certain aspects of this disclosure is shown, the memory interface including a physical layer (PHY) block arranged in two columns along a first side of the die and a PHY block arranged in two columns along a second side of the die.

[0015] Figure 6 An example is shown of increasing the number of PHY blocks on a die by adding additional columns to the PHY blocks, according to certain aspects of this disclosure.

[0016] Figure 7A A block diagram showing a first PHY block and a second PHY block located in adjacent columns according to certain aspects of this disclosure is illustrated.

[0017] Figure 7B It is shown that certain aspects of this disclosure are used for Figure 7A An exemplary layout of the bumps of the first PHY block and the second PHY block.

[0018] Figure 8A It is shown that certain aspects of this disclosure will Figure 7AAn example where the first and second PHY blocks are placed closer together.

[0019] Figure 8B It is shown that certain aspects of this disclosure are used for Figure 8A An exemplary layout of the bumps of the first PHY block and the second PHY block.

[0020] Figure 9A An example is shown of a first PHY block and a second PHY block sharing a phase-locked loop (PLL) according to certain aspects of this disclosure.

[0021] Figure 9B It is shown that certain aspects of this disclosure are used for Figure 9A An exemplary layout of the bumps of the first PHY block and the second PHY block.

[0022] Figure 10 An example is shown where a first PHY block and a second PHY block share a PLL and a multiplexer according to certain aspects of this disclosure.

[0023] Figure 11 An example is shown where the PHY blocks in the first part of the memory interface share clock resources and the PHY blocks in the second part of the memory interface share clock resources, according to certain aspects of this disclosure.

[0024] Figure 12 An exemplary specific implementation of a clock circuit, a first PHY block, and a second PHY block according to certain aspects of this disclosure is shown.

[0025] Figure 13A An example of a first input / output (IO) circuit according to certain aspects of this disclosure is shown.

[0026] Figure 13B An example of a second I / O circuit according to certain aspects of this disclosure is shown.

[0027] Figure 14A Another example of a first input / output (IO) circuit according to certain aspects of this disclosure is shown.

[0028] Figure 14B Another example of a second I / O circuit according to certain aspects of this disclosure is shown. Detailed Implementation

[0029] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein can be practiced. To provide a comprehensive understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0030] Figure 1 Examples of systems 100 that can utilize various aspects of this disclosure are shown. System 100 may be included in smartphones, laptops, tablets, Internet of Things (IoT) devices, etc.

[0031] In this example, system 100 includes a die 110 (i.e., a chip) and an external memory device 120. Die 110 includes a processor 112, a memory controller 118, and a memory interface 115. Memory device 120 can be used to store data and / or instructions for processor 112. Processor 112 is coupled to memory controller 118, which is configured to provide processor 112 with access to memory device 120, as discussed further below. Processor 112 may include a central processing unit (CPU), a modem processor, a graphics processor, a processor core, etc. Although Figure 1 A processor 112 is shown, and it should be understood that die 110 may include multiple processors (e.g., multiple processor cores) that use memory controller 118 to access memory device 120.

[0032] Memory controller 118 is coupled to memory interface 115, which interfaces memory controller 118 with memory device 120, as discussed further below. Memory interface 115 is coupled to memory device 120 via multiple links configured to transmit, for example, data (DQ), data strobe (DQS), command address (CA) signals, write clock (WCK) signals, etc.

[0033] Memory device 120 may include double data rate (DDR) memory (such as low-power DDR (LPDDR) memory) to save power. In this example, double data rate (DDR) increases the data transfer rate of memory device 120 by transmitting data on both the rising and falling edges of a clock signal. For the DDR example, memory interface 115 may also be referred to as a DDR interface.

[0034] As discussed above, memory controller 118 provides processor 112 with access to memory device 120. For example, memory controller 118 may read data from memory device 120 via memory interface 115 and forward the read data to processor 112. Memory controller 118 may also receive data from processor 112 and write data to memory device 120 via memory interface 115.

[0035] For example, to read data from memory device 120, processor 112 may transmit a read request for data from memory device 120 to memory controller 118. In response to the read request, memory controller 118 transmits a read command and the address of the requested data to memory device 120 via memory interface 115. Memory device 120 receives the read command and the address, and reads the requested data from memory (e.g., an array of memory cells) at the address. Memory device 120 may then send one or more data signals, including the read data, to memory interface 115. Memory device 120 may also send data strobe signals.

[0036] The memory interface 115 receives one or more data signals and data strobe signals from the memory device 120. The memory interface 115 uses the data strobe signals to capture read data from one or more data signals and transmits the captured read data to the memory controller 118, which forwards the read data to the processor 112.

[0037] exist Figure 1 In this example, processor 112, memory controller 118, and memory interface 115 are integrated on die 110 (i.e., chip), and memory device 120 is located outside die 110. Memory interface 115 includes multiple physical layer (PHY) blocks (also simply referred to as PHY or PHY interface). See below for further details. Figure 3 Examples of PHY discussion. Although memory interface 115 is in Figure 1 For simplicity, the image shows the memory interface 115 on one side of the die 110. It should be understood that the memory interface 115 may be located on both sides or more sides of the die 110, as discussed further below. In addition, in some specific implementations, the memory device 120 may be located above or below the die 110 (e.g., in a stacked package (PoP) configuration).

[0038] In this example, die 110 (i.e., the chip) is encapsulated in package 130. Package 130 and memory device 120 are mounted on substrate 125 (e.g., a printed circuit board (pPCB)), wherein a memory interface 115 on die 110 is coupled to memory device 120 via metal traces on substrate 125 and / or embedded in substrate 125 (e.g., PCB). Although Figure 1 A memory device 120 is shown, and it should be understood that the memory interface 115 on the die 110 can be coupled to multiple memory devices mounted on the substrate 125.

[0039] Figure 2 An example of a side view of a die 110, a package 130, and a substrate 125 according to certain aspects is shown. In this example, the die 110 resides within the package 130. The die 110 is flip-chip mounted to a surface 212 of the package 130 in an array of bumps 215 (e.g., solder bumps), which couples pins 210 on the die 110 to package pins 220 on the package 130 to provide electrical connections to the die 110. Pins 210 may also be referred to as pads or another term. The space between the die 110 and the surface 212 of the package 130 may be filled with an underfill 218 (e.g., resin). It should be understood that pins 210 and 220, as well as bumps 215, are... Figure 2 It may not be drawn to scale.

[0040] Figure 2 An example of a package 130 is also shown, which is mounted on a substrate 125 (e.g., a PCB) with an array of solder balls 235 (also referred to as a ball grid array (BGA)). This array of solder balls couples pins 230 on the package 130 to pads 240 on the substrate 125. Pins 230 can be coupled to package pins 220 via metal traces (not shown) in the package 130. Pads 240 on the substrate 125 can be coupled to a memory device 120 (in...) via metal traces (not shown) on the substrate 125. Figure 1 (as shown in the figure) and / or embedded in substrate 125.

[0041] Figure 3 An exemplary layout (i.e., layout plan) of a memory interface 115 on a die 110 is shown. In this example, the memory interface 115 includes a first portion 115a and a second portion 115b, the first portion extending along a first side 310 of the die 110, and the second portion extending along a second side 315 of the die 110. Figure 3 In the example shown, the first portion 115a of the memory interface 115 includes eight PHYs placed along the first side 310 of the die 110, and the second portion 115b of the memory interface 115 includes eight PHYs placed along the second side 315 of the die 110. Figure 3Each PHY in the example is shown as a block labeled "PHY". Therefore, a PHY can also be referred to as a PHY block. In this example, each PHY may support one channel capable of sending two bytes (i.e., 16 data bits in parallel) to and receiving two bytes in parallel from memory device 120. However, it should be understood that the PHY is not limited to this example. For illustrative purposes, processor 112 and memory controller 118 are not shown in the example. Figure 3 As shown in the diagram, the processor 112 and the memory controller 118 may be located between the first portion 115a and the second portion 115b of the memory interface 115.

[0042] Figure 4A An exemplary block diagram of PHY 410 is shown according to certain aspects. PHY 410 can be used to implement Figure 3 Each PHY in the PHY diagram shown (i.e., Figure 3 Each PHY in the PHY can be a separate example of PHY 410.

[0043] In this example, PHY 410 includes a first input / output (I / O) circuit 415 and a second I / O circuit 420. The first I / O circuit 415 may include a transmitter (i.e., a driver) for sending bytes (e.g., eight bits in parallel) from memory controller 118 to memory device 120, and a receiver for receiving bytes (e.g., eight bits in parallel) from memory device 120. The second I / O circuit 420 may include a transmitter (i.e., a driver) for sending bytes (e.g., eight bits in parallel) from memory controller 118 to memory device 120, and a receiver for receiving bytes (e.g., eight bits in parallel) from memory device 120. In this example, the first I / O circuit 415 and the second I / O circuit 420 together allow PHY 410 to send two bytes (e.g., 16 bits in parallel) to memory device 120 and receive two bytes (e.g., 16 bits in parallel) from memory device 120.

[0044] PHY 410 also includes a first phase-locked loop (PLL) 425, a second PLL 430, and a multiplexer 440. The first PLL 425 is configured to generate a first clock signal, and the second PLL 430 is configured to generate a second clock signal. The multiplexer 440 has a first input 442, a second input 444, and an output 446. The first input is coupled to the first PLL 425 to receive the first clock signal, the second input is coupled to the second PLL 430 to receive the second clock signal, and the output is coupled to a first I / O circuit 415 and a second I / O circuit 420. The multiplexer 440 is configured (e.g., based on a selection signal from memory controller 118 or another circuit) to select either the first clock signal or the second clock signal and output the selected clock signal to the first I / O circuit 415 and the second I / O circuit 420.

[0045] The first I / O circuit 415 and the second I / O circuit 420 may use a selected clock signal to time the transmission of data bits, command bits, and / or address bits to the memory device 120. The first I / O circuit 415 and the second I / O circuit 420 may also transmit the selected clock signal and / or transmit a clock signal to the memory device 120 based on the selected clock signal (e.g., to time the capture of data bits, command bits, and / or address bits at the memory device 120). The first clock signal from the first PLL 425 and the second clock signal from the second PLL 430 may have different frequencies. This allows the PHY 410 to quickly switch between clock frequencies by using a multiplexer 440 to switch between the first clock signal from the first PLL 425 and the second clock signal from the second PLL 430.

[0046] Figure 4B An exemplary layout of bumps (shown as circles) is illustrated, which couple the PHY 410 to package pins (e.g., package pin 220). In this example, the bumps include bumps for signaling (e.g., transmit data bits, command bits, and / or address bits, and receive data bits and / or data strobe signals), bumps for providing the PHY 410 supply voltage, and bumps for providing a ground connection to the PHY 410.

[0047] return Figure 3 , Figure 3 An example of layout (i.e., layout planning) is shown, where the PHY is arranged in a single column on each of the first side 310 and the second side 315 (i.e., the edges) of the bare die 110. Figure 3 In the example shown, the eight PHYs are arranged in a single column on the first side 310 of the die 110 and the eight PHYs are arranged in a single column on the second side 315 of the die 110.

[0048] Figure 3 The problem with the illustrated layout method is that, as the number of PHYs increases, this layout method can significantly increase the die area and / or cause an imbalance in the aspect ratio of die 110 (e.g., to accommodate more channels for artificial intelligence (AI) applications or high-bandwidth applications). For example, using Figure 3 In the example above, doubling the number of channels (and therefore the number of PHYs) might require doubling the height of die 110 to accommodate the additional PHYs along the first side 310 and the second side 315 of die 110. In this example, the larger die 110 requires a larger package size, which could result in larger bump sizes and larger pitch between the bumps (which could lead to die waste due to bump overhangs). Furthermore, when memory bandwidth (e.g., DDR bandwidth) decreases, Figure 3 The illustrated layout method may result in a loss of pin compatibility.

[0049] To address the aforementioned issues, various aspects of this disclosure provide a PHY layout plan (i.e., a layout) in which at least two columns of PHY are arranged along one side (i.e., the edge) of the die 110, as further discussed below.

[0050] Figure 5 An exemplary layout (i.e., layout plan) of a memory interface 115 on a die 110 is shown according to certain aspects. In this example, the memory interface 115 includes a first portion 115a and a second portion 115b, the first portion extending along a first side 510 of the die 110 and the second portion extending along a second side 515 of the die 110. Figure 5 In the example, sides 510 and 515 (i.e., edges) of bare sheet 110 are opposite sides (i.e., opposing sides) of bare sheet 110, wherein each of sides 510 and 515 extends in a direction 550 (e.g., vertical direction). However, it should be understood that this disclosure is not limited to this example.

[0051] The first portion 115a of the memory interface 115 includes PHYs arranged in two columns along a first side 510 of the die 110. The two columns include a first column 512 comprising a first set of PHYs; and a second column 514 comprising a second set of PHYs. Figure 5 In the example shown, the first group of PHYs in column 512 includes four PHYs, and the second group of PHYs in column 514 includes four PHYs. However, it should be understood that columns 512 and 514 are not limited to this example, and each of columns 512 and 514 may have different... Figure 5 The example shows the number of PHYs. Figure 5Each PHY in the PHY array is shown as a block labeled “PHY”. In this example, each of columns 512 and 514 extends in direction 550 (e.g., vertical), and columns 512 and 514 are arranged side-by-side in direction 555 (e.g., horizontal) perpendicular to direction 550. It should be understood that, depending on the orientation of viewing the bare film 110, the PHYs arranged in columns can also be described as arranged in rows. For example, if... Figure 5 If the bare die 110 shown is rotated 90 degrees, then columns 512 and 514 can be referred to as rows.

[0052] In this example, each of columns 512 and 514 extends in direction 550. The first column 512 has a first width (labeled "W1") in direction 555, and the second column 514 has a second width (labeled "W2") in direction 555, where W1 and W2 may be equal (i.e., columns 512 and 514 have the same width) or different. In this example, the distance (labeled "D") between the first column 512 and the second column 514 in direction 555 is less than the width of each of columns 512 and 514.

[0053] The second portion 115b of the memory interface 115 includes PHYs arranged in two columns along the second side 515 of the die 110. These two columns include a third column 522, which includes a third set of PHYs; and a fourth column 524, which includes a fourth set of PHYs. Figure 5 In the example shown, the third group of PHYs in column 522 includes four PHYs, and the fourth group of PHYs in column 524 includes four PHYs. However, it should be understood that columns 522 and 524 are not limited to this example, and each of columns 522 and 524 may have different PHYs. Figure 5 The example shows the number of PHYs. Figure 5 Each PHY in the PHY is shown as a block labeled “PHY”. In this example, each of columns 522 and 524 extends in direction 550 (e.g., vertical direction), and columns 522 and 524 are arranged side by side in direction 555 (e.g., horizontal direction).

[0054] Due to the arrangement of columns 512 and 514 or 524 and 522, the exemplary PHY layout shown can also be referred to as a stacked PHY layout. As used herein, when PHYs are arranged in an N×M array, PHYs can be stacked, where N is an integer greater than one and M is an integer greater than one. N may correspond to orientation 550, and M may correspond to orientation 555. For example, the PHYs arranged in columns 512 and 514... Figure 5 In the example shown, a 4×2 array. However, it should be understood that columns 512 and 514 are not limited to this example.

[0055] and Figure 3 Compared to the layout shown, Figure 5 The exemplary layout shown (i.e., layout planning) allows the height of the die 110 to be reduced (e.g., by 50%) for a given number of PHYs. This is because Figure 3 The layout shown has the PHY arranged in a single column on each of sides 310 and 315 of the bare die 110, while Figure 5 The exemplary layout shown arranges the PHY in two columns on each of sides 510 and 515.

[0056] In this example, each PHY can support one channel capable of sending two bytes (i.e., 16 data bits in parallel) to and receiving two bytes in parallel from memory device 120. However, it should be understood that the PHY is not limited to this example. In this example, processor 112 and memory controller 118 (in...) Figure 5 (Not shown) It may be located between the first portion 115a and the second portion 115b of the memory interface 115 on the die 110.

[0057] In some respects, Figure 5 The illustrated exemplary layout method can be used to increase the number of PHYs (e.g., to support more channels or greater bandwidth) without significantly increasing the area of ​​die 110 or significantly unbalanced the aspect ratio (e.g., the height-to-width ratio) of die 110. In this respect, Figure 6 The number of PHYs on die 110 is shown to be from eight PHYs (shown on...) Figure 6 The number of PHYs (shown on the left) has been increased to 16. Figure 6 Example (on the right). In Figure 6 In the example shown, the height of die 110 remains constant in orientation 550. This allows die 110 to maintain pin compatibility (e.g., with package 130) and reuse the same substrate 125 (e.g., PCB) and / or package 130. Figure 6 In the example, the width of the die 110 in direction 555 can be slightly increased to accommodate additional columns of the PHY on each side 510 and 515 of the die 110.

[0058] Figure 7A An exemplary block diagram of a first PHY 710a and a second PHY 710b according to certain aspects is shown. The first PHY 710a and the second PHY 710b are arranged side by side in a direction of 555 (e.g., a horizontal direction). The first PHY 710a and the second PHY 710b can be used to implement Figure 5 and Figure 6Each pair of parallel PHYs shown is configured such that the first PHY 710a and the second PHY 710b are located in two adjacent columns (e.g., the first PHY 710a is located in column 512 adjacent to the first side 510 of the die 110, and the second PHY 710b is located in column 512 adjacent to the first side 510 of the die 110). Figure 5 (As shown in column 512, adjacent to column 514). As used herein, two columns are adjacent when the distance between them is less than the width of each column in the column. For example, in Figure 5 In the example, columns 512 and 514 are adjacent because the distance between columns 512 and 514 (labeled "D") is less than the width of each of the first column 512 and the second column 514 (labeled "W1" and "W2" respectively).

[0059] In this example, the first PHY 710a includes a first I / O circuit 715a and a second I / O circuit 720a. The first I / O circuit 715a may include a transmitter (i.e., a driver) for sending bytes (e.g., eight bits in parallel) from memory controller 118 to memory device 120, and a receiver for receiving bytes (e.g., eight bits in parallel) from memory device 120. The second I / O circuit 720a may include a transmitter (i.e., a driver) for sending bytes (e.g., eight bits in parallel) from memory controller 118 to memory device 120, and a receiver for receiving bytes (e.g., eight bits in parallel) from memory device 120. In this example, the first I / O circuit 715a and the second I / O circuit 720a together allow the first PHY 710a to send two bytes (e.g., 16 bits in parallel) to memory device 120 and receive two bytes (e.g., 16 bits in parallel) from memory device 120. However, it should be understood that the first PHY 710a is not limited to this example.

[0060] The first PHY 710a also includes a first PLL 725a, a second PLL 730a, and a multiplexer 740a. The first PLL 725a is configured to generate a first clock signal, and the second PLL 730a is configured to generate a second clock signal. The multiplexer 740a has a first input 742a, a second input 744a, and an output 746a. The first input is coupled to the first PLL 725a to receive the first clock signal, the second input is coupled to the second PLL 730a to receive the second clock signal, and the output is coupled to a first I / O circuit 715a and a second I / O circuit 720a. The multiplexer 740a is configured (e.g., based on a selection signal from a memory controller 118 or another circuit) to select either the first clock signal or the second clock signal and output the selected clock signal to the first I / O circuit 715a and the second I / O circuit 720a.

[0061] The first I / O circuit 715a and the second I / O circuit 720a can use a selected clock signal to time the transmission of data bits, command bits, and / or address bits to the memory device 120. The first I / O circuit 715a and the second I / O circuit 720a can also transmit the selected clock signal and / or transmit a clock signal to the memory device 120 based on the selected clock signal (e.g., to time the capture of data bits, command bits, and / or address bits at the memory device 120). The first clock signal from the first PLL 725a and the second clock signal from the second PLL 730a can have different frequencies. This allows the first PHY 710a to quickly switch between clock frequencies by using a multiplexer 740a to switch between the first clock signal from the first PLL 725a and the second clock signal from the second PLL 730a.

[0062] In this example, the second PHY 710b includes a first I / O circuit 715b and a second I / O circuit 720b. The first I / O circuit 715b may include a transmitter (i.e., a driver) for sending bytes (e.g., eight bits in parallel) to memory device 120, and a receiver for receiving bytes (e.g., eight bits in parallel) from memory device 120. The second I / O circuit 720b may include a transmitter (i.e., a driver) for sending bytes (e.g., eight bits in parallel) to memory device 120, and a receiver for receiving bytes (e.g., eight bits in parallel) from memory device 120. In this example, the first I / O circuit 715b and the second I / O circuit 720b together allow the second PHY 710b to send two bytes (e.g., 16 bits in parallel) to memory device 120 and receive two bytes (e.g., 16 bits in parallel) from memory device 120. However, it should be understood that the second PHY 710b is not limited to this example.

[0063] The second PHY 710b also includes a first PLL 725b, a second PLL 730b, and a multiplexer 740b. The first PLL 725b is configured to generate a first clock signal, and the second PLL 730b is configured to generate a second clock signal. The multiplexer 740b has a first input 742b, a second input 744b, and an output 746b. The first input is coupled to the first PLL 725b to receive the first clock signal, the second input is coupled to the second PLL 730b to receive the second clock signal, and the output is coupled to a first I / O circuit 715b and a second I / O circuit 720b. The multiplexer 740b is configured (e.g., based on a selection signal from memory controller 118 or another circuit) to select either the first clock signal or the second clock signal and output the selected clock signal to the first I / O circuit 715b and the second I / O circuit 720b.

[0064] The first I / O circuit 715b and the second I / O circuit 720b can use a selected clock signal to time the transmission of data bits, command bits, and / or address bits to the memory device 120. The first I / O circuit 715b and the second I / O circuit 720b can also transmit the selected clock signal and / or transmit a clock signal to the memory device 120 based on the selected clock signal (e.g., to time the capture of data bits, command bits, and / or address bits at the memory device 120). The first clock signal from the first PLL 725b and the second clock signal from the second PLL 730b can have different frequencies. This allows the second PHY 710b to quickly switch between clock frequencies by using a multiplexer 740b to switch between the first clock signal from the first PLL 725b and the second clock signal from the second PLL 730b.

[0065] Figure 7B An exemplary layout of bumps (shown as circles) is illustrated, which couple a first PHY 710a and a second PHY 710b to package pins (e.g., package pin 220). In this example, the bumps include bumps for routing signals (e.g., data bits, command bits, and address bits) between the first PHY 710a and the package (e.g., package 130), bumps for providing a supply voltage for the first PHY 710a, and bumps for providing a ground connection for the first PHY 710a. The bumps also include bumps for routing signals (e.g., data bits, command bits, and address bits) between the second PHY 710b and the package (e.g., package 130), bumps for providing a supply voltage for the second PHY 710b, and bumps for providing a ground connection for the second PHY 710b. Figure 7B In the diagram, the bumps are shown as circles, with signal bumps shown as solid lines, supply bumps as dotted lines, and ground bumps as dashed lines.

[0066] In some respects, the distance between the first PHY 710a and the second PHY 710b is equal to or less than the shortest distance (i.e., pitch) between the centers of the bumps on the die 110. This helps PHY 710a and 710b to make efficient use of the bumps by allowing the bumps for PHY 710a and 710b to be placed close together and / or allowing PHY 710a and 710b to share one or more bumps, as discussed further below.

[0067] Figure 8A An exemplary layout is shown, in which... Figure 7A Compared to the example shown, the first PHY 710a and the second PHY 710b are placed closer together, and Figure 8BAn exemplary layout of bumps (shown as circles) is illustrated, which couple the first PHY 710a and the second PHY 710b to package pins (e.g., package pin 220). In this example, the first PHY 710a and the second PHY 710b share supply bumps and ground bumps, thereby reducing the number of bumps. Figure 8B In the example shown, each supply bump overlaps with the first PHY 710a and the second PHY 710b and provides a supply voltage to both. Each ground bump overlaps with the first PHY 710a and the second PHY 710b and provides a ground connection to both. As used herein, a supply bump is a bump that provides a supply voltage (e.g., from an external voltage source), and a ground bump is a bump that provides a connection to ground.

[0068] In some respects, the first PHY 710a and the second PHY 710b share clock resources. As used herein, shared clock resources may include shared clock generation circuitry (e.g., a shared PLL), shared clock wiring, and / or shared clock switching circuitry (e.g., a shared multiplexer). In this respect, Figure 9A An exemplary specific implementation of a shared PLL for a first PHY 710a and a second PHY 710b is shown, as further discussed below. In this example, the first PHY 710a includes the first I / O circuit 715a and the second I / O circuit 720a discussed above, and the second PHY 710b includes the first I / O circuit 715b and the second I / O circuit 720b discussed above.

[0069] exist Figure 9A In the example shown, the first PHY 710a includes a substitution Figure 7A and Figure 8A The first PLL 725a and the second PLL 730a shown are first PLL 910, and the second PHY 710b includes a replacement Figure 7A and Figure 8AThe first PLL 725b and the second PLL 730b are shown with a second PLL 915. The first PLL 910 is configured to generate a first clock signal, and the second PLL 915 is configured to generate a second clock signal, which may have a frequency different from the first clock signal. In this example, the first PHY 710a and the second PHY 710b share the first PLL 910 and the second PLL 915. This reduces the number of PLLs in the first PHY 710a and the second PHY 710b from four PLLs (i.e., PLLs 725a, 730a, 725b, and 730b) to two PLLs (i.e., PLLs 910 and 915), thereby reducing the effective power and leakage power associated with the PLLs.

[0070] In this example, the first PHY 710a includes a first multiplexer 920. The first multiplexer 920 has a first input 922, a second input 924, and an output 926. The first input is coupled to a first PLL 910 to receive a first clock signal, the second input is coupled to a second PLL 915 in the second PHY 710b to receive a second clock signal, and the output is coupled to a first I / O circuit 715a and a second I / O circuit 720a in the first PHY 710a. The first multiplexer 920 is configured (e.g., based on a selection signal from a memory controller 118 or another circuit) to select either the first clock signal or the second clock signal and output the selected clock signal to the first I / O circuit 715a and the second I / O circuit 720a.

[0071] As discussed above, the first I / O circuit 715a and the second I / O circuit 720a may use a selected clock signal to time the transmission of data bits, command bits, and / or address bits to the memory device 120. The first I / O circuit 715a and the second I / O circuit 720a may also transmit the selected clock signal and / or transmit a clock signal to the memory device 120 based on the selected clock signal (e.g., to time the capture of data bits, command bits, and / or address bits at the memory device 120).

[0072] In this example, the second PHY 710b includes a second multiplexer 930. The second multiplexer 930 has a first input 932, a second input 934, and an output 936. The first input is coupled to a first PLL 910 in the first PHY 710a to receive a first clock signal, the second input is coupled to a second PLL 915 to receive a second clock signal, and the output is coupled to a first I / O circuit 715b and a second I / O circuit 720b in the second PHY 710b. The second multiplexer 930 is configured (e.g., based on a selection signal from a memory controller 118 or another circuit) to select either the first clock signal or the second clock signal and output the selected clock signal to the first I / O circuit 715b and the second I / O circuit 720b.

[0073] As discussed above, the first I / O circuit 715b and the second I / O circuit 720b can use a selected clock signal to time the transmission of data bits, command bits, and / or address bits to the memory device 120. The first I / O circuit 715b and the second I / O circuit 720b can also transmit the selected clock signal and / or transmit a clock signal to the memory device 120 based on the selected clock signal (e.g., to time the capture of data bits, command bits, and / or address bits at the memory device 120).

[0074] In some aspects, the first multiplexer 920 and the second multiplexer 930 may receive the same selection signal (e.g., from memory controller 118 or another circuit). In this example, the first multiplexer 920 and the second multiplexer 930 select the same clock signal for both PHY 710a and 710b. In another example, the first multiplexer 920 and the second multiplexer 930 may receive separate selection signals (e.g., from memory controller 118 or another circuit). In this example, the first multiplexer 920 and the second multiplexer 930 select the same clock signal or different clock signals based on their respective selection signals.

[0075] Figure 9B An exemplary layout of bumps (shown as circles) is illustrated, which couple the first PHY 710a and the second PHY 710b to package pins (e.g., package pin 220). In this example, the bumps include bumps for routing signals (e.g., data bits, command bits, and address bits) between the first PHY 710a and package 130, and bumps for routing signals (e.g., data bits, command bits, and address bits) between the second PHY 710b and package 130. In this example, the bumps also include supply bumps and ground bumps shared by the first PHY 710a and the second PHY 710b. Figure 9BIn the example shown, each supply bump overlaps with the first PHY 710a and the second PHY 710b, providing a supply voltage to both. Each ground bump overlaps with the first PHY 710a and the second PHY 710b, providing a ground connection to both. However, it should be understood that this disclosure is not limited to this example. In other specific embodiments, the first PHY 710a and the second PHY 710b may have different supply bumps and / or different ground bumps. Figure 9B In the diagram, the bumps are shown as circles, with signal bumps shown as solid lines, supply bumps as dotted lines, and ground bumps as dashed lines.

[0076] Figure 10 An example is shown where the second multiplexer 930 is omitted and the first PHY 710a and the second PHY 710b share the first multiplexer 920. In this example, the output 926 of the first multiplexer 920 is also coupled to the first I / O circuit 715b and the second I / O circuit 720b of the second PHY 710b. In this example, since PHYs 710a and 710b share the first multiplexer 920, the same clock signal is selected for both PHYs 710a and 710b. In this example, the bump layout for the first PHY 710a and the second PHY 710b can be... Figure 9B The exemplary layouts shown are the same or similar. Although the first multiplexer 920 is in... Figure 10 The example shown is located in the first PHY 710a, but it should be understood that the first multiplexer 920 may be located in the second PHY 710b in other specific implementations.

[0077] Figure 11 An example of a shared clock resource (e.g., PLL) for the PHY on each of sides 510 and 515 of die 110 is shown. The shared clock resource reduces the power consumption associated with clock generation in memory interface 115.

[0078] In this example, the first portion 115a of the memory interface 115 includes a first clock circuit 1110 located between the PHYs in column 512. Figure 11 In the example shown, the first clock circuit 1110 is centrally located in the first portion 115a of the memory interface 115, between the first group of PHYs 1112 and the second group of PHYs 1114. However, it should be understood that the first clock circuit 1110 is not limited to this example. The first clock circuit 1110 is configured to output a clock signal via… Figure 11The exemplary clock wiring 1115 shown is distributed to each PHY in the first portion 115a of the memory interface 115. See below for reference. Figure 12 An exemplary specific implementation of the clock circuit 1110 is discussed. Each PHY in the PHY can use a clock signal provided by the first clock circuit 1110 to time the transmission of corresponding data bits, command bits, and / or address bits to the memory device 120. Each PHY can also transmit the clock signal provided by the first clock circuit 1110 and / or transmit a clock signal to the memory device 120 based on the clock signal provided by the first clock circuit 1110.

[0079] In this example, the second portion 115b of the memory interface 115 includes a second clock circuit 1120 located between the PHYs in column 522. Figure 11 In the example shown, the second clock circuit 1120 is centrally located in the second portion 115b of the memory interface 115, between the first group of PHYs 1122 and the second group of PHYs 1124. However, it should be understood that the second clock circuit 1120 is not limited to this example. The second clock circuit 1120 is configured to output a clock signal via… Figure 11 The exemplary clock wiring 1125 shown is assigned to each PHY in the second portion 115b of the memory interface 115. Each PHY can use a clock signal provided by the second clock circuit 1120 to time the transmission of data bits, command bits, and / or address bits to the memory device 120. Each PHY can also transmit the clock signal provided by the second clock circuit 1120 and / or transmit a clock signal to the memory device 120 based on the clock signal provided by the second clock circuit 1120.

[0080] Figure 12 An example implementation of a first clock circuit 1110 according to certain aspects of this disclosure is shown. The second clock circuit 1120 may also... Figure 12 The exemplary specific implementation shown is as follows. Figure 12 Exemplary specific implementations of a first PHY 710a and a second PHY 710b according to certain aspects are also shown. The first PHY 710a and the second PHY 710b are arranged side by side and can be used to implement Figure 11 Each pair of parallel PHYs shown.

[0081] In this example, clock circuit 1110 includes a first PLL 1210, a second PLL 1220, and a multiplexer 1230. The first PLL 1210 is configured to generate a first clock signal, and the second PLL 1220 is configured to generate a second clock signal, which may have a frequency different from the first clock signal. Multiplexer 1230 has a first input 1232, a second input 1234, and an output 1236. The first input is coupled to the first PLL 1210 to receive the first clock signal, the second input is coupled to the second PLL 1220 to receive the second clock signal, and the output is coupled to clock wiring 1115. Multiplexer 1230 is configured (e.g., based on a selection signal from memory controller 118 or another circuit) to select either the first clock signal or the second clock signal and output the selected clock signal to clock wiring 1115, which can distribute the selected clock signal to each PHY in the first portion 115a of memory interface 115.

[0082] exist Figure 12 In the example shown, the first PHY 710a includes the first I / O circuit 715a and the second I / O circuit 720a discussed above. In this example, the first I / O circuit 715a and the second I / O circuit 720a are coupled to clock wiring 1115 to receive a selected clock signal from the first clock circuit 1110. The first I / O circuit 715a and the second I / O circuit 720a can use the selected clock signal to time the transmission of data bits, command bits, and / or address bits to the memory device 120. The first I / O circuit 715a and the second I / O circuit 720a can also transmit the selected clock signal and / or transmit a clock signal to the memory device 120 based on the selected clock signal (e.g., to time the capture of data bits, command bits, and / or address bits at the memory device 120).

[0083] exist Figure 12 In the example shown, the second PHY 710b includes the first I / O circuit 715b and the second I / O circuit 720b discussed above. In this example, the first I / O circuit 715b and the second I / O circuit 720b are coupled to clock wiring 1115 to receive a selected clock signal from the first clock circuit 1110. The first I / O circuit 715b and the second I / O circuit 720b can use the selected clock signal to time the transmission of data bits, command bits, and / or address bits to memory device 120. The first I / O circuit 715b and the second I / O circuit 720b can also transmit the selected clock signal and / or transmit a clock signal to memory device 120 based on the selected clock signal (e.g., to time the capture of data bits, command bits, and / or address bits at memory device 120).

[0084] Figure 13AAn example of a first I / O circuit 715a according to certain aspects is shown. In this example, the first I / O circuit 715a includes a set of receivers 1320 configured to receive data from a memory device 120. For example, the set of receivers 1320 may include at least eight receivers (labeled “DQ_RX0” to “DQ_RX7”) configured to receive at least eight data bits from the memory device 120 in parallel, wherein each of the receivers may be configured to receive a corresponding data bit from the memory device 120. The receivers may be connected via corresponding signal bumps (e.g., Figure 7B , Figure 8B and Figure 9B The exemplary signal bumps shown in any of the examples are coupled to package 130 to receive corresponding data bits. This set of receivers 1320 may be coupled to memory controller 118 via signal wiring (not shown) on die 110.

[0085] In this example, the first I / O circuit 715a further includes a first set of transmitters 1310 and a second set of transmitters 1315, which are configured to transmit data and write clock signals to the memory device 120. The first set of transmitters 1310 includes transmitters (labeled "DQ_TX0" to "DQ_TX3"), each of which is configured to send a corresponding bit to the memory device 120. The second set of transmitters 1315 includes transmitters (labeled "DQ_TX4" to "DQ_TX7"), each of which is configured to send a corresponding data bit to the memory device 120. The transmitters in the first set of transmitters 1310 and the second set of transmitters 1315 may collectively include at least eight transmitters to transmit at least eight data bits in parallel.

[0086] The second set of transmitters 1315 may further include a write clock transmitter (labeled "WCK_TX") configured to generate a write clock signal WCK based on a clock signal received by the first I / O circuit 715a (e.g., a selected clock signal from any PLL of the exemplary PLLs discussed above), and to transmit the write clock signal WCK to the memory device 120. The write clock signal WCK may be a single-ended clock signal or a differential clock signal. The transmitters in the first set of transmitters 1310 and the second set of transmitters 1315 may time the transmission of corresponding bits based on the clock signal received by the first I / O circuit 715a.

[0087] The transmitters in the first group of transmitters 1310 and the second group of transmitters 1315 can be transmitted via corresponding signal bumps (e.g., Figure 7B , Figure 8B and Figure 9BAn exemplary signal bump (as shown in any of the examples) is coupled to package 130 to transmit corresponding data bits. In some aspects, the transmitter and receiver may share signal bumps, with each signal bump in the shared signal bumps coupled to a corresponding receiver and a corresponding transmitter. The transmitters in the first set of transmitters 1310 and the second set of transmitters 1315 may be coupled to memory controller 118 via signal wiring (not shown) on die 110.

[0088] exist Figure 13A In the example shown, the set of receivers 1320 is located between the first set of transmitters 1310 and the second set of transmitters 1315. The receivers in the set of receivers 1320 can be configured to receive one byte of data (e.g., eight data bits in parallel). The transmitters in the first set of transmitters 1310 and the second set of transmitters 1315 can be jointly configured to transmit one byte of data (e.g., eight data bits in parallel). In this example, a first portion of the byte is transmitted by the transmitter in the first set of transmitters 1310, and a second portion of the byte is transmitted by the transmitter in the second set of transmitters 1315.

[0089] It should be understood that the receiver is not limited to receiving one byte of data, and the transmitter is not limited to transmitting one byte of data. For example, in other embodiments, the set of receivers 1320 may include one or more additional receivers to receive twelve, sixteen, or another number of data bits in parallel, and the first set of transmitters 1310 and the second set of transmitters 1315 may include one or more additional transmitters to transmit twelve, sixteen, or another number of data bits in parallel. Furthermore, in some embodiments, the set of receivers 1320 may also include additional receivers for receiving data mask bits from the memory device 120, and the first set of transmitters 1310 and the second set of transmitters 1315 may include additional transmitters for sending data mask bits to the memory device 120 (e.g., for writing a data mask).

[0090] Figure 13B An example of a second I / O circuit 720a according to certain aspects is shown. In this example, the second I / O circuit 720a includes a set of receivers 1340 configured to receive data from a memory device 120. For example, the set of receivers 1340 may include at least eight receivers (labeled “DQ_RX0” to “DQ_RX7”) configured to receive at least eight data bits from the memory device 120 in parallel, wherein each of the receivers may be configured to receive a corresponding data bit from the memory device 120. The receivers may be connected via corresponding signal bumps (e.g., Figure 7B , Figure 8B and Figure 9B The exemplary signal bump shown in any of the examples is coupled to package 130 to receive the corresponding data bit. The receiver may be coupled to memory controller 118 via signal wiring (not shown) on die 110.

[0091] In this example, the second I / O circuit 720a further includes a first set of transmitters 1330 and a second set of transmitters 1335, which are configured to transmit data and write clock signals to the memory device 120. The first set of transmitters 1330 includes transmitters (labeled "DQ_TX0" to "DQ_TX3"), each of which is configured to send a corresponding data bit to the memory device 120. The second set of transmitters 1335 includes transmitters (labeled "DQ_TX4" to "DQ_TX7"), each of which is configured to send a corresponding data bit to the memory device 120. The transmitters in the first set of transmitters 1330 and the second set of transmitters 1335 may collectively include at least eight transmitters to transmit at least eight data bits in parallel.

[0092] The second set of transmitters 1335 may further include a write clock transmitter (labeled "WCK_TX") configured to generate a write clock signal WCK based on a clock signal received by the second IO circuit 720a (e.g., a selected clock signal from any of the exemplary PLLs discussed above), and to transmit the write clock signal WCK to the memory device 120. The write clock signal WCK may be a single-ended clock signal or a differential clock signal. The transmitters in the first set of transmitters 1330 and the second set of transmitters 1335 may time the transmission of corresponding data bits based on the clock signal received by the second IO circuit 720a.

[0093] The transmitters in the first group of transmitters 1330 and the second group of transmitters 1335 can be transmitted via corresponding signal bumps (e.g., Figure 7B , Figure 8B and Figure 9B An exemplary signal bump (as shown in any of the examples) is coupled to package 130 to transmit corresponding data bits. In some aspects, the transmitter and receiver may share signal bumps, with each signal bump in the shared signal bumps coupled to a corresponding receiver and a corresponding transmitter. The transmitters in the first set of transmitters 1330 and the second set of transmitters 1335 may be coupled to memory controller 118 via signal wiring (not shown) on die 110.

[0094] exist Figure 13BIn the example shown, the set of receivers 1340 is located between the first set of transmitters 1330 and the second set of transmitters 1335. The receivers in the set of receivers 1340 can be configured to receive one byte of data (e.g., eight data bits in parallel). The transmitters in the first set of transmitters 1330 and the second set of transmitters 1335 can be jointly configured to transmit one byte of data (e.g., eight data bits in parallel). In this example, a first portion of the byte is transmitted by the transmitter in the first set of transmitters 1330, and a second portion of the byte is transmitted by the transmitter in the second set of transmitters 1335. It should be understood that the receivers are not limited to receiving one byte of data, and the transmitters are not limited to transmitting one byte of data.

[0095] In this example, the second I / O circuit 720a may also include a set of transmitters 1350 for transmitting command and address signals to the memory device 120. The transmitters in this set of transmitters 1350 may be transmitted via corresponding signal bumps (e.g., Figure 7B , Figure 8B and Figure 9B The exemplary signal bumps shown in any of the examples are coupled to package 130 to send corresponding commands and address bits. The transmitters in this set of transmitters 1350 can be coupled to memory controller 118 via signal wiring (not shown) on die 110.

[0096] It should be understood that the receiver is not limited to receiving one byte of data, and the transmitter is not limited to transmitting one byte of data. For example, in other embodiments, the set of receivers 1340 may include one or more additional receivers to receive twelve, sixteen, or another number of data bits in parallel, and the first set of transmitters 1330 and the second set of transmitters 1335 may include one or more additional transmitters to transmit twelve, sixteen, or another number of data bits in parallel. Furthermore, in some embodiments, the set of receivers 1340 may also include additional receivers for receiving data mask bits from the memory device 120, and the first set of transmitters 1330 and the second set of transmitters 1335 may include additional transmitters for sending data mask bits to the memory device 120 (e.g., for writing a data mask).

[0097] It should also be understood that the transmitter for command and address signals may be located in the first IO circuit 715a in other embodiments, or the transmitter for command and address signals may be separated between the first IO circuit 715a and the second IO circuit 720a in other embodiments.

[0098] It should be understood that the receiver and transmitter in the first IO circuit 715a are not limited to Figure 13AThe exemplary arrangement shown is an example of a layout plan. In this respect, Figure 14A An example of a first I / O circuit 715a including a group of transmitters 1410 arranged in a column is shown, wherein the group of transmitters 1410 includes Figure 13A The transmitters in the first group of transmitters 1310 and the second group of transmitters 1315 are shown. Furthermore, in this example, the receivers in the group of receivers 1320 are also arranged in columns, wherein each receiver in the group of receivers 1320 may be placed side-by-side with a corresponding transmitter in the group of transmitters 1410. However, it should be understood that this disclosure is not limited to this example. It should be understood that, depending on the orientation of the first IO circuit 715a, the transmitters or receivers arranged in columns can also be described as arranged in rows.

[0099] It should be understood that the receiver and transmitter in the second IO circuit 720a are not limited to Figure 13B The exemplary arrangement shown is an example of a layout plan. In this respect, Figure 14B An example of a second I / O circuit 720a including a set of transmitters 1420 arranged in a column is shown, wherein the set of transmitters 1420 includes Figure 13B The transmitters in the first group of transmitters 1330 and the second group of transmitters 1335 are shown. Furthermore, in this example, the receivers in the group of receivers 1340 are also arranged in a column, wherein each receiver in the group of receivers 1340 may be placed side-by-side with a corresponding transmitter in the group of transmitters 1420. However, it should be understood that this disclosure is not limited to this example.

[0100] Specific implementation examples are described in the following numbered clauses:

[0101] 1. A system comprising:

[0102] The bare die includes:

[0103] A first group of physical layer (PHY) blocks, arranged in a first column, wherein the first column extends along one side of the bare die; and

[0104] The second group of PHY blocks is arranged in a second column adjacent to the first column, wherein the first group of PHY blocks includes a first PHY block, the second group of PHY blocks includes a second PHY block, and the first PHY block and the second PHY block share one or more clock resources.

[0105] 2. The system according to Clause 1, wherein said one or more clock resources include:

[0106] A first locked loop (PLL), located within the first PHY block, is configured to generate a first clock signal; and

[0107] A second PLL, located in the second PHY block, is configured to generate a second clock signal having a frequency different from the first clock signal.

[0108] 3. The system according to Clause 2, wherein the first PHY block comprises:

[0109] First input / output (IO) circuit;

[0110] Second I / O circuit; and

[0111] A first multiplexer has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to a first PLL, the second input terminal is coupled to a second PLL, and the output terminal is coupled to a first I / O circuit and a second I / O circuit.

[0112] 4. The system according to Clause 3, wherein each of the first IO circuit and the second IO circuit includes at least eight transmitters configured to transmit at least eight bits in parallel.

[0113] 5. The system according to Clause 4, wherein each of the first IO circuit and the second IO circuit includes at least eight receivers configured to receive at least eight bits in parallel.

[0114] 6. The system according to any one of clauses 3 to 5, wherein the second PHY block comprises:

[0115] Third I / O circuit;

[0116] Fourth I / O circuit; and

[0117] The second multiplexer has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the first PLL, the second input terminal is coupled to the second PLL, and the output terminal is coupled to the third I / O circuit and the fourth I / O circuit.

[0118] 7. The system according to Clause 2, wherein the first PHY block comprises:

[0119] First input / output (IO) circuit;

[0120] Second I / O circuit; and

[0121] A multiplexer having a first input terminal, a second input terminal, and an output terminal, the first input terminal being coupled to a first PLL, the second input terminal being coupled to a second PLL, and the output terminal being coupled to a first I / O circuit and a second I / O circuit.

[0122] 8. The system according to Clause 7, wherein the second PHY block comprises:

[0123] Third I / O circuit; and

[0124] A fourth I / O circuit, wherein the output of the multiplexer is coupled to the third I / O circuit and the fourth I / O circuit.

[0125] 9. The system according to Clause 2, wherein said one or more clock resources include:

[0126] A first locked loop (PLL) is configured to generate a first clock signal; and

[0127] A second PLL is configured to generate a second clock signal having a frequency different from that of the first clock signal.

[0128] 10. The system according to Clause 9, further comprising a multiplexer having a first input, a second input, and an output, the first input being coupled to a first PLL, the second input being coupled to a second PLL, and the output being coupled to each of a first set of PHY blocks including the first PHY block and to each of a second set of PHY blocks including the second PHY block.

[0129] 11. The system according to Clause 9 or 10, wherein the first PLL and the second PLL are located between a first portion of the first group of PHY blocks and a second portion of the first group of PHY blocks.

[0130] 12. The system according to any one of clauses 1 to 11, wherein the system further comprises:

[0131] Packages; and

[0132] The bump electrically couples the first PHY block and the second PHY block to pins on the package.

[0133] 13. The system according to Clause 12, wherein the bump includes one or more supply bumps that overlap with the first PHY block and the second PHY block.

[0134] 14. The system according to clause 12 or 13, wherein the bump includes one or more ground bumps that overlap with the first PHY block and the second PHY block.

[0135] 15. The system according to any one of clauses 12 to 14, wherein the system further comprises:

[0136] Substrate, wherein the package is mounted on the substrate; and

[0137] A memory device mounted on the substrate, wherein the memory device is electrically coupled to the pins on the package.

[0138] 16. The system according to any one of clauses 1 to 15, wherein:

[0139] Each of the first column and the second column extends in a first direction;

[0140] The first column has a first width in a second direction perpendicular to the first direction;

[0141] The second column has a second width in the second direction; and

[0142] The distance between the first column and the second column in the second direction is less than each of the first width and the second width.

[0143] 17. A system comprising:

[0144] A bare die, the bare die including a physical layer (PHY) block arranged in at least two columns, wherein a first column of the at least two columns extends along one side of the bare die, and a second column of the at least two columns is adjacent to the first column, the PHY block including a first PHY block in the first column and a second PHY block in the second column, and the first PHY block and the second PHY block sharing one or more clock resources.

[0145] 18. The system according to Clause 17, wherein said one or more clock resources include:

[0146] A first locked loop (PLL), located within the first PHY block, is configured to generate a first clock signal; and

[0147] A second PLL, located in the second PHY block, is configured to generate a second clock signal having a frequency different from the first clock signal.

[0148] 19. The system according to Clause 18, wherein the first PHY block comprises:

[0149] First input / output (IO) circuit;

[0150] Second I / O circuit; and

[0151] A first multiplexer has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to a first PLL, the second input terminal is coupled to a second PLL, and the output terminal is coupled to a first I / O circuit and a second I / O circuit.

[0152] 20. The system according to Clause 19, wherein each of the first I / O circuit and the second I / O circuit includes at least eight transmitters configured to transmit at least eight bits in parallel.

[0153] 21. The system according to Clause 20, wherein each of the first I / O circuit and the second I / O circuit includes at least eight receivers configured to receive at least eight bits in parallel.

[0154] 22. The system according to any one of clauses 19 to 21, wherein the second PHY block comprises:

[0155] Third I / O circuit;

[0156] Fourth I / O circuit; and

[0157] The second multiplexer has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the first PLL, the second input terminal is coupled to the second PLL, and the output terminal is coupled to the third I / O circuit and the fourth I / O circuit.

[0158] 23. The system according to Clause 18, wherein the first PHY block comprises:

[0159] First input / output (IO) circuit;

[0160] Second I / O circuit; and

[0161] A multiplexer having a first input terminal, a second input terminal, and an output terminal, the first input terminal being coupled to a first PLL, the second input terminal being coupled to a second PLL, and the output terminal being coupled to a first I / O circuit and a second I / O circuit.

[0162] 24. The system according to Clause 23, wherein the second PHY block comprises:

[0163] Third I / O circuit; and

[0164] A fourth I / O circuit, wherein the output of the multiplexer is coupled to the third I / O circuit and the fourth I / O circuit.

[0165] 25. The system according to Clause 17, further comprising:

[0166] Packages; and

[0167] The bump electrically couples the first PHY block and the second PHY block to pins on the package.

[0168] 26. The system according to Clause 25, wherein the bump includes one or more supply bumps that overlap with the first PHY block and the second PHY block.

[0169] 27. The system according to clause 25 or 26, wherein the bump includes one or more ground bumps that overlap with the first PHY block and the second PHY block.

[0170] 28. The system according to any one of clauses 25 to 27, wherein the system further comprises:

[0171] Substrate, wherein the package is mounted on the substrate; and

[0172] A memory device mounted on the substrate, wherein the memory device is electrically coupled to the pins on the package.

[0173] 29. The system according to any one of clauses 17 to 28, wherein:

[0174] Each of the first column and the second column extends in a first direction;

[0175] The first column has a first width in a second direction perpendicular to the first direction;

[0176] The second column has a second width in the second direction; and

[0177] The distance between the first column and the second column in the second direction is less than each of the first width and the second width.

[0178] The use of designations such as "first" and "second" to designate elements herein does not generally limit the number or order of those elements. Rather, these designations are used herein as a convenient way to distinguish two or more elements or instances of elements. Therefore, a reference to a first element and a second element does not imply that only two elements can be used, or that the first element must precede the second element. Furthermore, it should be understood that the elements are not limited to the numerical designations used above to describe various aspects of this disclosure. For example, the first I / O circuit 715b and the second I / O circuit 720b in the second PHY 710b may also be referred to as the third I / O circuit and the fourth I / O circuit, respectively, to distinguish these I / O circuits from the first I / O circuit 715a and the second I / O circuit 720a in the first PHY 710a.

[0179] Within this disclosure, the term "exemplary" is used to mean "serving as an example, instance, or illustration." Any specific implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term "aspect" does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. As used herein, the term "coupled" means electrical coupling and can refer to direct or indirect electrical coupling between two structures. It should also be understood that the term "grounded" can refer to DC ground or AC ground, and therefore the term "grounded" covers both possibilities. As used herein, "approximately" means within 90 percent to 110 percent of the stated values.

[0180] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Thus, this disclosure is not intended to be limited to the examples described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A system comprising: The bare die includes: A first group of physical layer (PHY) blocks, arranged in a first column, wherein the first column extends along one side of the bare die; and The second group of PHY blocks is arranged in a second column adjacent to the first column, wherein the first group of PHY blocks includes a first PHY block, the second group of PHY blocks includes a second PHY block, and the first PHY block and the second PHY block share one or more clock resources.

2. The system of claim 1, wherein the one or more clock resources include: A first locked loop (PLL) is located in the first PHY block, wherein the first PLL is configured to generate a first clock signal; and A second PLL, located in the second PHY block, is configured to generate a second clock signal having a frequency different from the first clock signal.

3. The system according to claim 2, wherein the first PHY block comprises: First input / output (IO) circuit; Second I / O circuit; and A first multiplexer has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to a first PLL, the second input terminal is coupled to a second PLL, and the output terminal is coupled to a first I / O circuit and a second I / O circuit.

4. The system of claim 3, wherein each of the first I / O circuit and the second I / O circuit comprises at least eight transmitters configured to transmit at least eight bits in parallel.

5. The system of claim 4, wherein each of the first I / O circuit and the second I / O circuit comprises at least eight receivers configured to receive at least eight bits in parallel.

6. The system of claim 3, wherein the second PHY block comprises: Third I / O circuit; Fourth I / O circuit; and The second multiplexer has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the first PLL, the second input terminal is coupled to the second PLL, and the output terminal is coupled to the third I / O circuit and the fourth I / O circuit.

7. The system according to claim 2, wherein the first PHY block comprises: First input / output (IO) circuit; Second I / O circuit; and A multiplexer having a first input terminal, a second input terminal, and an output terminal, the first input terminal being coupled to a first PLL, the second input terminal being coupled to a second PLL, and the output terminal being coupled to a first I / O circuit and a second I / O circuit.

8. The system of claim 7, wherein the second PHY block comprises: Third I / O circuit; and A fourth I / O circuit, wherein the output of the multiplexer is coupled to the third I / O circuit and the fourth I / O circuit.

9. The system of claim 1, wherein the one or more clock resources include: A first locking loop (PLL) is configured to generate a first clock signal; and A second PLL is configured to generate a second clock signal having a frequency different from that of the first clock signal.

10. The system of claim 9, further comprising a multiplexer having a first input, a second input, and an output, the first input being coupled to a first PLL, the second input being coupled to a second PLL, and the output being coupled to each PHY block in a first group of PHY blocks including the first PHY block and to each PHY block in a second group of PHY blocks including the second PHY block.

11. The system of claim 9, wherein the first PLL and the second PLL are located between a first portion of the first group of PHY blocks and a second portion of the first group of PHY blocks.

12. The system according to claim 1, further comprising: Package components; and The bump electrically couples the first PHY block and the second PHY block to pins on the package.

13. The system of claim 12, wherein the bump includes one or more supply bumps that overlap with the first PHY block and the second PHY block.

14. The system of claim 12, wherein the bump includes one or more ground bumps, the one or more ground bumps overlapping the first PHY block and the second PHY block.

15. The system of claim 12, further comprising: A substrate, wherein the package is mounted on the substrate; and A memory device mounted on the substrate, wherein the memory device is electrically coupled to the pins on the package.

16. The system according to claim 1, wherein: Each of the first column and the second column extends in a first direction; The first column has a first width in a second direction perpendicular to the first direction; The second column has a second width in the second direction; and The distance between the first column and the second column in the second direction is less than each of the first width and the second width.

17. A system comprising: A bare die, the bare die including a physical layer (PHY) block arranged in at least two columns, wherein a first column of the at least two columns extends along one side of the bare die, and a second column of the at least two columns is adjacent to the first column, the PHY block including a first PHY block in the first column and a second PHY block in the second column, and the first PHY block and the second PHY block sharing one or more clock resources.

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