Simplifying PCIe processing logic using shock absorber

Abstract

A computer-implemented method, computer system, and computer program product that simplify PCIe transaction layer packet (TLP) processing logic. The method includes providing a buffer between a data link layer and a transaction layer in a PCIe processing environment, where the buffer includes a maximum buffer size and a command interface facing the data link layer. The method also includes storing PCIe data from the data link layer in the buffer, and identifying a transaction layer packet in the stored PCIe data. The method further includes forwarding the transaction layer packet from the buffer, where the transaction layer packet is forwarded to the transaction layer for each of a plurality of clock cycles of the PCIe processing environment. Finally, the method includes determining that the maximum buffer size has been reached, and using the command interface to notify the data link layer to initiate PCIe replay.

Description

Background Technology

[0001] The embodiments generally relate to the field of data communication, and more specifically, to simplify the transaction layer (TLP) processing logic in the Peripheral Component Interconnect Express (PCIe) architecture.

[0002] In a computing environment, a High-Speed ​​Peripheral Component Interconnect (PCIe) architecture can be defined. PCIe can use one or more channels to perform point-to-point serial links and can be configured for interconnection at the motherboard level, expansion card interfaces, etc. In such an architecture, a layered structure including a software layer, transaction layer, data link layer, and physical layer can be defined to control and manage information transmission. The transaction layer is configured to generate Transaction Layer Packets (TLPs), and as a larger data bus width is required to handle inbound data streams from the PCIe link, the transaction layer packet processing logic may become more complex because multiple TLPs may fit perfectly within the data bus width in a single clock cycle. Summary of the Invention

[0003] The embodiments relate to a computer-implemented method for simplifying PCIe Transaction Layer Packet (TLP) processing logic. The method may include providing a buffer between a data link layer and a transaction layer in a PCIe processing environment, wherein the PCIe processing environment comprises multiple clock cycles, and the buffer includes a maximum buffer size and a command interface for the data link layer. The method may further include storing PCIe data from the data link layer in the buffer and identifying at least one transaction layer packet in the stored PCIe data. The method may further include forwarding transaction layer packets from the buffer, wherein at least one transaction layer packet is forwarded to the transaction layer for each of the multiple clock cycles of the PCIe processing environment. Finally, the method may include determining that the amount of stored PCIe data is at least equal to the maximum buffer size, and using the buffer's command interface to notify the data link layer that the buffer size has been reached.

[0004] In another embodiment, the method may include notifying the data link layer in response to a command interface using a buffer, wherein the data link layer requests a replay in the PCIe processing environment, wherein PCIe data from the data link layer is invalidated starting from the replay position in the PCIe data.

[0005] In another embodiment, the method may include storing PCIe data from the PCIe data link layer in a buffer in response to detecting a replay in the PCIe processing environment and determining that the amount of stored PCIe data is less than the maximum buffer size, starting from the replay position in the PCIe data from the data link layer.

[0006] In another additional embodiment, storing PCIe data from the data link layer in a buffer may include determining that the PCIe data from the data link layer is valid.

[0007] In another embodiment, the buffer may include multiple arrays, and the method may include obtaining metadata from at least one transaction layer group and associating the metadata with each of the multiple arrays.

[0008] In another embodiment, metadata is selected from a group that includes: a transaction layer group start indicator, a transaction layer group end indicator, and a transaction layer group invalidation indicator.

[0009] In another embodiment, each of the multiple arrays is four bytes wide.

[0010] In addition to computer-implemented methods, the repeated embodiments also relate to computer systems and computer program products for simplifying PCIe Transaction Layer Packet (TLP) processing logic.

[0011] This summary is provided to introduce, in a simplified form, some concepts that will be further described in the detailed embodiments described below. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to help determine the scope of the claimed subject matter. Attached Figure Description

[0012] Figure 1 A block diagram of an example computer system in which various embodiments can be implemented is depicted.

[0013] Figure 2 A flowchart is depicted illustrating a process for simplifying PCIe Transaction Layer Packet (TLP) processing logic according to an embodiment.

[0014] Figure 3 An example of a buffer deployed between the data link layer and the transaction layer in a PCIe processing environment, according to an embodiment, is depicted. Detailed Implementation

[0015] In high-bandwidth, multi-channel Fast Peripheral Component Interconnect (PCIe) processing environments, the PCIe transaction layer receive processing logic for handling transaction layer packets (TLPs) may require a data bus width of 32 bytes or more to manage inbound PCIe data streams. Meanwhile, an internal data link layer data bus width greater than 16 bytes can force the PCIe transaction layer receive processing logic to become extremely complex, as multiple TLPs may fit perfectly within the data bus width in a single clock cycle. For example, using a 32-byte bus width and considering the data link layer frame structure, it is possible to receive two 3DW headers without Enhanced CRC (ECRC) in a single PCIe clock cycle.

[0016] When inbound TLPs arriving in the same clock cycle have different "types," such as non-posted, posted, or completed, the PCIe transaction layer receive processing logic can easily handle this situation because each type must be pushed to its own receive data buffer within the transaction layer. However, if multiple TLPs of the same type are received within a single clock cycle, the inbound PCIe transaction layer receive processing logic can become increasingly complex. If the chip technology node supports multi-write port arrays (e.g., SRAM or GRAS), then each TLP must have a processing path to process the TLP in parallel, which doubles the overhead of the PCIe transaction layer receive processing logic, even though the array itself does not need to change its format or size, as each processing pipeline can have a dedicated write port to the target array. Inbound completed TLP processing can be even more complex because it must be able to handle multiple partial completions for a single request tag simultaneously. This means that the first completed TLP in the cycle affects the target data location of the second completed TLP received in the same clock cycle, as well as the validity check of the header field of the second TLP.

[0017] Therefore, it may be useful to provide a method or system to simplify PCIe Transaction Layer Packet (TLP) processing logic by providing a "Shock Absorber Buffer" (SAB) after the PCIe data link layer receive logic and before the transaction layer where the TLP processing pipeline resides. In this method or system, inbound data can be pushed into the SAB as it leaves the link from the PCIe data link layer, then pulled out of the SAB in FIFO order and pushed into the transaction layer processing pipeline, controlling the flow so that the transaction layer can process only one TLP per clock cycle. Limiting the transaction layer to processing only one TLP per clock cycle reduces the complexity of the receive processing logic and avoids the need for standard methods known in the art for processing multiple TLPs per clock cycle, such as multi-write port arrays in the transaction layer. All inbound buffers can be precisely sized, eliminating the need for arrays of double the size, and the complexity of the processing pipeline can be reduced, thereby enabling support for large outbound non-forwarding requests.

[0018] The additional processing time added by flow control applied to the SAB's output can cause the buffer to fill up in worst-case scenarios (such as a constant flow of two TLPs per clock cycle with no gaps in the data stream). To manage this possibility, the SAB can use an internal command feedback path oriented towards the data link layer to indicate when the SAB is "full," and support backpressure on the PCIe link data stream using the PCIe ACK / NAK protocol. For TLPs that cannot be pulled into the SAB from the data link layer, an NAK (e.g., a request for PCIe replay) is issued to the link partner. This TLP, along with all subsequent TLPs, is discarded by the PCIe transaction layer receive processing logic until a PCIe replay occurs on the link partner. Once a PCIe replay has been detected, as long as the SAB is not full, the inbound TLP will be pushed back into the SAB from the data link layer, and processing can resume from the point where the data was discarded. The time required to generate a PCIe replay (i.e., replay latency) gives the transaction layer time to process the backlog of data stored in the SAB and time to catch up, and may even empty the SAB.

[0019] In such methods or systems, the size of the SAB must be appropriately configured to handle normal data flow and link alignment without excessive PCIe replays, as each PCIe replay can degrade PCIe link performance. The worst-case scenario of two TLPs per clock cycle, mentioned above, rarely occurs in PCIe processing environments. Therefore, allowing the method or system to issue a NAK and trigger PCIe replays in the worst-case scenario is an acceptable trade-off for the potentially significant savings in transaction layer receive processing logic complexity. Since the transaction layer only receives one TLP per clock cycle after the SAB, the complexity of the processing pipeline can be minimized. Furthermore, using this method or system, the complexity of the completion processing pipeline can be further reduced by allowing backpressure to be applied to the SAB when additional completion table lookups or updates for partial completion can be completed one at a time. This method or system can also separate completion TLP processing from forwarding and non-forwarding request processing on the read side of the SAB. Using the methods or systems described herein, the receive header and data buffer can be a single-write port array, and its size can precisely meet the bandwidth depth requirements, thus eliminating the need for additional space to handle worst-case bandwidth or TLP alignment issues. Therefore, this method or system simplifies Transaction Layer Packet (TLP) processing logic and provides more efficient PCIe packet operations and processing.

[0020] refer to Figure 1 The computing environment 100 includes examples of environments for executing at least some of the computer code involved in the methods of the present invention, such as the shock absorber module 150. In addition to the shock absorber module 150, the computing environment 100 includes, for example, a computer 101, a wide area network (WAN) 102, an end-user equipment (EUD) 103, a remote server 104, a public cloud 105, and a private cloud 106. In this embodiment, the computer 101 includes a processor set 110 (including processing circuitry 120 and a cache 121), a communication infrastructure 111, volatile memory 112, persistent storage 113 (including an operating system 122 and the shock absorber module 150 as identified above), a peripheral device set 114 (including a user interface (UI) device set 123, a storage device 124, and an Internet of Things (IoT) sensor set 125), and a network module 115. The remote server 104 includes a remote database 130. Public cloud 105 includes gateway 140, cloud orchestration module 141, host physical machine set 142, virtual machine set 143, and container set 144.

[0021] Computer 101 may be a desktop computer, laptop computer, tablet computer, smartphone, smartwatch, or other wearable computer, mainframe computer, quantum computer, or any other form of computer or mobile device known now or developed in the future capable of running programs, accessing networks, or querying databases (such as remote database 130). As is well known in the field of computer technology, and depending on the technology, the performance of a computer-implemented method can be distributed across multiple computers and / or multiple locations. On the other hand, in the presentation of this computing environment 100, for the sake of simplicity, the detailed discussion focuses on a single computer, specifically computer 101. Computer 101 may be located in the cloud, although... Figure 1 It is not shown in the cloud. On the other hand, unless otherwise explicitly instructed, computer 101 does not require to be located in the cloud.

[0022] Processor assembly 110 includes one or more computer processors of any type now known or to be developed in the future. Processing circuitry 120 may be distributed across multiple packages, such as multiple coordinated integrated circuit chips. Processing circuitry 120 may implement multiple processor threads and / or multiple processor cores. Cache 121 is memory located within the processor chip package(s), typically used to store data or code that the threads or cores running on processor assembly 110 need to access quickly. Cache memory is typically organized into multiple levels based on its relative proximity to the processing circuitry. Alternatively, some or all of the cache for the processor assembly may be located "off-chip". In some computing environments, processor assembly 110 may be designed to process qubits and perform quantum computing.

[0023] Computer-readable program instructions are typically loaded onto computer 101 to cause a series of operational steps to be performed by the processor set 110 of computer 101, thereby implementing a computer-implemented method, such that the instructions thus executed instantiate the method specified in the flowcharts and / or the descriptive description of the computer-implemented method included in this document (collectively, the "method of the invention"). These computer-readable program instructions are stored in various computer-readable storage media, such as cache 121 and other storage media discussed below. The program instructions and associated data are accessed by the processor set 110 to control and direct the execution of the method of the invention. In computing environment 100, at least some of the instructions for performing the method of the invention may be stored in a shock absorber module 150 in persistent storage device 113.

[0024] Communication structure 111 is a signal transmission path that allows the various components of computer 101 to communicate with each other. Typically, this structure includes switches and conductive paths, such as switches and conductive paths including buses, bridges, physical input / output ports, etc. Other types of signal communication paths, such as fiber optic communication paths and / or wireless communication paths, can also be used.

[0025] Volatile memory 112 is any type of volatile memory now known or to be developed in the future. Examples include dynamic random access memory (RAM) or static RAM. Typically, volatile memory 112 is characterized by random access, but this is not necessary unless explicitly stated otherwise. In computer 101, volatile memory 112 is located in a single package and inside computer 101, but alternatively or additionally, volatile memory may be distributed across multiple packages and / or located outside of computer 101.

[0026] The persistent storage device 113 is any form of computer non-volatile memory known now or developed in the future. The non-volatility of this memory means that the stored data is maintained regardless of whether the computer 101 is powered or not, or whether the persistent storage device 113 is directly powered. The persistent storage device 113 may be a read-only memory (ROM), but typically at least part of the persistent storage device allows data to be written, deleted, and rewritten. Some common forms of persistent storage devices include hard disks and solid-state storage devices. The operating system 122 may take many forms, such as various known proprietary operating systems or open-source portable operating system interface type operating systems employing a kernel. The code included in the shock absorber module 150 typically includes at least some of the computer code involved in executing the methods of the present invention.

[0027] Peripheral device set 114 includes a set of peripheral devices for computer 101. Data communication connections between peripheral devices and other components of computer 101 can be implemented in various ways, such as Bluetooth connectivity, Near Field Communication (NFC) connectivity, cable connections (such as Universal Serial Bus (USB) cables), plug-in connections (e.g., Secure Digital (SD) cards), connections established via local area networks, and even connections established via wide area networks such as the Internet. In various embodiments, UI device set 123 may include components such as displays, speakers, microphones, wearable devices (such as goggles and smartwatches), keyboards, mice, printers, touchpads, game controllers, and haptic devices. Storage device 124 is an external storage device, such as an external hard drive, or a pluggable storage device, such as an SD card. Storage device 124 may be persistent and / or volatile. In some embodiments, storage device 124 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where computer 101 requires significant storage (e.g., where computer 101 stores and manages a large database locally), this storage can be provided by peripheral storage devices designed for storing very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The IoT sensor set 125 includes sensors that can be used for Internet of Things (IoT) applications. For example, one sensor could be a thermometer, and another could be a motion detector.

[0028] Network module 115 is a collection of computer software, hardware, and firmware that allows computer 101 to communicate with other computers via WAN 102. Network module 115 may include hardware such as a modem or Wi-Fi transceiver, software for packetizing and / or depacketizing data for communication network transmission, and / or web browser software for communicating data over the Internet. In some embodiments, the network control and network forwarding functions of network module 115 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software-defined networking (SDN), the control and forwarding functions of network module 115 are performed on physically separate devices, such that the control functions manage multiple different network hardware devices. Computer-readable program instructions for performing the methods of the present invention can typically be downloaded to computer 101 from an external computer or external storage device via a network adapter card or network interface included in network module 115.

[0029] WAN 102 is any wide area network (e.g., the Internet) capable of communicating computer data over non-local distances using any technology now known or to be developed for communicating computer data. In some embodiments, WAN 102 may be replaced by and / or supplemented by a local area network (LAN), which is designed for communicating data between devices located within a local area (e.g., a Wi-Fi network). WANs and / or LANs typically include computer hardware such as copper transmission cables, fiber optic transmission cables, wireless transmissions, routers, firewalls, switches, gateway computers, and edge servers.

[0030] End User Equipment (EUD) 103 is any computer system used and controlled by an end user (e.g., a customer of the enterprise operating computer 101), and may take any of the forms discussed above in conjunction with computer 101. EUD 103 typically receives useful data from the operation of computer 101. For example, if computer 101 is designed to provide recommendations to the end user, these recommendations are typically transmitted from network module 115 of computer 101 to EUD 103 via WAN 102. In this way, EUD 103 may display or otherwise present the recommendations to the end user. In some embodiments, EUD 103 may be a client device, such as a thin client, a thick client, a mainframe computer, a desktop computer, etc.

[0031] Remote server 104 is any computer system that provides at least some data and / or functionality to computer 101. Remote server 104 can be controlled and used by the same entity operating computer 101. Remote server 104 represents multiple machines that collect and store useful data by other computers (such as computer 101). For example, where computer 101 is designed and programmed to provide recommendations based on historical data, that historical data can be provided to computer 101 from a remote database 130 of remote server 104.

[0032] Public cloud 105 is any computer system available to multiple entities. Public cloud 105 provides computer system resources and / or other computing capabilities, particularly data storage (cloud storage) and computing power, on demand, without requiring direct active management by the user. Cloud computing typically leverages resource sharing to achieve consistency and economies of scale. Direct and active management of the computing resources of public cloud 105 is performed by the computer hardware and / or software of cloud orchestration module 141. The computing resources provided by public cloud 105 are typically implemented by virtual computing environments running on various computers, which constitute a host physical machine set 142, which is the entirety of physical computers in and / or available for use by public cloud 105. Virtual computing environments (VCEs) typically take the form of virtual machines from virtual machine set 143 and / or containers from container set 144. It should be understood that these VCEs can be stored as images and can be transferred between various physical machine hosts, whether as images or after VCE instantiation. Cloud orchestration module 141 manages the transfer and storage of images, deploys new VCE instances, and manages active VCE deployment instances. Gateway 140 is a collection of computer software, hardware, and firmware that allow public cloud 105 to communicate via WAN 102.

[0033] A further explanation of VCE will now be provided. VCE can be stored as an "image". New active VCE instances can be instantiated from an image. Two common types of VCE are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to the operating system's functionality, where the kernel allows multiple isolated user-space instances, called containers, to exist. From the perspective of the programs running within them, these isolated user-space instances typically behave like a real computer. Computer programs running on a regular operating system can utilize all the resources of that computer, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, programs running within a container can only use the contents of the container and the devices allocated to the container; this characteristic is called containerization.

[0034] Private cloud 106 is similar to public cloud 105, except that its computing resources are available only to a single enterprise. While private cloud 106 is depicted as communicating with WAN 102, in other embodiments, private cloud can be completely disconnected from the internet and accessed only through a local / private network. A hybrid cloud is a combination of multiple different types of clouds (e.g., private cloud, community cloud, or public cloud types), typically implemented by different providers. Each of the multiple clouds remains an independent and discrete entity, but the larger hybrid cloud architecture is bound together through standardization or proprietary technology that enables orchestration, management, and / or data / application portability between the multiple component clouds. In this embodiment, public cloud 105 and private cloud 106 are both part of a larger hybrid cloud.

[0035] Computer environment 100 can be used to simplify PCIe Transaction Layer Packet (TLP) processing logic. Specifically, damper module 150 can provide a buffer within the PCIe processing environment, particularly between the PCIe data link layer and the PCIe transaction layer, where inbound PCIe data (including transaction layer packets (TLPs)) can be pushed into the buffer as it is received from the PCIe link at full bandwidth. PCIe data can be pulled from the buffer and pushed into the transaction layer processing pipeline in a first-in-first-out (FIFO) order, but the maximum processing rate is one TLP per clock cycle. This means that, for example, if two TLPs are received from the data link layer in a single clock cycle, these TLPs will leave the buffer within two clock cycles. Due to this data flow rate control, in the worst case, the buffer may reach its maximum data capacity, i.e., become "full." To account for this possibility, the buffer can include a feedback path towards the data link layer, where the buffer can indicate a "full" condition to the data link layer, which can then request PCIe replay by issuing a PCIe NAK packet. In this scenario, starting from the NAK packet location, all inbound PCIe packets are discarded or dropped by the PCIe link (and thus the buffer). Inbound PCIe data from the NAK packet location is only accepted after PCIe replay is detected and the damper module 150 determines that the buffer is no longer "full". It should be noted that the time required to process the NAK, initiate PCIe replay, and then return to the NAK location allows the transaction layer to process any inbound PCIe data that may be in the buffer, and to clear any possible backlog in the buffer.

[0036] refer to Figure 2 According to at least one embodiment, an operational flowchart illustrating a simplified PCIe Transaction Layer Packet (TLP) processing logic process 200 is depicted. In 202, the damper module 150 can provide a damping buffer in the PCIe environment, for example, Figure 3A buffer 300 may be located between the PCIe data link layer (e.g., data link layer 320) and the PCIe transaction layer (e.g., transaction layer 340). Those skilled in the art will recognize that the size of the damping buffer must be sufficient to handle normal PCIe data flow and link alignment without requiring excessive PCIe replay operations, as PCIe replay can interfere with normal operation and degrade link performance. The damping buffer may comprise multiple independent arrays (e.g., array 308) nominally four bytes wide, since the size of PCIe transaction layer packets (TLPs) (including headers) increments by four bytes. Furthermore, the write interface (e.g., controller 302) and read interface (e.g., compressor 306) of the damping buffer must be able to push and pull data at the maximum data bus width per clock cycle, while allowing a minimum of four bytes / clock cycle to support applications with the minimum training bus width. The damping buffer also includes a feedback path to the data link layer (i.e., a command interface or credit manager 304) to indicate when the damping buffer is “full” (i.e., the buffer can no longer absorb any additional PCIe data from the data link layer). This allows the data link layer to backpressure the PCIe link data stream using the PCIe ACK / NAK protocol and request PCIe replay, at which point the damping buffer discards subsequent packets, as described below.

[0037] At 204, inbound data from the PCIe data link layer can be stored in a buffer, and Transaction Layer Packets (TLPs) can be identified within the stored PCIe data. In this embodiment, the write control logic of the shock buffer compresses the inbound data stream, ensuring that only valid TLP data from the PCIe link is written to the shock buffer, thereby reducing the use of shock buffer entries. Furthermore, to facilitate TLP processing on the read side of the shock buffer, metadata can be stored along with each four-byte data entry, including but not limited to TLP start, end, and invalidation indicators. The four-byte address offset used for read and write pointers can be used to indicate when the array has data to process and when it is empty or full, but the read side of the shock buffer only needs the write address to know when data is to be processed. It is important to note that the read side of the shock buffer will read as much data as possible within each clock cycle with processing capability; therefore, if only four bytes are valid in any given clock cycle, the shock buffer will read and process those four bytes.

[0038] In 206, transaction layer packets can be forwarded from the buffer to the PCIe transaction layer in a first-in, first-out (FIFO) order, accompanied by flow control, ensuring that only a known number of transaction layer packets reach the transaction layer each clock cycle. It's important to note that this is likely one TLP per clock cycle, and while this discussion involves a single transaction layer packet per clock cycle, it is not required to be limited to one transaction layer packet, but rather a consistent, specific, and known number of transaction layer packets per clock cycle. When processing data in the buffer, if another TLP is encountered in the same clock cycle, that TLP may not be pushed to the transaction layer. Instead, the buffer will retrieve as much stored data as possible in the next clock cycle to fill the remaining space in the processing pipeline, while pushing the current TLP forward to the transaction layer. In the next clock cycle, it will begin the next TLP, potentially with the full bus width of data. When reading PCIe data from the shock buffer, space in the buffer is freed up, allowing the data link layer to push more data forward into the buffer. However, due to the flow limit of one TLP per clock cycle, this means the shock buffer may fill up to the point where it cannot absorb any more TLPs. It should be noted that in order to identify individual TLPs within the PCIe data and for flow control, the read controller within the shock buffer must parse the aforementioned metadata from the shock buffer array entries to know when a TLP begins and ends.

[0039] At 208, the damper module 150 can determine that the amount of stored PCIe data is at least equal to the maximum buffer size (i.e., the buffer is full) and can notify the data link layer of this status so that the data link layer can backpressure the PCIe data stream by requesting replay by issuing PCIe NAK packets. At this point, PCIe data is discarded or dropped, starting from the replay position in the PCIe data (or the moment the NAK packet was issued). Once replay is detected and the buffer is not full, data is stored and processed starting from the point in the data that matches the moment the NAK packet was issued (i.e., the replay position). The replay delay gives the transaction layer time to process the backlog of data stored in the buffer and time to catch up, and may even empty the buffer.

[0040] As a result of process 200, by allowing backpressure to be applied to the shock buffer when additional completion table lookups or updates for partial completion can be completed one at a time, the complexity of the PCIe completion processing pipeline can be further reduced. Completion TLP processing can also be separated from combined forwarding and non-forwarding request processing on the read side of the shock buffer, thus requiring only two pipelines instead of three. The receive header and shock buffer in the transaction layer can also be single-write port arrays, and their size can precisely meet the depth requirements for bandwidth, thus eliminating the need for additional space to handle worst-case bandwidth or TLP alignment issues.

[0041] refer to Figure 3 According to an embodiment, an example of a buffer 300 deployed between the data link layer 320 and the transaction layer 340 in a PCIe processing environment is depicted. The buffer 300 may include a compressor 306, which can be used as a reference. Figure 2 The data link layer 320 includes a read interface; a controller 302, which can be used as a write interface to the transaction layer 340; and an array 308, which can be used as the aforementioned array. Furthermore, a credit manager 304 can be implemented, which interfaces with the compressor 306 (and therefore the data link layer 320) to provide the necessary communication interface to notify the data link layer 320 that the buffer 300 is full, thereby enabling PCIe replay.

[0042] Various aspects of this disclosure are described by descriptive text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in embodiments of a computer program product (CPP). With respect to any flowchart, depending on the technology involved, operations may be performed in a different order than shown in a given flowchart. For example, also depending on the technology involved, two operations shown in consecutive flowchart blocks may be performed in reverse order, as a single integrated step, concurrently, or with at least partial temporal overlap.

[0043] A Computer Program Product Implementation (“CPP Implementation” or “CPP”) is a term used to describe a collection of one or more storage media (also referred to as “media”) that collectively comprise a collection of one or more storage devices that collectively include machine-readable code corresponding to instructions and / or data for performing the computer operations specified in a given CPP claim. A “storage device” is any tangible device capable of holding and storing instructions for use by a computer processor. Not limited thereto, a computer-readable storage medium can be an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some known types of storage devices including these media include: floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), optical disc read-only memory (CD-ROM), digital versatile optical disc (DVD), memory sticks, floppy disks, mechanical encoding devices (such as punched cards or pits / bumps formed on the main surface of the disc), or any suitable combination of the foregoing. The term "computer-readable storage medium" as used in this disclosure should not be construed as storage in the form of signals themselves (such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides, optical pulses transmitted through fiber optic cables, electrical signals transmitted through wires, and / or other transmission media). As those skilled in the art will understand, during normal operation of a storage device (such as during access, defragmentation, or garbage collection), data will typically move at some occasional points in time, but this does not make the storage device transient, because data is not transient when stored.

[0044] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the embodiments disclosed herein. Numerous modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or improvements to techniques found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A computer-implemented method for simplifying PCIe Transaction Layer Packet (TLP) processing logic, the computer-implemented method comprising: A buffer is provided between the data link layer and the transaction layer in a PCIe processing environment, wherein the PCIe processing environment comprises multiple clock cycles, and the buffer includes a maximum buffer size and a command interface for the data link layer; The PCIe data from the data link layer is stored in the buffer, and at least one transaction layer packet is identified in the stored PCIe data; The transaction layer packets are forwarded from the buffer, wherein at least one transaction layer packet is forwarded to the transaction layer for each of the plurality of clock cycles of the PCIe processing environment; as well as The amount of stored PCIe data is determined to be at least equal to the maximum buffer size, and the command interface of the buffer is used to notify the data link layer that the maximum buffer size has been reached.

2. The computer-implemented method according to claim 1 further includes: In response to the command interface of the buffer being used to notify the data link layer, the data link layer requests a replay in the PCIe processing environment, wherein the PCIe data from the data link layer is invalidated starting from the replay position in the PCIe data.

3. The computer-implemented method according to claim 2 further includes: In response to detecting the replay in the PCIe processing environment and determining that the amount of stored PCIe data is less than the maximum buffer size, the PCIe data from the PCIe data link layer is stored in the buffer starting from the replay position in the PCIe data from the data link layer.

4. The computer-implemented method of claim 1, wherein storing the PCIe data from the data link layer in the buffer further comprises: The PCIe data from the data link layer is determined to be valid.

5. The computer-implemented method of claim 1, wherein the buffer comprises a plurality of arrays, and further comprises: Metadata is obtained from the at least one transaction layer group and associated with each of the plurality of arrays.

6. The computer-implemented method of claim 5, wherein the metadata is selected from a group, the group comprising: Transaction layer group start indicator, transaction layer group end indicator, and transaction layer group invalidation indicator.

7. The computer-implemented method of claim 5, wherein each of the plurality of arrays is four bytes wide.

8. A computer system for simplifying PCIe Transaction Layer Packet (TLP) processing logic, the computer system comprising: One or more processors, one or more computer-readable storage devices, and one or more computer-readable storage media; Program instructions, stored on at least one of the one or more computer-readable storage media, for execution by at least one of the one or more processors via at least one of the one or more computer-readable memories, to provide a buffer between the data link layer and the transaction layer in a PCIe processing environment, wherein the PCIe processing environment includes multiple clock cycles, and the buffer includes a maximum buffer size and a command interface to the data link layer; Program instructions, which are stored on at least one of the one or more computer-readable storage media, are executed by at least one of the one or more processors via at least one of the one or more computer-readable storage media to store PCIe data from the data link layer in the buffer and identify at least one transaction layer packet in the stored PCIe data. Program instructions, the program instructions being stored on at least one of the one or more computer-readable storage media, for execution by at least one of the one or more processors via at least one of the one or more computer-readable memories to forward the transaction layer packet from the buffer, wherein the at least one transaction layer packet is forwarded to the transaction layer for each of the plurality of clock cycles of the PCIe processing environment; as well as Program instructions, stored on at least one of the one or more computer-readable storage media, for execution by at least one of the one or more processors via at least one of the one or more computer-readable storage media, to determine that the amount of stored PCIe data is at least equal to the maximum buffer size, and to notify the data link layer that the maximum buffer size has been reached using the command interface of the buffer.

9. The computer system of claim 8, further comprising program instructions stored on at least one of the one or more computer-readable storage media for execution by at least one of the one or more processors via at least one of the one or more computer-readable storage media to notify the data link layer, in response to the command interface using the buffer, that the data link layer requests replay in the PCIe processing environment, wherein the PCIe data from the data link layer is invalidated starting from the replay position in the PCIe data.

10. The computer system of claim 9, further comprising program instructions stored on at least one of the one or more computer-readable storage media, for execution by at least one of the one or more processors via at least one of the one or more computer-readable memories to, in response to detecting the replay in the PCIe processing environment and determining that the amount of the stored PCIe data is less than the maximum buffer size, store the PCIe data from the PCIe data link layer in the buffer, starting from the replay position in the PCIe data from the data link layer.

11. The computer system of claim 8, wherein the program instructions for storing the PCIe data from the data link layer in the buffer further include program instructions stored on at least one of the one or more computer-readable storage media for execution by at least one of the one or more processors via at least one of the one or more computer-readable memories to determine that the PCIe data from the data link layer is valid.

12. The computer system of claim 8, wherein the buffer comprises a plurality of arrays and further comprises program instructions stored on at least one of the one or more computer-readable storage media for execution by at least one of the one or more processors via at least one of the one or more computer-readable storage media to obtain metadata from the at least one transaction layer group and associate the metadata with each of the plurality of arrays.

13. The computer system of claim 12, wherein the metadata is selected from a group, the group comprising: Transaction layer group start indicator, transaction layer group end indicator, and transaction layer group invalidation indicator.

14. The computer system of claim 12, wherein each of the plurality of arrays is four bytes wide.

15. A computer program product for simplifying PCIe Transaction Layer Packet (TLP) processing logic, the computer program product comprising: One or more computer-readable storage media; Program instructions, which are stored on at least one of the one or more computer-readable storage media, to provide a buffer between the data link layer and the transaction layer in a PCIe processing environment, wherein the PCIe processing environment includes multiple clock cycles, and the buffer includes a maximum buffer size and a command interface to the data link layer. Program instructions, which are stored on at least one of the one or more computer-readable storage media, to store PCIe data from the data link layer in the buffer and to identify at least one transaction layer packet in the stored PCIe data. Program instructions, the program instructions being stored on at least one of the one or more computer-readable storage media, for forwarding the transaction layer packets from the buffer, wherein the at least one transaction layer packet is forwarded to the transaction layer for each of the plurality of clock cycles of the PCIe processing environment; as well as Program instructions, stored on at least one of the one or more computer-readable storage media, to determine that the amount of stored PCIe data is at least equal to the maximum buffer size, and to use the command interface of the buffer to notify the data link layer that the maximum buffer size has been reached.

16. The computer program product of claim 15, further comprising program instructions stored on at least one of the one or more computer-readable storage media to notify the data link layer in response to using the command interface of the buffer, wherein the data link layer requests replay in the PCIe processing environment, wherein the PCIe data from the data link layer is invalidated starting from the replay position in the PCIe data.

17. The computer program product of claim 16, further comprising program instructions stored on at least one of the one or more computer-readable storage media to, in response to detecting the replay in the PCIe processing environment and determining that the amount of stored PCIe data is less than the maximum buffer size, store the PCIe data from the PCIe data link layer in the buffer, starting from the replay position in the PCIe data from the data link layer.

18. The computer program product of claim 15, wherein the program instructions for storing the PCIe data from the data link layer in the buffer further include program instructions stored on at least one of the one or more computer-readable storage media to determine that the PCIe data from the data link layer is valid.

19. The computer program product of claim 15, wherein the buffer comprises a plurality of arrays and further comprises program instructions stored on at least one of the one or more computer-readable storage media to obtain metadata from the at least one transaction layer group and to associate the metadata with each of the plurality of arrays.

20. The computer program product of claim 19, wherein the metadata is selected from a group, the group comprising: Transaction layer group start indicator, transaction layer group end indicator, and transaction layer group invalidation indicator.

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