Radio frequency front end bus optimization in power management circuit

Abstract

Radio frequency front end (RFFE) bus optimization in power management circuits is provided. In this, RFFE bus circuits are optimized to provide RFFE standard compliant mechanisms for canceling timers configured to fire event trigger(s). Thus, optimized RFFE bus circuits can be provided in power management circuits to configure and control multiple timers according to various operational scenarios.

Description

[0001] Related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 570,882, filed March 28, 2024, and U.S. Provisional Patent Application No. 63 / 651,189, filed May 23, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The technology disclosed herein generally relates to optimizing the radio frequency front-end (RFFE) bus used in power management circuits. Background Technology

[0004] Mobile communication devices have become increasingly prevalent in today's society. This widespread use is partly driven by the many features now available on such devices. The increased processing power in these devices means that they have evolved from mere communication tools into sophisticated mobile multimedia hubs capable of enhancing the user experience.

[0005] The redefined user experience demands higher data rates from wireless communication technologies such as Wi-Fi, LTE, and 5G-NR. To achieve higher data rates in mobile communication devices, complex power amplifiers can be used to increase the output power of the radio frequency (RF) signals transmitted by the mobile communication device (e.g., to maintain sufficient power per bit).

[0006] Figure 1 This is a schematic diagram of an exemplary power management circuit 10, in which the power amplifier circuit 12 is configured based on a voltage V supplied by the power management integrated circuit (PMIC) 16. CC The RF signal 14 is amplified. The power management circuit 10 includes a transceiver circuit 18. The transceiver circuit 18 is configured to generate the RF signal 14 and track the target voltage V that measures the time-varying power of the RF signal 14. TGT PMIC16 then adjusts the voltage according to the target voltage V. TGT Generated voltage V CC This makes the voltage V CC It can follow the time-varying power of RF signal 14, thereby helping the power amplifier circuit 12 achieve better efficiency and linearity.

[0007] Transceiver circuit 18 can be configured to provide target voltage V to PMIC 16 via radio frequency front-end (RFFE) bus 20. TGTOther parameters, where transceiver circuit 18 acts as the master circuit and PMIC 16 acts as the slave circuit. As defined by the MIPI® Alliance RFFE specification, RFFE 20 can support standard event triggering mechanisms, thereby allowing transceiver circuit 18 to be configured with a timer in PMIC 16 to trigger specific events (e.g., the voltage V). CC (From one level to another). However, the RFFE specification does not provide a method to cancel a timer once it is defined. In this regard, it is desirable to enhance the standard event triggering mechanism so that the transceiver circuit 18 can cancel the timer via the RFFE bus 20. Summary of the Invention

[0008] The aspects disclosed in the specific embodiments include optimization of the radio frequency front-end (RFFE) bus in the power management circuitry. Herein, the RFFE bus circuitry is optimized to provide an RFFE-compliant mechanism for canceling multiple timers configured to trigger event triggers. Therefore, optimized RFFE bus circuitry can be provided in the power management circuitry to configure and control multiple timers according to various operating scenarios.

[0009] In one aspect, an RFFE bus circuit is provided. The RFFE bus circuit includes an RFFE bus. The RFFE bus is coupled to a main circuit. The RFFE bus circuit also includes a plurality of slave circuits. Each of the plurality of slave circuits is coupled to the RFFE bus. Each of the plurality of slave circuits is configured to receive a corresponding timer setting message from a plurality of timer setting messages, the corresponding timer setting message including a corresponding timer value from a plurality of timer values. Each of the plurality of slave circuits is further configured to receive a corresponding high-level command message from a plurality of high-level command (HLC) messages, each of the plurality of high-level command messages including a plurality of data bytes. Each of the plurality of slave circuits is further configured to start a corresponding timer at the beginning of a first data byte from the plurality of data bytes in the corresponding HLC message. Each of the plurality of slave circuits is further configured to receive a timer control flag from one of the plurality of data bytes included in the corresponding HLC message. Each of the plurality of slave circuits is also configured to immediately stop the corresponding timer when the timer control flag is set to a false value.

[0010] In another aspect, a wireless device is provided. The wireless device includes transceiver circuitry and an RFFE bus coupled to the transceiver circuitry. The wireless device also includes a PMIC. The PMIC includes tracker circuitry and voltage circuitry. Each of the tracker circuitry and the voltage circuitry is coupled to the RFFE bus. Each of the tracker circuitry and the voltage circuitry is configured to receive a corresponding timer setting message from a plurality of timer setting messages, the corresponding timer setting message including a corresponding timer value from a plurality of timer values. Each of the tracker circuitry and the voltage circuitry is further configured to receive a corresponding HLC message from a plurality of HLC messages, each of the plurality of HLC messages including a plurality of data bytes. Each of the tracker circuitry and the voltage circuitry is further configured to start a corresponding timer at the beginning of a first data byte from the plurality of data bytes in the corresponding HLC message, setting a corresponding timer to a corresponding timer value from the plurality of timer values. Each of the tracker circuit and the voltage circuit is further configured to receive a timer control flag from one of the multiple data bytes included in a corresponding HLC message. Each of the tracker circuit and the voltage circuit is also configured to immediately stop the corresponding timer when the timer control flag is set to a false value.

[0011] In another aspect, a method for optimizing an RFFE bus is provided. The method includes receiving a corresponding timer setting message from a plurality of timer setting messages, the corresponding timer setting message including a corresponding timer value from a plurality of timer values. The method also includes receiving a corresponding HLC message from a plurality of HLC messages, each of the plurality of HLC messages including a plurality of data bytes. The method further includes starting a corresponding timer at the beginning of a first data byte from the plurality of data bytes in the corresponding HLC message, setting the corresponding timer to the corresponding timer value from the plurality of timer values. The method also includes receiving a timer control flag from one of the data bytes included in the plurality of data bytes in the corresponding HLC message. The method further includes immediately stopping the corresponding timer when the timer control flag is set to a false value.

[0012] After reading the following detailed description in conjunction with the accompanying drawings, those skilled in the art will understand the scope of this disclosure and recognize its additional aspects. Attached Figure Description

[0013] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0014] Figure 1 This is a schematic diagram of an exemplary existing power management circuit, in which the transceiver circuit communicates with the power management integrated circuit (PMIC) based on a radio frequency front-end (RFFE) bus structure as defined by the MIPI® Alliance.

[0015] Figure 2 This is a schematic diagram of an exemplary RFFE bus circuit optimized according to embodiments of the present disclosure;

[0016] Figure 3 It is shown Figure 2 A schematic diagram of the optimized event triggering scheme in the RFFE bus circuit;

[0017] Figure 4 It is configured to support Figure 3 A schematic diagram of an exemplary power management circuit for an optimized event triggering scheme;

[0018] Figure 5 It provides information about Figure 4 How can the power management circuit support Figure 3 A schematic diagram illustrating an optimized event triggering scheme;

[0019] Figure 6A and 6B It shows based on Figure 3 Optimization of event triggering scheme Figure 4 A schematic diagram illustrating an exemplary operating scenario of the power management circuit;

[0020] Figure 7 This is a schematic diagram of an exemplary communication device, in which it can provide Figure 4 The power management circuit; and

[0021] Figure 8 It is used for optimization Figure 2 A flowchart illustrating the exemplary process of the RFFE bus circuit. Detailed Implementation

[0022] The embodiments described below illustrate the information necessary to enable those skilled in the art to practice the embodiments and demonstrate the best mode of practice. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will appreciate the application of these concepts, even those not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0023] It will be understood that while the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0024] It should be understood that when an element, such as a layer, region, or substrate, is referred to as "on another element" or "extending to another element," it may be located directly on or directly extending to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly on another element" or "directly extending to another element," no intermediate elements are present. Similarly, it should be understood that when an element, such as a layer, region, or substrate, is referred to as "above another element" or "extending above another element," it may be directly above or directly extending above the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly above another element" or "extending directly above another element," no intermediate elements are present. It will also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements are present.

[0025] For example, relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It should be understood that these terms, and those discussed above, are intended to include different orientations of the device other than those depicted in the figures.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a”, “an”, and “described” are also intended to include the plural forms. It should also be understood that, when used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0027] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be further understood that the terms used herein shall be interpreted as having the same meaning as in the context of this specification and related art, and shall not be construed in an idealized or overly formal sense unless expressly defined herein.

[0028] The aspects disclosed in the specific embodiments include optimization of the radio frequency front-end (RFFE) bus in the power management circuitry. Herein, the RFFE bus circuitry is optimized to provide an RFFE-compliant mechanism for canceling multiple timers configured to trigger event triggers. Therefore, optimized RFFE bus circuitry can be provided in the power management circuitry to configure and control multiple timers according to various operating scenarios.

[0029] Figure 2 This is a schematic diagram of an exemplary RFFE bus circuit 22 optimized according to embodiments of the present disclosure. The RFFE bus circuit 22 includes a main circuit 24 and a plurality of slave circuits 26(1)-26(N). The main circuit 24 is coupled to the slave circuits 26(1)-26(N) via an RFFE bus 28, which is a two-wire serial bus including a data line 30 and a clock line 32 for transmitting bidirectional data signal SDATA and clock signal SCLK, respectively.

[0030] Each of the slave circuits 26(1)-26(N) includes a corresponding register group from a plurality of register groups REGMAP-1-REGMAP-N. In a non-limiting example, each register group from REGMAP-1-REGMAP-N may include up to 256 (256) 8-bit registers, labeled REG

[000] -REG

[255] . Using register groups REGMAP-1-REGMAP-N, the master circuit 24 may set corresponding timers to trigger specific events in each of the slave circuits 26(1)-26(N).

[0031] In this embodiment, the RFFE bus circuit 22 can be configured according to an optimized event triggering scheme to not only provide the master circuit 24 with the ability to coordinate multiple timers among the slave circuits 26(1)-26(N), but also allow the master circuit 24 to selectively cancel any of the timers. Therefore, the RFFE bus circuit 22 can provide a much-needed enhancement to the standard event triggering mechanism defined in the RFFE specification.

[0032] Figure 3 It provides Figure 2A schematic diagram illustrating an optimized event triggering scheme in the RFFE bus circuit 22. Figure 2 and Figure 3 The common elements between them are indicated by common element labels and will not be described again here. For simplicity, this paper illustrates the optimized event triggering scheme based on slave circuits 26(1) and 26(2). It will be understood that the working principle of the optimized event triggering scheme shown in this paper can be applied to more slave circuits 26(1)-26(N).

[0033] In a non-limiting example, slave circuits 26(1) and 26(2) are uniquely identified by Universal Slave Identifiers (USIDs) "11" and "12", respectively. To set timers in slave circuits 26(1) and 26(2), the master circuit 24 first transmits a pair of timer setting messages 34 and 36 to slave circuits 26(1) and 26(2), respectively. It is worth noting that since the RFFE bus 28 is a serial bus, the master circuit 24 can only provide timer setting messages 34 and 36 sequentially.

[0034] Timer set message 34 includes the USID (USID = "11") of slave circuit 26(1) and the timer value T11. In a non-limiting example, the timer value T11 is written to a selected register (e.g., REG

[057] ) in registers REG

[000] -REG

[255] of register group REGMAP-1. Similarly, timer set message 36 includes the USID (USID = "12") of slave circuit 26(2) and the timer value T12. In a non-limiting example, the timer value T12 is written to a selected register (e.g., REG

[059] ) in registers REG

[000] -REG

[255] of register group REGMAP-2.

[0035] After providing timer set messages 34 and 36, the master circuit 24 transmits a pair of High-Level Command (HLC) messages 38 and 40 to the slave circuits 26(1) and 26(2), respectively. Similar to timer set messages 34 and 36, since the RFFE bus 28 is a serial bus, the master circuit 24 can only provide HLC messages 38 and 40 sequentially. In this embodiment, the master circuit 24 is configured to transmit HLC messages 38 and 40 in the same order as timer set messages 34 and 36. In other words, since timer set message 34 is transmitted before timer set message 36, HLC message 38 will also be transmitted before HLC message 40. It is understood that the master circuit 24 may also transmit HLC messages 38 and 40 in a different order than timer set messages 34 and 36.

[0036] In the embodiment, each HLC message in HLC messages 38 and 40 includes multiple data bytes B0-B3, and is therefore encoded to carry multiple high-level configuration commands. Each data byte in data bytes B0-B3 includes eight bits b0-b7. In this document, each slave circuit in slave circuits 26(1) and 26(2) can be configured to start the corresponding timer to the corresponding timer values ​​T11 and T12 upon receiving the first data byte B0 (e.g., upon receiving b7 of the first data byte B0).

[0037] In this document, b7 in the third data byte B2 is designated as a timer control flag, thereby allowing the main circuit 24 to cancel the corresponding timers in slave circuits 26(1) and 26(2). More specifically, b7 in the third data byte B2 of HLC message 38 can be used to cancel the corresponding timer in slave circuit 26(1), while b7 in the third data byte B2 of HLC message 40 can be used to cancel the corresponding timer in slave circuit 26(2).

[0038] In this embodiment, when b7 in the third data byte B2 is set to a false value (e.g., binary "0"), the corresponding timers in slave circuits 26(1) and 26(2) will be immediately (e.g., after b7 in the third data byte B2). Therefore, each slave circuit in slave circuits 26(1) and 26(2) will immediately trigger the corresponding HLC event triggers HLC11EVT and HLC12EVT upon receiving b0 in the fourth data byte B3 of the corresponding HLC messages 38 and 40. In other words, when the corresponding timer in slave circuit 26(1) is canceled, slave circuit 26(1) will immediately trigger the HLC event trigger HLC11EVT upon receiving b0 in the fourth data byte B3 of the HLC message 38. Similarly, when the corresponding timer in slave circuit 26(2) is canceled, slave circuit 26(2) will immediately trigger the HLC event trigger HLC12EVT upon receiving b0 in the fourth data byte B3 of the HLC message 40.

[0039] In contrast, when b7 in the third data byte B2 is set to a true value (e.g., binary "1"), the corresponding timers in slave circuits 26(1) and 26(2) will remain active. Therefore, each slave circuit in 26(1) and 26(2) will fire the corresponding HLC event triggers HLC11EVT and HLC12EVT when the corresponding timer expires. For example, the timer value T11 used to set the corresponding timer in slave circuit 26(1) can be determined such that slave circuit 26(1) fires the corresponding HLC event trigger HLC11EVT at any time during HLC message 40. Therefore, by setting the timer value T11 to be equal to the entire duration of HLC message 40, slave circuits 26(1) and 26(2) can fire HLC event triggers HLC11EVT and HLC12EVT simultaneously.

[0040] In an alternative embodiment, a timer control flag may be provided in b0 of the fourth data byte B3. Therefore, each slave circuit in slave circuits 26(1) and 26(2) may (e.g., from b7 in the third data byte B2 to b0 in the fourth data byte B3) have more time to decide what to do in response to the timer control flag. As described above in conjunction with the timer control flag provided in b0 of the third data byte B2, the corresponding actions of slave circuits 26(1) and 26(2) may remain identical.

[0041] In this embodiment, the activation of the HLC event trigger HLC11EVT causes the slave circuit 26(1) to interpret the high-level configuration command carried in the HLC message 38 as specific low-level configuration parameters, and to store the low-level configuration parameters in pre-specified registers in registers REG

[000] -REG

[255] of the corresponding register group REGMAP-1. Therefore, the slave circuit 26(1) can perform (multiple) specific actions based on the low-level configuration parameters.

[0042] Similarly, the activation of the HLC event trigger HLC12EVT causes the slave circuit 26(2) to interpret the high-level configuration command carried in the HLC message 40 as specific low-level configuration parameters, and store the low-level configuration parameters in the pre-specified registers REG

[000] -REG

[255] in the corresponding register group REGMAP-2. Therefore, the slave circuit 26(2) can perform (multiple) specific actions based on the low-level configuration parameters.

[0043] The RFFE bus circuit 22 can be used in various circuits to be based on Figure 3 An optimized event-triggered scheme is used to implement serial communication. In one embodiment, Figure 4 It is configured to support Figure 3A schematic diagram of an exemplary power management circuit 42 for an optimized event triggering scheme.

[0044] In this document, the power management circuit 42 includes a transceiver circuit 44, which is configured to act as a transceiver circuit. Figure 2 The main circuit 24 in the RFFE bus circuit 22. The power management circuit 42 also includes a power management integrated circuit (PMIC) 46 and a distributed PMIC (DPMIC) 48. In an embodiment, the PMIC 46 is configured to supply voltage V to the power amplifier circuit 50. CC The voltage can be an envelope tracking (ET) voltage or an average power tracking (APT) voltage. DPMIC 48 is configured to supply a distributed voltage V to the distributed power amplifier circuit 52. CC-D The distributed voltage can also be an ET voltage or an APT voltage. In this document, PMIC 46 is positioned closer to the power amplifier circuit 50 than to the distributed power amplifier circuit 52 to help reduce the voltage V at the power amplifier circuit 50, which could potentially distort the voltage. CC The trace inductance. Similarly, DPMIC 48 is positioned closer to the distributed power amplifier circuit 52 than to the power amplifier circuit 50 to help reduce the voltage V at the distributed power amplifier circuit 52, which could potentially distort the voltage. CC-D The trace inductance.

[0045] PMIC 46 includes a tracker circuit 54 and a voltage circuit 56. The tracker circuit 54 is coupled to the voltage output 58 via a first switch S1 and is configured to provide a low-frequency current I to the voltage output 58 when the first switch S1 is closed. DC On the other hand, voltage circuit 56 is configured to generate voltage V at voltage output 58. CC .

[0046] In this paper, each of the tracker circuit 54 and the voltage circuit 56 is configured to act as Figure 2 A corresponding slave circuit in slave circuits 26(1)-26(N) of the RFFE bus circuit 22. In a non-limiting example, tracker circuit 54 and voltage circuit 56, uniquely identified by USID “11” and “12” respectively, are coupled to transceiver circuit 44 via first RFFE bus 60. Similar to slave circuits 26(1)-26(N), tracker circuit 54 includes a corresponding register set REGMAP-1, and voltage circuit 56 includes a corresponding register set REGMAP-2. In this document, each register set in register sets REGMAP-1 and REGMAP-2 includes multiple registers REG

[000] -REG

[255] .

[0047] In operating mode, tracker circuit 54 and voltage circuit 56 are simultaneously coupled to voltage output 58 to simultaneously supply low-frequency current I to power amplifier circuit 50. DC and voltage V CC In this regard, Figure 5 This provides information on how transceiver circuit 44 can be based on Figure 3 A schematic diagram illustrating the optimized event triggering scheme configuration of tracker circuit 54 and voltage circuit 56. Figure 3 , Figure 4 and Figure 5 The common elements between them are indicated by common element labels and will not be described again here.

[0048] In this document, the timer setting message 34 is directed to the tracker circuit 54, where the timer value T11 is set to the total duration T of HLC messages 38 and 40. TOTAL The timer setting message 36 points to voltage circuit 56, where the timer value T12 can be set to any value.

[0049] The address of HLC message 38 points to tracker circuit 54, where the timer control flag in b7 of the third data byte B2 is set to true (binary "1"). Therefore, tracker circuit 54 will start the timer at the beginning of HLC message 38 (corresponding to b7 of the first data byte B0) and trigger the corresponding HLC event trigger HLC11EVT when the timer expires.

[0050] HLC message 40's address points to voltage circuit 56, where the timer control flag in b7 of the third data byte B2 is set to a false value (binary "0"). Therefore, voltage circuit 56 will cancel the timer and fire the corresponding HLC event trigger HLC12EVT at the end of HLC message 40 (corresponding to b0 of the fourth data byte B3). This is because the timer value T11 is set to the total duration T of HLC messages 38 and 40. TOTAL Therefore, the HLC event triggers HLC11EVT and HLC12EVT are activated simultaneously.

[0051] In this embodiment, the activation of the HLC event trigger HLC11EVT causes the tracker circuit 54 to derive a set of current generation parameters from data bytes B0-B3 in the HLC message 38, thereby providing a low-frequency current I. DCThe tracker circuit 54 can store the derived current generation parameters in any one of the registers REG

[000] -REG

[255] in the register group REGMAP-1. On the other hand, the activation of the HLC event trigger HLC12EVT causes the voltage circuit 56 to derive a set of voltage generation parameters from data bytes B0-B3 in the HLC message 40, thereby generating voltage V. CC Voltage circuit 56 can store the derived voltage generation parameters in any of the registers REG

[000] -REG

[255] in register group REGMAP-2.

[0052] Return to reference Figure 4 The DPMIC 48 includes a distributed tracker circuit 62 and a distributed voltage circuit 64. The distributed tracker circuit 62 is coupled to the distributed voltage output 66 via a second switch S2 and is configured to provide a distributed low-frequency current I to the distributed voltage output 66 when the second switch S2 is closed. DC-D The distributed tracker circuit 62 is also coupled to the voltage output 58 via a third switch S3 and is configured to provide a distributed low-frequency current I to the voltage output 58 when the third switch S3 is closed. DC-D On the other hand, the distributed voltage circuit 64 is configured to generate a distributed voltage V at the distributed voltage output 66. CC-D .

[0053] In this paper, each of the distributed tracker circuit 62 and the distributed voltage circuit 64 is configured to act as Figure 2 The corresponding slave circuit in the slave circuits 26(1)-26(N) in the RFFE bus circuit 22. In a non-limiting example, the distributed tracker circuit 62 and the distributed voltage circuit 64, uniquely identified by USID “13” and “14” respectively, are coupled to the transceiver circuit 44 via the second RFFE bus 68. Similar to the slave circuits 26(1)-26(N), the distributed tracker circuit 62 includes a corresponding register set REGMAP-D1, and the distributed voltage circuit 64 includes a corresponding register set REGMAP-D2. In this document, each register set in register sets REGMAP-D1 and REGMAP-D2 includes multiple registers REG

[000] -REG

[255] .

[0054] The transceiver circuit 44 can also be configured to control the distributed tracker circuit 62 and the distributed voltage circuit 64 based on the same optimized event triggering scheme described above. Furthermore, since the first RFFE bus 60 and the second RFFE bus 68 operate independently of each other, the transceiver circuit 44 can coordinate timer setting messages and HLC messages transmitted via the first RFFE bus 60 and the second RFFE bus 68 to enable more concurrent operation scenarios. Figure 6A and 6B It is shown Figure 4 A schematic diagram of various concurrent operation scenarios in the power management circuit.

[0055] In one example, the third switch S3 can be closed to couple the distributed tracker circuit 62 to the voltage output 58. In this regard, as... Figure 6A As shown, voltage circuit 56 and distributed tracker circuit 62 can be configured according to an optimized event triggering scheme to concurrently fire HLC event triggers. Meanwhile, first switch S1 and second switch S2 can remain open.

[0056] In another example, the first switch S1 and the third switch S3 can be closed to concurrently couple the tracker circuit 54 and the distributed tracker circuit 62 to the voltage output 58. In this regard, as... Figure 6B As shown, the tracker circuit 54, voltage circuit 56, and distributed tracker circuit 62 can be configured according to an optimized event triggering scheme to concurrently fire HLC event triggers. Meanwhile, the second switch S2 can remain open.

[0057] Can be provided in communication devices Figure 4 The power management circuit 42 is configured to support the embodiments described above. In this regard, Figure 7 This is a schematic diagram of an exemplary communication device 100, which can provide... Figure 4 The power management circuit 42.

[0058] In this document, communication device 100 can be any type of communication device, such as a mobile terminal, smartwatch, tablet computer, computer, navigation device, access point, base station (e.g., eNB, gNB), and similar wireless communication devices that support wireless communication (e.g., cellular, wireless local area network (WLAN), Bluetooth, ultra-wideband (UWB), and near-field communication). Communication device 100 typically includes a control system 102, a baseband processor 104, a transmitting circuit system 106, a receiving circuit system 108, an antenna switching circuit system 110, multiple antennas 112, and a user interface circuit system 114. In a non-limiting example, for example, the control system 102 may be a field-programmable gate array (FPGA). In this regard, the control system 102 may include at least multiple microprocessors, multiple embedded memory circuits, and multiple communication bus interfaces. The receiving circuit system 108 receives radio frequency signals from one or more base stations via multiple antennas 112 and via the antenna switching circuit system 110. Low-noise amplifiers and filters are used in conjunction to amplify and eliminate broadband interference in the received signals for processing. Then, a downconversion and digitization circuitry system (not shown) downconverts the filtered received signal to an intermediate frequency (IF) or baseband frequency signal, and then uses (multiple) analog-to-digital converters (ADCs) to digitize the IF or baseband frequency signal into one or more digital streams.

[0059] The baseband processor 104 processes the digitized received signal to extract the information or data bits transmitted in the received signal. This processing typically includes demodulation, decoding, and error correction operations, as will be discussed in more detail below. The baseband processor 104 is typically implemented in one or more digital signal processors (DSPs) and application-specific integrated circuits (ASICs).

[0060] For transmission, baseband processor 104 receives digitized data representing voice, data, or control information from control system 102 and encodes it for transmission. The encoded data is output to transmit circuitry system 106, where multiple digital-to-analog converters (DACs) convert the digitized data into analog signals, and a modulator modulates the analog signals into carrier signals at one or more desired transmission frequencies. A power amplifier amplifies the modulated carrier signal to a level suitable for transmission and delivers it to antenna 112 via antenna switching circuitry system 110. Multiple antennas 112 and replicated transmit circuitry system 106 and receive circuitry system 108 provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

[0061] In an embodiment, the transmitting circuit system 106 can be configured to act as Figure 4 The transceiver circuit 44 is provided in the middle, while PMIC 46 and DPMIC 48 can be provided between the transmitting circuit system 106 and the antenna switching circuit system 110.

[0062] Figure 2 The RFFE bus circuit 22 can be optimized based on a process. In this regard, Figure 8 It is used for optimization Figure 2 A flowchart of an exemplary process 200 for the RFFE bus circuit 22.

[0063] In this document, process 200 includes receiving a timer setting message from timer setting messages 34 and 36, each containing a timer value from timer values ​​T11 and T12 (step 202). Process 200 also includes receiving a corresponding HLC message from HLC messages 38 and 40, each HLC message containing data bytes B0-B3 (step 204). Process 200 further includes starting the corresponding timer to a timer value from timer values ​​T11 and T12 at the beginning of the first data byte (B0-B3) in the corresponding HLC message (38, 40) (step 206). Process 200 also includes receiving a timer control flag from one of the data bytes B0-B3 in the corresponding HLC message (38, 40) (step 208). Process 200 further includes immediately stopping the corresponding timer when the timer control flag is set to a false value "0" (step 210).

[0064] Those skilled in the art will recognize improvements and modifications to the embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the claims below.

Claims

1. A radio frequency front-end (RFFE) bus circuit, comprising: RFFE bus, which is coupled to the main circuitry; as well as Multiple slave circuits, each coupled to the RFFE bus and configured to: Receive a corresponding timer setting message from a plurality of timer setting messages, wherein the corresponding timer setting message includes a corresponding timer value from a plurality of timer values; Receive a corresponding high-level command message from a plurality of high-level command (HLC) messages, each of the plurality of high-level command messages including a plurality of data bytes; At the beginning of the first data byte among the multiple data bytes in a corresponding HLC message, the corresponding timer is started to the corresponding timer value among the multiple timer values; Receive the timer control flag from one of the data bytes in one of the multiple data bytes included in a corresponding HLC message; and The corresponding timer is stopped immediately when the timer control flag is set to a false value.

2. The RFFE bus circuit according to claim 1, wherein the plurality of data bytes in each of the plurality of HLC messages include a first data byte, a second data byte, a third data byte, and a fourth data byte, and the timer control flag is carried in the first bit of the third data byte.

3. The RFFE bus circuit according to claim 1, wherein the plurality of data bytes in each of the plurality of HLC messages include a first data byte, a second data byte, a third data byte, and a fourth data byte, and the timer control flag is carried in the first bit of the fourth data byte.

4. The RFFE bus circuit according to claim 1, wherein each of the plurality of slave circuits is further configured to trigger a corresponding HLC event trigger at the end of a corresponding HLC message among the plurality of HLC messages when the timer control flag is set to the false value.

5. The RFFE bus circuit of claim 4, wherein each of the plurality of slave circuits is further configured to trigger the corresponding HLC event trigger when the corresponding timer expires, provided that the timer control flag is set to true.

6. The RFFE bus circuit of claim 1, wherein the main circuit is configured to transmit the plurality of timer setting messages before the plurality of HLC messages.

7. The RFFE bus circuit of claim 6, wherein the main circuit is further configured to transmit the plurality of HLC messages in the same order as the plurality of timer setting messages.

8. A wireless device, the wireless device including a power management circuit, the power management circuit comprising: Transceiver circuitry and a radio frequency front-end (RFFE) bus coupled to the transceiver circuitry; as well as Power management integrated circuit (PMIC), the power management integrated circuit including: Tracker circuitry and voltage circuitry, each coupled to the RFFE bus and configured as follows: Receive a corresponding timer setting message from a plurality of timer setting messages, wherein the corresponding timer setting message includes a corresponding timer value from a plurality of timer values; Receive a corresponding high-level command message from a plurality of high-level command (HLC) messages, each of the plurality of high-level command messages including a plurality of data bytes; At the beginning of the first data byte among the multiple data bytes in a corresponding HLC message, the corresponding timer is started to the corresponding timer value among the multiple timer values; Receive the timer control flag from one of the data bytes in one of the multiple data bytes included in a corresponding HLC message; and The corresponding timer is stopped immediately when the timer control flag is set to a false value.

9. The wireless device of claim 8, wherein each of the tracker circuit and the voltage circuit is further configured to fire a corresponding HLC event trigger at the end of a corresponding HLC message among the plurality of HLC messages when the timer control flag is set to the false value.

10. The wireless device of claim 9, wherein each of the tracker circuit and the voltage circuit is further configured to trigger the corresponding HLC event trigger when the corresponding timer expires, provided that the timer control flag is set to true.

11. The wireless device according to claim 10, wherein: The tracker circuit is configured to: When the corresponding HLC event trigger is activated, a set of current generation parameters is derived from a corresponding HLC message among the plurality of HLC messages; as well as A low-frequency current is generated based on the set of current generation parameters; and The voltage circuit is configured to: When the corresponding HLC event trigger is activated, a set of voltage modulation parameters is derived from a corresponding HLC message among the plurality of HLC messages; as well as A voltage is generated based on the set of voltage modulation parameters.

12. The wireless device of claim 8, wherein the transceiver circuitry is configured to transmit the plurality of timer setting messages prior to the plurality of HLC messages.

13. The wireless device of claim 12, wherein the transceiver circuitry is further configured to transmit the plurality of HLC messages in the same order as the plurality of timer setting messages.

14. A method for optimizing a radio frequency front-end (RFFE) bus, comprising: Receive a corresponding timer setting message from a plurality of timer setting messages, wherein the corresponding timer setting message includes a corresponding timer value from a plurality of timer values; Receive a corresponding high-level command message from a plurality of high-level command (HLC) messages, each of the plurality of high-level command messages including a plurality of data bytes; At the beginning of the first data byte among the multiple data bytes in a corresponding HLC message, the corresponding timer is started to the corresponding timer value among the multiple timer values; Receive the timer control flag from one of the data bytes in one of the multiple data bytes included in a corresponding HLC message; and The corresponding timer is stopped immediately when the timer control flag is set to a false value.

15. The method of claim 14, wherein the plurality of data bytes in each of the plurality of HLC messages include a first data byte, a second data byte, a third data byte, and a fourth data byte, and the timer control flag is carried in the first bit of the third data byte.

16. The method of claim 14, wherein the plurality of data bytes in each of the plurality of HLC messages includes a first data byte, a second data byte, a third data byte, and a fourth data byte, and the timer control flag is carried in the first bit of the fourth data byte.

17. The method of claim 14, further comprising, when the timer control flag is set to the false value, firing a corresponding HLC event trigger at the end of a corresponding HLC message among the plurality of HLC messages.

18. The method of claim 17, further comprising, when the timer control flag is set to true, triggering the corresponding HLC event trigger when the corresponding timer expires.

19. The method of claim 14, further comprising transmitting the plurality of timer setting messages before the plurality of HLC messages.

20. The method of claim 19, further comprising transmitting the plurality of HLC messages in the same order as the plurality of timer setting messages.

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