Flux lines for manipulating qubits

Abstract

Provided is mitigation of Purcell loss at a qubit frequency. A flux line for manipulating at least one qubit, comprising: a first section (1302) for connecting to an input for receiving a control signal; and a second section (1304, 1604) for coupling the control signal to a superconducting quantum interference device (SQUID) operably connected to the at least one qubit, the second section being arranged in succession relative to the first section (1302), and the first section and the second section being configured to have an impedance mismatch at a qubit frequency of the at least one qubit.

Description

Technical Field

[0001] This invention relates generally to the field of quantum computing. Specifically, this invention relates to flux lines for carrying control signals that manipulate qubits. Background Technology

[0002] A quantum computing device (also known as a quantum computer) uses quantum mechanical phenomena, such as superposition and entanglement, to perform desired quantum computing operations. Unlike conventional computers that manipulate information in the form of bits (e.g., "1" or "0"), quantum computers manipulate information using qubits. A qubit can refer not only to the basic unit of quantum information, but also to a quantum device (e.g., a superposition of "0" and "1") used to store information of one or more qubits.

[0003] Quantum computing devices are implemented using superconducting circuits, which typically employ one or more resonators per qubit for frequency-reused qubit readout, with multiple qubits read out via a single shared probe line. The qubits are coupled to this single shared probe line via the readout resonator and one or more Purcell filter resonators. The resonators should be tuned relative to each other to achieve accurate and reliable readout of the qubit's state.

[0004] Quantum bit manipulation is used in quantum computers to perform quantum operations. Transmission lines (i.e., flux lines) carry control signals, whose magnetic fields are coupled to the qubits to manipulate them. Grounding the flux lines on the same plane near the qubits can cause current to propagate along the qubit plane, as well as DC (direct current) crosstalk to other flux lines and qubits. In large quantum processing units, the number of qubits can be 20 or more, where flux lines and qubits may be close to each other, potentially leading to increased crosstalk.

[0005] In a transmission line, signals propagate through a “transmission line mode,” which is a two-dimensional electromagnetic field pattern that ideally “fits” the cross-section of the transmission line. This is a special field distribution that, if excited at one end, will propagate regularly along the transmission line with the same field distribution. This transmission line mode can be described by a pair of parameters, such as impedance and propagation velocity. In lossy media, there is a third parameter (i.e., loss rate), which is very low for superconducting flux lines. A transmission line with a single conductor supports a single transmission line mode. Therefore, it has a single impedance and propagation velocity. A dual coplanar waveguide supports two transmission line modes. These are two different field distributions that propagate regularly without changing shape or transitioning from one mode to the other. It turns out that (for a symmetrical dual CPW) these modes each have different symmetries: a “differential” mode, where the voltage on one conductor is always opposite to the voltage on the other; and a “common-mode” mode, where the voltages on both conductors are always the same. Each mode has its own characteristic impedance and propagation velocity. The specific values ​​of these parameters depend on the geometry of the transmission line (e.g., linewidth and gap).

[0006] The flux line should be matched to the system impedance (e.g., a 50Ω system impedance) to allow for minimal distortion in the flux pulses at DC and from DC to intermediate frequencies (i.e., below the qubit frequency). However, a 50Ω flux line is difficult to implement on platforms containing multilayer wiring on silicon. Parasitic capacitive coupling leads to Purcell decay channels, which will become limiting as we move towards higher coherence qubits. Summary of the Invention

[0007] This synopsis is provided to introduce, in a simplified form, a series of concepts further described below in the detailed description. This synopsis is neither intended to identify key features of the invention nor to limit its scope.

[0008] The purpose of this invention is to provide a technical solution to reduce Purcell loss at the frequency of qubits.

[0009] The above objectives are achieved by the features of the independent claims in the appended claims. Other embodiments and examples will be apparent from the dependent claims, detailed descriptions, and drawings.

[0010] According to a first aspect, a flux line for manipulating at least one qubit is provided, comprising: - The first section, which is used to connect to the input terminal for receiving control signals; and - A second segment for coupling a control signal to a superconducting quantum interference device (SQUID) operably connected to the at least one qubit, the second segment being arranged continuously relative to the first segment, and the first and second segments being configured to have impedance mismatch at the qubit frequency of the at least one qubit.

[0011] According to a second aspect, a superconducting chip or chip package is provided, comprising one or more qubits and one or more flux lines for manipulating the one or more qubits according to one aspect.

[0012] According to a third aspect, a quantum computing device is provided, comprising at least one superconducting chip or chip package according to one aspect and a control unit connected to the at least one superconducting chip or chip package, wherein the control unit is configured to feed one or more control signals to at least one flux line for manipulating at least one qubit.

[0013] At least some aspects offer ways to mitigate Purcell loss at qubit frequencies. Attached Figure Description

[0014] The invention will now be described with reference to the accompanying drawings, in which: Figure 1a Examples of superconducting circuits according to at least some embodiments are shown; Figure 1b Examples of superconducting chips according to at least some embodiments are shown; Figure 2 and Figure 3 An example of grounding a flux line for control signals in a superconducting chip comprising a single substrate is shown, according to at least some embodiments. Figures 4 to 11 An example of grounding a flux line for control signals in a superconducting chip package is shown, according to at least some embodiments; Figure 12 A block diagram of a quantum computing device according to at least some embodiments is shown; Figures 13 to 16 Examples of flux lines according to at least some embodiments are shown; and Figure 17 and Figure 18 Examples of the characteristics of a flux line according to at least some embodiments are shown. Detailed Implementation

[0015] Various embodiments of the present invention are described in further detail with reference to the accompanying drawings. However, the invention may be embodied in many other forms and should not be construed as limited to any particular structure or function discussed in the following description. Rather, these embodiments are provided to make the description of the invention detailed and complete. Based on the detailed description, it will be apparent to those skilled in the art that the scope of the invention covers any embodiment disclosed herein, whether implemented independently or in combination with any other embodiment of the invention. For example, the chips and devices disclosed herein can indeed be implemented using any number of the embodiments provided herein. Furthermore, it should be understood that any embodiment of the invention may be implemented using one or more elements presented in the appended claims.

[0016] In this application, similar or corresponding elements and components in different figures and embodiments are represented by the same reference numerals. Unless otherwise stated, the use of consistent reference numerals is intended to indicate their similarity or correspondence.

[0017] The term "exemplary" as used herein means "used as an example." Unless otherwise stated, any embodiment described herein as "exemplary" should not be construed as being more preferred or advantageous than other embodiments.

[0018] For convenience, any positioning terms (such as "left," "right," "up," "down," etc.) may be used herein to describe the relationship of an element or feature to one or more other elements or features in accordance with the accompanying drawings. It should be apparent that, in addition to the orientations depicted in the drawings, these positioning terms are intended to cover different orientations of the chip disclosed herein. For example, if the chip in the drawings is imaginarily rotated 90 degrees clockwise, the elements or features described as "left" and "right" relative to other elements or features would be oriented "above" and "below" the other elements or features, respectively. Therefore, the positioning terms used herein should not be construed as any limitation on the invention.

[0019] Although numerical terms such as "first" and "second" may be used herein to describe various embodiments and features, it should be understood that these embodiments and features should not be limited by such numerical terms. These numerical terms are used only herein to distinguish one embodiment or feature from another. Therefore, the first embodiment discussed below may be referred to as the second embodiment, and vice versa, without departing from the teachings of the invention.

[0020] The following embodiments are exemplary. Although the specification may refer to "an," "a," or "some" embodiments in multiple places, this does not necessarily mean that each reference refers to the same embodiment, nor does it mean that the feature is applicable only to a single embodiment. Individual features of different embodiments may also be combined to provide other embodiments.

[0021] As used herein, “at least one of the following” and “at least one” and similar wording, where a list of two or more elements is connected by “and” or “or”, means at least any one element, or at least any two or more elements, or at least all elements.

[0022] As used in the embodiments disclosed herein, a qubit can refer to a superconducting quantum device or superconducting element configured to store one or more qubits of information (or simply qubits). In this sense, a qubit serves as a quantum information storage and processing device. The nonlinear sources in a qubit can be embodied by one or more Josephson junctions. The term "Josephson junction" as used herein has its general meaning and can refer to a quantum mechanical device made of two superconducting electrodes separated by a potential barrier (e.g., a thin insulating tunnel barrier, a common metal, a semiconductor, a ferromagnet, etc.).

[0023] According to embodiments disclosed herein, a quantum computing device (also known as a quantum computer) may refer to a device comprising at least one superconducting chip and a control unit connected to the at least one superconducting chip, wherein the control unit is configured to feed one or more control signals to at least one flux line for manipulating at least one qubit. Manipulating the at least one qubit, or more generally qubit manipulation, enables the quantum computing device to perform quantum computing operations, such as reading the state of the qubit, initializing the state of the qubit, and entanglement of the state of the qubit with the states of other qubits in the quantum computing device. Existing implementations of such quantum computing devices may include superconducting quantum computers, ion trap quantum computers, spin-based quantum computers in semiconductors, cavity quantum electrodynamics-based quantum computers, optical photonic quantum computers, and defect-center-based quantum computers in diamond, etc. The reading may be a frequency-multiplexed reading of qubits connected to a common feed line via a resonator structure.

[0024] As used in the embodiments disclosed herein, flux lines and transmission lines are used interchangeably, with the transmission line arranged to couple a control signal to a superconducting quantum interference device (SQUID) operatively connected to at least one qubit within a superconducting chip or superconducting chip package. The control signal can be a microwave signal carried by the flux line. In one example, the control signal is inductively coupled to the SQUID. Thus, the magnetic field induced by the control signal induces a current in the SQUID, thereby coupling the control signal to both the SQUID and the qubit island containing the qubit. In this way, the qubit can be manipulated by the control signal. The SQUID operates based on the Josephson effect, where superconducting current can tunnel through a thin insulating barrier between two superconductors. This effect is extremely sensitive to magnetic fields in and around the loop formed by the superconductors, which alter the phase difference of the superconducting wavefunction across the junction, thereby changing the current. Therefore, the voltage coupled to the SQUID depends on the magnetic field induced by the control signal. It should be noted that the voltage coupled to the SQUID via inductive coupling should be distinguished from other forms of coupling, such as capacitive coupling (i.e., coupling via an electric field) and coupling via both magnetic and electric fields.

[0025] The exemplary embodiments disclosed herein provide a technical solution for flux lines of superconducting chips or chip packages, wherein Purcell loss at the frequency of qubits can be managed, thereby mitigating or even eliminating the disadvantages of the prior art described above.

[0026] Superconducting circuits are collections of interconnected superconducting elements that work together to perform a specific function. These circuits are typically fabricated on a substrate using superconducting materials such as niobium or aluminum, which exhibit zero resistance at extremely low temperatures. Superconducting circuits can take various forms, such as flux lines, transmission lines, transmission line resonators, coplanar waveguides, Josephson junctions, SQUIDs (superconducting quantum interference devices), or qubits for quantum computing. They are designed to utilize the unique properties of superconductors, such as the ability to carry continuous current and exhibit quantum effects. Superconducting circuits are used in applications such as quantum computing, high-speed digital electronics, and ultrasensitive detectors.

[0027] A superconducting chip refers to the physical realization of superconducting circuits on a chip-scale device. It involves fabricating superconducting circuits on a small semiconductor substrate, typically made of silicon or sapphire, using advanced microfabrication techniques. A superconducting chip typically contains multiple superconducting elements, such as flux lines, transmission lines, transmission line resonators, coplanar waveguides, Josephson junctions, or SQUIDs, which are interconnected to form a functional circuit. The chip may also include control and readout electronics, cryogenic cooling infrastructure, and other components required for its operation. In the context of quantum computing, multiple superconducting qubits can be integrated onto a single chip. These qubits can be collectively manipulated and measured to perform quantum computations. Superconducting chips are also used in other applications such as analog-to-digital converters, microwave amplifiers, and signal processing systems.

[0028] Flip-chip bonding is a packaging technique used for electronic devices, particularly in the microelectronics and semiconductor industries. It involves directly attaching an integrated circuit (IC) chip to a substrate or another chip, typically using solder bumps or other conductive materials. The term "flip-chip" refers to the orientation of the IC chip during the bonding process. Unlike traditional packaging methods where the active side of the chip faces upwards, the chip is flipped so that the active side containing the circuitry and contact pads faces downwards. This allows for direct electrical connections between the chip and the substrate or other chips. The bonding process involves aligning the solder bumps or conductive contacts on the chip with corresponding pads or traces on the substrate. The chip is then pressed onto the substrate, and the solder bumps are heated, melting the solder and establishing electrical and mechanical connections between the chip and the substrate. Once the solder cools and solidifies, it forms a reliable and high-density interconnect between the chip and the substrate.

[0029] A qubit plane is a conductive plane on a superconducting chip that includes one or more qubits. Flux lines used to control the associated qubits are located on adjacent conductive planes on the superconducting chip. Each flux line is connected at one end to a control signal source and at the other end positioned close to the qubit associated with that flux line. In this way, the magnetic flux of the control signal can be coupled to a SQUID operatively connected to the qubit associated with that flux line.

[0030] A qubit island refers to a portion (e.g., region) of a superconducting chip that contains one or more qubits.

[0031] Figure 1aAn example of a superconducting circuit according to at least some embodiments is shown. The superconducting circuit includes at least one qubit 102 and a flux line 106 arranged to manipulate the at least one qubit. Manipulation of the at least one qubit is provided by coupling a control signal to the at least one qubit. The control signal can be coupled to the at least one qubit via inductive coupling from a control signal to a SQUID, which is operatively coupled to the at least one qubit. The flux line extends longitudinally between opposite ends. At one end of the flux line, the flux line is connected to at least one input terminal 103 for receiving the control signal, and at the other end of the flux line, very close to the at least one qubit, for coupling the control signal to the at least one qubit. At the end of the flux line close to the at least one qubit, the flux line can be arranged to route to at least one ground terminal 105. Thus, at one end of the flux line, the flux line can be arranged at a location 111 that provides coupling of the control signal to the at least one qubit and routing of the flux line to ground. In one example, at the end of the flux line near the at least one qubit, the flux line can be connected to a conductor arrangement 108, which is connected to at least one ground terminal. This at least one ground terminal can be on the opposite side of a substrate different from the at least one qubit, or on another substrate different from the at least one qubit, whereby the conductor arrangement is configured to deflect the flux line away from the qubit plane. This helps mitigate crosstalk from the grounded flux line to other flux lines and their associated qubits. In one example, in the coupling of a control signal to the at least one qubit 102, the control signal can induce a magnetic flux Mcpl to the at least one qubit, thereby allowing the at least one qubit to be manipulated. Grounding the flux line at the end near the at least one qubit helps control parasitic coupling Ccpl that causes Purcell decay. In one example, the superconducting circuit can be implemented using a superconducting chip or chip package, whereby the flux line can be disposed together with the at least one qubit on an adjacent plane. It should be noted that the flux line is electrically isolated from the at least one qubit and is sufficiently close to the at least one qubit at a location (e.g., at a sufficiently close distance) where the magnetic flux of the control signal is coupled to the at least one qubit (Mcpl). It should also be noted that when the flux line is at least partially a self-coupled transmission line, the flux line can be routed to the return path of the differential signal, rather than routing the control signal to the at least one ground terminal.

[0032] Figure 1b Examples of superconducting chips according to at least some embodiments are shown. Figure 1b The superconducting chip shows Figure 1aA chip-level implementation of a superconducting circuit. The superconducting chip includes a qubit island 110, which includes at least one qubit and a SQUID 107 operably connected to the at least one qubit. A flux line is positioned very close to the qubit island for coupling control signals to the SQUID to manipulate the qubit. In one example, the control signal can induce a magnetic flux Mcpl to the SQUID operably connected to the at least one qubit, thereby allowing the at least one qubit to be manipulated. The end of the flux line near the at least one qubit is routed to ground 109, for example, via a conductor arrangement 108.

[0033] Figure 2 and Figure 3 An example of grounding flux lines for control signals in a superconducting chip comprising a single substrate is shown, according to at least some embodiments. The flux lines are routed away from the qubit plane and terminated to ground, thereby mitigating crosstalk between the grounded flux lines and the qubit plane. Superconducting chips 100 and 101 can implement... Figure 1a Superconducting circuit or reference Figure 1a At least some of the elements described. Figure 2 and Figure 3The examples shown can be used in superconducting chip packages including more than one superconducting chip bonded together. Each superconducting chip 100, 101 includes at least one substrate 104 on which at least one qubit 102 is disposed and a flux line 106 arranged to couple control signals to the qubit. The superconducting chip includes at least one ground terminal 105 on the opposite side of the substrate relative to the at least one qubit 102. The superconducting chip includes a conductor arrangement 108 connected to an end of the flux line arranged at the at least one qubit. The conductor arrangement is arranged to connect the flux line to the at least one ground terminal 105. The conductor arrangement may include at least one portion 208 configured to extend through the first substrate 104 and at least one portion 210 configured to connect the flux line 106 to the at least one ground terminal located on the opposite side of the substrate relative to the at least one qubit 102. In one example according to at least some embodiments, the conductor arrangement (e.g., a first portion of the conductor arrangement) includes a through-silicon via (TSV). In one example, the TSV may be configured to extend through the first substrate 104 between opposing surfaces of the substrate. In one example according to at least some embodiments, the conductor arrangement (e.g., a first portion of the conductor arrangement) includes a through-silicon via (TSV) and a wire (e.g., a second portion) configured to connect the TSV to the at least one ground terminal. In one example, the TSV may be configured to extend through the first substrate 104 between opposing surfaces of the substrate, and the wire may extend between an end of the TSV located on a different side of the substrate from the at least one qubit and the at least one ground terminal. In one example, the at least one ground terminal 105 may be located on a different side of the substrate 104 from the at least one qubit, at the edge of the first substrate 104.

[0034] Figures 4 to 11 An example of grounding flux lines used for control signals in a superconducting chip package is shown, according to at least some embodiments. The flux lines are routed away from the qubit plane and terminated to ground, thereby mitigating crosstalk between the grounded flux lines and other flux lines and their associated qubits. The superconducting chip package includes superconducting chips bonded together to form a chip package. (Refer to...) Figure 4 and Figure 5 , Figure 4 and Figure 5 Each superconducting chip package 400, 401 includes a first substrate 104, wherein the grounding arrangement of the flux lines for control signals is consistent with that of the reference. Figure 2 and Figure 3 Similar to the description of superconducting chips, the difference being that the superconducting chip package includes a bonding substrate, and the first substrate 104 is relative to... Figure 2 and Figure 3The superconducting chip shown is vertically flipped. Therefore, superconducting chip package 400 includes another substrate 406 or a second substrate bonded to the first substrate 104 via one or more bonding elements 410, wherein the at least one qubit 102 is disposed. Similarly, superconducting chip package 401 includes another substrate 406 or a second substrate bonded to the first substrate 104 via one or more bonding elements 410, wherein the at least one qubit 102 is disposed. Thus, superconducting chip packages 400, 401 include stacked substrates, wherein at least one surface of each substrate faces the other substrate. In one example, the stacked substrates can be provided by flip-chip bonding of substrates 104, 406. In one example, the other substrate 406 and the first substrate 104 are separated by a gap 402 formed between the other substrate 406 and the first substrate 104 by the one or more bonding elements.

[0035] Reference Figure 6 and Figure 7 , Figure 6 and Figure 7 Each superconducting chip package 600, 601 includes superconducting chips bonded together to form a chip package. (See reference...) Figure 6 and Figure 7 , Figure 6 and Figure 7Each superconducting chip package 600, 601 includes a first substrate 104 and another substrate 406 or a second substrate. The first substrate includes at least one qubit 102. The other substrate or second substrate is bonded to the first substrate 104 via one or more bonding elements 410, wherein the at least one qubit 102 is disposed. The other substrate 406 includes at least one flux line 106 arranged to couple a control signal to the at least one qubit 102 and at least one ground terminal 105. The flux line includes one end disposed at the at least one qubit for coupling the control signal to the at least one qubit. In one example, the end of the flux line is disposed on the other substrate at a position below the at least one qubit on the first substrate. Therefore, the end of the flux line can be positioned on the side of the other substrate 406 facing the first substrate, whereby the flux line can be coupled to the at least one qubit through the gap 602 between the substrates. In one example, the at least one ground terminal 105 is on the opposite side of another substrate relative to the at least one qubit 102, whereby the at least one ground terminal is separated from the first substrate by the other substrate and a gap 602 between the first substrate and the other substrate. In one example, a flux line 106 may be positioned on the side of another substrate 406 facing the first substrate 104. Each superconducting chip package 600, 601 may include a conductor arrangement 108 connected to said end of the flux line, the conductor arrangement being arranged to route the flux line to the at least one ground terminal 105. In one example according to at least some embodiments, the conductor arrangement 108 is configured to extend through the other substrate 406 and connect the flux line 106 to the at least one ground terminal 105 on the opposite side of the other substrate opposite to the side facing the at least one qubit. Figure 6 In one example, the conductor arrangement may include a portion 208 configured to extend through a first substrate 104 and connect a flux line 106 to at least one portion 208 of at least one ground terminal 105 located on the opposite side of the substrate relative to the at least one qubit 102. According to... Figure 7In one example, the conductor arrangement may include at least one portion 208 (e.g., a TSV) configured to extend through a first substrate 104 and at least one portion 210 (e.g., a wire) configured to connect to a first portion located on the side of the substrate opposite to the at least one qubit 102 and to the at least one ground terminal 105 located on the other side of the substrate to connect a flux line 106 to the at least one ground terminal. In one example according to at least some embodiments, the conductor arrangement includes at least one through-silicon via (TSV); or a series connection of at least one TSV and at least one wire. In one example, the TSV may be configured to extend through another substrate 406 between opposing surfaces of another substrate. In one example according to at least some embodiments, the conductor arrangement includes a TSV and a wire configured to connect the TSV to the at least one ground terminal. In one example, the TSV may be configured to extend through another substrate 406 between opposing surfaces of another substrate, and the wire may extend between the end of the TSV located on the side of the other substrate opposite to the side facing the at least one qubit and the at least one ground terminal. In one instance, the at least one ground terminal 105 may be located on a side of another substrate 406 that is different from the at least one qubit, at the edge of the other substrate 406.

[0036] Reference Figures 8 to 11 , Figures 8 to 11 Each superconducting chip package 800, 801, 1000, 1001 includes a first substrate 104 and another substrate 406 or a second substrate. The first substrate includes at least one qubit 102 located on the first substrate and at least one flux line 106 including one end disposed at the at least one qubit for coupling a control signal to the at least one qubit. The other substrate or the second substrate includes at least one ground terminal 105. Each superconducting chip package 800, 801, 1000, 1001 includes a conductor arrangement 108 connected to said one end of the flux line, the conductor arrangement being arranged to connect the flux line to the at least one ground terminal 105. (Refer to reference...) Figure 4 , Figure 5 , Figure 6 and Figure 7 The superconducting chip packaging described is similar. Figures 8 to 11 The superconducting chip packages 800, 801, 1000, and 1001 include superconducting chips bonded together to form a chip package, and the superconducting chip package includes bonding substrates separated by gaps 802. Unlike superconducting chip packages 600 and 601, Figures 8 to 11 The superconducting chip packages 800, 801, 1000, and 1001 in the reference are... Figure 2 , Figure 3 , Figure 4 and Figure 5The described superconducting chip similarly includes at least one quantum bit 102 and flux line 106 on the same substrate 104. On the other hand, unlike the superconducting chip packages 400, 401, 600, and 601, Figures 8 to 11 The superconducting chip packages 800, 801, 1000, and 1001 include a conductor arrangement 108 that includes a bonding element 808 for connecting a flux line 106 to the at least one ground terminal 105 on another substrate. In one example according to at least some embodiments, the conductor arrangement 108 includes at least one bonding element 808 configured to extend between a first substrate 104 and a second substrate 406 and connect the flux line 106 to the at least one ground terminal 105 on the second substrate 406.

[0037] According to Figure 8 In one example, conductor arrangement 108 may include at least one bonding element 808 configured to extend between a first substrate 104 and a second substrate 406 and to connect flux line 106 to the at least one ground terminal 105 on the second substrate 406.

[0038] According to Figure 9 In one example, conductor arrangement 108 may include at least one bonding element 808 configured to extend between a first substrate 104 and a second substrate 406 and to connect flux line 106 to at least one conductor 910 configured to connect to bonding element 808 and at least one ground terminal 105.

[0039] In one example according to at least some embodiments, conductor arrangement 108 is configured to connect flux line to at least one ground terminal 105 by at least one of the following: bonding element 808; or series connection of at least one through-silicon via and at least one conductor 910; or series connection of at least one bonding element 808, at least one through-silicon via and at least one conductor 910.

[0040] In one example, the TSV can be configured to extend through the other substrate 406 between opposing surfaces, and the wire 910 can extend at one end of the TSV on the side of the other substrate opposite to the side facing the at least one qubit 102. The at least one ground terminal 105 can be located on the side of the other substrate 406 different from the at least one qubit, at the edge of the other substrate 406. In one example, the TSV can be connected at one end to the wire 910 and at the other end to the junction element 808.

[0041] Examples of materials used for conductive layers, conductive surface layers, or conductors include at least one of the following: copper; or copper oxide; or indium; or germanium; or niobium; aluminum; aluminum oxide; or alloys of one or more of the above; or other materials that exhibit superconducting behavior at low temperatures. Examples of other materials include organically engineered materials, such as carbon nanotubes. Various engineered silicon-based / ceramic materials are also foreseeable when made into superconductors during chip substrate fabrication.

[0042] Figure 12 A block diagram of a quantum computing device 1200 according to at least some embodiments is shown. Device 1200 includes at least one superconducting chip or superconducting chip package 1202 and a control unit 1204 connected to the at least one superconducting chip or chip package. Chip 1202 may include, according to reference... Figures 2 to 11 The one or more superconducting chips or superconducting chip packages described herein. The one or more superconducting chips or chip packages may include, according to reference... Figures 13 to 16 The described one or more flux lines. Control unit 1204 is configured to feed one or more control signals to at least one flux line of the one or more superconducting chips or chip packages to manipulate at least one quantum bit.

[0043] In one example according to at least some embodiments, the quantum computing device 1200 includes at least one superconducting chip or superconducting chip package 1202, the superconducting chip or superconducting chip package including at least one arrangement including at least one qubit located on a first substrate; at least one flux line including one end arranged at the at least one qubit for coupling control signals to a superconducting quantum interference device (SQUID) operatively connected to the at least one qubit; at least one ground terminal located on the other side of the first substrate relative to the at least one qubit or on a second substrate stacked with the first substrate; and a conductor arrangement connected to said one end of the flux line and arranged to route the flux line to the at least one ground terminal; and the quantum computing device 1200 further includes a control unit 1204 connected to the at least one superconducting chip or superconducting chip package, and the control unit is configured to feed one or more control signals to the at least one flux line for manipulating the at least one qubit. Device 1200 may also include a memory 1206 storing executable instructions 1208, which, when executed by control unit 1204, enable control unit 1204 to perform quantum computing operations. Control unit 1204 may also store the results of the quantum computing operations in memory 1206. Note that the number, arrangement, and interconnection of the building blocks constituting device 1200 (e.g., Figure 12 (As shown) is not intended to limit this disclosure in any way, but is merely intended to provide a general concept of how building elements can be implemented within the device 1000.

[0044] Control unit 1204 may refer to a central processing unit (CPU), a general-purpose processor, a single-purpose processor, a microcontroller, a microprocessor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a complex programmable logic device, etc. It should also be noted that control unit 1204 can be implemented as any combination of one or more of the above. As an example, control unit 1204 may be a combination of two or more microprocessors.

[0045] The memory 1206 can be implemented as a classic non-volatile or volatile memory used in modern electronic computing devices. Examples of non-volatile memory include read-only memory (ROM), ferroelectric random access memory (RAM), programmable ROM (PROM), electrically erasable PROM (EEPROM), solid-state drives (SSDs), flash memory, disk storage devices (such as hard disk drives and magnetic tapes), optical disk storage devices (such as CDs, DVDs, and Blu-ray discs), etc. Examples of volatile memory include dynamic RAM, synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), static RAM, etc.

[0046] The executable instructions 1208 stored in memory 1206 can be configured as computer-executable code, which enables control unit 1204 to perform quantum computing operations using chip 1202. The computer-executable code for performing quantum computing operations can be written in any combination of one or more programming languages, such as Java, C++, etc. In some instances, the computer-executable code can be in high-level language form or pre-compiled form and generated on-the-fly by an interpreter (also pre-stored in memory 1206).

[0047] Figure 13 Examples of flux lines according to at least some embodiments are shown. Flux lines help mitigate Purcell loss at qubit frequencies. Flux line 106 passes through... Figure 1a A chip-level implementation of a superconducting circuit is illustrated. A flux line is disposed on a superconducting chip including a qubit island 110. The qubit island includes at least one qubit and a SQUID 107 operatively connected to the at least one qubit. According to at least some embodiments, the flux line includes a first segment 1302 for connection to an input for receiving a control signal, and a second segment 1304 for coupling the control signal to the at least one qubit arranged continuously relative to the first segment. The first and second segments are configured to have an impedance mismatch 1306 at the qubit frequency of the at least one qubit.

[0048] In one example according to at least some embodiments, the second segment 1304 has a longitudinal dimension that is a multiple of half the wavelength of the wave of the control signal carried by the flux line at the qubit frequency of the at least one qubit.

[0049] In one example according to at least some embodiments, the second segment 1304 has a lower impedance than the first segment at least at the qubit frequency of the at least one qubit. This mitigates Purcell loss at the qubit frequency. In one example, the first segment has an impedance matched to the system impedance connected to the first segment at the input for feeding control signals to the flux line. The second segment is impedance mismatched with the system impedance. In one example, the impedance of the first segment may be 50 Ω, and the impedance of the second segment may be at least 10 Ω at the qubit frequency of the at least one qubit.

[0050] In one example according to at least some embodiments, the second segment 1304 includes one end coupled to the first segment 1302 and another end located near the qubit associated with the flux line 106. The end near the qubit (i.e., the other end) is routed to ground. In this way, the magnetic flux of the control signal can be coupled to the qubit associated with the flux line, while mitigating parasitic coupling to the qubit.

[0051] Figure 14 Examples of flux lines according to at least some embodiments are shown. Flux lines help mitigate Purcell loss at qubit frequencies. Flux line reference Figure 13 Describe the project as described. (Refer to the reference.) Figure 13 The flux lines described are different. Figure 14 The flux line segments are connected via inductor 1406. Thus, the first segment 1302 and the second segment 1404 of the flux line are configured to have impedance mismatch at the qubit frequency of at least one qubit manipulated by the control signal carried by the flux line 106. In one example, the impedance of the segment 1404 of the flux line closest to the qubit may be lower than the impedance of the segment 1302 used for connection to the input, or the impedances of these segments may be the same, for example, at least 50Ω at the qubit frequency of the at least one qubit. Therefore, in Figure 14In the flux line 106, a first segment 1302 is included for connection to an input for receiving a control signal, and a second segment 1404 is included for coupling the control signal to a superconducting quantum interference device (SQUID) operatively connected to the at least one qubit, wherein the second segment is arranged continuously relative to the first segment. The flux line also includes an inductor 1406 configured to connect the first segment 1302 and the second segment 1304. Thus, the inductor is connected in series with the first and second segments, resulting in an impedance mismatch between the first and second segments at the qubit frequency of the at least one qubit. In one example, the inductor 1406 may be, for example, a junction line, a lumped element inductor, or a waveguide segment with an inductance per unit length greater than that of the second segment 1404.

[0052] In one example according to at least some embodiments, the second segment 1404 has a longitudinal dimension that is a multiple of half the wavelength of the wave of the control signal carried by the flux line at the qubit frequency of the at least one qubit.

[0053] Figure 15 Examples of flux lines according to at least some embodiments are shown. Flux lines help mitigate Purcell loss at qubit frequencies. Flux line reference Figure 13 Describe the project as described. (Refer to the reference.) Figure 13 The described flux line differs from others, in that it includes a filter, such as a low-pass filter or a band-stop filter (F) 1506, configured to connect a first segment 1302 of the flux line to a second segment 1504. Thus, the first segment 1302 and the second segment 1504 of the flux line are configured to have impedance mismatch at the qubit frequency of at least one qubit manipulated by a control signal carried by the flux line 106. For example, the impedance of the second segment 1504 of the flux line near the qubit may be lower than the impedance of the segment 1302 used for connection to the input, or the impedances of these segments may be the same, for example, at least 50Ω at the qubit frequency of the at least one qubit. In one example, the order of the low-pass filter or band-stop filter 1506 may be designed to increase Purcell protection and to adjust the frequency response of the filter at low frequencies, such as the flatness of the frequency response. In one example according to at least some embodiments, the second segment 1504 has a longitudinal dimension that is a multiple of half the wavelength of the wave of the control signal carried by the flux line at the qubit frequency of the at least one qubit.

[0054] In one example, filter 1506 may be a low-pass filter having a passband at a frequency of the control signal below the qubit frequency of the at least one qubit, and the qubit frequency being located in the stopband of the low-pass filter. In one example, mitigation of Purcell loss can be achieved by designing the impedances of the passband and stopband of the low-pass filter. The impedance of the low-pass filter may be matched to the impedance of the first segment 1302 at the passband, and the impedance of the low-pass filter may be higher than the impedance of the first segment 1302 at the stopband. The second segment 1504 may have the same impedance as the first segment. In one example, both the first and second segments may have an impedance of 50Ω at least at the qubit frequency of the at least one qubit.

[0055] In one example, a band-stop filter has a stopband at the qubit frequency.

[0056] In one instance, Figure 13 , Figure 14 and Figure 15 The longitudinal dimension or length of the second segment 1304, 1404, 1504 can be defined relative to the wave propagation speed in the flux line. Therefore, for the flux line and the segment to have a phase propagation speed v, the wavelength λ in the flux line or the segment of the flux line becomes... λ = v / f, (1) Where f is the frequency of the quantum bit.

[0057] Figure 16 Examples of flux lines according to at least some embodiments are shown. Flux lines help mitigate Purcell loss at qubit frequencies. Flux lines are referenced where applicable. Figure 13 The described item is used to describe the flux line. The flux line includes a first segment 1302 for connection to an input for receiving a control signal 1301 and a second segment 1604 for coupling the control signal to a superconducting quantum interference device (SQUID) operably connected to the at least one qubit, wherein the second segment is arranged continuously relative to the first segment. (Refer to reference...) Figure 13Unlike the described flux line, the second segment 1604 is a self-coupled transmission line having at least two transmission line modes, including a differential mode and a common-mode mode. The differential mode has an impedance matched to the impedance of the first segment, and the common-mode mode has an impedance lower than that of the differential mode. Thus, the flux line is configured to have impedance mismatch at the qubit frequency of at least one qubit manipulated by the control signal carried by the flux line 106. For example, the second segment 1604 can be formed by two consecutive portions of the transmission line, namely, the second segment 1604. The consecutive portions of the second segment 1604 may include a first portion 1606, which routes from the first segment 1302 toward the at least one qubit to a position 1601 close to the at least one qubit, for coupling the control signal from the second segment to the at least one qubit. From this position, a second portion 1608 of the second segment 1604 begins, and the second portion of the second segment routes parallel to the first segment away from the qubit. At the end of the second portion 1608, the second segment 1604 can be routed to ground 105. Alternatively, at the end of the second portion, the second segment can be routed to ground 105 or to the return path of the differential signal. In one example, the first and second portions of the second segment can have at least one common-mode mode and at least one differential mode, and the impedance of the second segment in the at least one common-mode mode is lower than the impedance of the second segment in the at least one differential mode. It should be noted that Purcell attenuation occurs through the at least one common-mode mode, and the second segment can have low impedance in the at least one common-mode mode to mitigate Purcell attenuation. It should be noted that the impedance of the at least one differential mode can be matched to the impedance of the input terminal used to receive the control signal or the system impedance. Figure 16 In the example of a flux line, the voltage on the qubit is coupled to the common-mode of the second segment, thereby producing (approximately) equal voltages on the left and right conductors of the transmission line (i.e., the first and second portions of the second segment). On the other hand, the control signal can be coupled to the differential mode of the second segment. The differential mode has an impedance matched to the impedance of the control current source (e.g., the impedance of the first segment), and the impedance of the common-mode is lower than that of the differential mode, which helps reduce Purcell losses.

[0058] In one example according to at least some embodiments, flux line 106 includes a filter 1610 for common-mode rejection, which is operatively connected to the self-coupled transmission line. This filter provides an enhanced effect in mitigating Purcell loss at qubit frequencies. In one example, the filter is connected to two consecutive portions of a second segment 1604.

[0059] In one example according to at least some embodiments, the second segment 1604 is a double-coplanar waveguide. In one example, the double-coplanar waveguide includes parallel conductive paths (or stripes) on the same plane as a nearby ground plane. These two conductive paths are closely spaced and can be coupled to each other, a form of self-coupling. The double-coplanar waveguide supports two transmission line modes. These two transmission line modes are two different field distributions, each propagating regularly without changing shape or transitioning from one mode to the other. For a symmetrical double-coplanar waveguide, the two transmission line modes each have different symmetries: a "differential" mode, where the voltage on one conductor is always opposite to the voltage on the other conductor; and a "common-mode" mode, where the voltages on both conductors are always the same. Each mode has its own characteristic impedance and propagation speed. The impedance and propagation speed depend on the geometry of the transmission line (e.g., linewidth and gap). Figure 16 In this example, the voltage of the qubit is coupled to the common-mode: the voltage of the qubit causes (approximately) equal voltages on the left and right conductors of the transmission line. On the other hand, the control current can be coupled to the differential mode via connections as shown and described herein. The benefit is gained when the common-mode has a lower impedance than the differential mode (reducing Purcell losses) but the differential mode has an impedance matched to the control current source.

[0060] According to at least some embodiments, reference Figures 13 to 15 The described flux lines can be used in superconducting chips and superconducting chip packages according to reference. Figures 2 to 11 The method described is grounding.

[0061] Figure 17 and Figure 18 Examples of characteristics of a flux line according to at least some embodiments are shown. The flux line may have impedance mismatch between segments. An impedance-mismatched flux line includes a first segment each having a 50Ω impedance and a second segment each having a 10Ω impedance. Impedance-mismatched flux lines with second segments having different longitudinal dimensions or lengths, as well as a standard 50Ω flux line 'SL', are shown with amplitude response 1702, phase response 1704, and Purcell limit 1710 on T1. 'SL' does not have impedance mismatch and is impedance matched to the system, in this case, 50Ω. The length of the second segment is a multiple of half the wavelength of the wave of the control signal carried by the flux line at the qubit frequency of the at least one qubit, therefore... n×λq / 2, (2) Where n is an integer value of 1, 2, 3, 4, 5, 6, 7, 8, 10 or higher, and λq is the wavelength of the qubit frequency. The first segment can be connected to a control signal source with a 50Ω impedance. Therefore, the first segment is impedance matched to the signal source. The response of the control signal fed to the flux line is shown by the amplitude response 1702 and the phase response 1704 over the frequency range of 0 to 6 GHz. At low frequencies, the amplitude response of the impedance-mismatched flux line is essentially the same as that of the standard 50Ω flux line 'SL'. The phase response of the flux line is flat at low frequencies, similar to 'SL'. The Purcell limit 1710 on T1 of the flux line shows an improvement 1712 at the qubit frequency (i.e., 5 GHz) compared to the conventional flux line 'SL'.

[0062] Figure 18 The impulse response 1802 and step response 1804 of an impedance-mismatched flux line with a second segment length of 3×λq / 2 are shown. Impulse response 1802 and step response 1804 illustrate attenuated reflections due to impedance mismatch between segments of the flux line. The pulse shape 1806 of a Gaussian pulse with a rise time of 1 ns and sigma = 1 ns entering an impedance-mismatched flux line with a second segment length of 3×λq / 2 shows a negligible change in pulse shape between the input and output pulses.

[0063] Electromagnetic coupling between components of a superconducting circuit can be, for example, capacitive, inductive, or both. In some embodiments, coupling between components is achieved through spatial coupling between two chips on which two components are respectively positioned. For example, in some embodiments, qubits positioned on a first substrate can be electromagnetically coupled to a readout resonator or flux line positioned on a second substrate, which can be bump-bonded to and facing the first substrate. In some embodiments, the coupling is in-plane coupling, with the direction of the coupling electric and / or magnetic fields substantially in the plane of a side surface of the chip on which both components are positioned. For example, in some embodiments, qubits on a first surface of a silicon substrate can be electromagnetically coupled to a readout resonator or flux line on the first surface of the silicon substrate.

[0064] Superconducting quantum circuits include components for performing computational operations based on quantum operations. The components of the superconducting quantum circuits disclosed herein (also referred to as quantum circuit components or quantum computing circuit components) include circuit components for performing quantum operations. That is, superconducting quantum circuit components are configured to perform operations on data in a nondeterministic manner using quantum mechanical phenomena such as superposition and entanglement. Some superconducting quantum circuit components (such as qubits) can be configured to represent and manipulate information in more than one state simultaneously. Examples of superconducting quantum circuit components include circuit elements such as quantum LC oscillators, qubits (e.g., flux qubits, phase qubits, or charge qubits), readout resonators, flux lines, readout transmission lines, coplanar waveguides, amplifiers, and superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUIDs or DC SQUIDs), etc.

[0065] In contrast, classical circuit elements typically process data in a deterministic manner. Classical circuit elements can be configured to collectively execute the instructions of a computer program by performing basic arithmetic, logic, and / or input / output operations on data, where the data is represented in analog or digital form. In some implementations, classical circuit elements can be used to send data to and / or receive data from quantum circuit components via electrical or electromagnetic connections. Examples of classical circuit elements include CMOS-based circuit elements, fast single-flux quantum (RSFQ) devices, reciprocal quantum logic (RQL) devices, and ERSFQ devices, which are energy-efficient versions of RSFQs that do not use bias resistors.

[0066] Any or all components mentioned in this disclosure, including qubits, readout resonators, flux lines, readout transmission lines, and amplifiers, may be made of superconducting materials such as aluminum, niobium, or titanium nitride, as well as other superconducting materials. These components may include both superconducting and nonconducting materials.

[0067] The fabrication of the electrical components disclosed herein may require the deposition of one or more materials, such as superconductors, dielectrics, and / or metals. Depending on the selected materials, these materials may be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), or epitaxial techniques, as well as other deposition processes. The processes described herein for fabricating electrical components may require the removal of one or more materials from the device during fabrication. Depending on the material to be removed, the removal process may include, for example, wet etching, dry etching, or a stripping process. The materials forming the electrical components described herein may be patterned using known photolithography techniques, such as photolithography or electron beam lithography. It should be noted that the processes described herein for fabricating electrical components may further involve flip-chip fabrication, in which devices are flipped over and directly attached to another device, thereby enabling more efficient and compact packaging.

[0068] During the operation of a quantum computing system using circuit elements partially formed of superconductors (such as those described herein), the circuit elements are cooled within a cryostat to a temperature that allows the superconducting material to exhibit superconducting properties. Superconducting materials can be understood as materials that exhibit superconducting properties at or below the superconducting critical temperature. Examples of superconducting materials include aluminum (superconducting critical temperature of 1.2 Kelvin) and niobium (superconducting critical temperature of 9.3 Kelvin). Therefore, superconducting structures (such as superconducting traces and superconducting ground planes) are formed from materials that exhibit superconducting properties at or below the superconducting critical temperature.

[0069] In some implementations, control signals for quantum circuit components (e.g., qubits and qubit couplers) can be provided using classical circuit elements electrically and / or electromagnetically coupled to the quantum circuit components. The control signals can be provided in digital and / or analog form.

[0070] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of the claimed protection, but rather as descriptions of features that may be specific to a particular implementation. Some features described in this specification in the context of standalone embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually in multiple embodiments or in any suitable sub-combination.

[0071] Although exemplary embodiments of the invention have been described herein, it should be noted that various changes and modifications can be made to the embodiments of the invention without departing from the legal protection defined by the appended claims. In the appended claims, the word "comprising" does not exclude other elements or operations, and the indefinite article "a" or "an" does not exclude a plurality. The fact that certain measures are recited in mutually different dependent claims does not imply that combinations of these measures cannot be advantageously used.

[0072] Furthermore, although the features may be described above as functioning in certain combinations and even initially claimed to be so, in some cases, one or more features from the claimed combinations may be removed from the combinations and the claimed combinations may involve sub-combinations or variations thereof.

[0073] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired result. As an example, the processes depicted in the drawings do not necessarily require the specific order or sequence shown to achieve the desired result.

[0074] Reference Symbol List

Claims

1. A flux line for manipulating at least one qubit, comprising: - The first section (1302) is used to connect to the input terminal for receiving control signals; as well as - A second segment (1304, 1604) for coupling the control signal to a superconducting quantum interference device (SQUID) operably connected to the at least one qubit, the second segment being arranged consecutively relative to the first segment (1302), and the first and second segments being configured to have impedance mismatch at the qubit frequency of the at least one qubit.

2. The flux line according to claim 1, wherein the longitudinal dimension of the second segment (1302) is a multiple of half the wavelength of the wave of the control signal carried by the flux line at the qubit frequency of the at least one qubit.

3. The flux line according to claim 1 or 2, wherein the second segment (1304) has a lower impedance than the first segment at least at the qubit frequency of the at least one qubit.

4. The flux line according to claim 1, 2 or 3, comprising a low-pass filter or a band-stop filter configured to connect the first segment (1302) and the second segment (1304).

5. The flux line according to claim 1, 2 or 3, comprising an inductor connected in series with the first segment (1324) and the second segment (1304).

6. The flux line according to any one of claims 1 to 5, wherein the second segment (1304) comprises one end coupled to the first segment (1302) and another end located near the qubit associated with the flux line, and the other end is routed to ground or a return path of a differential signal.

7. The flux line according to claim 1, wherein the second segment (1604) is a self-coupled transmission line comprising two transmission line modes, the two transmission line modes comprising a differential mode and a common mode, the differential mode having an impedance matched to the impedance of the first segment, and the common mode having an impedance lower than that of the differential mode.

8. The flux line according to claim 7, wherein the self-coupled transmission line is a double coplanar waveguide.

9. The flux line according to claim 7 or 8, wherein a filter for common-mode suppression is operatively connected to the self-coupled transmission line.

10. The flux line according to claim 7, 8 or 9, wherein the self-coupled transmission line is configured to be connected to a differential signal source.

11. A superconducting chip or chip package comprising one or more qubits and one or more flux lines for manipulating the one or more qubits according to any one of claims 1 to 10.

12. A quantum computing device comprising at least one superconducting chip or chip package according to claim 11 and a control unit connected to said at least one superconducting chip or chip package, wherein said control unit is configured to feed one or more control signals to one or more flux lines for manipulating said one or more qubits.

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