Multilayer ceramic capacitor

Abstract

A multilayer ceramic capacitor is provided. A multilayer ceramic capacitor (1) includes a laminate (2), a first external electrode (3A) provided at a first end surface (CA) and connected to an internal electrode (15), and a second external electrode (3B) provided at a second end surface (CB) and connected to the internal electrode. The first external electrode (3A) has a first base electrode layer (31A) connected to the internal electrode (15) and containing a conductive metal and a glass (52). In a (LT) cross section through a central portion in a width direction (W) of the laminate (2), a ratio of a length of a line along an outer surface of a first base electrode end surface region (31Ac) to a length of a line along the first end surface (CA) is smaller than a ratio of a length of a line along an outer surface of a first base electrode main surface region (31Aa) to a length of a line along a portion of the first main surface (AA) in which the first base electrode layer (31A) is disposed.

Description

Technical Field

[0001] This invention relates to multilayer ceramic capacitors. Background Technology

[0002] There exists a type of multilayer ceramic capacitor, which comprises a stack of internal electrodes and dielectric layers alternately stacked, and external electrodes connected to the internal electrodes (e.g., Patent Document 1). Multilayer ceramic capacitors are one of the important electronic components. Existing technical documents Patent documents

[0003] Patent Document 1: Japanese Patent Application Publication No. 2003-243249 Summary of the Invention The problem the invention aims to solve

[0004] In recent years, due to the widespread use of electric vehicles and smartphones, there has been a growing demand for multilayer ceramic capacitors that offer high reliability and stable operation.

[0005] The purpose of this invention is to provide a multilayer ceramic capacitor with excellent reliability. Solution for solving the problem

[0006] To address the aforementioned problems, the multilayer ceramic capacitor of the present invention comprises: a multilayer body having a plurality of stacked dielectric layers and a plurality of internal electrodes, and having a first main surface and a second main surface opposite to each other in the stacking direction, a first side surface and a second side surface opposite to each other in a width direction orthogonal to the stacking direction, and a first end surface and a second end surface opposite to each other in a length direction orthogonal to the stacking direction and the width direction; a first external electrode disposed on the first end surface and connected to the internal electrodes; and a second external electrode disposed on the second end surface and connected to the internal electrodes, wherein the first external electrode has a first base electrode layer connected to the first internal electrode and comprising a conductive metal and a glass. The first base electrode layer has: a first base electrode end face region, which is a region that overlaps with the first end face when viewed along the length direction; and a first base electrode main face region, which is a region that overlaps with the first main face when viewed along the stacking direction. In a cross section extending parallel to the stacking direction and the length direction through the central portion of the width direction of the laminate, the ratio of the length of a line along the outer surface of the first base electrode end face region to the length of a line along the first end face is smaller than the ratio of the length of a line along the outer surface of the first base electrode main face side region to the length of a line along the portion of the first main face in which the first base electrode layer is disposed. The effects of the invention

[0007] According to the present invention, a multilayer ceramic capacitor with excellent reliability can be provided. Attached Figure Description

[0008] Figure 1 This is a schematic perspective view of the multilayer ceramic capacitor 1 according to the first embodiment. Figure 2 yes Figure 1 Sectional view II-II. Figure 3 yes Figure 1 Sectional view III-III. Figure 4 yes Figure 1 Sectional view IV-IV. Figure 5 This is a schematic perspective view of the stacked ceramic capacitor 1 according to the second embodiment. Figure 6 yes Figure 5 Sectional view VI-VI. Figure 7 This is a diagram obtained by observing the first external electrode 3A of the second embodiment along the length direction L. Figure 8 yes Figure 6 Enlarged view of section VIII. Figure 9 yes Figure 8 Enlarged view of section IX. Detailed Implementation

[0009] The following is for reference Figures 1-4 A multilayer ceramic capacitor 1, illustrating an embodiment of the present invention, is described.

[0010] (Laminated ceramic capacitor 1) like Figure 1 As shown, the multilayer ceramic capacitor 1 is a so-called two-terminal multilayer ceramic capacitor. The multilayer ceramic capacitor 1 includes a stacked body 2, a first external electrode 3A, and a second external electrode 3B. The stacked body 2 is generally cuboid in shape and has six outer surfaces. The stacked body 2 includes an inner layer 11 formed by stacking a dielectric layer 14 and an internal electrode 15. Furthermore, the first external electrode 3A and the second external electrode 3B are sometimes collectively referred to as "external electrodes 3".

[0011] In this specification, the stacking direction of the dielectric layer 14 and the internal electrode 15 in the multilayer ceramic capacitor 1 is defined as the stacking direction T. One of the directions orthogonal to the stacking direction T is defined as the length direction L. The directions orthogonal to both the length direction L and the stacking direction T are defined as the width direction W.

[0012] Of the six outer surfaces of the laminate 2, one pair of outer surfaces located on both sides of the lamination direction T are designated as the first main surface AA and the second main surface AB. Another pair of outer surfaces extending along the lamination direction T and located on both sides of the width direction W are designated as the first side surface BA and the second side surface BB. Finally, another pair of outer surfaces extending along the lamination direction T and located on both sides of the length direction L are designated as the first end surface CA and the second end surface CB. The first main surface AA and the second main surface AB are sometimes collectively referred to as "each main surface A". The first side surface BA and the second side surface BB are sometimes collectively referred to as "each side surface B". The first end surface CA and the second end surface CB are sometimes collectively referred to as "each end surface C".

[0013] The section parallel to the stacking direction T and the length direction L is designated as the "LT section". The section parallel to the stacking direction T and the width direction W is designated as the "WT section". Figure 2 The cross section is the LT section at the center of the width direction W of the stacked ceramic capacitor 1. Figure 3 The cross section is the WT section at the center of the length direction L of the stacked ceramic capacitor 1. Figure 4 The cross section is the WT section at the center of the portion of the first external electrode 3A that overlaps with the first main surface AA when viewed along the stacking direction T.

[0014] (Layered body 2) The laminate 2 has an inner layer portion 11 and an outer layer portion 12 disposed across the inner layer portion 11 in the lamination direction T. The laminate 2 preferably has rounded corners and edges. Furthermore, a corner refers to the portion where three faces of the laminate 2 intersect. An edge refers to the portion where two faces of the laminate 2 intersect.

[0015] Regarding the external dimensions of the laminate, for example, the dimension in the length direction L is 0.2 mm or more and 5.7 mm or less, and the dimension in the width direction W is 0.1 mm or more and 5.0 mm or less. The external dimensions of the laminated ceramic capacitor 1 can be measured using a micrometer.

[0016] (Inner layer 11) like Figure 2 and Figure 3 As shown, the inner layer 11 has a plurality of dielectric layers 14 and a plurality of internal electrodes 15. The dielectric layers 14 and the internal electrodes 15 are stacked alternately.

[0017] The dielectric layer 14 is composed of a perovskite-type compound containing Ba or Ti. Dielectric ceramics with BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as the main components can be used as the material constituting the dielectric layer 14. Alternatively, materials in which Mn compounds, Mg compounds, Si compounds, Fe compounds, Cr compounds, Co compounds, Ni compounds, Al compounds, V compounds, or rare earth compounds are added as secondary components to these main components can also be used.

[0018] The internal electrode 15 is formed by sintering a conductive paste containing a metal powder that serves as a conductor, an organic solvent, a binder, and a dispersant onto the dielectric layer 14. For example, metals such as Ni, Cu, Ag, Pd, Ag-Pd alloys, and Au can be used as the metal powder that serves as the conductor. Alternatively, these metals can also be compounds containing these metal elements or alloys with other metals.

[0019] The internal electrode 15 has a plurality of first internal electrodes 15A and a plurality of second internal electrodes 15B. The first internal electrodes 15A are exposed only on the first end face CA. The second internal electrodes 15B are exposed only on the second end face CB. The first internal electrodes 15A and the second internal electrodes 15B are arranged alternately.

[0020] The first internal electrode 15A has a first opposing portion 15Aa and a first lead-out portion 15Ab. The first opposing portion 15Aa is the part of the first internal electrode 15A that opposes the second internal electrode 15B adjacent in the stacking direction T. The first opposing portion 15Aa is located at the center between each end face C. The first lead-out portion 15Ab is the part of the first internal electrode 15A that extends from the first opposing portion 15Aa toward the first end face CA.

[0021] The second internal electrode 15B has a second opposing portion 15Ba and a second lead-out portion 15Bb. The second opposing portion 15Ba is the part of the second internal electrode 15B that opposes the adjacent first internal electrode 15A (first opposing portion 15Aa). The second opposing portion 15Ba is located at the center between each end face C. The second lead-out portion 15Bb is the part of the second internal electrode 15B that extends from the second opposing portion 15Ba toward the second end face CB side.

[0022] Furthermore, the first internal electrode 15A and the second internal electrode 15B are sometimes collectively referred to as "internal electrode 15". The first opposing portion 15Aa and the second opposing portion 15Ba are sometimes collectively referred to as "opposing portion 15a".

[0023] (Outer layer 12) The outer layer 12 is formed of the same material as the dielectric layer 14 of the inner layer 11. Furthermore, no internal electrode 15 is disposed in the outer layer 12.

[0024] (External electrode 3) The first external electrode 3A is disposed on the first end face CA. The first external electrode 3A not only covers the first end face CA, but also a portion of the main face A and a portion of the side face B. The first external electrode 3A is connected to the first internal electrode 15A. The first external electrode 3A includes a first base electrode layer 31A formed in contact with the surface of the laminate 2 and a first plating layer 32A disposed on the first base electrode layer 31A. The first plating layer 32A includes a first lower plating layer 33A disposed on the first base electrode layer 31A and a first upper plating layer 34A disposed on the first lower plating layer 33A.

[0025] The second external electrode 3B is disposed on the second end face CB. The second external electrode 3B not only covers the second end face CB, but also a portion of the main face A and a portion of the side face B. The second external electrode 3B is connected to the second internal electrode 15B. The second external electrode 3B includes a second base electrode layer 31B formed in contact with the surface of the laminate 2 and a second plating layer 32B disposed on the second base electrode layer 31B. The second plating layer 32B includes a second lower plating layer 33B disposed on the second base electrode layer 31B and a second upper plating layer 34B disposed on the second lower plating layer 33B.

[0026] Furthermore, the first base electrode layer 31A and the second base electrode layer 31B are sometimes collectively referred to as "base electrode layer 31". The first plating layer 32A and the second plating layer 32B are sometimes collectively referred to as "plating layer 32". The first lower plating layer 33A and the second lower plating layer 33B are sometimes collectively referred to as "lower plating layer 33". The first upper plating layer 34A and the second upper plating layer 34B are sometimes collectively referred to as "upper plating layer 34".

[0027] The base electrode layer 31 comprises a conductive metal, glass 52, and voids 53. The base electrode layer 31 is, for example, a sintered layer. The conductive metal is, for example, a suitable metal such as Ni (nickel), Cu (copper), Ag (silver), Pd (palladium), Au (gold), or Ag-Pd alloys, preferably Cu. The metal contained in the base electrode layer 31 can be confirmed using a wavelength dispersive X-ray diffraction (WDX) analyzer after grinding the multilayer ceramic capacitor 1. The maximum thickness of the base electrode layer 31 is preferably 10 μm or more and 200 μm or less. The thickness of the base electrode layer 31 thins at the corners of the laminate 2. The glass 52 is granular. The glass 42 and voids 53 can be confirmed using a scanning electron microscope (SEM) after grinding the multilayer ceramic capacitor 1.

[0028] The coating 32 is, for example, made of a metal selected from the group consisting of Ni, Cu, Ag, Pd, Au, and Sn, or an alloy containing that metal.

[0029] The lower plating layer 33 is, for example, a Ni plating layer. The upper plating layer 34 is, for example, a Sn (tin) plating layer. The thickness of each plating layer is preferably 1.5 μm or more and 15.0 μm or less. In addition, the plating layer can be a single layer, or it can be a Cu plating layer or an Au plating layer.

[0030] Furthermore, when mounting the multilayer ceramic capacitor 1, the external electrode 3 is connected to the substrate using solder. The multilayer ceramic capacitor 1 is mounted on the substrate with its first main surface AA facing the substrate.

[0031] Here, details of the first substrate electrode layer 31A will be described. Furthermore, since the structure of the second substrate electrode layer 31B is the same as that of the first substrate electrode layer 31A, its description is omitted.

[0032] like Figure 2 and Figure 4 As shown, the first external electrode 3A has: a first external electrode end face region 3Ac, which is a region that overlaps with the first end face CA when viewed along the length direction L; a first external electrode main face region 3Aa, which is a region that overlaps with the first main face AA when viewed along the stacking direction T; and a first external electrode corner region 3Ad, which is a region that connects at least one of the first external electrode side face region 3Ab and the first external electrode main face region 3Aa to the first external electrode end face region 3Ac.

[0033] The first base electrode layer 31A has: a first base electrode end face region 31Ac, which is a region that overlaps with the first end face CA when viewed along the length direction L; a first base electrode main face region 31Aa, which is a region that overlaps with the first main face AA when viewed along the stacking direction T; and a first base electrode corner region 31Ad, which is a region that connects at least one of the first base electrode side face region 31Ab and the first base electrode main face region 31Aa to the first base electrode end face region 31Ac.

[0034] The first coating 32A has: a first coating end face region 32Ac, which is a region that overlaps with the first end face CA when viewed along the length direction L; a first coating main face region 32Aa, which is a region that overlaps with the first main face AA when viewed along the stacking direction T; and a first coating corner region 32Ad, which is a region that connects at least one of the first coating side face region 32Ab and the first coating main face region 32Aa to the first coating end face region 32Ac.

[0035] The first lower plating layer 33A has: a first lower plating end face region 33Ac, which is a region that overlaps with the first end face CA when viewed along the length direction L; a first lower plating main face region 33Aa, which is a region that overlaps with the first main face AA when viewed along the stacking direction T; and a first lower plating corner region 33Ad, which is a region that connects at least one of the first lower plating side face region 33Ab and the first lower plating main face region 33Aa to the first lower plating end face region 33Ac.

[0036] Furthermore, the first lower plating layer 33A covers the entire area of ​​the outer surface of the first substrate electrode layer 31A. Therefore, the entire outer surface of the first substrate electrode end face region 31Ac corresponds to the area in the outer surface of the first substrate electrode end face region 31Ac that is opposite to the first plating layer 32A.

[0037] Furthermore, the first upper plating layer 34A covers the entire area of ​​the outer surface of the first lower plating layer 33A. The outer surface of the first upper plating layer 34A becomes the outer surface of the first external electrode 3A and also becomes the outer surface of the first plating layer 32A.

[0038] (Surface smoothness) The outer surface of the first substrate electrode end face region 31Ac is smoother than the outer surface of the first substrate electrode main face region 31Aa, for example, with less surface roughness.

[0039] The outer surface of the first substrate electrode end face region 31Ac is smoother than the outer surface of the first substrate electrode side face region 31Ab, for example, with less surface roughness.

[0040] The region on the outer surface of the first base electrode terminal face region 31Ac that faces the first plating layer 32A is smoother than either the region on the outer surface of the first base electrode main face region 31Aa that faces the first plating layer 32A or the region on the outer surface of the first base electrode side face region 31Ab that faces the first plating layer 32A, for example, has a smaller surface roughness.

[0041] The outer surface of the first lower plating end face region 33Ac is smoother than the outer surface of the first lower plating main face region 33Aa, for example, with a smaller surface roughness.

[0042] The outer surface of the first lower plating end face region 33Ac is smoother than the outer surface of the first lower plating side face region 33Ab, for example, with less surface roughness.

[0043] The surface roughness of the outer surface of the first lower plating end face region 33Ac is 0 μm or more and 0.1 μm or less. The surface roughness of the outer surface of the first lower plating main face region 33Aa and the surface roughness of the outer surface of the first lower plating side face region 33Ab are both greater than 0.1 μm and less than 0.4 μm. More preferably, the surface roughness of the outer surface of the first lower plating main face region 33Aa and the surface roughness of the outer surface of the first lower plating side face region 33Ab are both greater than 0.1 μm and less than 0.4 μm.

[0044] The outer surface of the corner region 31Ad of the first base electrode is smoother than either the outer surface of the main surface region 31Aa of the first base electrode or the outer surface of the side surface region 31Ab of the first base electrode, for example, with less surface roughness.

[0045] The outer surface of the corner region 33Ad of the first lower plating material is smoother than either the outer surface of the main surface region 33Aa of the first lower plating material or the outer surface of the side surface region 33Ab of the first lower plating material, for example, it has a smaller surface roughness.

[0046] The surface roughness of the outer surface of the first lower plating end face region 33Ac is divided by the average of the surface roughness of the outer surface of the first lower plating main face region 33Aa and the surface roughness of the outer surface of the first lower plating side face region 33Ab, and the resulting value is greater than 0 and less than 0.7. This allows the solder to fully wet the first outer electrode end face region 3Ac.

[0047] The surface roughness of the first base electrode layer 31A, the first lower plating layer 33A, and the first upper plating layer 34A are measured by acquiring images of the object using a laser microscope and analyzing the images using analysis software. The surface roughness is set as the arithmetic mean height Sa. The size of the acquired image is set, for example, to 280 μm × 210 μm.

[0048] Before measuring the surface roughness of the first lower plating layer 33A, the first upper plating layer 34A is peeled off. The first upper plating layer 34A is peeled off by immersing the first external electrode 3A in a metal stripping solution for a predetermined time. During this time, the metal stripping solution is stirred appropriately. In the case of a Sn plating layer, the metal stripping solution is, for example, ENSTRIP TL-105. The immersion time is, for example, set to 1.5 minutes to 9 minutes. Since the thickness of the lower plating layer is approximately uniform, if the surface roughness of the lower plating layer can be measured, the surface roughness of the substrate electrode layer can also be measured.

[0049] In the LT section passing through the central portion of the width direction W of the laminate 2, the ratio of the length of the line along the outer surface of the first substrate electrode end face region 31Ac to the length of the line along the first end face CA is smaller than the ratio of the length of the line along the outer surface of the first substrate electrode main face region 31Aa to the length of the line along the portion of the first main face AA in which the first substrate electrode layer 31A is disposed.

[0050] In the LT section passing through the central part of the width direction W of the laminate 2, when the ratio of the length of the line along the outer surface of the first base electrode end face region 31Ac to the length of the line along the first end face CA is set as A1, and the ratio of the length along the outer surface of the first base electrode main face region 31Aa to the length of the line along the portion of the first main face AA that contacts the first base electrode main face region 31Aa is set as B1, the relationship between A1 and B1 satisfies 0.5≤A1 / B1<1.

[0051] In the LT section passing through the central portion of the width direction W of the laminate 2, a rectangular region with dimensions of 75μm × 55μm, having an edge extending parallel to the first main surface AA and an edge extending parallel to the first end surface CA, is designated as the "reference region". The lengths of the lines along the first end surface CA, the lines along the outer surface of the first substrate electrode end face region 31Ac, the lines along the portion of the first main surface AA that contacts the first substrate electrode main surface region 31Aa, and the lengths along the outer surface of the first substrate electrode main surface region 31Aa are respectively designated as the lengths of the portions located in the reference region.

[0052] Furthermore, when obtaining the length of the line along the first end face CA and the length of the line along the outer surface of the first substrate electrode end face region 31Ac, the position of the reference region is set to the position where the central portion of the reference region in the stacking direction T overlaps with the central portion of the first substrate electrode end face region 31Ac in the stacking direction T. When obtaining the length of the line along the portion of the first main face AA that contacts the first substrate electrode main face region 31Aa and the length along the outer surface of the first substrate electrode main face region 31Aa, the position of the reference region is set to the position where the central portion of the reference region in the length direction overlaps with the central portion of the first substrate electrode main face region 31Aa in the width direction W.

[0053] Images of the reference area were acquired using an optical microscope. The lengths of various lines were measured in the acquired images. Furthermore, the cross-section of the multilayer ceramic capacitor 1, which was the object of measurement, was set to the state exposed by grinding the multilayer ceramic capacitor 1.

[0054] (Hardness of the first substrate electrode layer 31A) The hardness Hv of the first substrate electrode end face region 31Ac is higher than either the hardness Hv of the first substrate electrode main face region 31Aa or the hardness Hv of the first substrate electrode side face region 31Ab.

[0055] The hardness Hv of the first substrate electrode end face region 31Ac is above 100 and below 200.

[0056] The hardness Hv of the corner region 31Ad of the first base electrode is higher than either the hardness Hv of the main surface region 31Aa of the first base electrode or the hardness Hv of the side surface region 31Ab of the first base electrode.

[0057] The hardness Hv of each portion of the first base electrode layer 31A is measured using a micro hardness tester in the multilayer ceramic capacitor 1 after the first upper plating layer 34A has been removed. The hardness Hv of each portion of the first base electrode layer 31A is set as the hardness Hv of the outer surface of each portion of the first base electrode layer 31A. The hardness Hv of the outer surface of the first base electrode layer 31A is measured from the first lower plating layer 33A with the first lower plating layer 33A attached. Since the thickness of the first lower plating layer 33A is extremely small, the first lower plating layer 33A has little influence on the measured value of the hardness Hv of the outer surface of the first base electrode layer 31A. The first upper plating layer 34A is pre-removed using a metal stripping solution as described above.

[0058] (Manufacturing method of multilayer ceramic capacitor 1) Next, the manufacturing method of the multilayer ceramic capacitor 1 according to the embodiment will be described.

[0059] (Internal electrode pattern formation process) First, a ceramic green sheet is prepared by forming a ceramic paste into a sheet shape. The pattern of the internal electrode 15 is then printed onto the ceramic green sheet using a conductive paste. This yields a ceramic green sheet for use in the inner layer where the internal electrode 15 is disposed. Furthermore, the pattern of the internal electrode 15 can be formed, for example, by screen printing, gravure printing, letterpress printing, or similar printing methods.

[0060] (Layering process) Next, ceramic green sheets for the inner layer are stacked. The inner layer ceramic green sheets are stacked such that the internal electrode patterns are staggered by half a spacing in the length direction L between adjacent sheets. Next, outer layer ceramic green sheets are stacked on both sides of the stacked ceramic green sheets in the stacking direction T to form the outer layer 12. The outer layer ceramic green sheets are then heat-pressed onto the stacked ceramic green sheets. This yields the master block.

[0061] Furthermore, each outer layer 12 can be composed of multiple ceramic green sheets stacked together, or it can be composed of a single ceramic green sheet. In addition, the ceramic green sheets used in the inner layer and the ceramic green sheets used in the outer layer can contain different compositions.

[0062] (Main block cutting process) Next, the mother block is cut along a cutting line corresponding to the size of the laminate 2. For example, the mother block is cut in the length direction L and the width direction W. This yields a plurality of cuboid blocks (called "laminated chips"). Furthermore, it is preferable that the corners and edges of the laminated chips are rounded by, for example, tumbling.

[0063] (Laminated body firing process) Next, the stacked chips are heated in a nitrogen atmosphere at a predetermined firing temperature for a predetermined time. This yields the stack 2.

[0064] (Substrate electrode layer formation process) Next, a base electrode layer 31 is formed on each end face C of the laminate 2. A conductive paste containing glass and metal is applied onto the laminate 2. Each base electrode layer 31 is formed, for example, in a manner that covers a portion of each end face C, each main face A, each side face B, and each edge line 5 on the side closest to the end face C. However, this is not a limitation, and each base electrode layer 31 may also be disposed only on each end face C.

[0065] (Substrate electrode layer baking process) Next, the laminate 2 to which the base electrode layer 31 is formed is heated for a predetermined time at a predetermined firing temperature in a nitrogen atmosphere. This fires the base electrode layer 31 onto the laminate 2. Alternatively, the laminate firing process and the base electrode layer firing process can be performed simultaneously after the material of the base electrode layer 31 is disposed on the laminated chip. Furthermore, by causing the solvent or the like in the conductive paste to disappear during firing, voids 53 are formed within the base electrode layer 31.

[0066] (Pressing process) Here, the outer surface of the first base electrode layer 31A is pressed using a pressing member. The pressing member is, for example, a sheet of metal. The pressing member is formed from a raw material harder than the first base electrode layer 31A, preferably from a raw material harder than Cu. This smooths the outer surface of the first base electrode layer 31A. Compared to the main surface region 31Aa and the side surface region 31Ab of the first base electrode, the pressing member is used to press the end face region 31Ac of the first base electrode with emphasis. Compared to the main surface region 31Aa and the side surface region 31Ab of the first base electrode, the pressing member is used to press the corner region 31Ad of the first base electrode with emphasis.

[0067] Therefore, the outer surfaces of the first substrate electrode end face region 31Ac and the first substrate electrode corner region 31Ad can be made smoother than the outer surfaces of the first substrate electrode main face region 31Aa and the first substrate electrode side face region 31Ab. This also allows the hardness of the outer surfaces of the first substrate electrode end face region 31Ac and the first substrate electrode corner region 31Ad to be higher than the hardness of the outer surfaces of the first substrate electrode main face region 31Aa and the first substrate electrode side face region 31Ab.

[0068] (Plating process) Next, a first lower plating layer 33A is formed on the outer surface of the first base electrode layer 31A. Then, a first upper plating layer 34A is formed on the outer surface of the first lower plating layer 33A. The first lower plating layer 33A is formed, for example, by a Ni plating layer. The first upper plating layer 34A is formed, for example, by a Sn plating layer. The first lower plating layer 33A and the first upper plating layer 34A are formed sequentially, for example, by an electrolytic plating method. Thus, a first external electrode 3A is formed on the first end face CA.

[0069] The thickness of the first lower plating layer 33A is relatively small. Therefore, the shape of the outer surface of the first lower plating layer 33A is approximately the same as the shape of the outer surface of the first base electrode layer 31A. Consequently, the outer surfaces of the end face region 33Ac and the corner region 33Ad of the first lower plating material are smoother than the outer surfaces of the main face region 33Aa and the side face region 33Ab of the first lower plating material.

[0070] The thickness of the first upper plating layer 34A is relatively small. Therefore, the shape of the outer surface of the first upper plating layer 34A is approximately the same as the shape of the outer surfaces of the first base electrode layer 31A and the first lower plating layer 33A. Consequently, the outer surfaces of the first external electrode end face region 3Ac and the first external electrode corner region 3Ad are smoother than the outer surfaces of the first external electrode main face region 3Aa and the first external electrode side face region 3Ab.

[0071] In addition, the pressing and plating processes are also performed on the second base electrode layer 31B.

[0072] Through the above procedures, obtain Figure 1 The stacked ceramic capacitor 1 shown.

[0073] (Effects of the first embodiment) According to this embodiment, the following effects can be obtained.

[0074] According to this embodiment, the outer surface of the first substrate electrode end face region 31Ac is smoother than the outer surface of the first substrate electrode main face region 31Aa.

[0075] According to this structure, since the outer surface of the region on the end face of the first external electrode 3A can be made smooth, the solder can be well wetted into the region on the end face of the first external electrode 3A.

[0076] Furthermore, the outer surface of the region on the first main surface AA of the first external electrode 3A can be roughened. As a result, an anchoring effect can be generated between the portion of the first external electrode 3A that faces the substrate and the solder, thus enabling good bonding between the solder and the multilayer ceramic capacitor 1.

[0077] Therefore, it is possible to provide multilayer ceramic capacitors with excellent reliability.

[0078] According to this embodiment, the outer surface of the first substrate electrode end face region 31Ac is smoother than the outer surface of the first substrate electrode side face region 31Ab.

[0079] According to this structure, the outer surface of the region on the first side BA of the first external electrode 3A can be made relatively rough. As a result, an anchoring effect can also be generated between the region on the first side BA of the first external electrode 3A and the solder, thus enabling better bonding between the solder and the multilayer ceramic capacitor 1.

[0080] According to this embodiment, the region on the outer surface of the first substrate electrode end face region 31Ac that faces the first plating layer 32A is smoother than either the region on the outer surface of the first substrate electrode main face region 31Aa that faces the first plating layer 32A or the region on the outer surface of the first substrate electrode side face region 31Ab that faces the first plating layer 32A.

[0081] According to this structure, the outer surface of the first plating layer 32A reflects the shape of the outer surface of the first base electrode layer 31A. Therefore, in the structure in which the first plating layer 32A is provided on the first base electrode layer 31A, the solder can be well wetted into the region on the first end face CA of the first external electrode 3A, and an anchoring effect can be generated between the first external electrode 3A and the solder.

[0082] According to this embodiment, the outer surface of the first lower plating end face region 33Ac is smoother than the outer surface of the first lower plating main face region 33Aa.

[0083] According to this structure, the outer surface of the first upper plating layer 34A reflects the shape of the outer surface of the first base electrode layer 31A and the shape of the outer surface of the first lower plating layer 33A. Therefore, in the structure in which the first lower plating layer 33A and the first upper plating layer 34A are provided on the first base electrode layer 31A, the solder can be well wetted into the region on the first end face CA of the first external electrode 3A, and an anchoring effect can be generated between the first external electrode 3A and the solder.

[0084] According to this embodiment, the outer surface of the first lower plating end face region 33Ac is smoother than the outer surface of the first lower plating side face region 33Ab.

[0085] According to this structure, the outer surface of the first upper plating layer 34A reflects the shape of the outer surface of the first base electrode layer 31A and the shape of the outer surface of the first lower plating layer 33A. Therefore, in the structure in which the first lower plating layer 33A and the first upper plating layer 34A are provided on the first base electrode layer 31A, the solder can be well wetted into the region on the first end face CA of the first external electrode 3A, and an anchoring effect between the first external electrode 3A and the solder can be generated over a larger area.

[0086] According to this embodiment, the surface roughness of the outer surface of the first lower plating end face region 33Ac is 0 μm or more and 0.1 μm or less, and the surface roughness of the outer surface of the first lower plating main face region 33Aa and the surface roughness of the outer surface of the first lower plating side face region 33Ab are greater than 0.1 μm and less than 0.4 μm, respectively.

[0087] According to this structure, the solder can be more reliably wetted into the region on the first end face CA of the first external electrode 3A, and an anchoring effect is generated between the first external electrode 3A and the solder.

[0088] According to this embodiment, the outer surface of the corner region 31Ad of the first base electrode is smoother than one of the outer surfaces of the main surface region 31Aa of the first base electrode and the outer surface of the side surface region 31Ab of the first base electrode.

[0089] According to this structure, the outer surface of the region between the area of ​​the first external electrode 3A that faces the substrate and the region on the first end face CA can be made smooth. As a result, the solder can be well wetted into the region on the first end face CA of the first external electrode 3A.

[0090] Furthermore, the outer surface of the region on the first main surface AA of the first external electrode 3A can be roughened. As a result, an anchoring effect can be generated between the portion of the first external electrode 3A that faces the substrate and the solder, thus enabling good bonding between the solder and the multilayer ceramic capacitor 1.

[0091] According to this embodiment, the outer surface of the first lower plating corner region 33Ad is smoother than either the outer surface of the first lower plating main surface region 33Aa or the outer surface of the first lower plating side surface region 33Ab.

[0092] According to this structure, the outer surface of the first plating layer 32A reflects the shape of the outer surface of the first base electrode layer 31A. Therefore, in the structure in which the first plating layer 32A is provided on the first base electrode layer 31A, the solder can be well wetted into the region on the first end face CA of the first external electrode 3A, and an anchoring effect can be generated between the first external electrode 3A and the solder.

[0093] According to this embodiment, in a cross section extending parallel to the stacking direction T and the length direction L and passing through the central portion of the width direction W of the laminate 2, the ratio of the length of the line along the outer surface of the first substrate electrode end face region 31Ac to the length of the line along the first end face CA is smaller than the ratio of the length of the line along the outer surface of the first substrate electrode main face region 31Aa to the length of the line along the portion of the first main face AA in which the first substrate electrode layer 31A is disposed.

[0094] According to this structure, the solder can be well wetted into the region on the first end face CA of the first external electrode 3A, and an anchoring effect is generated between the first external electrode 3A and the solder. Therefore, a multilayer ceramic capacitor 1 with excellent reliability can be provided.

[0095] According to this embodiment, in a cross section extending parallel to the stacking direction T and the length direction L and passing through the central portion of the width direction W of the laminate 2, when the ratio of the length of the line along the surface of the first substrate electrode end face region 31Ac to the length of the line along the first end face CA is set as A1, and the ratio of the length along the outer surface of the first substrate electrode main face region 31Aa to the length of the line along the portion of the first main face AA that contacts the first substrate electrode main face region 31Aa is set as B1, the relationship between A1 and B1 satisfies 0.5≤A1 / B1<1.

[0096] According to this structure, the solder can be more reliably wetted into the region on the first end face CA of the first external electrode 3A, and an anchoring effect is generated between the first external electrode 3A and the solder.

[0097] According to this embodiment, the hardness Hv of the first substrate electrode end face region 31Ac is higher than either the hardness Hv of the first substrate electrode main face region 31Aa or the hardness Hv of the first substrate electrode side face region 31Ab.

[0098] The higher the hardness of the first base electrode layer 31A, the denser the first base electrode layer 31A becomes, thus appropriately suppressing the permeation of water into the first base electrode layer 31A. According to this structure, the hardness Hv of the first base electrode end face region 31Ac can be increased, thereby suppressing the penetration of water into the laminate 2 through the first end face CA.

[0099] In addition, the lower the hardness Hv of the first base electrode layer 31A, the more it can suppress the compaction of the laminate 2, and thus suppress the generation of cracks in the laminate 2.

[0100] Therefore, it is possible to provide multilayer ceramic capacitors with excellent reliability.

[0101] According to this embodiment, the hardness Hv of the first substrate electrode end face region 31Ac is 100 or more and 200 or less.

[0102] According to this structure, since the first base electrode layer 31A can be made dense, the penetration of water into the first end face CA can be suppressed more reliably.

[0103] According to this structure, the lower the hardness of the base electrode layer 31, the weaker the compression of the laminate 2 caused by the base electrode layer 31. As a result, the compression of the laminate 2 caused by the first base electrode main surface region 31Aa can be suppressed, and thus the generation of cracks in the laminate 2 due to stress can be suppressed.

[0104] According to this embodiment, the hardness Hv of the corner region of the first base electrode is higher than either the hardness Hv of the main surface region of the first base electrode or the hardness Hv of the side surface region of the first base electrode.

[0105] According to this structure, by increasing the hardness of the corner region 31Ad of the first base electrode to make it dense, the infiltration of water into the laminate 2 through the ridge portion of the laminate 2 can be suppressed. In addition, since the hardness of the main surface region 31Aa of the first base electrode and the hardness of the side surface region 31Ab of the first base electrode can be reduced, the compaction of the laminate 2 caused by the main surface region 31Aa of the first base electrode and the side surface region 31Ab of the first base electrode can be suppressed.

[0106] <Second Implementation> Next, based on Figures 5-9 The second embodiment of the multilayer ceramic capacitor 1 of the present invention will be described below. The description will focus on the differences from the first embodiment, and sometimes the same reference numerals are used for structures identical to those in the first embodiment, and descriptions are omitted. Furthermore, Figure 6 The cross section is the LT section at the center of the width direction W of the stacked ceramic capacitor 1.

[0107] (Dimple 55) like Figures 5-9As shown, in the second embodiment, the surface of the first plating layer 32A (specifically, the surface of the first upper plating layer 34A) is provided with a plurality of recesses 55 that are recessed from the surface of the first plating layer 32A toward the laminate 2 side, and a region, namely a recessed region 58, formed by adjacent recesses 55. The surface of the first base electrode layer 31A is provided with a plurality of recesses 54 and a region, namely a recessed region 58, formed by adjacent recesses 54. The recesses 55 and recessed regions 58 of the first plating layer 32A are formed by the first plating layer 32A (specifically, the first lower plating layer 33A and the first upper plating layer 34A) being recessed in a way that matches the shape of the recesses 54 and recessed regions 58 of the first base electrode layer 31A.

[0108] The first plating material end face region 32Ac has a recessed area 58 and multiple recessed portions 55. The first plating material main surface region 32Aa does not have recessed portions 55 or recessed areas 58. The second plating material side surface region Ab does not have recessed portions 55 or recessed areas 58.

[0109] The sum of the area of ​​the recessed portion 55 in the end face region 32Ac of the first plating material and the area of ​​the recessed region 58 is greater than one of the sum of the areas of the recessed portion 55 in the main face region 32Aa of the first plating material and the sum of the areas of the recessed portion 55 in the side face region 32Ab of the first plating material. The number of recessed portions 55 in the end face region 32Ac of the first plating material is greater than one of the number of recessed portions 55 in the main face region 32Aa of the first plating material and the number of recessed portions 55 in the side face region 32Ab of the first plating material.

[0110] The first plating corner area 32Ad has a recessed area 58 and multiple recessed portions 55.

[0111] The sum of the area of ​​the recessed portion 55 in the corner region 32Ad of the first plating material and the area of ​​the recessed region 58 is greater than one of the sum of the areas of the recessed portion 55 in the main surface region 32Aa of the first plating material and the sum of the areas of the recessed portion 55 in the side surface region 32Ab of the first plating material. The number of recessed portions 55 in the corner region 32Ad of the first plating material is greater than one of the number of recessed portions 55 in the main surface region 32Aa of the first plating material and the number of recessed portions 55 in the side surface region 32Ab of the first plating material.

[0112] Images of the object being measured are acquired using a laser microscope, and the acquired images are analyzed using analysis software to measure the area of ​​the recess 55 and the area of ​​the recess region 58. Next, the area of ​​the recess 55 is summed for each of the following regions: the first plating end face region 32Ac, the first plating main face region 32Aa, the first plating side face region 32Ab, and the first plating corner region 32Ad. Furthermore, the imaging direction for the first plating end face region 32Ac is set to the length direction L. The imaging direction for the first plating main face region 32Aa is set to the stacking direction T. The imaging direction for the first plating side face region 32Ab is set to the width direction W. The imaging direction for the first plating corner region 32Ad is set to the direction of a straight line extending from the intersection of the tangent to the first end face CA (parallel to the stacking direction T) and the tangent to the first main face AA (parallel to the length direction L), and the intersection of the tangent to the second end face CB (parallel to the stacking direction T) and the tangent to the second main face AB (parallel to the length direction L).

[0113] When viewed along the direction of the recess 55 (specifically, the length direction L), the recess 55 is, for example, circular or partially circular. The periphery of the opening of the recess 55 is partially arc-shaped. The periphery of the opening of the recess 55 is, for example, annular. The radius of the annulus (in other words, the radius of curvature of the arc) of the annulus including the periphery of the opening of the recess 55 is 5 μm or more, preferably 5 μm or more and 100 μm or less. The radius of the annulus formed by the periphery of the opening of the recess 55 is 5 μm or more, preferably 5 μm or more and 100 μm or less.

[0114] The inner circumferential surface of the recess 55 in the cross section extending along the direction of the recess 55 is arc-shaped.

[0115] Furthermore, the "section extending along the recessed direction of the recess 55" is, for example, an LT section when the recess 55 is formed in the first base electrode end face region 31Ac, and an WT section when the recess 55 is formed in one of the first base electrode main face region 31Aa, the first base electrode side face region 31Ab, and the first base electrode corner region 31Ad.

[0116] The first plating corner area 32Ad has a recessed area 58 and multiple recessed portions 55.

[0117] (Glass 52 covered by a thin metal film 56) like Figure 9As shown, the first base electrode layer 31A comprises a plurality of granular glass particles 52. The first base electrode layer 31A has a metal thin film 56, which is the region between the glass particles 52 and the first plating layer 32A (specifically, the first lower plating layer 33A), and is a region containing a conductive metal with a thickness of 1 μm or less. In other words, the portion of the glass particles 52 on the side adjacent to the first plating layer 32A is covered by the metal thin film 56 containing metal and formed in a thin film shape. Furthermore, the thickness of the metal thin film 56 refers to the shortest distance between the portion of the metal thin film 56 in contact with the glass particles 52 and the portion in contact with the first plating layer 32A.

[0118] The conductive metal with the highest content among the conductive metals contained in the first base electrode layer 31A is, for example, Cu. The metal thin film 56 contains the conductive metal with the highest content among the conductive metals contained in the first base electrode layer 31A, specifically Cu.

[0119] The glass 52 covered by the metal thin film 56 is exposed on the outer surface of the first base electrode layer 31A. The glass 52 covered by the metal thin film 56 is in contact with the first lower plating layer 33A.

[0120] The first substrate electrode end face region 31Ac includes a glass 52 covered by a metal film 56. The glass 52 covered by the metal film 56 is exposed on the outer surface of the first substrate electrode end face region 31Ac. The glass 52 covered by the metal film 56 is in contact with the first lower plated end face region 33Ac.

[0121] The first base electrode corner region 31Ad includes a glass 52 covered by a metal film 56. The glass 52 covered by the metal film 56 is exposed on the outer surface of the first base electrode corner region 31Ad. The glass 52 covered by the metal film 56 is in contact with the first lower plating corner region 33Ad.

[0122] (Manufacturing method of multilayer ceramic capacitor 1) Next, the manufacturing method of the multilayer ceramic capacitor 1 according to the second embodiment will be described. The differences between the manufacturing method of the multilayer ceramic capacitor 1 and that of the first embodiment will be explained.

[0123] In the second embodiment, during the pressing process, the pressing member is provided as a pressing member with a curved surface. When the pressing member presses the outer surface of the first base electrode layer 31A, a generally hemispherical recess is formed on the outer surface of the first base electrode layer 31A. Thus, a recessed portion 54 is formed on the outer surface of the first base electrode layer 31A. When the pressing member presses the position of the first base electrode layer 31A overlapping with the recessed portion 54, a recessed region is formed in the first base electrode layer 31A. Compared to the main surface region 31Aa and the side surface region 31Ab of the first base electrode, more pressing members are used to press the end face region 31Ac of the first base electrode. Compared to the main surface region 31Aa and the side surface region 31Ab of the first base electrode, more pressing members are used to press the corner region 31Ad of the first base electrode. As a result, more pits 54 are formed on the outer surface of the first base electrode end face region 31Ac and the outer surface of the first base electrode corner region 31Ad than on the outer surface of the first base electrode main face region 31Aa and the outer surface of the first base electrode side face region 31Ab.

[0124] Furthermore, the first substrate electrode layer 31A is pressed and compacted by a pressing member. The hardness of the first substrate electrode end face region 31Ac is higher than that of the first substrate electrode main face region 31Aa.

[0125] Furthermore, when the first base electrode layer 31A is pressed using the pressing member, the first base electrode layer 31A is compressed. As a result, a thin film is formed in the region between the glass 52 and the first plating layer 32A in the first base electrode layer 31A. Additionally, when the first base electrode layer 31A is pressed using the pressing member, the conductive metal within the first base electrode layer 31A is compressed and stretched, thus the conductive metal present near the glass 52 extends into the region between the glass 52 and the first plating layer 32A. Therefore, the mass ratio of the conductive metal to the dielectric component in the metal thin film 56 is greater than the mass ratio of the conductive metal to the dielectric component in the portion of the metal thin film 56 in the first base electrode layer 31A excluding the metal thin film 56 itself. Thus, a metal thin film 56 is formed between the glass 52 and the first plating layer 32A.

[0126] When the first base electrode layer 31A is pressed using a pressing member, the glass 52 may be exposed on the outer surface of the first base electrode layer 31A. However, by forming a metal thin film 56 between the glass 52 and the first coating layer 32A, the exposure of the glass 52 can be suppressed.

[0127] Next, during the plating process, the outer surface of the first base electrode layer 31A is made to reflect the shape of the outer surface of the first base electrode layer 31A on the outer surface of the first lower plating layer 33A and the outer surface of the first upper plating layer 34A, respectively. A pit portion 55 and a pit region 58 are formed on the outer surface of the first plating layer 32A (specifically, the outer surface of the first upper plating layer 34A).

[0128] (Effects of the second implementation method) According to this embodiment, the following effects can be obtained.

[0129] According to this embodiment, a plurality of recesses 54 are provided on the surface of the first plating layer 32A, which are recessed from the surface of the first plating layer 32A toward the laminate 2, and a region 58 formed by adjacent recesses 54 is provided.

[0130] According to this structure, a recess 55 and a recess region 58 can be formed on the outer surface of the first external electrode 3A. The recess 55 and the recess region 58 on the first external electrode 3A can capture solder. As a result, the adhesion between the first external electrode 3A and the solder during installation can be improved.

[0131] Therefore, it is possible to provide a multilayer ceramic capacitor 1 with excellent reliability.

[0132] According to this embodiment, the sum of the area of ​​the recessed portion 55 and the area of ​​the recessed region 58 in the end face region 32Ac of the first plating material is greater than one of the sum of the area of ​​the recessed portion 55 and the area of ​​the recessed region 58 in the main face region 32Aa of the first plating material and the sum of the area of ​​the recessed portion 55 and the area of ​​the recessed region 58 in the side face region 32Ab of the first plating material.

[0133] According to this structure, in the first plating end face region 32Ac, the recessed portion 55 and the recessed region 58 can be formed over a larger area, thereby improving the adhesion between the first plating end face region 32Ac and the solder during installation.

[0134] Furthermore, a recess 55 is formed by pressing the first external electrode 3A with a pressing member. As a result, the recess 55 in the first base electrode layer 31A and the area between the recess 55 and the laminate 2 are compacted and densified. If the first base electrode layer 31A is densely formed, water will not easily pass through it.

[0135] According to this structure, the recessed portion 55 and the recessed region 58 can be formed over a larger area in the first plating end face region 32Ac. As a result, the first base electrode layer 31A can be compacted over a larger area, thus more reliably suppressing the penetration of water into the laminate 2 through the first end face CA.

[0136] According to this structure, the range of the recesses 55 and 58 formed in the first plating material main surface region 32Aa and the range of the recesses 55 and 58 formed in the first plating material side surface region 32Ab can be reduced. Therefore, the compacted area in the first substrate electrode main surface region 31Aa and the first substrate electrode side surface region 31Ab can be reduced. Thus, the situation where the laminate 2 is compressed due to the first substrate electrode main surface region 31Aa and the first substrate electrode side surface region 31Ab can be suppressed. Therefore, the occurrence of cracks in the laminate 2 due to stress can be suppressed.

[0137] According to this embodiment, in the first plating end face region 32Ac, the peripheral edge of the opening of the recess 55 is partially arc-shaped.

[0138] According to this structure, the solder can be properly captured by the recessed portion 55, thus improving the adhesion between the first external electrode 3A and the solder during installation.

[0139] According to this embodiment, in the first plating end face region 32Ac, the radius of curvature of the arc formed by the periphery of the opening of the pit portion 55 is 5 μm or more, preferably 5 μm or more and 100 μm or less.

[0140] According to this structure, the solder can be captured more appropriately by the recessed portion 55, thus further improving the adhesion between the first external electrode 3A and the solder during installation.

[0141] According to this embodiment, a recessed portion 55 and a recessed area 58 are provided in the first plating material corner area 32Ad.

[0142] This structure can improve the adhesion between the first plating corner area 32Ad and the solder during installation.

[0143] Furthermore, by utilizing the portion of the first base electrode layer 31A that overlaps with the main surface region 32Aa and the side surface region 32Ab of the first plating material, it is possible to suppress the compaction of the laminate 2. This, in turn, can prevent cracking of the laminate 2 due to stress.

[0144] According to this embodiment, the first plating layer 32A has a first lower plating layer 33A that contacts the first base electrode layer 31A, and the first lower plating layer 33A is a Ni plating layer.

[0145] According to this structure, it is possible to suppress the erosion of the multilayer ceramic capacitor 1 by solder during installation. By providing a recess 55 on the outer surface of the first base electrode layer 31A, the Ni plating layer can be more reliably attached to the first base electrode layer 31A, thus more reliably suppressing the erosion of the multilayer ceramic capacitor 1 by solder.

[0146] According to this embodiment, the first base electrode layer 31A has a metal thin film 56, which is the region between the glass 52 and the first plating layer 32A and is a region containing the conductive metal with a thickness of 1 μm or less. The first base electrode layer 31A includes a conductive metal and glass 52, and the glass 52 is covered by the metal thin film 56, which is a thin film of metal.

[0147] The glass 52 included in the first base electrode layer 31A is sometimes exposed on the surface of the first base electrode layer 31A. In this case, since it is difficult to form a plating material on the glass 52, the plating material may not be able to adhere smoothly to the first base electrode layer 31A if a plating layer is to be formed on the first base electrode layer 31A. According to this structure, the glass 52 is covered by a metal film 56, which is a thin film of metal. Since the metal film 56 contains a metal component, the plating material can be properly adhered. Therefore, the plating material can be properly adhered to the glass 52 covered by the metal film 56. As a result, a plating layer can be easily and continuously formed on the first base electrode layer 31A. Therefore, the erosion of the multilayer ceramic capacitor 1 by solder during installation and the penetration of water into the multilayer 2 can be appropriately suppressed.

[0148] According to this embodiment, the metal thin film 56 contains the conductive metal with the highest content among the conductive metals contained in the first base electrode layer 31A.

[0149] Based on this structure, glass 52 covered by a metal film 56 can be easily obtained.

[0150] According to this embodiment, the first substrate electrode end face region 31Ac includes glass 52 covered by a metal thin film 56.

[0151] According to this structure, a plating layer can be easily and continuously formed on the first substrate electrode end face region 31Ac. Therefore, it is possible to appropriately suppress the erosion of the multilayer ceramic capacitor 1 by solder during installation, and the penetration of water into the multilayer 2.

[0152] According to this embodiment, the first base electrode corner region 31Ad includes glass 52 covered by a metal thin film 56.

[0153] Because the first base electrode layer 31A is relatively thin, the plating material is not easily adhered to the corner region 31Ad of the first base electrode. Based on this structure, a plating layer can be easily formed continuously on the corner region 31Ad of the first base electrode.

[0154] The embodiments of the present invention have been described above, but the present invention is not limited to the above embodiments and various changes and modifications can be made.

[0155] The structure of the multilayer ceramic capacitor 1 is not limited to Figure 1-Figure 2 The structure shown in Figure 2. For example, the multilayer ceramic capacitor may also be a three-terminal multilayer ceramic capacitor including a pair of external electrodes disposed on each end face and a pair of external electrodes disposed on each side face. In this case, the external electrodes disposed on each side face extend not only to each side face but also to each main face. The external electrodes disposed on each side face have a base electrode layer and a plating layer (e.g., a lower plating layer and an upper plating layer) similar to the external electrodes 3 in the above embodiment.

[0156] In the three-terminal type multilayer ceramic capacitor, the desired effect can be obtained by making the external electrodes arranged in pairs on each end face the same as the external electrodes 3 in the above embodiments.

[0157] Furthermore, by setting the structure of the external electrodes disposed on each side to correspond to the structure of the external electrodes disposed on the end faces in the above-described embodiments, the same effects as in the above-described embodiments can be obtained in the external electrodes disposed on each side. For example, in the portions of the base electrode layer and plating disposed on each side that overlap with the side when viewed in the width direction, smoothing the surface roughness or increasing the number of pits can improve solder wetting. In the portions of the base electrode layer disposed on each side that overlap with the side when viewed in the width direction, increasing the hardness can improve moisture resistance reliability. In the portions of the base electrode layer and plating disposed on each side that overlap with the main surface when viewed in the stacking direction, reducing the hardness can suppress the compaction of the laminate.

[0158] Furthermore, it is not necessary to press the external electrodes arranged on each side using a pressing component during the pressing process.

[0159] In the second embodiment described above, the recessed portion 55 and the recessed area 58 are only provided in the end face area 32Ac and the corner area 32Ad of the first plating material, but are not limited thereto. The recessed portion 55 and the recessed area 58 may also be provided in the main surface area 32Aa of the first plating material, or in the side surface area Ab of the second plating material.

[0160] However, preferably, the sum of the area of ​​the recessed portion 55 and the area of ​​the recessed region 58 in the first plating material end face region 32Ac is greater than one of the sum of the area of ​​the recessed portion 55 and the area of ​​the recessed region 58 in the first plating material main face region 32Aa and the sum of the area of ​​the recessed portion 55 and the area of ​​the recessed region 58 in the first plating material side face region 32Ab. Preferably, the number of recessed portions 55 provided in the first plating material end face region 32Ac is greater than one of the number of recessed portions 55 provided in the first plating material main face region 32Aa and the number of recessed portions 55 provided in the first plating material side face region 32Ab.

[0161] Furthermore, without departing from the spirit of the present invention, the constituent elements in the above embodiments can be appropriately replaced with well-known constituent elements, and the aforementioned embodiments can also be appropriately combined.

[0162] For example, the multilayer ceramic capacitor 1 of the first embodiment described above may also have the structure of the multilayer ceramic capacitor 1 of the second embodiment described above. The multilayer ceramic capacitor 1 of the second embodiment described above may also have the structure of the multilayer ceramic capacitor 1 of the first embodiment described above. The multilayer ceramic capacitor may also have at least a portion of the structure of the multilayer ceramic capacitor 1 of the first embodiment described above and at least a portion of the structure of the multilayer ceramic capacitor 1 of the second embodiment described above. For example, in the multilayer ceramic capacitor 1 of the first embodiment described above, a recessed portion 55 may be provided on the external electrode 3, and a metal thin film 56 may be provided between the glass 52 and the first plating layer 32A.

[0163] More specifically, in the multilayer ceramic capacitor 1, the outer surface of the first substrate electrode end face region 31Ac is smoother than the outer surface of the first substrate electrode main face region 31Aa. Furthermore, in a cross-section extending parallel to the stacking direction T and the length direction L and passing through the central portion of the width direction W of the multilayer 2, the ratio of the length of a line along the outer surface of the first substrate electrode end face region 31Ac to the length of a line along the first end face CA is the ratio of the length of a line along the outer surface of the first substrate electrode main face region 31Aa to the length of a line along the portion of the first main face AA where the first substrate electrode layer 31A is disposed. The first base electrode terminal face region 31Ac has a smaller hardness Hv than either the hardness Hv of the first base electrode main face region 31Aa or the hardness Hv of the first base electrode side face region 31Ab. The surface of the first plating layer 32A has multiple recesses 54 extending from the surface of the first plating layer 32A towards the laminate 2, and a recessed region 58 formed by adjacent recesses 54. The first base electrode layer 31A has a metal thin film 56, which is the region between the glass 52 and the first plating layer 32A and contains a conductive metal with a thickness of 1 μm or less. The first base electrode layer 31A may also contain conductive metal and glass 52, with the glass 52 covered by the metal thin film 56, which is a thin film of metal.

[0164] Additionally, the multilayer ceramic capacitor 1 may have at least one of the following structures: the outer surface of the first substrate electrode end face region 31Ac is smoother than the outer surface of the first substrate electrode main face region 31Aa; the ratio of the length of the line along the outer surface of the first substrate electrode end face region 31Ac to the length of the line along the first end face CA in a cross section extending parallel to the stacking direction T and the length direction L and passing through the center portion of the width direction W of the multilayer 2 is smaller than the ratio of the length of the line along the outer surface of the first substrate electrode main face region 31Aa to the length of the line along the portion of the first main face AA in which the first substrate electrode layer 31A is disposed; and the hardness Hv of the first substrate electrode end face region 31Ac is smoother than that of the first substrate electrode main face region 31Aa. The structure has a higher hardness Hv of the main surface region 31Aa of the bottom electrode and the hardness Hv of the side surface region 31Ab of the first base electrode, and may have at least one of the following structures: a structure in which a plurality of pit portions 54 recessed from the surface of the first plating layer 32A toward the laminate 2 and a region formed by adjacent pit portions 54, i.e., a pit region 58, are respectively provided on the surface of the first plating layer 32A; a structure in which the first base electrode layer 31A has a metal thin film 56 that is the region between the glass 52 and the first plating layer 32A and contains the conductive metal with a thickness of less than 1 μm; a structure in which the first base electrode layer 31A contains the conductive metal and the glass 52 and the glass 52 is covered by the metal thin film 56, which is a thin film of metal.

[0165] Alternatively, in the multilayer ceramic capacitor 1, the outer surface of the first base electrode end face region 31Ac may be smoother than the outer surface of the first base electrode main face region 31Aa, and the hardness Hv of the first base electrode end face region 31Ac may be higher than either the hardness Hv of the first base electrode main face region 31Aa or the hardness Hv of the first base electrode side face region 31Ab.

[0166] In the multilayer ceramic capacitor 1, the outer surface of the first base electrode end face region 31Ac may be smoother than the outer surface of the first base electrode main face region 31Aa, and the surface of the first plating layer 32A may be provided with a plurality of pits 54 recessed from the surface of the first plating layer 32A toward the multilayer body 2 and a region formed by adjacent pits 54, namely a pit region 58.

[0167] In the multilayer ceramic capacitor 1, the outer surface of the first substrate electrode terminal region 31Ac is smoother than the outer surface of the first substrate electrode main region 31Aa, and the first substrate electrode layer 31A has a metal thin film 56, which is the region between the glass 52 and the first plating layer 32A and is a region containing the conductive metal with a thickness of less than 1 μm. Alternatively, the first substrate electrode layer 31A may contain conductive metal and glass 52, with the glass 52 covered by the metal thin film 56, which is a thin film of metal.

[0168] In the multilayer ceramic capacitor 1, in a cross section extending parallel to the stacking direction T and the length direction L and passing through the central portion of the width direction W of the multilayer 2, the ratio of the length of the line along the outer surface of the first base electrode end face region 31Ac to the length of the line along the first end face CA is smaller than the ratio of the length of the line along the outer surface of the first base electrode main face region 31Aa to the length of the line along the portion of the first main face AA in which the first base electrode layer 31A is disposed, and the hardness Hv of the first base electrode end face region 31Ac is higher than either the hardness Hv of the first base electrode main face region 31Aa or the hardness Hv of the first base electrode side face region 31Ab.

[0169] In the multilayer ceramic capacitor 1, in a cross section extending parallel to the stacking direction T and the length direction L and passing through the central portion of the width direction W of the multilayer body 2, the ratio of the length of the line along the outer surface of the first base electrode end face region 31Ac to the length of the line along the first end face CA is smaller than the ratio of the length of the line along the outer surface of the first base electrode main face region 31Aa to the length of the line along the portion of the first main face AA in which the first base electrode layer 31A is disposed. Furthermore, the surface of the first plating layer 32A is provided with a plurality of recesses 54 that are recessed from the surface of the first plating layer 32A toward the multilayer body 2 and a region consisting of adjacent recesses 54, namely a recess region 58.

[0170] In the multilayer ceramic capacitor 1, in a cross-section extending parallel to the stacking direction T and the length direction L and passing through the central portion of the width direction W of the multilayer 2, the ratio of the length of the line along the outer surface of the first base electrode end face region 31Ac to the length of the line along the first end face CA is smaller than the ratio of the length of the line along the outer surface of the first base electrode main face region 31Aa to the length of the line along the portion of the first main face AA in which the first base electrode layer 31A is disposed. The first base electrode layer 31A has a metal thin film 56, which is the region between the glass 52 and the first plating layer 32A and is a region containing the conductive metal with a thickness of 1 μm or less. Alternatively, the first base electrode layer 31A may contain conductive metal and glass 52, with the glass 52 covered by the metal thin film 56, which is a thin film of metal. Explanation of reference numerals in the attached figures

[0171] 1. Multilayer ceramic capacitor; 2. Laminate; 3A. First external electrode; 3B. Second external electrode; 14. Dielectric layer; 15. Internal electrode; 15a. Opposing portion; 15b. Lead-out portion; 31A. First base electrode layer; 31Aa. Main surface area of ​​the first base electrode; 31Ab. Side surface area of ​​the first base electrode; 31Ac. End face area of ​​the first base electrode; 31Ad. Corner area of ​​the first base electrode; 32A. First plating layer; 32Aa. Main surface area of ​​the first plating material; 32Ab. Side surface area of ​​the first plating material; 32Ac. 32Ad, Corner area of ​​the first plating material; 33A, Lower plating layer; 33Aa, Main surface area of ​​the first lower plating material; 33Ab, Side surface area of ​​the first lower plating material; 33Ac, End face area of ​​the first lower plating material; 33Ad, Corner area of ​​the first lower plating material; 34A, Upper plating layer; 52, Glass; 55, Recess; 56, Metal film (conductive metal); 57, Recess area; AA, First main surface; AB, Second main surface; BA, First side surface; BB, Second side surface; CA, First end face; CB, Second end face.

Claims

1. A multilayer ceramic capacitor, wherein, The multilayer ceramic capacitor includes: A laminate having multiple stacked dielectric layers and multiple internal electrodes, and having a first main surface and a second main surface opposite to each other in the stacking direction, a first side surface and a second side surface opposite to each other in the width direction orthogonal to the stacking direction, and a first end surface and a second end surface opposite to each other in the length direction orthogonal to the stacking direction and the width direction. A first external electrode, disposed on the first end face, is connected to the internal electrode; and The second external electrode is located on the second end face and is connected to the internal electrode. The first external electrode has a first base electrode layer that is connected to the internal electrode and comprises a conductive metal and glass. The first substrate electrode layer has: a first substrate electrode end face region, which is the region that overlaps with the first end face when viewed along the said length direction; and a first substrate electrode main face region, which is the region that overlaps with the first main face when viewed along the said stacking direction. In a cross-section extending parallel to the stacking direction and the length direction at the center of the width direction of the laminated body... The ratio of the length of the line along the outer surface of the first substrate electrode end face region to the length of the line along the first end face is smaller than the ratio of the length of the line along the outer surface of the first substrate electrode main face region to the length of the line along the portion of the first main face in which the first substrate electrode layer is disposed.

2. The multilayer ceramic capacitor according to claim 1, wherein, In a cross-section extending parallel to the stacking direction and the length direction at the center of the width direction of the laminated body... Let A1 be the ratio of the length of the line along the surface of the first substrate electrode end face region to the length of the line along the first end face. And when the ratio of the length along the outer surface of the first base electrode main surface region to the length of the line along the portion of the first main surface that contacts the first base electrode main surface region is set to B1, The relationship between A1 and B1 satisfies 0.5 ≤ A1 / B1 < 1.

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