Plasma processing system configured for transmission of pulsed voltage waveforms

Abstract

A plasma processing system includes a pulsed voltage source configured to generate a pulsed voltage waveform having a first frequency. The plasma processing system includes a radio frequency source configured to generate a radio frequency waveform having a second frequency that is higher than the first frequency. The plasma processing system includes a junction box housing that electrically couples the pulsed voltage source to a direct current conductor coupled to a substrate support and further electrically couples the pulsed voltage source to a radio frequency conductor coupled to a radio frequency backplane. The junction box housing includes a pulsed voltage filter circuit coupled between the radio frequency source and the radio frequency conductor and operable to filter the pulsed voltage waveform. The junction box housing further includes a radio frequency filter circuit coupled between the pulsed voltage source and the direct current conductor and operable to filter the radio frequency waveform.

Description

Background Technology

[0001] field

[0002] The embodiments of this disclosure are generally related to systems used in the manufacture of semiconductor devices. More specifically, embodiments of this disclosure relate to plasma processing systems for handling substrates.

[0003] Related technical descriptions

[0004] Reliably manufacturing high aspect ratio features is a major technological challenge for next-generation VLSI and ULSI semiconductor devices. One approach to forming high aspect ratio features is to use plasma-assisted etching processes, such as reactive ion etching (RIE) plasma processes, to form high aspect ratio openings in a material layer (e.g., a dielectric layer) of a substrate. In a typical RIE plasma process, plasma is generated in a RIE processing chamber, and ions from the plasma are accelerated toward the surface of the substrate to form openings in a material layer beneath a mask layer formed on the substrate surface.

[0005] A typical reactive ion etching (RIE) plasma processing chamber includes a radio frequency (RF) bias generator that supplies an RF voltage to a "power electrode" (e.g., a bias electrode), such as a metal plate, positioned adjacent to an "electrostatic chuck" (ESC) assembly, more commonly referred to as a "cathode." The power electrode can be capacitively coupled to the plasma of the processing system via a thick dielectric material (e.g., a ceramic material) that is part of the ESC assembly. In capacitively coupled gas discharge, the plasma is generated using an RF generator coupled to the RF electrode via an RF matching network ("RF matching") that adjusts the apparent load to 50 Ω to minimize reflected power and maximize power transfer efficiency. Applying an RF voltage to the power electrode forms an electron-repellent plasma shell (also called a "cathode shell") above the processing surface of the substrate, which is positioned on the substrate support surface of the ESC assembly during processing. The nonlinear diode-like characteristics of the plasma shell cause rectification of the applied RF field, resulting in a DC voltage drop, or "self-bias," between the substrate and the plasma. This makes the substrate potential negative relative to the plasma potential. This voltage drop determines the average energy of the plasma ions that accelerate towards the substrate, thus affecting the etching anisotropy. More specifically, the directionality of the ions, the feature profile, and the etch selectivity of the mask and stop layer are controlled by the ion energy distribution function (IEDF). In a plasma with RF bias, the IEDF typically has two non-discrete peaks and an ion cluster, one at a low energy and the other at a high energy, with the energy range of the ion cluster extending between these two peaks. The presence of the ion cluster between the two peaks in the IEDF reflects the voltage drop between the substrate and the plasma oscillating at the RF bias frequency. When using a lower-frequency RF bias generator to achieve a higher self-bias voltage, the energy difference between these two peaks can be quite significant; moreover, this can lead to bending of the etched feature walls due to the more isotropic etching profile caused by the ions at the lower energy peaks. Compared to high-energy ions, low-energy ions are less effective at reaching the corners at the bottom of etched features (e.g., due to charging effects), but result in less mask material sputtering. This is particularly important in high aspect ratio etching applications (e.g., hard mold opening or dielectric mold etching). As feature sizes continue to shrink and aspect ratios increase, while feature profile control requirements become increasingly stringent, IEDFs that provide good control over the substrate surface during processing become increasingly important.

[0006] Other known plasma processes and processing chamber designs have also found that transmitting multiple different RF frequencies to one or more electrodes within a plasma processing chamber can be used to control various plasma characteristics, such as plasma density, ion energy, and / or plasma chemistry. However, it has been found that transmitting multiple conventional sinusoidal waveforms from two or more RF sources, each configured to provide different RF frequencies, is insufficient for adequate or ideal control of shell characteristics and can lead to undesirable arcing problems. Furthermore, due to direct or capacitive coupling between RF sources during processing, each RF source may induce RF currents supplied to the output of other connected RF sources (e.g., commonly referred to as "crosstalk"), which can cause power deviations from the intended load (plasma) and potentially damage each RF source.

[0007] Therefore, the industry needs novel, robust, and reliable plasma processing and biasing methods that can maintain a nearly constant shell voltage to generate ideal and repeatable IEDFs on the substrate surface, enabling precise control over the shape of the IEDFs and, in some cases, control over the etch profiles of features formed on the substrate surface. Summary of the Invention

[0008] The embodiments provided herein typically include apparatus, plasma processing systems, and methods for generating substrate plasma processing waveforms in a processing chamber.

[0009] In one aspect, a plasma processing system is provided. The plasma processing system includes a processing chamber defining a processing volume. The plasma processing system further includes a substrate support assembly disposed within the processing volume. The substrate support assembly includes an RF base plate and a substrate support member positioned on the RF base plate. The plasma processing system includes a pulse voltage source configured to generate a pulse voltage waveform having a first frequency. The plasma processing system also includes an RF source configured to generate an RF waveform having a second frequency higher than the first frequency. The plasma processing system further includes a junction box housing that electrically couples the pulse voltage source to a DC conductor coupled to the substrate support member and further electrically couples the pulse voltage source to an RF conductor coupled to the RF base plate. The junction box housing includes a pulse voltage filtering circuit coupled between the RF source and the RF conductor, operable for filtering the pulse voltage waveform. The junction box housing further includes an RF filtering circuit coupled between the pulse voltage source and the DC conductor, operable for filtering the RF waveform.

[0010] In another aspect, a plasma processing system is provided. The plasma processing system includes a processing chamber defining a processing volume. The plasma processing system includes a substrate support assembly disposed within the processing volume. The substrate support assembly includes an RF base plate and a substrate support member positioned on the RF base plate. The plasma processing system includes an inductively coupled plasma assembly. The inductively coupled plasma assembly includes an RF coil positioned outside the processing volume. The inductively coupled plasma assembly further includes a first RF source configured to drive the RF coil. The plasma processing system includes a pulse voltage source configured to generate a pulse voltage waveform having a first frequency. The plasma processing system also includes a second RF source configured to generate an RF waveform having a second frequency higher than the first frequency. The plasma processing system also includes a junction box housing that electrically couples the pulse voltage source to a DC conductor coupled to the substrate support member and further electrically couples the pulse voltage source to an RF conductor coupled to the RF base plate. The junction box housing includes a pulse voltage filtering circuit coupled between the second RF source and the RF conductor, operable for filtering the pulse voltage waveform. The junction box housing further includes an RF filter circuit coupled between a pulse voltage source and a DC conductor, operable to filter RF waveforms.

[0011] Brief description of the attached figures

[0012] To gain a detailed understanding of the features described above, reference can be made to embodiments for a more specific description of the disclosure, some of which are shown in the accompanying drawings. It should be noted that the drawings illustrate exemplary embodiments only and should not be construed as limiting their scope, and may allow for other equally effective embodiments.

[0013] Figure 1A The figure shows a schematic side cross-sectional view of a plasma processing system according to certain embodiments of the present disclosure.

[0014] Figure 1B The figure shows a voltage waveform diagram established on a substrate due to the application of a voltage waveform to an electrode in a processing chamber, according to certain embodiments of the present disclosure.

[0015] Figure 2 The figure shows a junction box housing according to certain embodiments of the present disclosure, which electrically couples a pulse voltage waveform to the electrodes of the substrate support member of the substrate support assembly, and further electrically couples an RF bias source to the RF base plate of the substrate support assembly.

[0016] Figure 3A The figure shows a circuit diagram of a pulse voltage filtering circuit for a junction box housing according to certain embodiments of the present disclosure.

[0017] Figure 3BThe figure shows a circuit diagram of an RF filtering circuit for a junction box housing according to certain embodiments of the present disclosure.

[0018] Figure 4A The illustrations are based on certain embodiments of this disclosure. Figure 3A A graphical representation of the frequency response of a pulse voltage filter circuit.

[0019] Figure 4B The illustrations are based on certain embodiments of this disclosure. Figure 3B A graphical representation of the frequency response of the radio frequency filter circuit.

[0020] Figure 5 The figure shows a junction box housing according to certain embodiments of the present disclosure, which electrically couples a pulse voltage source and an RF bias source to an RF base plate of a substrate support assembly.

[0021] Figures 6A-6C The illustration shows different embodiments of a junction box housing according to certain embodiments of the present disclosure, wherein the junction box housing electrically couples a pulse voltage source to the electrodes of the substrate support member of the substrate support assembly, and further electrically couples the pulse voltage source to the radio frequency base plate of the substrate support assembly.

[0022] Figures 7A-7C The diagram illustrates different pulse voltage filtering circuits for a junction box housing according to certain embodiments of the present disclosure.

[0023] Figures 8A-8F The illustration shows different radio frequency filtering circuits for junction box housings according to certain embodiments of the present disclosure.

[0024] For ease of understanding, the same reference numerals have been used where possible to designate the same elements shared across the figures. It is anticipated that elements and features of one embodiment may be advantageously combined in other embodiments without further explanation. Detailed Implementation

[0025] An exemplary aspect of this disclosure relates to a junction box housing for a plasma processing system, the plasma processing system including at least one pulse voltage source and one radio frequency (RF) bias source. The pulse voltage source is configured to generate a pulse voltage waveform (e.g., having a series of harmonics) having a first frequency (e.g., about 100 kHz to 2 MHz), and the RF bias source is configured to generate an RF waveform having a second frequency higher than the first frequency (e.g., between 2 MHz and 200 MHz). In some embodiments, the first frequency may correspond to a first harmonic (e.g., a fundamental harmonic) included in the series of harmonics constituting the pulse voltage waveform. In other embodiments, the first frequency may correspond to a different harmonic of the pulse voltage waveform (e.g., different from the first harmonic). These waveforms (i.e., the pulse voltage waveform and the RF waveform) can be transmitted to components of a substrate support assembly of the plasma processing system, the assembly including a substrate support (e.g., including bias electrodes and edge control electrodes) and an RF baseplate on which the substrate support is positioned.

[0026] The junction box according to this disclosure can electrically couple an RF bias source to an RF conductor (e.g., a portion of a power transmission line) connected to an RF base plate. In this way, an RF waveform generated by the RF bias source can be provided to the RF base plate to generate plasma, for example, within the processing volume of a plasma processing system. Furthermore, the junction box housing can electrically couple a pulse voltage source to at least one of an RF conductor or a DC conductor (e.g., another portion of a power transmission line) connected to a substrate support (e.g., its bias electrode). Thus, a pulse voltage waveform generated by the pulse voltage source can be transmitted to at least one of the RF base plate and the substrate support.

[0027] The junction box according to this disclosure may include dedicated filtering circuitry for the RF bias source and the pulse voltage source. For example, the junction box housing may include a pulse voltage waveform filtering circuit (e.g., a bandpass filter) coupled between the RF bias source and the RF conductor of the power transmission line. The pulse voltage waveform filtering circuitry allows the RF waveform generated by the RF bias source to be transmitted to the RF baseboard. Furthermore, the pulse voltage waveform filtering circuitry filters (e.g., blocks) the pulse voltage waveform generated by the pulse voltage source. In this way, the pulse voltage waveform filtering circuitry can prevent the pulse voltage waveform from coupling to the RF bias source, which could potentially damage the RF bias source in some cases.

[0028] The junction box housing further includes an RF filtering circuit (e.g., a band-stop filter) coupled between the pulse voltage source and the DC conductor of the power transmission line. The RF filtering circuit allows the pulse voltage waveform generated by the pulse voltage source to be transmitted to the substrate support (e.g., its bias electrodes). Furthermore, the RF filtering circuit filters the RF waveform generated by the RF bias source. In this way, the RF filtering circuit prevents the RF waveform from coupling to the pulse voltage source, which could potentially damage the pulse voltage source in some cases.

[0029] Exemplary aspects of this disclosure also relate to junction box housings (e.g., seen in...). Figure 6A , Figure 6B and Figure 6C The junction box housing is configured to electrically couple a pulse voltage source to a substrate support (e.g., its bias electrodes) and an RF baseplate, such that a pulse voltage waveform generated by the pulse voltage source can be simultaneously transmitted to both the substrate support and the RF baseplate. By providing the pulse voltage waveform generated by the pulse voltage source to both the substrate support and the RF baseplate, the junction box housing according to this disclosure allows the plasma processing system to achieve a single output pulse voltage source, rather than two separate pulse voltage sources, one generating a pulse voltage source for the substrate support and the other generating a pulse voltage source for the RF baseplate.

[0030] The exemplary aspects of this disclosure provide numerous technical effects and benefits. For example, the junction box housing according to this disclosure can be implemented in plasma processing systems that include, for example, an induction coil driven by a radio frequency source (e.g., located outside the processing volume) to generate plasma within the processing volume, thereby providing greater flexibility in plasma generation. For example, adding a junction box housing to such a plasma processing system enables the plasma processing system to generate inductively coupled plasma (e.g., via an induction coil driven by a radio frequency source) or capacitively coupled plasma (e.g., via a radio frequency source and / or a pulsed voltage source connected to the junction box). Adding such capability to the plasma processing system provides greater control over various process parameters (e.g., controlling the ion-to-RF ratio, ion energy, etc.) that are not possible with conventional plasma processing systems.

[0031] Plasma processing system

[0032] Figure 1AThis is a schematic cross-sectional view of a plasma processing system 100 according to certain embodiments of the present disclosure. The plasma processing system 100 is configured for plasma-assisted etching processes, such as reactive ion etching (RIE) plasma processing. However, it should be noted that the plasma processing system 100 can also be configured for other plasma-assisted processes, such as plasma-enhanced deposition processes, such as plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), plasma-enhanced atomic layer deposition (PEALD), plasma processing processes, or plasma-based ion implantation processes, such as plasma doping (PLAD).

[0033] The plasma processing system 100 typically includes a processing chamber 102. The processing chamber 102 includes a chamber body 104. The chamber body 104 includes one or more sidewalls 106 and a chamber base 108. The sidewalls 106 and the chamber base 108 together define a processing volume 110. The processing chamber 102 further includes a cover assembly 112 having a chamber cover 114. As shown, the chamber cover 114 can be positioned on the chamber body 104 to enclose the processing volume 110.

[0034] The sidewall 106 and chamber base 108 typically comprise materials sized and shaped to form structural supports for components used in the processing chamber 102, thus configuring the sidewall 106 and chamber base 108 to withstand the pressures and additional energy exerted during the generation of plasma 116 in the vacuum environment maintained within the processing volume 110. For example, the sidewall 106 and chamber base 108 may be made of metal, such as aluminum, aluminum alloys, or stainless steel alloys.

[0035] In some embodiments, the plasma processing system 100 may include a gas inlet 118 disposed on a chamber cover 114. The gas inlet 118 may transfer one or more processing gases from a processing gas source 120 in fluid communication with it to the processing volume 110. A substrate 122 may be loaded and removed from the processing volume 110 through an opening (not shown) on a sidewall 106, which is sealed by a slit valve (not shown) during plasma processing of the substrate 122.

[0036] The plasma processing system 100 includes a system controller 124. The system controller 124, also known as a processing chamber controller, includes a central processing unit (CPU) 126, memory 128, and support circuitry 130. The system controller 124 controls the process sequence required by the processing substrate 122. The CPU 126 is a general-purpose computer processor configured to control the processing chamber and associated subprocessors in an industrial environment. The memory 128 described herein is typically non-volatile memory and may include random access memory, read-only memory, floppy disk or hard disk, or other suitable forms of digital storage, whether local or remote. The support circuitry 130 is typically coupled to the CPU 126 and includes cache, clock circuitry, input / output subsystems, power supplies, and combinations thereof. Software instructions (programs) and data may be decoded and stored in memory 128 to instruct the processors within the CPU 126. The software program (or computer instructions) readable by the CPU 126 in the system controller 124 determines which tasks the components in the plasma processing system 100 can perform. Typically, the software program that can be read by the CPU 126 in the system controller 124 includes code that, when executed by the CPU 126, performs tasks related to the plasma processing method described herein. This program may include instructions for controlling various hardware and electrical components within the plasma processing system 100.

[0037] In some embodiments, the cover assembly 112 includes one or more inductively coupled plasma (ICP) assemblies, such as a first ICP assembly 132 and a second ICP assembly 134, positioned above the chamber cover 114 (e.g., along the z-direction). Thus, both the first ICP assembly 132 and the second ICP assembly 134 can be positioned outside the processing volume 110. As shown, the first ICP assembly 132 and the second ICP assembly 134 include coils 136 and 138, respectively. The first ICP assembly 132 includes a first radio frequency (RF) source 140 configured to drive coil 136 such that coil 136 inductively couples an RF waveform generated by the first RF source 140 to the plasma 116 formed in the processing volume 110 during plasma processing. Similarly, the second ICP assembly 134 includes a second RF source 142 configured to drive coil 138 such that coil 138 inductively couples an RF waveform generated by the second RF source 142 to the plasma 116 formed in the processing volume 110 during plasma processing. Embodiments of this disclosure include a plasma processing system 100, which includes one or more inductively coupled plasma (ICP) components configured together with the junction box housing disclosed herein, such as... Figures 2-8F The configuration is illustrated and discussed in the diagram.

[0038] In some embodiments, the chamber cover 114 includes a dielectric material configured to allow the coils 136, 138 to transmit fields generated during the transmission of asymmetric voltage waveforms by the first radio frequency source 140 and the second radio frequency source 142, respectively, to help generate and sustain plasma 116 in the processing volume 110.

[0039] The plasma processing system 100 includes a substrate support assembly 144. The substrate support assembly 144 includes a substrate support 146 (e.g., an electrostatic chuck) and one or more lower electrodes, such as a bias electrode 148 and / or an edge control electrode 150 formed within the substrate support 146.

[0040] In some embodiments, the substrate support assembly 144 includes an RF base plate 152, an insulating plate 154, and a ground plane 156. The RF base plate 152 can be electrically isolated from the chamber base 108 via the insulating plate 154. Furthermore, the ground plane 156 can be inserted between the insulating plate 154 and the chamber base 108. The substrate support 146 can be thermally coupled to and disposed on the RF base plate 152. In some embodiments, the RF base plate 152 is configured to regulate the temperature of the substrate support 146 and the substrate 122 disposed on the substrate support 146 during substrate processing.

[0041] The substrate support 146 is typically made of a dielectric material, such as a sintered ceramic material block, a corrosion-resistant metal oxide or metal nitride material, such as alumina (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, or combinations thereof. In the embodiments herein, the substrate support 146 further includes a bias electrode 148 embedded in its dielectric material.

[0042] In some embodiments, the bias electrode 148 may be a clamping electrode for securing (i.e., holding) the substrate 122 to the substrate support surface 146A of the substrate support 146 and applying a bias voltage to the substrate 122 relative to the plasma 116 treatment. Typically, the bias electrode 148 is formed of one or more conductive components, such as one or more metal meshes, foils, plates, or combinations thereof. Therefore, the bias electrode 148 may also be referred to as a mesh electrode.

[0043] As described above, in some embodiments, the substrate support assembly 144 includes an edge control electrode 150 positioned below the edge ring 160 of the plasma processing system 100. The edge control electrode 150 may surround the bias electrode 148 and / or be configured to maintain a distance from the center of the bias electrode 148. Generally, if the processing chamber 102 is configured to process a circular substrate, the edge control electrode 150 is annular, made of a conductive material, and configured to surround at least a portion of the bias electrode 148. In some embodiments, the edge control electrode 150 is positioned within a region of the substrate support 105. In some embodiments, the edge control electrode 150 includes conductive meshes, foils, and / or plates configured to maintain a similar distance (i.e., in the Z direction) from the substrate support surface 146A of the substrate support 146 as from the bias electrode 148. In some other embodiments, the edge control electrode 150 includes conductive meshes, foils, and / or plates positioned on or within a region of the quartz tube 162 of the processing chamber 102, and surrounding at least a portion of the bias electrode 148 and / or the substrate support 146. Alternatively, in some other embodiments (not shown), the edge control electrode 150 is positioned within or coupled to an edge ring 160 disposed on and adjacent to the substrate support 146. In this configuration, the edge ring 160 is made of a semiconductor or dielectric material (e.g., AlN).

[0044] In some embodiments, the quartz tube 162 at least partially surrounds certain portions of the substrate support assembly 144 to prevent the substrate support 146 and / or the RF baseplate 152 from contacting corrosive processing gases or plasmas, cleaning gases or plasmas, or their byproducts. Typically, the quartz tube 162, the insulating plate 154, and the ground plane 156 are surrounded by a gasket 164. In some embodiments, a plasma screen 166 is positioned between the gasket 164 and the sidewall 106 to prevent plasma from forming in a volume beneath the plasma screen 166 located between the gasket 164 and the sidewall 106.

[0045] The plasma processing system 100 includes an radio frequency (RF) bias source 168. In some embodiments, RF power for plasma production (e.g., from the RF bias source 168) may be transmitted to an RF base plate 152. In some embodiments, the frequency of the RF power may be greater than 1 MHz but less than 200 MHz, for example, about 13.56 MHz, and may be transmitted to the RF base plate 152 via an RF matching circuit 176. For example, the RF power may only be provided for a short period of time during the initial generation of plasma 116 in the processing volume 110.

[0046] The plasma processing system 100 includes a pulsed voltage source 170. The pulsed voltage source 170 can be configured to bias a bias electrode 148 of a substrate support assembly 144. Alternatively or additionally, the pulsed voltage source 170 can also be configured to bias a radio frequency (RF) substrate 152. In some embodiments, the pulsed voltage waveform generated by the pulsed voltage source 170 and supplied to the bias electrode 148, the RF substrate 152, or both may range from about 100 kHz to about 1 MHz, for example, between about 100 kHz and about 500 kHz.

[0047] The plasma processing system 100 may include a high-voltage DC power supply 172 configured to deliver a clamping voltage (e.g., about -5,000 volts to about +5,000 volts) to a bias electrode.

[0048] Figure 1B A graph 190 illustrates a typical voltage waveform established at a substrate disposed on the substrate support surface (e.g., the upper surface) of a substrate support assembly 144 in a plasma processing system 100. This typical voltage waveform is caused by a pulse voltage waveform transmitted from a pulse voltage source 170 to a bias electrode 148. A first waveform (e.g., pulse voltage waveform 195) is an example of an uncompensated pulse voltage waveform established at the substrate during plasma processing. The pulse voltage waveform period of waveform 195 has a period T. p For example, period T p Typically, the pulse voltage waveform spans between 2 microseconds (µs) and 10 microseconds, for example, 2.5 microseconds. The ion current phase of the pulse voltage waveform period usually occupies approximately 50% to approximately 95% of the period T. p For example, the period T from about 80% to about 90% p .

[0049] The pulsed voltage waveform 195 comprises two main phases: an ion current phase and a shell collapse phase. During plasma processing, these two portions of the pulsed voltage waveform 195 (e.g., the ion current phase and the shell collapse phase) can be established alternately and / or individually at the substrate. At the start of the ion current phase, the voltage at the substrate decreases due to the transfer of the negative portion (e.g., the ion current portion) of the pulsed voltage waveform supplied by the pulsed voltage source 170 to the bias electrode 148, which forms a high-voltage shell over the substrate. The high-voltage shell allows positive ions generated by the plasma to be accelerated toward the biased substrate during the ion current phase, thus controlling the number and characteristics of etching processes occurring on the substrate surface during plasma processing in the RIE process. The shell collapse phase includes positive voltage swings (e.g., generated by a positive wafer voltage), while the ion current phase includes negative voltage swings (e.g., also generated by a positive wafer voltage), such as... Figure 1B As shown.

[0050] In some embodiments, the RF bias source 168, the pulse voltage source 170, and the high-voltage DC power supply 172 may each be coupled to the electrode via a single power transmission line 174. The power transmission line 174 may include: (a) a coaxial cable, such as a flexible coaxial cable connected in series with a rigid coaxial cable, (b) an insulated high-voltage corona-resistant connecting wire, (c) a bare wire, (d) a metal rod, (e) an electrical connector, or (f) any combination of electrical components in (a)-(e).

[0051] The plasma processing system 100 includes a junction box housing 180 coupled to each of an RF bias source 168, a pulse voltage source 170, and a high-voltage DC power supply 172. For example, the junction box housing 180 may include three separate inputs, such as a first input coupled to the RF bias source 168, a second input coupled to the pulse voltage source 170, and a third input coupled to the high-voltage DC power supply 172. The junction box housing 180 may, for example, be configured to couple the pulse voltage source 170 to a bias electrode 148 (e.g., as shown in the image). Figure 2 As shown), RF baseboard (e.g., as shown) Figure 5 (as shown) or both (e.g., as shown) Figures 6A-6C (As shown).

[0052] Exemplary junction box housing configuration

[0053] Figure 2 The illustration shows components of a junction box housing 200 according to an embodiment of the present disclosure. The junction box housing 200 can be used in the above-described reference. Figure 1A The plasma processing system 100. For example, the junction box housing 200 may be the junction box housing 180.

[0054] Junction box housing 200 electrically couples pulse voltage source 170 to bias electrode 148 of substrate support assembly 144 via power transmission line 174, so that bias electrode 148 can be driven by pulse voltage waveform. Furthermore, junction box housing 200 couples RF bias source 168 to RF baseboard 152 so that RF waveform generated by RF bias source 168 can be transmitted to RF baseboard 152. Details of junction box housing 200 will now be discussed.

[0055] Junction box housing 200 includes multiple inputs. For example, junction box housing 180 includes a first input 202 coupled to an RF bias source 168. Junction box housing 200 also includes a second input 204 coupled to a pulse voltage source 170 and a third input 206 coupled to a high-voltage DC power supply 172.

[0056] The junction box housing 200 includes a single output coupled to a power transmission line 174, as referenced above. Figure 1AAs discussed in the plasma processing system 100, this output can be used to transmit power (e.g., radio frequency and direct current) to the bias electrode 148 and the radio frequency base plate 152 (e.g., designated as the RF base plate). More specifically, the output of the junction box housing 200 can be coupled to the bias electrode 148 (e.g., associated with the electrostatic chuck of the plasma processing system 100) via the DC conductor 208 (e.g., designated as the DC conductor) of the power transmission line 174. The output of the junction box housing 180 can also be coupled to the radio frequency base plate 152 via the radio frequency conductor 210 of the power transmission line 174.

[0057] In some embodiments, the bias electrode 148 is spaced apart from the substrate support surface 146A of the substrate support member 146 of the substrate support assembly 144, and thus spaced apart from the substrate 122, by a dielectric material layer of the substrate support member 146. In some embodiments, the substrate support member 146 includes an electrostatic chuck (ESC), which may be a Coulomb ESC or a Johnsen-Rahbek ESC. Generally, the bias electrode 148 and the dielectric material layer form a parallel-plate-like structure, which typically has an effective capacitance C between about 5 nF and about 50 nF. E For example, between about 7 and about 10 nF. Typically, the dielectric material layer (e.g., aluminum nitride (AlN), aluminum oxide (Al2O3), etc.) has a thickness between about 0.1 mm and about 1 mm, for example between about 0.1 mm and about 0.5 mm, for example about 0.3 mm.

[0058] refer to Figure 1A and Figure 2 In some embodiments, the RF base plate 152 and the bias electrode 148 are separated by a portion of dielectric material. In some configurations, this portion of dielectric material is the same dielectric material used to form the substrate support assembly 144 and extends from the back side of the substrate support 146 to the bias electrode 148. This portion of dielectric material of the substrate support 146 has a dielectric material that is compatible with the ESC capacitor C. E Series-connected supporting base capacitor C CL In some embodiments, the thickness of the dielectric material portion disposed between the RF base plate 152 and the bias electrode 148 is greater than the thickness of the dielectric material disposed between the bias electrode 148 and the substrate 122, wherein these dielectric materials are the same material and / or form part of the substrate support 146. In one example, the thickness of the dielectric material portion (e.g., Al2O3 or AlN) of the substrate support 146 disposed between the RF base plate 152 and the bias electrode 148 is greater than 1 mm, for example, between about 1.5 mm and about 20 mm.

[0059] In the illustrated embodiment, the pulse voltage waveform generated by the pulse voltage source 170 and / or the high-voltage DC power generated by the high-voltage DC power supply 172 can be transmitted to the bias electrode 148 via the DC conductor 208 of the power transmission line 174. Conversely, the radio frequency waveform generated by the radio frequency bias source 168 can be transmitted to the radio frequency base plate 152 via the radio frequency conductor 210.

[0060] Since both the RF bias source 168 and the pulse voltage source 170 are coupled to the power transmission line 174 and generate waveforms of different frequencies (e.g., RF waveforms from 2MHz to 200MHz and pulse voltage waveforms from approximately 100kHz to 2MHz), the junction box housing 200 includes dedicated filtering circuitry to prevent waveforms from one source from coupling to the other. Details of the dedicated filtering circuitry will be discussed later.

[0061] Junction box housing 180 includes a pulse voltage filter circuit 212 (e.g., designated as a PVT filter) coupled between the RF bias source 168 and the RF conductor 210 of the power transmission line 174. The pulse voltage filter circuit 212 can be configured to pass through the RF waveform generated by the RF bias source 168 and filter (e.g., block) the pulse voltage waveform generated by the pulse voltage source 170. In this way, the pulse voltage filter circuit 212 can prevent the pulse voltage waveform from coupling into the RF bias source 168. It should be understood that the pulse voltage filter circuit 212 can also isolate the RF bias source 168 from the high-voltage DC power supply 172 by filtering (e.g., blocking) the high-voltage DC waveform generated by the high-voltage DC power supply 172.

[0062] Junction box housing 180 includes an RF filter circuit 214 (e.g., designated as an RF filter) coupled between the pulse voltage source 170 and the DC conductor 208 of the power transmission line 174. The RF filter circuit 214 can be configured to pass through the pulse voltage waveform generated by the pulse voltage source 170 and filter (e.g., block) the RF waveform generated by the RF bias source 168. In this way, the RF filter circuit 214 can prevent RF waveforms from coupling into the pulse voltage source 170. It should be understood that the RF filter circuit 214 can also isolate the high-voltage DC power supply 172 from the RF bias source 168 by filtering (e.g., blocking) the RF waveform generated by the RF bias source 168.

[0063] In some implementations, the junction box housing 200 may include a bias compensation module 216 coupled between the radio frequency filter circuit 214 and the high-voltage DC power supply 172. The bias compensation module 216 may be configured to stabilize the DC voltage applied to the bias electrode 148 (e.g., through the DC conductor 208 of the bias electrode 148).

[0064] In some implementations, the junction box housing 200 may include a blocking capacitor 218 coupled between the pulse voltage source 170 and the RF filter circuit 214. In this way, the blocking capacitor 218 can further isolate the pulse voltage source 170 from the RF bias source 168 by blocking RF waveforms that may not be filtered by the RF filter circuit 214.

[0065] Exemplary pulse voltage filter circuit and radio frequency filter circuit

[0066] Figure 3A A circuit diagram of a filter circuit 300 according to certain embodiments of the present disclosure is shown. The filter circuit 300 can be used in the above-described reference. Figure 2 The junction box housing 200 mentioned above. For example, the filter circuit 300 can be implemented as a pulse voltage filter circuit 212 of the junction box housing 200.

[0067] As shown, the filter circuit 300 can be a bandpass filter. More specifically, the filter circuit 300 can be a second-order bandpass filter including a first capacitor C1 and a first inductor L1, which are arranged in series. It should be understood that the filter circuit 300 is not limited to... Figure 3A The configuration shown can therefore be configured in any suitable way.

[0068] Figure 3B A circuit diagram of another filter circuit 310 according to certain embodiments of the present disclosure is shown. The filter circuit 310 can be used in the above-described reference. Figure 2 The junction box housing 200 mentioned above. For example, the filter circuit 310 can be implemented as the radio frequency filter circuit 214 of the junction box housing 200.

[0069] In some embodiments, the filter circuit 310 may be configured as a band-stop filter. For example, the filter circuit 310 may include a parallel circuit 312 and / or a serial circuit 314, with the serial circuit 314 coupled in parallel to the parallel circuit 312. The parallel circuit 312 includes a first inductor L1 and a first capacitor C1. The serial circuit 314 includes a second capacitor C2 and a second inductor L2. By using these circuits, the filter circuit 310 exhibits a narrower bandwidth and greater selectivity. Furthermore, this arrangement can provide impedance matching because the parallel circuit 312 can provide complementary impedance to the serial circuit 314, resulting in better impedance matching.

[0070] Frequency response of the filter circuit in the junction box housing

[0071] Figure 4A The diagram illustrates a pulse voltage filter circuit 212 according to certain embodiments of the present disclosure (e.g., in...). Figure 2The graphical representation of the frequency response 400 (shown in the figure) is shown. Specifically, this graphical representation shows the change in gain (e.g., in decibels along the vertical axis) of the pulse voltage filter circuit 212 as a function of frequency. The pulse voltage filter circuit 212 is located at the pulse voltage source 170 (e.g., in the figure). Figure 2 The gain of the pulse voltage waveform generated (as shown in the diagram) at a frequency (e.g., up to 2MHz) is related to the pulse voltage filter circuit 212 at the RF bias source 168 (e.g., in the diagram). Figure 2 The difference in gain between the frequencies (e.g., approximately 13 MHz) of the generated radio frequency waveforms (as illustrated in the diagram) is significant. For example, in some embodiments, the gain of the pulse voltage filter circuit 212 at the frequency associated with the pulse voltage waveform may be approximately -40 dB, while the gain of the pulse voltage filter circuit 212 at the frequency associated with the radio frequency waveform may be approximately 0 dB. Therefore, the pulse voltage filter circuit 212 filters (e.g., blocks) the pulse voltage waveform (as well as the high-voltage DC waveform) and allows the radio frequency waveform to pass through.

[0072] Figure 4B The illustration shows an RF filter circuit 214 according to certain embodiments of the present disclosure (e.g., in...). Figure 2 The graphical representation of the frequency response 410 (shown in the figure) is shown. Specifically, this graphical representation shows the change in gain of the RF filter circuit 214 (e.g., expressed in decibels along the vertical axis) as a function of frequency. The gain of the RF filter circuit 214 at frequencies associated with the pulse voltage waveform generated by the pulse voltage source 170 (e.g., up to 2 MHz) is compared with the gain of the RF filter circuit 214 at the RF bias source 168 (e.g., at...). Figure 1A The difference in gain between the frequencies (e.g., 13 MHz) of the generated RF waveforms (as illustrated in the diagram) is significant. For example, the gain of the RF filter circuit 214 at the frequency associated with the pulse voltage waveform may be approximately 0 dB, while the gain of the RF filter circuit 214 at the frequency associated with the RF waveform may be approximately -40 dB. Therefore, the RF filter circuit 214 filters (e.g., blocks) the RF waveform and allows the RF waveform (as well as the high-voltage DC waveform) to pass through.

[0073] An exemplary junction box housing couples the pulse voltage source to the radio frequency baseplate of the plasma processing system.

[0074] Figure 5 The illustration shows components of a junction box housing 500 according to another embodiment of this disclosure. The junction box housing 500 may be similar to the one described above. Figure 2 The junction box housing 200 mentioned is similar. Therefore, the junction box housing 500 previously referenced Figure 2 The same reference numerals will be retained for the parts described.

[0075] and Figure 2Unlike the junction box housing 200, which only couples the RF bias source 168 to the RF base plate 152, this one has a different design. Figure 5 The junction box housing 500 couples both the RF bias source 168 and the pulse voltage source 170 to the RF base plate 152. In this way, both the RF waveform generated by the RF base plate 152 and the pulse voltage waveform generated by the pulse voltage source 170 can be transmitted to the RF base plate 152.

[0076] The junction box housing 500 includes a first radio frequency (RF) filter circuit 502 coupled between the RF conductor 210 and the pulse voltage source 170. The first RF filter circuit 502 allows the pulse voltage waveform generated by the pulse voltage source 170 to be transmitted to the RF base plate 152. Furthermore, the first RF filter circuit 502 can block (e.g., filter) the RF waveform generated by the RF bias source 168. In this way, the first RF filter circuit 502 can isolate the pulse voltage source 170 from the RF bias source 168, preventing the RF waveform generated by the RF bias source 168 from being transmitted through the RF conductor 210 of the power transmission line 174 to the RF base plate 152 and coupled to the pulse voltage source 170.

[0077] In some embodiments, the junction box housing 500 may include a blocking capacitor 504 coupled between the pulse voltage source 170 and the first radio frequency filter circuit 502. The blocking capacitor 504 may be configured to further isolate the pulse voltage source 170 from the radio frequency bias source 168.

[0078] It should be understood that, Figure 5 The pulse voltage filter circuit 212 depicted (e.g., designated as a PVT filter) may be similar to that in previous references. Figure 2 The discussion operates in essentially the same way. For example, pulse voltage filter circuit 212 can isolate RF bias source 168 from pulse voltage source 170. More specifically, pulse voltage filter circuit 212 can filter (e.g., block) the pulse voltage waveform generated by pulse voltage source 170 to prevent the pulse voltage waveform from coupling into RF bias source 168.

[0079] It should also be understood that the pulse voltage filter circuit 212 can isolate the RF bias source 168 from the high-voltage DC power supply 172. For example, the pulse voltage filter circuit 212 can filter (e.g., block) the high-voltage DC power generated by the high-voltage DC power supply to prevent the high-voltage DC power from coupling into the RF bias source 168.

[0080] The junction box housing 500 may include a second radio frequency (RF) filter circuit 506 coupled between the high-voltage DC power supply 172 and the DC conductor 208 of the power transmission line 174. The second RF filter circuit 506 may be configured to isolate the high-voltage DC power supply 172 from the RF bias source 168 to prevent RF waveforms generated by the RF bias source 168 from coupling into the high-voltage DC power supply 172.

[0081] The exemplary junction box housing couples the pulse voltage source to DC and RF.

[0082] Figure 6A , Figure 6B and Figure 6C The illustration shows a junction box housing 600 according to certain embodiments of the present disclosure. Figure 6A ), 620 Figure 6B ) and 640 ( Figure 6C More specifically, junction box housings 600, 620, and 640 represent different configurations for connecting the pulse voltage source 170 to both the DC conductor 208 and the RF conductor 210 of the power transmission line 174, so as to simultaneously transmit the pulse waveform generated by the pulse voltage source 170 to the bias electrode 148 and the RF baseplate 152.

[0083] Junction box housings 600, 620, and 640 may differ from the above references. Figure 2 The junction box housings 200 and 500 discussed herein are similar. Therefore, the junction box housings 600, 620, and 640 previously referenced are similar. Figure 2 The components described will retain the same reference numerals. Details of the different junction box housings 600, 620, and 640 will be discussed in detail below.

[0084] Figure 6A The junction box housing 600 includes a first radio frequency (RF) filter circuit 602 coupled between the pulse voltage source 170 and the DC conductor 208 of the power transmission line 174. The first RF filter circuit 602 can transmit the pulse voltage waveform generated by the pulse voltage source 170 to the bias electrode 148. Furthermore, the first RF filter circuit 602 can isolate the pulse voltage source 170 from the RF bias source 168 to prevent the RF waveform generated by the RF bias source 168 from coupling into the pulse voltage source 170.

[0085] It should be noted that the first RF filter circuit 602 can also be coupled between the high-voltage DC power supply 172 and the DC conductor 208 of the power transmission line 174. In this way, the first RF filter circuit 602 can isolate the high-voltage DC power supply 172 from the RF bias source 168 to prevent the RF waveform generated by the RF bias source 168 from coupling into the high-voltage DC power supply 172.

[0086] In some embodiments, the junction box housing 600 may include a first blocking capacitor 604 coupled between the pulse voltage source 170 and the first radio frequency filter circuit 602. The first blocking capacitor 604 may further isolate the pulse voltage source 170 from the radio frequency bias source 168. For example, the first blocking capacitor 604 may block radio frequency waveforms propagating along the DC conductor 208 to the pulse voltage source 170. More specifically, if the first radio frequency filter circuit 602 does not filter (e.g., block) the radio frequency waveform, the first blocking capacitor 604 may block the radio frequency waveform, thereby preventing the radio frequency waveform from coupling into the pulse voltage source 170.

[0087] Figure 6A The junction box housing 600 further includes a second RF filter circuit 606 coupled between the pulse voltage source 170 and the RF conductor 210 of the power transmission line 174. The second RF filter circuit 606 of the junction box housing 600 can transmit the pulse voltage waveform generated by the pulse voltage source 170 to the RF base plate 152. Furthermore, the second RF filter circuit 606 can also isolate the pulse voltage source 170 from the RF bias source 168 to prevent the RF waveform generated by the RF bias source 168 from being coupled to the pulse voltage source 170 via the RF conductor 210 of the power transmission line 174 and also transmitted to the RF base plate 152.

[0088] In some embodiments, the junction box housing 600 may include a second blocking capacitor 608 coupled between the pulse voltage source 170 and the second RF filter circuit 606. The second blocking capacitor 608 further isolates the pulse voltage source 170 from the RF bias source 168. For example, the second blocking capacitor 608 may block RF waveforms propagating along the RF conductor 210 to the pulse voltage source 170. More specifically, if the second RF filter circuit 606 does not filter (e.g., block) the RF waveform, the second blocking capacitor 608 may block the RF waveform, thereby preventing the RF waveform from coupling into the pulse voltage source 170.

[0089] Figure 6B Junction box housing 620 and Figure 6A The junction box housing 610 is substantially similar. For example, Figure 6B The junction box housing 620 includes a first radio frequency filter circuit 602, a first blocking capacitor 604, and a second radio frequency filter circuit 606. However, with Figure 6A Compared to the 600 junction box housing, Figure 6B The junction box housing does not include the second blocking capacitor 608. Therefore, the junction box housing 620 illustrates the above-mentioned reference. Figure 6A The second barrier capacitor 608 mentioned in the junction box housing 600 may be optional.

[0090] Figure 6C Junction box housing 640 and Figure 6B The junction box casings are essentially similar. For example, Figure 6C The junction box housing 640 includes a first radio frequency filter circuit 602 and a first blocking capacitor 604. However, with Figure 6B Compared to the junction box housing 620, Figure 6C The junction box housing 640 does not include the second RF filter circuit 606. Instead... Figure 6C The junction box housing 640 includes a conductor 650 (e.g., a wire) coupled between the DC conductor 208 and the RF conductor 210 of the power transmission line 174. Thus, conductor 650 provides an electrical path from the pulse voltage source 170 to the RF conductor 210 of the power transmission line 174, so that the pulse voltage waveform generated by the pulse voltage source 170 can be transmitted to the RF baseplate 152 in addition to being transmitted to the bias electrode via the DC conductor 208 of the power transmission line 174.

[0091] like Figure 6A , Figure 6B and Figure 6C As shown, in some embodiments, the substrate support assembly 144 may include a conductor 153 that couples (e.g., directly couples) the RF base plate 152 of the substrate support assembly 144 to the edge control electrode 150 of the substrate support assembly 144. In this way, a pulse voltage waveform generated by the pulse voltage source 170 is transmitted to the RF base plate 152 through the RF conductor 210 of the power transmission line 174, and can then be further transmitted to the edge control electrode 150 through the conductor 153, thereby coupling the RF base plate 152 to the edge control electrode 150.

[0092] Additional configuration of pulse voltage filter circuit

[0093] Figures 7A-7C The diagram illustrates alternative circuit designs for the pulse voltage filter circuit 212 in a junction box housing according to certain embodiments of this disclosure, as referenced above. Figure 2 , Figure 5 and Figures 6A-6C Discussion. For example, Figure 7A A first embodiment of the pulse voltage filter circuit 212 is shown, wherein a single capacitor C1 (e.g., a blocking capacitor) is implemented to block the pulse voltage waveform generated by the pulse voltage source 170.

[0094] Figure 7BA second embodiment of the pulse voltage filter circuit 212 is shown, wherein the pulse voltage filter circuit 212 includes a serial circuit 700, which includes a capacitor C1 and an inductor L1 coupled in series with the capacitor C1. The serial circuit 700 allows the pulse voltage filter circuit to be powered by an RF bias source 168 ( Figure 1A The generated radio frequency waveform passes through. In addition, the serial circuit 700 filters (e.g., blocks) the pulse voltage waveform and decouples it back to the radio frequency bias source 168.

[0095] Figure 7B The pulse voltage filter circuit also includes a parallel circuit 702. This parallel circuit 702 includes an inductor L2 and a capacitor C2 coupled in parallel with the inductor L2. The parallel circuit 702 can be adjusted to be connected in parallel with the pulse voltage source 170 (…). Figure 1A The frequency of the generated pulse voltage waveform is correlated to attenuate the pulse voltage waveform. In this way, the parallel circuit 702 provides additional pulse voltage waveform filtering to prevent the pulse voltage waveform from coupling into the RF bias source 168 and potentially damaging the RF bias source 168.

[0096] Figure 7C A third embodiment of the pulse voltage filter circuit 212 is shown, wherein the pulse voltage filter circuit 212 includes a blocking capacitor C1 and a parallel circuit 704. The blocking capacitor C1 can pass through the radio frequency waveform and filter (e.g., block) the pulse voltage waveform. The parallel circuit 704 includes an inductor L1 and a capacitor C2. The parallel circuit 704 can be as described in the above reference. Figure 7B The parallel circuit 702 of the pulse voltage filter circuit 212 operates in the same way. For example, the parallel circuit 704 can provide additional pulse voltage waveform filtering to prevent the pulse voltage waveform from coupling into the RF bias source 168 and potentially damaging the RF bias source 168.

[0097] Additional configuration of RF filtering circuit

[0098] Figures 8A-8F The illustration shows an RF filter circuit 800 for a junction box housing according to certain embodiments of the present disclosure, the junction box housings being referenced above. Figure 2 , Figure 5 and Figures 6A-6C Discussion. For example, Figure 8A The illustration shows one embodiment of an RF filter circuit 800, wherein the RF filter circuit 800 is a parallel circuit 802, which includes a capacitor C1 and an inductor L1 connected in parallel with the capacitor C1. The values ​​of the capacitor C1 and the inductor L1 can be selected so that the parallel circuit 802 can be powered by a pulse voltage source 170 (…). Figure 1A The pulse voltage waveform generated by the RF bias source 168 is filtered (e.g., blocked) and filtered by the RF bias source 168. Figure 1AThe generated radio frequency waveform. In this way, the parallel circuit 802 prevents the radio frequency waveform from coupling with the pulse voltage source 170.

[0099] Figure 8B A second embodiment of the radio frequency filter circuit 800 is shown. As shown, the radio frequency filter circuit 800 includes the components described above. Figure 8A The parallel circuit 802 is described above. The radio frequency filter circuit 800 also includes a first serial circuit 804, which includes a capacitor C2 and an inductor L2. The first serial circuit can be configured to filter (e.g., block) certain harmonics of the main frequency (e.g., the frequency of a pulse voltage waveform).

[0100] Figure 8B The RF filter circuit 800 also includes a second serial circuit 806 and an inductor L4. The inductor L4 and the second serial circuit 806 can be used to adjust (e.g., block) certain frequencies.

[0101] Figure 8C A third embodiment of the radio frequency filter circuit 800 is shown. Figure 8C The RF filter circuit 800 is the same as the one mentioned above. Figure 8B The RF filter circuit discussed earlier is similar to the 800. For example, Figure 8C The RF filter circuit 800 includes a parallel circuit 802 and an inductor L4. However, Figure 8C The RF filter circuit 800 includes only one of the serial circuits. More specifically, Figure 8C The RF filter circuit 800 only includes the second serial circuit 806. Thus, Figure 8C The RF filter circuit 800 indicates Figure 8B The first serial circuit 804 included in the radio frequency filter circuit 800 is optional.

[0102] Figure 8D The fourth embodiment of the radio frequency filter circuit 800 is shown. Figure 8D RF filter circuit 800 and Figure 8C The RF filter circuit is similar to the 800. For example, Figure 8D The RF filter circuit 800 includes a parallel circuit 802 and an inductor L4. However, Figure 8D The RF filter circuit 800 does not include Figure 8C The inductor L3 is included in the RF filter circuit.

[0103] also, Figure 8D The RF filter circuit 800 includes a capacitor C4 coupled in parallel with the parallel circuit 802 and the inductor L4. The addition of capacitor C4 can be used to filter high-frequency components associated with the RF waveform, thus further improving the performance of the RF filter circuit 800. Capacitor C4 may also affect the pulse voltage source 170 (… Figure 1A The pulse voltage waveform generated.

[0104] Figure 8E A fifth embodiment of the radio frequency filter circuit 800 is shown. Figure 8E RF filter circuit 800 and Figure 8D The RF filter circuit is similar to the 800. For example, Figure 8E The RF filter circuit 800 includes a parallel circuit 802 and a capacitor C4. However, Figure 8E The RF filter circuit 800 does not include inductor L4.

[0105] Figure 8F A sixth embodiment of the radio frequency filter circuit 800 is shown. This radio frequency filter circuit 800 is related to... Figure 8D The RF filter circuit 800 is similar to that of the RF filter circuit 800. For example, the RF filter circuit 800 includes a parallel circuit 802, an inductor L4, and a capacitor C4. However, the arrangement of the inductor L4 and the capacitor C4 is different. For example, the parallel circuit 802 is coupled between the capacitor C4 and the inductor L4.

[0106] Additional considerations

[0107] While this specification includes numerous specific implementation details, these should not be construed as limiting the scope that may be claimed, but rather as descriptions of features that may be specific to certain implementations. Some features described in this specification in the context of a single implementation may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations, separately or in any suitable sub-combination. Furthermore, while previously described features may be described as operating in certain combinations, or even initially stated as such, in some cases one or more features from a declared combination may be excluded from that combination, and the declared combination may refer to a sub-combination or a variation of a sub-combination.

[0108] The objectives of a particular implementation have been described. Other implementations, modifications, and arrangements are also within the scope of the following claims, and will be apparent to those skilled in the art. Although operations are depicted in a particular order in the illustrations or claims, this should not be construed as requiring that these operations must be performed in the specific order or sequence shown, or that all illustrated operations must be performed (some operations may be considered optional) to achieve the desired result. In some cases, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and may be performed as needed. In a particular implementation of a method or process, although the various steps are presented and described sequentially, those skilled in the art will understand that some or all steps may be performed in a different order, may be combined or omitted, and some or all steps may be performed in parallel. These steps may be performed actively or passively. Furthermore, this method or process may be repeated or extended to support multiple components or multiple users in a field environment. Therefore, its scope should not be considered limited to the specific arrangement of steps shown in the flowcharts or illustrations.

[0109] Furthermore, any stated implementation is considered applicable to at least one computer-implemented method; a non-transitory computer-readable medium storing computer-readable instructions to perform the computer-implemented method; and a computer system including computer memory interoperably coupled to a hardware processor configured to perform the computer-implemented method or instructions stored on a non-transitory computer-readable medium.

[0110] Unless otherwise defined, all technical and scientific terms used have the same meaning as understood by one of ordinary skill in the art to which this system, equipment, method, process and composition pertain.

[0111] In this disclosure, the terms “top,” “bottom,” “side,” “above,” “below,” “up,” “down,” “upward,” “downward,” “horizontal,” and “vertical,” etc., do not refer to absolute directions. Rather, these terms refer to directions relative to an unspecified reference plane. This unspecified reference plane can be vertical, horizontal, or oriented at other angles.

[0112] The singular forms “a,” “an,” “an,” and “the” include references to the plural, unless the context clearly indicates otherwise. In the claims, references to the singular element are not intended to mean “the only one,” unless specifically stated otherwise, but rather to mean “one or more.” Unless otherwise specified, the term “some” refers to one or more.

[0113] Embodiments of this disclosure may suitably include, consist of, or substantially consist of the limiting features disclosed, and may be implemented without excluding undisclosed limiting features. In this and in the appended claims, the terms “comprising,” “having,” and “including,” and all grammatical variations thereof, are intended to have an open, non-limiting meaning and do not exclude other elements or steps.

[0114] "Optional" and "optionally" indicate whether the material, event, or situation described below may or may not exist or occur. The description includes both the scenarios in which the material, event, or situation occurs and the scenarios in which it does not occur.

[0115] The term "determine" as used here encompasses a wide variety of actions. For example, "determine" can include calculation, operation, processing, deduction, investigation, querying (e.g., searching in a table, database, or other data structure), and ascertainment. Furthermore, "determine" can include receiving (e.g., receiving information), and accessing (e.g., accessing data in memory). "Determine" can also include resolving, selecting, picking, and establishing.

[0116] When the word “about” or “approximately” is used, the term can indicate that the value may vary by a range of up to ±10%, up to 5%, up to 2%, up to 1%, up to 0.5%, up to 0.1%, or up to 0.01%.

[0117] A range can be expressed as from about one specific value to about another specific value, including all specific values ​​within that range and combinations thereof. When such a range is expressed, it should be understood that another implementation is from one specific value to another specific value, and all specific values ​​within that range and combinations thereof.

[0118] As used in the terminology, "first" and "second" are arbitrarily assigned and are used only to distinguish two or more components of a system, device, or combination. It should be understood that the words "first" and "second" do not serve any other purpose, are not part of the component names or descriptions, and do not necessarily define the relative positions or locations of the components. Furthermore, the use of the terms "first" and "second" alone does not require the existence of any "third" component, although such a possibility is considered within the scope of the various described embodiments.

[0119] Although only a few exemplary embodiments have been described in detail, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without materially departing from the scope of the disclosure. Therefore, all such modifications are intended to be included within the scope of this disclosure, as defined in the following claims. In the claims, the clauses describing a component plus function are intended to cover structures described as performing said function, including not only equivalents of the structure but also equivalent structures. The applicant's explicit intention is not to invoke 35 U.S.SC §112(f) in any limitation of any claim unless the claim expressly uses the phrase "means for" in conjunction with the associated function.

[0120] The following claims are not intended to limit the provided embodiments, but should be given the full scope consistent with the language of the claims.

Claims

1. A plasma processing system, the plasma processing system comprising: A processing chamber, wherein the processing chamber defines a processing volume; A substrate support assembly is disposed within the processing volume, and the substrate support assembly includes an RF base plate and a substrate support member positioned on the RF base plate. A pulse voltage source configured to generate a pulse voltage waveform having a first frequency; A radio frequency (RF) source configured to generate an RF waveform having a second frequency higher than the first frequency; as well as A junction box housing, wherein the junction box housing electrically couples the pulse voltage source to a DC conductor coupled to the substrate support, and the junction box housing further electrically couples the pulse voltage source to an RF conductor coupled to the RF base plate, the junction box housing comprising: A pulse voltage filter circuit is coupled between the radio frequency source and the radio frequency conductor, and the pulse voltage filter circuit is operable to filter the pulse voltage waveform. as well as A radio frequency (RF) filter circuit is coupled between the pulse voltage source and the DC conductor, and the RF filter circuit is operable to filter the RF waveform.

2. The plasma processing system as described in claim 1, wherein: The substrate support includes a bias electrode and an edge electrode; and The DC conductor is coupled to the bias electrode.

3. The plasma processing system of claim 2, further comprising: A conductor that couples the RF substrate to the edge electrode.

4. The plasma processing system of claim 2, wherein the junction box housing further comprises: A blocking capacitor is coupled between the pulse voltage source and the radio frequency filter circuit.

5. The plasma processing system of claim 2, wherein the radio frequency filter circuit includes a first radio frequency filter circuit, and wherein the junction box housing further includes: A second radio frequency (RF) filter circuit is coupled between the pulse voltage source and the RF conductor coupled to the RF base plate, and the second RF filter circuit is configured to filter the RF waveform.

6. The plasma processing system of claim 5, wherein the junction box housing further comprises: A first blocking capacitor is coupled between the pulse voltage source and the DC conductor; as well as A second blocking capacitor is coupled between the pulse voltage source and the radio frequency conductor.

7. The plasma processing system of claim 1, wherein the second frequency range is from 2 MHz to 200 MHz.

8. The plasma processing system of claim 7, wherein the second frequency is less than 2 MHz.

9. The plasma processing system as claimed in claim 2, wherein: The pulse voltage filtering circuit includes a bandpass filter; and The radio frequency filtering circuit includes a band-stop filter.

10. A plasma processing system, the plasma processing system comprising: A processing chamber, wherein the processing chamber defines a processing volume; A substrate support assembly is disposed within the processing volume, and the substrate support assembly includes an RF base plate and a substrate support member positioned on the RF base plate. An inductively coupled plasma assembly, the inductively coupled plasma assembly including a radio frequency coil located outside the processing volume, the inductively coupled plasma assembly further including a first radio frequency source configured to drive the radio frequency coil; A pulse voltage source configured to generate a pulse voltage waveform having a first frequency; A second radio frequency source is configured to generate a radio frequency waveform having a second frequency higher than the first frequency; as well as A junction box housing, wherein the junction box housing electrically couples the pulse voltage source to a DC conductor coupled to the substrate support, and the junction box housing further electrically couples the pulse voltage source to an RF conductor coupled to the RF base plate, the junction box housing comprising: A pulse voltage filter circuit is coupled between the second radio frequency source and the radio frequency conductor, and the pulse voltage filter circuit is operable to filter the pulse voltage waveform. and A radio frequency (RF) filter circuit is coupled between the pulse voltage source and the DC conductor, and the RF filter circuit is operable to filter the RF waveform.

11. The plasma processing system of claim 10, wherein: The substrate support includes a bias electrode and an edge electrode; and The DC conductor is coupled to the bias electrode.

12. The plasma processing system of claim 11, further comprising: A conductor that couples the radio frequency base plate to the edge electrode.

13. The plasma processing system of claim 11, wherein the junction box housing further comprises: A blocking capacitor is coupled between the pulse voltage source and the radio frequency filter circuit.

14. The plasma processing system of claim 11, wherein the radio frequency filter circuit includes a first radio frequency filter circuit, and wherein the junction box housing further includes: A second radio frequency (RF) filter circuit is coupled between the pulse voltage source and the RF conductor coupled to the RF base plate, and the second RF filter circuit is configured to filter the RF waveform.

15. The plasma processing system of claim 14, wherein the junction box housing further comprises: A first blocking capacitor is coupled between the pulse voltage source and the DC conductor; and A second blocking capacitor is coupled between the pulse voltage source and the radio frequency conductor.

16. The plasma processing system of claim 10, wherein the pulse voltage filtering circuit includes a blocking capacitor.

17. The plasma processing system of claim 10, wherein the first radio frequency source is configured to generate the radio frequency waveform having the second frequency.

18. The plasma processing system of claim 10, wherein the pulse voltage waveform includes a series of harmonics, the series of harmonics including a fundamental harmonic and one or more additional harmonics, and the first frequency corresponds to the fundamental harmonic.

19. The plasma processing system of claim 10, further comprising: A DC power supply, operable to generate a high-voltage DC voltage waveform; and The junction box housing electrically couples the DC power supply to the radio frequency filter circuit.

20. The plasma processing system of claim 19, wherein the junction box housing further comprises: A bias compensation module is coupled between the DC power supply and the RF filter circuit.

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