Digital-to-analog converter (DAC) digital pre-distortion (DPD)

Abstract

Certain aspects of the present disclosure relate to techniques and apparatus for wireless communications. An example apparatus generally includes a baseband processor, a first baseband path coupled to the baseband processor and including a first digital pre-distortion (DPD) circuit and a first digital-to-analog converter (DAC), an output of the first DPD circuit coupled to an input of the first DAC, a second baseband path coupled to the baseband processor and including a second DPD circuit and a second DAC, an output of the second DPD circuit coupled to an input of the second DAC, a first combiner having a first input coupled to the first baseband path and a second input coupled to the second baseband path, and an amplifier coupled to an output of the first combiner.

Description

Cross-reference to related applications

[0001] This application claims priority to Israel Application No. 311517, filed on March 17, 2024, which is incorporated herein by reference. Technical Field

[0002] Certain aspects of this disclosure relate generally to electronic circuits, and more specifically to techniques for digital predistortion in digital-to-analog converters. Background Technology

[0003] Wireless communication devices are widely deployed to provide a variety of communication services, such as telephone, video, data, messaging, broadcasting, and so on. These wireless communication devices can transmit and / or receive radio frequency (RF) signals via any of a variety of suitable radio access technologies (RATs), including but not limited to 5G New Radio (NR), LTE, CDMA, TDMA, WCDMA, GSM, GSM, Bluetooth, Bluetooth Low Energy (BLE), ZigBee, WLAN RATs (e.g., WiFi), etc.

[0004] A wireless communication network may include multiple base stations capable of supporting communication with multiple mobile stations. A mobile station (MS) may communicate with a base station (BS) via downlink and uplink. A downlink (or forward link) refers to the communication link from the base station to the mobile station, while an uplink (or reverse link) refers to the communication link from the mobile station to the base station. The base station may transmit data and control information to the mobile station on the downlink and / or receive data and control information from the mobile station on the uplink. The base station and / or mobile station may include a digital-to-analog converter (DAC) for converting signals from the digital domain to the analog domain. Summary of the Invention

[0005] The systems, methods, and apparatuses of this disclosure each have several aspects, none of which are solely responsible for their desired properties. Without limiting the scope of this disclosure as set forth in the following claims, some features will now be briefly discussed. Upon consideration of this discussion, and particularly after reading the section entitled "Detailed Description," it will be understood how the features of this disclosure provide advantages including reduced area and power consumption.

[0006] Certain aspects of this disclosure relate to an apparatus for wireless communication. The apparatus generally includes: a baseband processor; a first baseband path coupled to the baseband processor and including a first digital predistortion (DPD) circuit and a first digital-to-analog converter (DAC), the output of the first DPD circuit being coupled to an input of the first DAC; a second baseband path coupled to the baseband processor and including a second DPD circuit and a second DAC, the output of the second DPD circuit being coupled to an input of the second DAC; a first combiner having a first input coupled to the first baseband path and a second input coupled to the second baseband path; and an amplifier coupled to the output of the first combiner.

[0007] Certain aspects of this disclosure relate to a method for wireless communication. The method generally includes: receiving a first baseband signal from a baseband processor at an input of a first DPD circuit in a first baseband path, the first baseband path including a first DAC having an input coupled to an output of the first DPD circuit; receiving a second baseband signal from a baseband processor at an input of a second DPD circuit in a second baseband path, the second baseband path including a second DAC having an input coupled to an output of the second DPD circuit; generating a first adjusted baseband signal and a second adjusted baseband signal, respectively, via the first and second DPD circuits based on the first and second baseband signals; generating a first analog signal via the first DAC and a second analog signal via the second DAC, respectively, based on the first and second adjusted baseband signals; generating a combined signal via a combiner based on the first and second analog signals; and amplifying the combined signal to generate an amplified signal for transmission.

[0008] Certain aspects of this disclosure relate to an apparatus for wireless communication. The apparatus generally includes: a baseband processor; a baseband path coupled to the baseband processor and including a DPD circuit and a DAC, the output of the DPD circuit coupled to the input of the DAC; a first DPD feedback path coupled between a node of the baseband path and the DPD circuit; an amplifier having an input coupled to the baseband path; and a second DPD feedback path coupled between the output of the amplifier and the baseband processor.

[0009] To achieve the foregoing and related objectives, one or more aspects include the features fully described below and specifically pointed out in the claims. The following description and drawings illustrate some exemplary features of one or more aspects in detail. However, these features indicate only some of the various ways in which the principles of the various aspects may be employed, and this description is intended to include all such aspects and their equivalents. Attached Figure Description

[0010] To gain a more detailed understanding of the foregoing features of this disclosure, a more specific description, which has been briefly summarized above, can be obtained by referring to various aspects, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only certain typical aspects of this disclosure and are therefore not to be construed as limiting its scope, as other equally valid aspects may be acknowledged in this description.

[0011] Figure 1 This is a diagram illustrating an example wireless communication network in which various aspects of the present disclosure can be practiced.

[0012] Figure 2 It is a block diagram conceptually illustrating the design of an example base station (BS) and user equipment (UE) in which various aspects of this disclosure can be practiced.

[0013] Figure 3 This is a block diagram of an example radio frequency (RF) transceiver in which various aspects of this disclosure can be practiced.

[0014] Figure 4 A transmitter including a digital-to-analog converter (DAC) and digital predistortion (DPD) circuitry according to certain aspects of this disclosure is illustrated.

[0015] Figure 5 An example baseband path with DAC DPD circuitry and a feedback path for calibration is illustrated according to certain aspects of this disclosure.

[0016] Figure 6 An example baseband path operating in mission mode according to certain aspects of this disclosure is illustrated.

[0017] Figure 7 Example specific implementations of a high-pass filter (HPF) for a DAC DPD circuit according to certain aspects of this disclosure are illustrated.

[0018] Figure 8 This is a graph illustrating the correction input signal provided to the lookup table (LUT) based on the data input signal according to certain aspects of this disclosure.

[0019] Figure 9 This is a graph illustrating multiple data input signals associated with the same correction input signal according to certain aspects of this disclosure.

[0020] Figure 10 This is a graph illustrating the baseband path response correction using interpolation according to certain aspects of this disclosure.

[0021] Figure 11 An example current guiding unit for a DAC is illustrated according to certain aspects of this disclosure.

[0022] Figure 12 This is a flowchart illustrating example operations for wireless communication according to certain aspects of this disclosure.

[0023] For ease of understanding, the same reference numerals have been used where possible to denote common elements in the figures. It is conceivable that elements disclosed in one aspect may be usefully applied to other aspects without specific description. Detailed Implementation

[0024] The linearity of the baseband circuitry for in-phase and quadrature (I / Q) transmitters affects the error vector magnitude (EVM), spectrum transmission mask (SEM), adjacent channel leakage ratio (ACLR), and harmonics of the modulated signal. Linearity specifications on baseband circuitry can lead to increased power consumption (e.g., reduced power efficiency) in circuitry due to the use of higher voltage supply rails. Furthermore, baseband filters (BBFs) may also utilize higher voltage supply rails to increase BBF linearity and achieve wider bandwidths with higher transconductance (gm) and supply current. Additionally, the high linearity specifications of baseband hardware make the use of power-efficient passive mixers challenging in many cases. Tight linearity specifications may also lead to the use of DAC segmentation and more thermometer bits, which typically increases silicon area and the use of designs that promote accurate DAC unit element matching, often increasing transceiver area. In some respects, to reduce / relax the linearity specifications of baseband circuitry from the DAC to the BBF, the nonlinearity of the transceiver in the baseband domain can be corrected (or at least reduced). For example, some aspects can be corrected (or at least reduced) by digital predistortion to correct (or at least reduce) the nonlinearity of the baseband paths of the in-phase (I) and quadrature (Q) paths, respectively, so that circuits with more nonlinearity and closer to compression can be used in DACs, BBFs, and mixers.

[0025] Various aspects of this disclosure are described more fully below with reference to the accompanying drawings. However, this disclosure may be embodied in many different forms and should not be construed as limited to any particular structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be comprehensive and complete, and will fully convey the scope of protection of this disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art should understand that the scope of this disclosure is intended to cover any aspect of the disclosure herein, whether implemented independently or in combination with any other aspect of this disclosure. For example, any number of aspects set forth herein may be used to implement an apparatus or method of practice. Furthermore, the scope of this disclosure is intended to cover such apparatuses or methods implemented using structures, functions, or structures and functions other than or different from the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure herein may be embodied by one or more elements of the claims.

[0026] The word “exemplary” is used in this document to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” in this document is not necessarily to be construed as preferred or superior to other aspects.

[0027] As used herein, the term “connected to” in various tenses of the verb “connect” can mean that element A is directly connected to element B or that other elements can be connected between element A and element B (i.e., element A and element B are indirectly connected). In the context of electronic components, the term “connected to” can also be used herein to mean that a conductor, trace, or other conductive material is used to electrically connect element A and element B (and any components electrically connected between them).

[0028] Example wireless system

[0029] Figure 1 Example wireless communication network 100 is illustrated in which various aspects of this disclosure can be practiced. For example, wireless communication network 100 may be a new radio (NR) system (e.g., a fifth-generation (5G) NR network), an evolved universal terrestrial radio access (E-UTRA) system (e.g., a fourth-generation (4G) network), a universal mobile telecommunications system (UMTS) (e.g., a second-generation / third-generation (2G / 3G) network), or a code division multiple access (CDMA) system (e.g., a 2G / 3G network), or may be configured to communicate according to IEEE standards such as one or more standards in the 802.11 standard.

[0030] like Figure 1As illustrated, the wireless communication network 100 may include multiple base stations (BS) 110a to 110z (each individually referred to herein as BS 110 or collectively as BS 110) and other network entities. BS may also be referred to as access point (AP), evolved Node B (eNodeB or eNB), next-generation Node B (gNodeB or gNB), or some other terminology.

[0031] BS 110 can provide communication coverage for a specific geographic area (sometimes referred to as a "cell"), which can be stationary or mobile depending on the location of the mobile BS. In some examples, BS 110 can use any suitable transport network, interconnected with each other through various types of backhaul interfaces (e.g., direct physical connection, wireless connection, virtual network, etc.) and / or connected to one or more other BSs or network nodes (not shown) in the wireless communication network 100. Figure 1 In the example shown, BS 110a, 110b, and 110c can be macro BSs for macro cells 102a, 102b, and 102c, respectively. BS 110x can be a pico BS for pico cell 102x. BS 110y and 110z can be femto BSs for femto cells 102y and 102z, respectively. A BS can support one or more cells.

[0032] BS 110 communicates with one or more user equipment (UEs) 120a to 120y (each individually referred to herein as "UE 120" or collectively as "UE 120") in the wireless communication network 100. The UE can be fixed or mobile and can also be referred to as a user terminal (UT), mobile station (MS), access terminal, station (STA), client, wireless device, mobile device, or some other term. The user terminal can be a wireless device such as a cellular phone, smartphone, personal digital assistant (PDA), handheld device, wearable device, wireless modem, laptop computer, tablet computer, personal computer, etc.

[0033] BS 110 is considered a transmitting entity for downlink and a receiving entity for uplink. UE 120 is considered a transmitting entity for uplink and a receiving entity for downlink. As used herein, a “transmitting entity” is an independently operating apparatus or device capable of transmitting data via a frequency channel, and a “receiving entity” is an independently operating apparatus or device capable of receiving data via a frequency channel. In the following description, the subscript “dn” denotes downlink, and the subscript “up” denotes uplink. N can be selected. up One UE is used for simultaneous transmission on the uplink, and N can be selected. dn Each UE is used for simultaneous transmission on the downlink. N upIt can be equal to or not equal to N dn And N up and N dn It can be a static value or it can change for each scheduling interval. Beam control or some other spatial processing techniques can be used at BS 110 and / or UE 120.

[0034] UEs 120 (e.g., 120x, 120y, etc.) may be distributed throughout the wireless communication network 100, and each UE 120 may be stationary or mobile. The wireless communication network 100 may also include relay stations (e.g., relay station 110r) (also referred to as repeaters, etc.) that receive transmissions of data and / or other information from upstream stations (e.g., BS 110a or UE 120r) and transmit the transmissions of data and / or other information to downstream stations (e.g., UE 120 or BS 110), or relay transmissions between UEs 120 to facilitate communication between devices.

[0035] BS 110 can communicate with one or more UE 120s on both the downlink and uplink at any given time. The downlink (i.e., the forward link) is the communication link from BS 110 to UE 120, while the uplink (i.e., the reverse link) is the communication link from UE 120 to BS 110. UE 120 can also communicate peer-to-peer with another UE 120.

[0036] The wireless communication network 100 can use multiple transmit antennas and multiple receive antennas to transmit data on the downlink and uplink. BS 110 can be equipped with several (N) ap (N) antennas are used to achieve transmit diversity for downlink transmission and / or receive diversity for uplink transmission. A group (N) u Each UE 120 can receive downlink transmissions and send uplink transmissions. Each UE 120 can send user-specific data to and / or receive user-specific data from the BS 110. Typically, each UE 120 may be equipped with one or more antennas. u Each UE 120 can have the same or different number of antennas.

[0037] The wireless communication network 100 can be a time-division duplex (TDD) system or a frequency-division duplex (FDD) system. In a TDD system, the downlink and uplink share the same frequency band. In an FDD system, the downlink and uplink use different frequency bands. The wireless communication network 100 can also utilize a single carrier or multiple carriers for transmission. Each UE 120 can be equipped with a single antenna (e.g., to reduce cost) or multiple antennas (e.g., where additional cost can be supported).

[0038] Network controller 130 (sometimes referred to as a "system controller") can communicate with a group of BSs 110 and (e.g., via backhaul) provide coordination and control for these BSs 110. In some cases (e.g., in a 5G NR system), network controller 130 may include centralized units (CUs) and / or distributed units (DUs). In some aspects, network controller 130 can communicate with core network 132 (e.g., a 5G core network (5GC)) that provides various network functions such as access and mobility management, session management, user plane functions, policy control functions, authentication server functions, unified data management, application functions, network openness functions, network repository functions, network slice selection functions, etc.

[0039] In certain aspects of this disclosure, BS 110 and / or UE 120 may include a transmitter implemented using a DAC DPD, as described in more detail herein.

[0040] Figure 2 Examples of BS 110a and UE 120a in which aspects of this disclosure may be implemented (e.g., from...) Figure 1 Example components of a wireless communication network 100.

[0041] On the downlink, at BS 110a, the transmitting processor 220 can receive data from data source 212, control information from controller / processor 240, and / or other data (e.g., from scheduler 244). Various types of data can be transmitted on different transport channels. For example, control information can be designated for the Physical Broadcast Channel (PBCH), Physical Control Format Indicator Channel (PCFICH), Physical Hybrid Automatic Repeat Request (HARQ) Indicator Channel (PHICH), Physical Downlink Control Channel (PDCCH), Group Common PDCCH (GC PDCCH), etc. Data can be designated for the Physical Downlink Shared Channel (PDSCH), etc. The Media Access Control (MAC)-Control Element (MAC-CE) is a MAC layer communication structure that can be used for exchanging control commands between wireless nodes. The MAC-CE can be carried in shared channels such as PDSCH, Physical Uplink Shared Channel (PUSCH), or Physical Sidelink Shared Channel (PSSCH).

[0042] Processor 220 can process (e.g., encode and symbol map) data and control information to obtain data symbols and control symbols, respectively. Transmitter processor 220 can also generate reference symbols such as those for primary synchronization signal (PSS), secondary synchronization signal (SSS), PBCH demodulation reference signal (DMRS), and channel state information reference signal (CSI-RS).

[0043] The transmit (TX) multiple-input multiple-output (MIMO) processor 230 can perform spatial processing (e.g., pre-decoding) on ​​data symbols, control symbols, and / or reference symbols where applicable, and can provide the output symbol stream to the modulators (MODs) in transceivers 232a to 232t. Each modulator in transceivers 232a to 232t can process its own output symbol stream (e.g., for orthogonal frequency division multiplexing (OFDM), etc.) to obtain an output sample stream. Each transceiver in transceivers 232a to 232t can further process (e.g., convert to analog, amplify, filter, and up-convert) the output sample stream to obtain a downlink signal. The downlink signal from transceivers 232a to 232t can be transmitted via antennas 234a to 234t, respectively.

[0044] At UE 120a, antennas 252a to 252r can receive downlink signals from BS 110a and can provide the received signals to transceivers 254a to 254r respectively. Transceivers 254a to 254r can adjust (e.g., filter, amplify, downconvert, and digitize) the corresponding received signals to obtain input samples. Each demodulator (DEMOD) in transceivers 232a to 232t can further process the input samples (e.g., for OFDM, etc.) to obtain received symbols. MIMO detector 256 can obtain the received symbols from all demodulators in transceivers 254a to 254r, perform MIMO detection on the received symbols (where applicable), and provide the detected symbols. Receiver processor 258 can process (e.g., demodulate, deinterleave, and decode) the detected symbols, provide the decoded data for UE 120a to data sink 260, and provide the decoded control information to controller / processor 280.

[0045] On the uplink, at UE 120a, the transmit processor 264 can receive and process data from data source 262 (e.g., for the Physical Uplink Shared Channel (PUSCH)) and control information from controller / processor 280 (e.g., for the Physical Uplink Control Channel (PUCCH)). The transmit processor 264 can also generate reference symbols for reference signals (e.g., for the Sounding Reference Signal (SRS)). Symbols from the transmit processor 264 can be pre-decoded by the TX MIMO processor 266 where applicable, further processed by modulators (MODs) in transceivers 254a to 254r (e.g., for Single Carrier Frequency Division Multiplexing (SC-FDM), etc.), and transmitted to BS 110a. At BS 110a, the uplink signal from UE 120a can be received by antenna 234, processed by demodulators in transceivers 232a to 232t, detected by MIMO detector 236 where applicable, and further processed by receiver processor 238 to obtain decoded data and control information transmitted by UE 120a. Receiver processor 238 can provide the decoded data to data sink 239 and the decoded control information to controller / processor 240.

[0046] Memory 242 and 282 can store data and program code for BS 110a and UE 120a, respectively. Memory 242 and 282 can also interface with controller / processor 240 and 280, respectively. Scheduler 244 can schedule the UE for data transmission on the downlink and / or uplink.

[0047] In some aspects of this disclosure, transceiver 232 and / or transceiver 254 may be implemented using a DAC DPD, as described in more detail herein.

[0048] NR can use Orthogonal Frequency Division Multiplexing (OFDM) with a cyclic prefix (CP) on both the uplink and downlink. NR can use Time Division Duplex (TDD) to support half-duplex operation. OFDM and Single-Carrier Frequency Division Multiplexing (SC-FDM) divide the system bandwidth into multiple orthogonal subcarriers, which are often referred to as tones, frequency bands, etc. Each subcarrier can be modulated with data. Modulation symbols can be transmitted in the frequency domain using OFDM and in the time domain using SC-FDM. The spacing between adjacent subcarriers can be fixed, and the total number of subcarriers can depend on the system bandwidth. The system bandwidth can also be divided into subbands. For example, a subband can cover multiple resource blocks (RBs).

[0049] Example RF transceiver

[0050] Figure 3This is a block diagram of an example radio frequency (RF) transceiver circuit 300 according to certain aspects of this disclosure. The RF transceiver circuit 300 includes at least one transmit (TX) path 302 (also referred to as a "transmit chain") for transmitting signals via one or more antennas 306 and at least one receive (RX) path 304 (also referred to as a "receive chain") for receiving signals via antenna 306. When the TX path 302 and RX path 304 share antenna 306, these paths can be connected to the antenna via an interface 308, which may include any of a variety of suitable RF devices, such as switches, duplexers, double-ended converters, multiplexers, etc.

[0051] Receiving in-phase (I) and / or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 310, the TX path 302 may include a baseband filter (BBF) 312, a mixer 314, a driver amplifier (DA) 316, and a power amplifier (PA) 318. The BBF 312, mixer 314, DA 316, and PA 318 may be included in a radio frequency integrated circuit (RFIC). In some respects, the PA 318 may be external to the RFIC. In some respects, a DAC DPD may be implemented to increase the linearity associated with the DAC 310, BBF 312, and / or mixer 314, as described in more detail herein.

[0052] BBF 312 filters the baseband signal received from DAC 310, and mixer 314 mixes the filtered baseband signal with the transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., up-convert from baseband to RF). This frequency conversion process produces a sum and difference frequency between the LO frequency and the frequency of the baseband signal of interest. This sum and difference frequency is referred to as the "beat frequency". The beat frequency is typically in the RF range, such that the signal output from mixer 314 is typically an RF signal, which can be amplified by DA 316 and / or PA 318 before being transmitted by antenna 306. When one mixer 314 is exemplified, several mixers can be used to up-convert the filtered baseband signal to one or more intermediate frequencies and subsequently up-convert the intermediate frequency (IF) signal to the frequency used for transmission.

[0053] The RX path 304 may include a low-noise amplifier (LNA) 324, a mixer 326, and a baseband filter (BBF) 328. The LNA 324, mixer 326, and BBF 328 may be included in one or more RFICs, which may be the same RFIC as the RFIC including the TX path components, or may not be the same RFIC as the RFIC including the TX path components. The RF signal received via antenna 306 may be amplified by the LNA 324, and the mixer 326 mixes the amplified RF signal with a received local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (e.g., down-conversion). The baseband signal output from the mixer 326 may be filtered by the BBF 328 before being converted to digital I and / or Q signals by an analog-to-digital converter (ADC) 330 for digital signal processing.

[0054] Some transceivers may employ a frequency synthesizer with a variable-frequency oscillator (e.g., a voltage-controlled oscillator (VCO) or a digitally controlled oscillator (DCO)) to generate a stable, tunable LO with a specific tuning range. Thus, the transmit LO may be generated by the TX frequency synthesizer 320, which may be buffered or amplified by amplifier 322 before being mixed with the baseband signal in mixer 314. Similarly, the receive LO may be generated by the RX frequency synthesizer 332, which may be buffered or amplified by amplifier 334 before being mixed with the RF signal in mixer 326. In some aspects, a single frequency synthesizer may be used for both TX path 302 and RX path 304. In some aspects, the TX frequency synthesizer 320 and / or the RX frequency synthesizer 332 may include a frequency multiplier (such as a doubler) driven by an oscillator (e.g., a VCO) in the frequency synthesizer.

[0055] Controller 336 (e.g., Figure 2 The controller / processor 280 in the controller can direct the operation of the RF transceiver circuit 300A, such as transmitting signals via TX path 302 and / or receiving signals via RX path 304. The controller 336 can be a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof. Memory 338 (e.g., Figure 2 The memory 282 in the memory can store data and / or program code used to operate the RF transceiver circuit 300. The controller 336 and / or the memory 338 may include control logic (e.g., complementary metal-oxide-semiconductor (CMOS) logic).

[0056] although Figures 1 to 3Wireless communication is provided as an example application in which certain aspects of this disclosure can be implemented to facilitate understanding, but certain aspects described herein can be used in any of a variety of other suitable systems.

[0057] Example techniques for digital predistortion (DPD)

[0058] The linearity of the baseband circuitry in in-phase and quadrature (I / Q) (e.g., or other multiphase) transmitters affects various quality parameters of the transmitter, such as error vector magnitude (EVM), spectrum transmit mask (SEM), and adjacent channel leakage ratio (ACLR). Linearity specifications make it difficult to design power- and area-efficient digital-to-analog converters (DACs) for transceivers due to the use of higher supply voltage rails and well-designed unit element matching to improve linearity. Relaxed linearity specifications for DACs allow for fewer thermometer bits, thus reducing area consumption. Relaxing linearity specifications also simplifies the baseband filter (BBF), reducing the gain-bandwidth (GBW) product and supply margin, and facilitating a simpler architecture.

[0059] Some digital predistortion (DPD) techniques reduce the memoryless and memory-based nonlinearities (e.g., nonlinearities with memory effects) of power amplifiers. Power amplifier (PA) DPDs operate on radio frequency (RF) signals while attempting to reduce the nonlinearity response of the PA. Some DPD techniques target severe nonlinearities and strong memory effects in PAs and can be complex, employing envelope memory polynomials or memory polynomials (e.g., a polynomial for a DPD can be implemented using numerous multipliers and adders).

[0060] Certain aspects of this disclosure relate to a DAC DPD that attempts to correct the nonlinearity of each baseband path (including the DAC and BBF, and in some cases, the mixer of that baseband path). The DAC DPD can be implemented independently of the PA DPD and can provide power and area savings for each DAC, BBF, and / or mixer of the transmitter. The DAC DPD described herein implements a simpler architecture and allows for the use of lower power margin circuitry, thereby reducing area and power consumption.

[0061] Figure 4A transmitter 400 including a DAC DPD circuit 410 according to certain aspects of this disclosure is illustrated. As shown, the transmitter 400 may include multiple baseband paths for processing in-phase (I), quadrature (Q), I (I45) signals with a 45° phase shift, and Q (Q45) signals with a 45° phase shift. For example, the transmitter 400 may include an I baseband path having an I DAC (labeled "DAC_I") having an output coupled to an input of an I BBF (labeled "BBF_I") having an output coupled to an input of an I mixer (labeled "Mixer_I"). DAC_I may convert I signals from the baseband processor 402 from the digital domain to the analog domain. Analog I signals may be provided to BBF_I to generate filtered analog I signals, which are then up-converted from the baseband frequency to the radio frequency (RF) frequency using the I mixer. In some cases, one mixer is used to convert the baseband signal from the baseband frequency to the intermediate frequency (IF), while another mixer is used to convert the signal from the IF to the RF.

[0062] Similarly, transmitter 400 may include an I45 baseband path having an I45 DAC (labeled "DAC_I45"), the I45 DAC having an output coupled to an input of an I45 BBF (labeled "BBF_I45"), and the I45 BBF having an output coupled to an input of an I45 mixer (labeled "Mixer_I45"). Transmitter 400 may include a Q baseband path having a Q DAC (labeled "DAC_Q"), the Q DAC having an output coupled to an input of a Q BBF (labeled "BBF_Q"), and the Q BBF having an output coupled to an input of a Q mixer (labeled "Mixer_Q"). Transmitter 400 may also include a Q45 baseband path having a Q45 DAC (labeled "DAC_Q45") with an output coupled to the input of a Q45 BBF (labeled "BBF_Q45"), which in turn has an output coupled to the input of a Q45 mixer (labeled "Mixer_Q45"). As shown, each of the I, I45, Q, and Q45 mixers receives a local oscillator (LO) signal for up-converting the signal from the corresponding BBF. The RF signals from the I, Q, I45, and Q45 mixers may be provided to combiner 404 to generate a combined signal for amplification via PA 318 for transmission.

[0063] As shown in the figure, transmitter 400 may include a feedback path for PA DPD. For example, the feedback path may include a feedback receiver 406 (e.g., for down-conversion of the PA output signal) and a feedback ADC 408 (labeled "FBADC") for converting the down-converted PA output signal from the analog domain to the digital domain. The digital feedback signal generated by ADC 408 may be provided to baseband processor 402, which may include PA DPD circuitry for correcting (or at least reducing) the nonlinearity associated with the PA based on the feedback signal.

[0064] In some aspects of this disclosure, each of the I, I45, Q, and Q45 baseband paths may include DAC DPD circuitry, such as an I DAC DPD circuit (labeled "DAC_DPD_I"), an I45 DAC DPD circuit (labeled "DAC_DPD_I45"), a Q DAC DPD circuit (labeled "DAC_DPD_Q"), and a Q45 DAC DPD circuit (labeled "DAC_DPD_Q45"). The DAC DPD circuitry may be configured to reduce the nonlinearity associated with the DAC of the respective baseband path, and in some aspects, to reduce the nonlinearity associated with the BBF of the respective baseband path. The DAC DPD circuitry may also be configured to reduce the nonlinearity associated with the mixer coupled to each of the respective baseband paths, as described in more detail herein.

[0065] In some aspects, the DAC DPD circuitry for the I, Q, I45, and Q45 paths can be individually calibrated (e.g., trained) to reduce nonlinearity. For example, the DAC DPD circuitry can be coupled to the corresponding DAC DPD feedback path. In some aspects, each DAC DPD feedback path in the DAC DPD feedback path can be coupled between a node of the corresponding baseband path and the corresponding DPD circuitry for calibration. For example, the feedback path can be coupled to the corresponding output of the I, I45, Q, and Q45 BBF. The feedback path may include a feedback ADC (FBADC) circuit 412 configured to convert the corresponding output signals of the I, I45, Q, and Q45 BBF from the analog domain to the digital domain, based on which the corresponding I, I45, Q, and Q45 DAC DPD circuitry is calibrated to reduce the nonlinearity associated with the corresponding DAC and BBF during mission mode.

[0066] In some respects, the feedback path of the DAC DPD circuit can be coupled to the outputs of the corresponding I, I45, Q, and Q45 mixers, thereby allowing the DAC DPD circuit to reduce the nonlinearity associated with the corresponding mixers. The up-converted signals from the I, I45, Q, and Q45 mixers can be down-converted using the down-conversion circuit 414 before being provided to the FBADC 412 for conversion to the digital domain and used for calibrating the corresponding DAC DPD. In this way, the DAC DPD circuit can be calibrated to account not only the nonlinearity of the corresponding DAC and BBF, but also the nonlinearity of the corresponding mixer, as described.

[0067] Figure 5 An example baseband path is illustrated according to certain aspects of this disclosure, having a DAC DPD circuit 502 and a feedback path for calibrating (e.g., training) the DAC DPD circuit 502. The DAC DPD circuit 502 may be coupled to a non-ideal DAC and a BBF, such as relative to... Figure 4 The baseband path is described by the DAC and BBF, such as DAC_I and BBF_I. Calibration may involve iterative measurement and estimation of the polynomial coefficients of the DAC DPD circuit in the presence of a high-pass filter (HPF) to capture the frequency-dependent effects of the DAC and BBF nonlinearities. The polynomial coefficients and filter parameters can be identified during calibration using methods such as gradient descent and error reduction. For example, the DAC DPD circuit 502 may include a digital HPF 506 (labeled "HPF"). d The digital HPF is configured to receive digital input signals (e.g., digital input bits), also known as baseband signals, from a baseband processor. HPF 506 has an output coupled to the input of a DPD correction circuit 508 (e.g., signal adjustment based on a polynomial), where the DPD correction circuit 508 generates an adjusted signal provided to the input of a combiner 510, another input of which receives the digital input signal. The combiner 510 combines the digital input signal with the adjusted signal from the DPD correction circuit 508 to produce an adjusted baseband signal.

[0068] The adjusted baseband signal from the DAC DPD circuit 502 can be provided to the baseband processing circuit 504, which includes the DAC and BBF. Figure 5 In the middle, the baseband processing circuit 504 consists of an ideal DAC 512 and an analog domain HPF 514 (labeled "HPF"). aThe diagram shows the nonlinearity model circuit 516, whose output is combined with the output of the ideal DAC 512 using a combiner 518. The output of the combiner 518 is provided to a low-pass filter (LPF) 520, representing the BBF. During calibration, the baseband processing circuit 504 may include the DAC and BBF to be calibrated, such as relative to... Figure 4 The DAC_I and BBF_I are described. The baseband processing circuit 504 generates the analog output voltage.

[0069] The nonlinearity of the DAC, BBF, and DAC-BBF interface decreases at higher frequencies. This increased nonlinearity at higher frequencies is modeled by HPF 514 (e.g., providing a larger amplitude for the high-frequency signal supplied to the nonlinearity modeling circuit 516). HPF 514 has a lower gain at DC and a higher gain at higher frequencies, resulting in increased nonlinearity at those frequencies. DAC DPD circuit 502 also includes HPF 506 to correct for the increased nonlinearity at higher frequencies. That is, the higher-frequency component associated with the digital input signal has a higher amplitude at the output of HPF 506, and therefore, the higher-frequency component receives a larger amount of DPD correction from correction circuit 508.

[0070] The analog output voltage generated by the baseband processing circuit 504 can be provided to the input of the ADC 522 in the feedback path for generating a digital signal based on the analog output voltage. The digital signal can be provided to a filter equalization circuit 524, which is configured to remove (e.g., cancel) the filtering effect of the LPF 520 to produce a signal representing the nonlinearity of the baseband processing circuit 504, as described in more detail herein. The output signal y is subtracted from the digital input signal via a combiner 526 (e.g., also referred to herein as a “comparator circuit”). 均衡 An error signal is generated. This error signal can be provided to the DPD block update circuit 528, which controls the HPF and DPD correction circuit 508 to reduce the nonlinearity of the baseband processing circuit 504. In other words, as described, iterative measurements of the error signal in response to different DAC DPD polynomial coefficients and BBF parameters can be performed until the baseband path nonlinearity reaches a threshold.

[0071] In some respects, a small-signal multi-modulated input signal can be provided to the DAC to characterize the BBF (e.g., LPF 520) drop without exciting the nonlinearity of the BBF. Once the BBF is characterized, the effects of the LPF (e.g., no associated nonlinearity) can be eliminated during calibration using a filter equalization circuit 524, such that the output signal y from the equalization circuit 524 is... 均衡This indicates the nonlinearity of the baseband path (e.g., the filtering characteristics without an LPF), as described.

[0072] Based on the error signal generated from combiner 526, DPD block update circuit 528 updates the parameters of HPF 506 and / or the polynomial coefficients of DPD correction circuit 508 to reduce the nonlinearity associated with the baseband path. The DPD block update circuit changes the parameters until the error at the output of combiner 526 is minimized (or at least meets an error threshold). Relative to Figure 5 The described calibration process can be iterative and involves multiple iterations to converge. Once calibration (e.g., training) is complete, the calibration parameters can be used during task mode, such as relative to... Figure 6 A more detailed description.

[0073] In some respects, the scalable gain stage 590 may be coupled between the HPF 506 and the DPD correction circuit 508. The gain stage 590 may have a constant gain to amplify the amplitude of the signal before it is provided to the correction circuit 508 after being high-pass filtered by the HPF 506. In some respects, the gain of the gain stage 590 may be set based on the modulation scheme used for transmission (e.g., selected via the baseband processor 402). Different modulation schemes may have different peak-to-average power ratios and signal peak values, which will guarantee different amounts of gain for the gain stage 590.

[0074] Figure 6 An example baseband path operating in a post-calibration task mode according to certain aspects of this disclosure is illustrated. As shown, once the polynomial coefficients of the DPD correction circuit 508 are identified during calibration, DPD correction can be implemented using a lookup table (LUT) 602 that stores adjustment values ​​to be applied to the digital input signal for DPD correction. The DAC DPD circuit 502 can drive a baseband processing circuit 504, which may include a non-ideal DAC 604 (e.g., Figure 4 DAC_I) and non-ideal BBF 606 (e.g., Figure 4 BBF_I).

[0075] Some aspects involve measuring the baseband path separately during calibration (e.g., relative to the actual path). Figure 4The nonlinearity of the described I, Q, I45, Q45 paths is assessed, and digital predistortion is generated using DAC DPD circuitry 502. Digital predistortion can be implemented using any suitable architecture. In some aspects, LUT 602, which has a filter (e.g., HPF 506) preceding it, can be used to perform predistortion or modification of the incoming digital input signal (e.g., input bits) to amplify the high-frequency nonlinearity. The calibration process described herein reduces the error signal as the output of combiner 526, estimates the coefficients to be used to create the nonlinear term of LUT 602, and computes the predistortion filter (e.g., parameters of HPF 506) to produce a low-cost memory effect. As described, scalable gain stage 590 can be coupled between HPF 506 and LUT 602 for implementing DPD correction. The gain of gain stage 590 can be set based on the modulation scheme used for transmission, as described herein.

[0076] Figure 7 An example specific implementation of the HPF 506 according to certain aspects of this disclosure is illustrated. As shown, the HPF 506 may include a D flip-flop 702 having an output Q coupled to an input of a gain element 704. The D flip-flop 702 may apply a delay to a digital input x[n] (e.g., a baseband signal from a baseband processor 402 during clock cycle n, where n is a positive integer). In other words, the data input of the flip-flop 702 may receive the digital input x[n], while the digital input x[n-1] during a previous clock cycle is at the output Q of the flip-flop 702. The digital input x[n-1] is provided to the gain element 704 to apply a gain k. The output of the gain element 704 is subtracted from the digital input x[n] via a combiner 706 to produce a digital signal represented by the following equation:

[0077]

[0078] In this way, the HPF 506 captures most of the memory effect associated with the baseband path frequency-dependent nonlinearity. The HPF 506 can be calibrated to simulate relative to... Figure 5 The effects of the HPF514 are described. In some specific implementations, the HPF514 can be a simple 2-tap digital filter.

[0079] The digital signal at the output of combiner 706 is provided to a LUT and predistorted (modified) based on a correction input signal (e.g., a correction bit indicating the amount of correction to be applied to the digital signal to obtain a linearity response). The correction input signal selects the predistortion (e.g., an adjustment value) stored in the LUT to be applied to the digital signal, and can be selected based on the digital input x[n] to the baseband path. The predistorted signal (e.g., the adjusted baseband signal) is then provided to DAC 604 for conversion to the analog domain and to BBF 606 to produce a filtered baseband signal.

[0080] Figure 8 This is a graph 800 illustrating the correction input signal provided to LUT 602 based on a baseband path-based data input signal (e.g., a baseband signal) according to certain aspects of this disclosure. Line 804 represents the data input signal provided to LUT 602 based on the baseband path (e.g., DAC_I and BBF_I, and in some cases, ...). Figure 4 The linearity response is associated with the Mixer_I, while curve 802 represents the actual response of the baseband path without DPD. As shown, for each data input signal, a correction input can be provided to LUT 602 to implement DPD and increase the linearity of the baseband path response. For example, for data input signal 806, a correction input signal 808 can be provided to the LUT based on previous training (calibration) to achieve the correction indicated by arrow 810. Storing a correction input signal for each of the data input signals could result in an oversized LUT (e.g., 65,536 adjustment values ​​might have to be stored for a 16-bit DAC). Therefore, in some respects, the LUT could store only a single correction input signal for multiple data input signals to reduce the memory overhead associated with the LUT.

[0081] Figure 9 This is a graph 900 illustrating multiple data input signals associated with the same correction input signal according to certain aspects of this disclosure. For example, a subset 902 of the data input signals may be associated with a correction input signal 904, thereby producing a baseband path response 906. In the example described relative to graph 900, one correction input signal is used for multiple data input signals (e.g., DAC codes). Therefore, only one data input signal in the subset 902 of the data input signals may cause the baseband path response to fall on line 804, which represents the linearity response. Furthermore, the transition from one correction input signal (e.g., correction input signal 904) to another correction input signal (e.g., correction input signal 908) may cause high-frequency components in the DAC response, thereby increasing quantization noise. In some aspects, interpolation may be used to identify one or more correction inputs (e.g., for selecting adjustment values ​​stored in a LUT) to reduce quantization noise associated with the DAC.

[0082] Figure 10 This is a graph 1000 illustrating baseband path response correction using interpolation according to certain aspects of this disclosure. For example, interpolation can be used to identify associated correction input signals for one or more data input signals. For example, for data input signal 1004, interpolation can be used to determine associated correction input signals based on correction input signals 904, 908, thereby generating baseband path response 1006.

[0083] The DAC DPD correction technique described in this paper enables a new class of transmitters where efficiency can be achieved using a low-power-rail DAC and BBF, while consuming less silicon area. In some aspects, it allows the transmitter to utilize simpler and easier DAC designs by compensating for the memory effect of baseband path nonlinearity, as described.

[0084] Figure 11 An example current-guiding unit 1101 for a DAC is illustrated according to certain aspects of this disclosure. As shown, by using the DAC DPD technology described herein, the voltage rail of the current-guiding unit 1100 can be reduced (e.g., in some specific embodiments, from 1.9V for the current-guiding unit 1100 to 1.15V for the current-guiding unit 1101), thereby allowing for reduced DAC power consumption. Furthermore, the number of transistors used to implement the current source of the current-guiding unit can be reduced. For example, the current source 1102 of unit 1100 can use six transistors coupled in a cascode manner, while the current source 1103 of unit 1101 can use only three transistors coupled in a cascode manner, thereby allowing for a smaller DAC size. Therefore, the techniques described herein reduce the DAC margin specifications, thereby reducing power consumption while also reducing DAC area consumption. Specifications regarding the maximum common-mode voltage (VCM) of the DAC can be relaxed, thereby allowing for more efficient BBF designs.

[0085] Figure 12 This is a flowchart illustrating an example operation 1200 for wireless communication according to certain aspects of this disclosure. Operation 1200 may be performed, for example, by a wireless device (such as including...) Figure 4 The transmitter 400 is a wireless device that may include information about Figures 5 to 7 The circuit described is executed.

[0086] At box 1202, the wireless device can be located in the first DPD circuit of the first baseband path (e.g., Figure 6 The DPD circuit 502, which can correspond to Figure 4The first baseband signal is received from the input of a baseband processor (e.g., baseband processor 402) at the input of a first DAC (e.g., DAC_DPD_I, DAC_DPD_Q, DAC_DPD_I45, or DAC_DPD_Q45), the first baseband path including a first DAC (e.g., Figure 6 The DAC 604, which can correspond to Figure 4 The first DAC has an input terminal coupled to the output terminal of the first DPD circuit (one of DAC_I, DAC_Q, DAC_I45 or DAC_Q45).

[0087] At box 1204, the wireless device may be connected to the second DPD circuit in the second baseband path (e.g., Figure 6 The DPD circuit 502, which can correspond to Figure 4 The second baseband signal is received from the baseband processor at the input of the second DAC (e.g., DAC_DPD_I, DAC_DPD_Q, DAC_DPD_I45, or DAC_DPD_Q45), and the second baseband path includes the second DAC (e.g., Figure 6 The DAC604, which can be corresponding to Figure 4 The second DAC (which is one of DAC_I, DAC_Q, DAC_I45 or DAC_Q45) has an input that is coupled to the output of the second DPD circuit.

[0088] At block 1206, the wireless device can generate a first adjusted baseband signal and a second adjusted baseband signal via a first DPD circuit and a second DPD circuit, respectively, based on the first baseband signal and the second baseband signal. At block 1208, the wireless device can generate a first analog signal via a first DAC and a second analog signal via a second DAC, respectively, based on the first adjusted baseband signal and the second adjusted baseband signal.

[0089] At box 1210, the wireless device can transmit the first analog signal and the second analog signal via a combiner (e.g., Figure 4 The combiner 404 generates a combined signal, and at block 1212, the combined signal is amplified (e.g., via PA 318) to generate an amplified signal for transmission.

[0090] In some aspects, the wireless device may generate one or more first feedback signals via a first feedback path coupled between a node in the first baseband path and a first DPD circuit. A first adjustment value for the baseband signal used to generate the first adjustment may be identified based on the one or more first feedback signals. The wireless device may also generate one or more second feedback signals via a second feedback path coupled between a node in the second baseband path and a second DPD circuit. A second adjustment value for the baseband signal used to generate the second adjustment may be identified based on the one or more second feedback signals.

[0091] Wireless devices can use HPF (e.g., Figure 6 The first baseband signal is filtered using an HPF 506, and the first adjusted baseband signal is generated based on the filtered first baseband signal. The wireless device can generate (e.g., via combiner 510) a signal representing the difference between the first baseband signal and the first adjusted baseband signal. A first analog signal can be generated based on this signal. In some aspects, the wireless device can apply gain to the filtered first baseband signal based on a modulation scheme used for transmission. In some aspects, the first DPD circuitry may include a LUT (e.g., a baseband filter) storing adjustment values ​​used to generate the first adjusted baseband signal. Figure 6 LUT 602).

[0092] Example

[0093] In addition to the various aspects described above, specific combinations of these aspects are also within the scope of this disclosure, some of which are detailed below:

[0094] Aspect 1: An apparatus for wireless communication, the apparatus comprising: a baseband processor; a first baseband path coupled to the baseband processor and including a first digital predistortion (DPD) circuit and a first digital-to-analog converter (DAC), the output of the first DPD circuit being coupled to an input of the first DAC; a second baseband path coupled to the baseband processor and including a second DPD circuit and a second DAC, the output of the second DPD circuit being coupled to an input of the second DAC; a first combiner having a first input coupled to the first baseband path and a second input coupled to the second baseband path; and an amplifier coupled to an output of the first combiner.

[0095] Aspect 2: The apparatus according to aspect 1 further includes: a first feedback path coupled between a node of the first baseband path and the first DPD circuit; and a second feedback path coupled between a node of the second baseband path and the second DPD circuit.

[0096] Aspect 3: The apparatus according to Aspect 2, wherein the first feedback path comprises: a comparator circuit having a first input coupled to an input of the first baseband path and a second input coupled to the node of the first baseband path; and a DPD update circuit having an input coupled to an output of the comparator circuit and a first output coupled to the first DPD circuit.

[0097] Aspect 4: The apparatus according to aspect 3, wherein the first DPD circuit includes a filter coupled between the input terminal of the first baseband path and the first DPD circuit, wherein the DPD update circuit includes a second output terminal coupled to the filter.

[0098] Aspect 5: The apparatus according to aspect 3 or 4, wherein the first feedback path further includes an analog-to-digital converter (ADC) coupled between the node of the first baseband path and the first input terminal of the comparator circuit.

[0099] Aspect 6: The apparatus according to any one of Aspects 3 to 5, wherein the first baseband path includes a baseband filter (BBF); and the first feedback path further includes a filter equalization circuit coupled between the node of the first baseband path and the first input of the comparator circuit, and configured to cancel the filtering effect of the BBF to generate a signal representing the nonlinearity of the BBF.

[0100] Aspect 7: The apparatus according to any one of Aspects 2 to 6, further comprising: a first mixer having an input coupled to the first baseband path and an output coupled to one of the inputs of the first combiner; and a second mixer having an input coupled to the second baseband path and an output coupled to the other input of the first combiner, wherein: the first feedback path is coupled between the output of the first mixer and the first DPD circuit; and the second feedback path is coupled between the output of the second mixer and the second DPD circuit.

[0101] Aspect 8: The apparatus according to aspect 7, wherein: the first feedback path includes a first downconversion circuit coupled between the output of the first mixer and the first DPD circuit; and the second feedback path includes a second downconversion circuit coupled between the output of the second mixer and the second DPD circuit.

[0102] Aspect 9: The apparatus according to any one of Aspects 2 to 8, wherein: the first baseband path further includes a first baseband filter (BBF), the first feedback path being coupled between the output of the first BBF and the first DPD circuit; and the second baseband path further includes a second BBF, the second feedback path being coupled between the output of the second BBF and the second DPD circuit.

[0103] Aspect 10: The apparatus according to any one of Aspects 1 to 9, wherein the first baseband path comprises an in-phase (I) baseband path, and wherein the second baseband path comprises an orthogonal (Q) baseband path.

[0104] Aspect 11: The apparatus according to aspect 10 further includes: an I (I45) baseband path having a 45° phase shift, the I (I45) baseband path having a third DPD circuit coupled to a third DAC; a Q (Q45) baseband path having a 45° phase shift, the Q (Q45) baseband path having a 45° phase shift, the Q (Q45) baseband path having a fourth DPD circuit coupled to a fourth DAC, wherein a third input of a first combiner is coupled to the I45 baseband path, and wherein a fourth input of the first combiner is coupled to the Q45 baseband path; a first feedback path coupled between a node of the I baseband path and the first DPD circuit; a second feedback path coupled between a node of the Q baseband path and the second DPD circuit; a third feedback path coupled between a node of the I45 baseband path and the third DPD circuit; and a fourth feedback path coupled between a node of the Q45 baseband path and the fourth DPD circuit.

[0105] Aspect 12: The apparatus according to any one of Aspects 1 to 11, wherein the first DPD circuit includes a DPD correction circuit and a high-pass filter (HPF) coupled between an input terminal of the first DPD circuit and an input terminal of the DPD correction circuit, the input terminal of the first DPD circuit being coupled to the baseband processor.

[0106] Aspect 13: The apparatus according to aspect 12, wherein the first DPD circuit includes a second combiner having a first input coupled to the input of the first DPD circuit and a second input coupled to the output of the DPD correction circuit.

[0107] Aspect 14: The apparatus according to aspect 12 or 13, wherein the first DPD circuit further includes a gain stage coupled between the HPF and the DPD correction circuit.

[0108] Aspect 15: The apparatus according to aspect 14, wherein the gain associated with the gain stage is configured to be set based on a modulation scheme for transmission using the first baseband path.

[0109] Aspect 16: The apparatus according to any one of Aspects 1 to 15, wherein the first DPD circuitry includes a lookup table (LUT) configured to store adjustment values ​​to be applied to digital input values ​​from the baseband processor based on one or more correction input values.

[0110] Aspect 17: The apparatus according to any one of Aspects 1 to 16, wherein the first DPD circuitry includes a lookup table (LUT) configured to store a first adjustment value of a first subset of digital input values ​​from the baseband processor and a second adjustment value of a second subset of the digital input values.

[0111] Aspect 18: The apparatus according to aspect 17, wherein the baseband processor is configured to determine at least one third adjustment value based on the first adjustment value and the second adjustment value using interpolation.

[0112] Aspect 19: A method for wireless communication, the method comprising: receiving a first baseband signal from a baseband processor at an input of a first DPD circuit of a first baseband path, the first baseband path including a first DAC having an input coupled to an output of the first DPD circuit; receiving a second baseband signal from the baseband processor at an input of a second DPD circuit of a second baseband path, the second baseband path including a second DAC having an input coupled to an output of the second DPD circuit; generating a first adjusted baseband signal and a second adjusted baseband signal via the first DPD circuit and the second DPD circuit, respectively, based on the first baseband signal and the second baseband signal; generating a first analog signal via the first DAC and a second analog signal via the second DAC, respectively, based on the first adjusted baseband signal and the second adjusted baseband signal; generating a combined signal via a combiner based on the first analog signal and the second analog signal; and amplifying the combined signal to generate an amplified signal for transmission.

[0113] Aspect 20: The method according to aspect 19, the method further comprising: generating one or more first feedback signals via a first feedback path coupled between a node of the first baseband path and the first DPD circuit, wherein a first adjustment value for generating the baseband signal of the first adjustment is identified based on the one or more first feedback signals; and generating one or more second feedback signals via a second feedback path coupled between a node of the second baseband path and the second DPD circuit, wherein a second adjustment value for generating the baseband signal of the second adjustment is identified based on the one or more second feedback signals.

[0114] Aspect 21: The method according to aspect 19 or 20 further includes using a high-pass filter (HPF) to filter the first baseband signal, the first adjusted baseband signal being generated based on the filtered first baseband signal.

[0115] Aspect 22: According to the method of aspect 21, the method further includes generating a signal representing the difference between the first baseband signal and the first adjusted baseband signal, wherein the first analog signal is generated based on the signal.

[0116] Aspect 23: The method according to aspect 21 or 22 further includes applying a gain to the filtered first baseband signal based on the modulation scheme used for the transmission.

[0117] Aspect 24: The method according to any one of Aspects 19 to 23, wherein the first DPD circuit includes a lookup table (LUT) that stores adjustment values ​​for generating the baseband signal of the first adjustment.

[0118] Aspect 25: An apparatus for wireless communication, the apparatus comprising: a baseband processor; a baseband path coupled to the baseband processor and including a digital predistortion (DPD) circuit and a digital-to-analog converter (DAC), the output of the DPD circuit being coupled to an input of the DAC; a first DPD feedback path coupled between a node of the baseband path and the DPD circuit; an amplifier having an input coupled to the baseband path; and a second DPD feedback path coupled between an output of the amplifier and the baseband processor.

[0119] The above description provides examples and is not intended to limit the scope, applicability, or examples set forth in the claims. Changes may be made to the function and arrangement of the elements discussed without departing from the scope of this disclosure. Various processes or components may be omitted, substituted, or added as appropriate in various examples. For example, the described method may be performed in a different order than described, and various steps may be added, omitted, or combined. Furthermore, features described with respect to some examples may be combined in others. For example, any number of aspects set forth herein may be used to implement an apparatus or practice. Moreover, the scope of this disclosure is intended to cover such apparatuses or methods implemented using structures, functions, or structures and functions other than those set forth herein or different from those aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure herein may be embodied by one or more elements of the claims.

[0120] The various operations of the methods described above can be performed by any suitable component capable of performing the corresponding function. This component can include various hardware and / or software components and / or modules, including but not limited to circuits, application-specific integrated circuits (ASICs), or processors. Generally, in the presence of operations illustrated in the accompanying drawings, these operations can have corresponding components plus functional elements.

[0121] As used in this article, the phrase “at least one of” in a list of items refers to any combination of these items, including a single member. For example, “at least one of a, b, or c” is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c).

[0122] The methods disclosed herein include one or more steps or actions for implementing the described methods. The steps and / or actions of the methods may be interchanged without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of a particular step and / or action may be modified without departing from the scope of the claims.

[0123] It should be understood that the claims are not limited to the precise configurations and components illustrated above. Various modifications, variations, and alterations may be made to the arrangement, operation, and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. An apparatus for wireless communication, the apparatus comprising: Baseband processor; A first baseband path, coupled to the baseband processor and including a first digital predistortion (DPD) circuit and a first digital-to-analog converter (DAC), wherein the output of the first DPD circuit is coupled to the input of the first DAC; A second baseband path, coupled to the baseband processor and including a second DPD circuit and a second DAC, wherein the output of the second DPD circuit is coupled to the input of the second DAC; A first combiner has a first input coupled to the first baseband path and a second input coupled to the second baseband path; and An amplifier coupled to the output of the first combiner.

2. The apparatus according to claim 1, further comprising: The first feedback path is coupled between the node of the first baseband path and the first DPD circuit. and The second feedback path is coupled between the node of the second baseband path and the second DPD circuit.

3. The apparatus according to claim 2, wherein the first feedback path comprises: A comparator circuit having a first input coupled to an input terminal of the first baseband path and a second input terminal coupled to the node of the first baseband path; and The DPD update circuit has an input terminal coupled to the output terminal of the comparator circuit and a first output terminal coupled to the first DPD circuit.

4. The apparatus of claim 3, wherein the first DPD circuit includes a filter coupled between the input terminal of the first baseband path and the first DPD circuit, wherein the DPD update circuit includes a second output terminal coupled to the filter.

5. The apparatus of claim 3, wherein the first feedback path further includes an analog-to-digital converter (ADC) coupled between the node of the first baseband path and the first input terminal of the comparator circuit.

6. The apparatus according to claim 3, wherein: The first baseband path includes a baseband filter (BBF); and The first feedback path further includes a filter equalization circuit coupled between the node of the first baseband path and the first input of the comparator circuit, and configured to cancel the filtering effect of the BBF to generate a signal representing the nonlinearity of the BBF.

7. The apparatus according to claim 2, further comprising: A first mixer having an input coupled to the first baseband path and an output coupled to one of the inputs of the first combiner; and A second mixer has an input coupled to the second baseband path and an output coupled to another input of the first combiner, wherein: The first feedback path is coupled between the output of the first mixer and the first DPD circuit; and The second feedback path is coupled between the output of the second mixer and the second DPD circuit.

8. The apparatus according to claim 7, wherein: The first feedback path includes a first down-conversion circuit coupled between the output of the first mixer and the first DPD circuit; and The second feedback path includes a second down-conversion circuit coupled between the output of the second mixer and the second DPD circuit.

9. The apparatus according to claim 2, wherein: The first baseband path further includes a first baseband filter (BBF), and the first feedback path is coupled between the output of the first BBF and the first DPD circuit; and The second baseband path also includes a second BBF, and the second feedback path is coupled between the output of the second BBF and the second DPD circuit.

10. The apparatus of claim 1, wherein the first baseband path comprises an in-phase (I) baseband path, and wherein the second baseband path comprises an orthogonal (Q) baseband path.

11. The apparatus of claim 10, further comprising: An I (I45) baseband path with a 45° phase shift, wherein the I (I45) baseband path with a 45° phase shift has a third DPD circuit coupled to a third DAC; A Q (Q45) baseband path with a 45° phase shift, the Q (Q45) baseband path having a fourth DPD circuit coupled to a fourth DAC, wherein the third input of the first combiner is coupled to the Q45 baseband path, and wherein the fourth input of the first combiner is coupled to the Q45 baseband path; A first feedback path is coupled between a node of the I baseband path and the first DPD circuit. The second feedback path is coupled between the node of the Q baseband path and the second DPD circuit. The third feedback path is coupled between the node of the I45 baseband path and the third DPD circuit. and A fourth feedback path is coupled between a node of the Q45 baseband path and the fourth DPD circuit.

12. The apparatus of claim 1, wherein the first DPD circuit includes a DPD correction circuit and a high-pass filter (HPF) coupled between an input terminal of the first DPD circuit and an input terminal of the DPD correction circuit, the input terminal of the first DPD circuit being coupled to the baseband processor.

13. The apparatus of claim 12, wherein the first DPD circuit includes a second combiner having a first input coupled to the input of the first DPD circuit and a second input coupled to the output of the DPD correction circuit.

14. The apparatus of claim 12, wherein the first DPD circuit further includes a gain stage coupled between the HPF and the DPD correction circuit.

15. The apparatus of claim 14, wherein the gain associated with the gain stage is configured based on a modulation scheme for transmission using the first baseband path.

16. The apparatus of claim 1, wherein the first DPD circuitry includes a lookup table (LUT) configured to store adjustment values ​​to be applied to digital input values ​​from the baseband processor based on one or more correction input values.

17. The apparatus of claim 1, wherein the first DPD circuitry includes a lookup table (LUT) configured to store a first adjustment value of a first subset of digital input values ​​from the baseband processor and a second adjustment value of a second subset of the digital input values.

18. The apparatus of claim 17, wherein the baseband processor is configured to determine at least one third adjustment value using interpolation based on the first adjustment value and the second adjustment value.

19. A method for wireless communication, the method comprising: A first baseband signal is received from a baseband processor at the input of a first DPD circuit in a first baseband path, the first baseband path including a first DAC having an input coupled to the output of the first DPD circuit; A second baseband signal is received from the baseband processor at the input of a second DPD circuit in the second baseband path, the second baseband path including a second DAC having an input coupled to the output of the second DPD circuit; A first adjusted baseband signal and a second adjusted baseband signal are generated respectively based on the first baseband signal and the second baseband signal via the first DPD circuit and the second DPD circuit; A first analog signal is generated via the first DAC and a second analog signal is generated via the second DAC, based on the first adjusted baseband signal and the second adjusted baseband signal, respectively. as well as A combined signal is generated based on the first analog signal and the second analog signal via a combiner; as well as The combined signals are amplified to generate an amplified signal for transmission.

20. An apparatus for wireless communication, the apparatus comprising: Baseband processor; A baseband path, coupled to the baseband processor and including digital predistortion (DPD) circuitry and a digital-to-analog converter (DAC), the output of the DPD circuitry being coupled to the input of the DAC; A first DPD feedback path is coupled between a node of the baseband path and the DPD circuit. An amplifier having an input terminal coupled to the baseband path; and The second DPD feedback path is coupled between the output of the amplifier and the baseband processor.

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