Low power synchronization using transition detection

Abstract

A method of synchronization using samplers includes receiving a digital control code, converting the digital control code into control signals, inputting each of the control signals into a respective one of the samplers, detecting at least one bit transition in the digital control code, generating a synchronization pulse in response to detecting the at least one bit transition in the digital control code, and inputting the synchronization pulse to a clock input of the samplers.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to non-provisional patent application serial number 18 / 608,728, filed on March 18, 2024, with the United States Patent and Trademark Office, the entire contents of which are as fully set forth herein and incorporated herein for all applicable purposes. Background Technology Technical Field

[0003] All aspects of this disclosure relate to synchronization in general, and more specifically to synchronization using signal transition detection. Background Technology

[0004] Programmable delay circuits can be used to delay signals to a digitally programmable delay. For example, a delay circuit can delay a data signal to adjust the timing of the data signal relative to a clock signal or another data signal. The delay of a delay circuit can be programmed by delay control signals input in parallel to the delay circuit. Summary of the Invention

[0005] The following is a simplified overview of one or more embodiments to provide a basic understanding of such embodiments. This overview is not an exhaustive summary of all anticipated embodiments, nor is it intended to identify key or essential elements of all embodiments, nor to depict the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed descriptions that follow.

[0006] The first aspect relates to a system. The system includes a decoder having inputs and outputs, wherein the decoder is configured to receive digital control codes at its inputs, generate control signals based on the digital control codes, and output each control signal at a corresponding output of the decoder. The system also includes samplers, wherein each sampler has a corresponding signal input, a corresponding clock input, and a corresponding output, the corresponding signal input being coupled to a corresponding output of the decoder. The system further includes: a transition detection circuit configured to detect at least one bit transition in the digital control codes; and a pulse generation circuit coupled to the transition detection circuit and the corresponding clock input of the sampler, wherein the pulse generation circuit is configured to output a synchronization pulse to the corresponding clock input of the sampler when the transition detection circuit detects at least one bit transition in the digital control codes.

[0007] The second aspect relates to a method for synchronization using a sampler. The method includes: receiving a digital control code; converting the digital control code into control signals; inputting each control signal in the control signals to a corresponding sampler in the sampler; detecting at least one bit transition in the digital control code; generating a synchronization pulse in response to detecting at least one bit transition in the digital control code; and inputting the synchronization pulse to a clock input of the sampler.

[0008] The third aspect relates to a system. The system includes: a decoder configured to receive digital control codes and convert the digital control codes into control signals; a transition detection circuit configured to detect at least one bit transition in the digital control codes; a pulse generation circuit configured to output a synchronization pulse when the transition detection circuit detects at least one bit transition in the digital control codes; and samplers, wherein each sampler is configured to receive a corresponding control signal in the control signals, capture a bit value of the corresponding control signal in the control signals based on the synchronization pulse, and output the captured bit value of the corresponding control signal in the control signals. Attached Figure Description

[0009] Figure 1 Examples of delay circuits and control circuits according to certain aspects of this disclosure are shown.

[0010] Figure 2 An example of a control circuit according to certain aspects of this disclosure is shown, which is time-controlled by a clock signal.

[0011] Figure 3 An exemplary embodiment of a control circuit including a clock-timed trigger is shown, according to certain aspects of this disclosure.

[0012] Figure 4 This illustrates certain aspects of this disclosure. Figure 3 A timing diagram of an example of signals in a control circuit.

[0013] Figure 5 An exemplary embodiment of a control circuit including a transition detection circuit and a pulse generation circuit according to certain aspects of this disclosure is shown.

[0014] Figure 6 This illustrates certain aspects of this disclosure. Figure 5 A timing diagram of an example of signals in a control circuit.

[0015] Figure 7 Exemplary specific implementations of transition detection circuits and pulse generation circuits according to certain aspects of this disclosure are shown.

[0016] Figure 8An exemplary specific implementation of a transition detector according to certain aspects of this disclosure is shown.

[0017] Figure 9 Exemplary specific implementations of combiners according to certain aspects of this disclosure are shown.

[0018] Figure 10A This is a timing diagram illustrating an example of multiple detection pulses being combined to generate a synchronization pulse according to certain aspects of this disclosure.

[0019] Figure 10B This is a timing diagram illustrating an example of the deviation between detection pulses according to certain aspects of this disclosure.

[0020] Figure 11 Examples of delay circuits according to certain aspects of this disclosure are shown, including coarse delay circuits and fine delay circuits.

[0021] Figure 12 Exemplary specific implementations of control circuitry, including flip-flops for coarse control bits and flip-flops for fine control bits, are shown according to certain aspects of this disclosure.

[0022] Figure 13 An example of a control circuit including a sampler is shown according to certain aspects of this disclosure.

[0023] Figure 14 This is a flowchart illustrating a method for synchronizing a sampler according to certain aspects of this disclosure. Detailed Implementation

[0024] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein can be practiced. To provide a comprehensive understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0025] Figure 1 An example of a system 100 including a digitally programmable delay circuit 110 according to certain aspects of this disclosure is shown. The delay circuit 110 is configured to receive a signal at input 112, delay the signal by a programmable (i.e., tunable) delay, and output the delayed signal at output 114. The delay circuit 110 may also be referred to as a delay line or another term. The signal may be a data signal, a clock signal, or another type of signal. For example, the delay circuit 110 can be used to adjust the timing of a data signal relative to a clock signal (e.g., to adjust clock data skew) or to adjust the timing relative to another data signal.

[0026] In this example, delay circuit 110 has control inputs 116-1 to 116-m configured to receive m delay control signals in parallel, where m is an integer greater than one, and each of the inputs 116-1 to 116-m receives a corresponding delay control signal from the m delay control signals. Delay circuit 110 is configured to set its delay based on the delay control signals. For example, each delay control signal may include a corresponding control bit from the m control bits, wherein delay circuit 110 is configured to set its delay based on the bit values ​​of the m control bits.

[0027] Figure 1 An example of a control circuit 120 coupled to the delay circuit 110 is also shown. The control circuit 120 has inputs 122-1 to 122-n configured to receive n digital signals in parallel, where n is an integer greater than one, and each of the inputs 122-1 to 122-n receives a corresponding digital signal from the n digital signals. In some respects, each digital signal includes a digital control code delay_ctrl specifying the delay of the delay circuit 110. <n-1:0>The corresponding bit among the n bits. In this example, the control circuit 120 also has outputs 124-1 to 124-m, each of which is coupled to a corresponding control input among the control inputs 116-1 to 116-m of the delay circuit 110. The digital control code delay_ctrl is discussed further below. <n-1:0>The relationship between the number of bits (i.e., n) and the number of control bits (i.e., m).

[0028] Control circuit 120 is configured to transmit digital control code delay_ctrl <n-1:0>The control is converted into m control bits, and these m control bits are output in parallel to the delay circuit 110 via outputs 124-1 to 124-m. In one example, the digital control code delay_ctrl <n-1:0>This includes a binary digital code that specifies the delay of the delay circuit 110. In this example, the control circuit 120 can be configured to convert the binary digital code into thermometer code (sometimes referred to as unary code), where the bits in the thermometer code provide m control bits, as discussed further below.

[0029] Figure 2 An example of a flip-flop 210 coupled to input 112 of delay circuit 110 is shown. Flip-flop 210 has: a signal input D configured to receive a signal (e.g., a data signal) delayed by delay circuit 110; a clock input configured to receive a clock signal Clk; and an output Q coupled to input 112 of delay circuit 110. In this example, flip-flop 210 can be used to synchronize a signal (e.g., a data signal) with clock signal Clk before the signal is input to delay circuit 110. Delay circuit 110 can then delay the signal to adjust its timing relative to the clock signal. However, it should be understood that this disclosure is not limited to this example and flip-flop 210 may be omitted in some specific implementations (e.g., implementations where delay circuit 110 is used to delay a signal relative to another signal or a timing reference signal).

[0030] exist Figure 2 In the example, the clock signal Clk is also input to control circuit 120 to time the operations within control circuit 120. In this example, before the m control bits are output to delay circuit 110 via outputs 124-1 to 124-m, control circuit 120 uses the clock signal Clk to synchronize the m control bits with the clock signal Clk. Synchronization of the m control bits helps prevent minor faults in delay circuit 110 when the m control bits are updated (e.g., one or more bit values ​​of the m control bits change). Minor faults in delay circuit 110 may cause it to output narrow pulses, which could cause malfunctions (e.g., timing violations) in downstream circuits (e.g., flip-flops).

[0031] Figure 3 An exemplary specific implementation of a control circuit 120 according to certain aspects is shown. In this example, the control circuit 120 includes flip-flops 310-1 to 310-n, flip-flops 320-1 to 320-m, and a decoder 330. The decoder 330 is configured to receive the digital control code delay_ctrl via inputs 332-1 to 332-n. <n-1:0>The nth bit will be the digital control code delay_ctrl <n-1:0>The n bits are converted into m control bits, and the m control bits are output in parallel via output terminals 334-1 to 334-m.

[0032] In some respects, decoder 330 may be implemented using one or more binary-to-thermometer decoders. Binary-to-thermometer decoders for converting binary code to thermometer code are known in the art and are typically implemented using combinational logic. For example, a binary-to-thermometer decoder may receive binary code representing the number N in binary form and convert that binary code into thermometer code representing the number N using 1s repeated N times. For example, the number 4 can be represented as 100 in 3-bit binary code and as 00001111 in 8-bit thermometer code. However, it should be understood that decoder 330 is not limited to this example.

[0033] In this example, each of the flip-flops 310-1 to 310-n has a corresponding signal input D (also referred to as a data input), a corresponding clock input, and a corresponding output Q. The corresponding signal input D of each of the flip-flops 310-1 to 310-n is coupled to a corresponding input in inputs 122-1 to 122-n to receive the digital control code delay_ctrl. <n-1:0>The corresponding bit in the n bits. The corresponding clock input of each of the flip-flops 310-1 to 310-n is configured to receive the clock signal Clk. The corresponding output Q of each of the flip-flops 310-1 to 310-n is coupled to the corresponding input of the decoder 330 from input 332-1 to 332-n. In this example, flip-flops 310-1 to 310-n enable the digital control code delay_ctrl <n-1:0>The bits are synchronized with the clock signal Clk, and the synchronized bits of the digital control code are output to the decoder 330. For example, the digital control code delay_ctrl <n-1:0>The bits may be skewed (this is due to the delay_ctrl generated from the numeric control code). <n-1:0>(Mismatch in the signal path from the circuit to the bit of the control circuit 120). In this example, flip-flops 310-1 to 310-n can be used to reduce the bit deviation (i.e., to deskew the bits) by synchronizing the bits with the clock signal Clk. Flip-flops 310-1 to 310-n can be implemented using rising-edge triggered flip-flops (also known as positive-edge triggered flip-flops) or falling-edge triggered flip-flops (also known as negative-edge triggered flip-flops).

[0034] In this example, each of the flip-flops 320-1 to 320-m has a corresponding signal input D, a corresponding clock input, and a corresponding output Q. The corresponding signal input D of each of the flip-flops 320-1 to 320-m is coupled to a corresponding output of the decoder 330 (334-1 to 334-m) to receive a corresponding delay control signal in the delay control signal. The corresponding clock input of each of the flip-flops 320-1 to 320-m is configured to receive a clock signal Clk. The corresponding output Q of each of the flip-flops 320-1 to 320-m is coupled to a corresponding output of the control circuit 120 (124-1 to 124-m). In this example, the flip-flops 320-1 to 320-m synchronize m control bits of the delay control signal with the clock signal Clk, and output the synchronized m control bits to the delay circuit 110 (e.g., via the corresponding outputs 124-1 to 124-m of the control circuit 120). Figure 2 (As shown). Flip-flops 320-1 to 320-m can be implemented using rising-edge triggered flip-flops or falling-edge triggered flip-flops.

[0035] Therefore, in this example, m control bits are input to the delay circuit 110 (e.g., Figure 2 (As shown) Before this, flip-flops 320-1 to 320-m use the clock signal Clk to synchronize the m control bits of the delay control signal. The synchronization of the m control bits helps prevent minor faults in the delay circuit 110.

[0036] However, using the clock signal Clk to synchronize the m control bits of the delay control signal consumes a large amount of power and may not be suitable for high-frequency, low-power applications. This is because flip-flops 310-1 to 310-n and 320-1 to 320-m switch at the frequency of the clock signal clk (which consumes power), even in the digital control code delay_ctrl. <n-1:0>This also applies when (and therefore m control bits) do not change frequently. For example, the delay circuit 110 can be programmed during the calibration process at startup and then periodically updated at a rate much slower than the frequency of the clock signal Clk (e.g., to account for temperature changes).

[0037] Figure 4 An example of this situation is illustrated in the timing diagram, which shows the digital control code delay_ctrl. <n-1:0>An example of a clock signal Clk. Figure 4 The numeric control code delay_ctrl is shown. <n-1:0>Examples of the first update 410 and the second update 420, where each update may include the numeric control code delay_ctrl <n-1:0>One or more bit values ​​in the clock signal Clk change. In this example, the clock signal Clk includes a large number of pulses between updates 410 and 415, which causes switching activity in flip-flops 310-1 to 310-n and 320-1 to 320-m between updates 410 and 415. Even though the digital control code delay_ctrl is not present between updates 410 and 415... <n-1:0>Despite the changes, switching activities still consumes power.

[0038] To address the aforementioned issues, this disclosure detects various aspects of the digital control code delay_ctrl. <n-1:0>The change is detected, and a pulse is generated for the synchronization delay control signal. This is done using the digital control code `delay_ctrl`. <n-1:0>When changes are not frequent, this significantly reduces power consumption compared to using a clock signal Clk for synchronization. The above and other features of this disclosure are further discussed below.

[0039] Figure 5 An exemplary specific implementation of a control circuit 120 for synchronization using transition detection is shown, according to certain aspects. In this example, the control circuit 120 includes the decoder 330 discussed above and triggers 320-1 to 320-m. According to certain aspects, the control circuit 120 also includes a transition detection circuit 510 and a pulse generation circuit 520. In this example, the control circuit 120 does not include... Figure 3 The flip-flops 310-1 to 310-n are shown. This is because the transition detection circuit 510 and the pulse generation circuit 520 can tolerate the digital control code delay_ctrl. <n-1:0>The deviation between the positions will be discussed further below.

[0040] exist Figure 5 In the example, each of the inputs 332-1 to 332-n of the decoder 330 is coupled to a corresponding input of the control circuit 120 122-1 to 122-n to receive the digital control code delay_ctrl. <n-1:0>The corresponding bit among the n bits. Each output terminal of decoder 330 from 334-1 to 334-m is coupled to the signal input terminal D of the corresponding flip-flop in flip-flops 320-1 to 320-m to output the corresponding control bit among the m control bits to the corresponding flip-flop in flip-flops 320-1 to 320-m. As discussed above, the output terminal Q of each flip-flop in flip-flops 320-1 to 320-m is coupled to the corresponding output terminal of control circuit 120 from 124-1 to 124-m.

[0041] In this example, the transition detection circuit 510 is coupled to each of the inputs 122-1 to 122-n of the control circuit 120. The pulse generation circuit 520 is coupled to the transition detection circuit 510 and the clock inputs of the flip-flops 320-1 to 320-m, as shown below. Figure 5 As shown.

[0042] The transition detection circuit 510 is configured to use the digital control code delay_ctrl <n-1:0>When being updated, the numeric control code delay_ctrl is checked. <n-1:0>At least one bit of the n bits is changed (i.e., transformed). This occurs when the numeric control code `delay_ctrl`... <n-1:0>When updated, decoder 330 receives the updated digital control code delay_ctrl <n-1:0>And based on the updated digital control code delay_ctrl <n-1:0>To output the updated m control bits.

[0043] When the transition detection circuit 510 detects the digital control code delay_ctrl <n-1:0>When at least one of the n bits changes, the pulse generation circuit 520 is configured to generate a synchronization pulse. The pulse generation circuit 520 outputs a synchronization pulse to the clock inputs of flip-flops 320-1 to 320-m, causing flip-flops 320-1 to 320-m to synchronize the outputs of the updated m control bits to the delay circuit 110 based on the synchronization pulse. Figure 2 (As shown). In one example, each of the flip-flops 320-1 to 320-m may be implemented using a rising-edge triggered flip-flop configured to latch (i.e., capture) the corresponding control bit value at the corresponding signal input D on the rising edge of a sync pulse at the corresponding clock input, and output the latched (i.e., captured) control bit value at the corresponding output Q until the rising edge of the next sync pulse at the corresponding clock input. In another example, each of the flip-flops 320-1 to 320-m may be implemented using a falling-edge triggered flip-flop configured to latch (i.e., capture) the corresponding control bit value at the corresponding signal input D on the falling edge of a sync pulse at the corresponding clock input, and output the latched (i.e., captured) control bit value at the corresponding output Q until the falling edge of the next sync pulse at the corresponding clock input. However, it should be understood that this disclosure is not limited to this example.

[0044] Compared to using the clock signal Clk for synchronization, the transition detection circuit 510 and the pulse generation circuit 520 significantly reduce the power consumption in the flip-flops 320-1 to 320-m. This is because the pulse generation circuit 520 uses the digital control code delay_ctrl. <n-1:0>A synchronization pulse is generated when an update is made, but this does not happen frequently. Figure 6 An example of this situation is illustrated in the timing diagram, which shows the digital control code delay_ctrl. <n-1:0>Examples of synchronization pulses 610 and 615 are also provided. Figure 6 As shown, the pulse generation circuit 620 responds to the digital control code delay_ctrl. <n-1:0>The first update 410 and the second update 415 output synchronization pulses 610 and 615. Conversely, Figure 4 The clock signal Clk, as shown, inputs pulses at the frequency of the clock signal Clk to the clock input terminals of flip-flops 320-1 to 320-m, regardless of the digital control code delay_ctrl. <n-1:0>Has it been updated?

[0045] Figure 7 An exemplary embodiment of a transition detection circuit 510 and a pulse generation circuit 520 is shown. In this example, the transition detection circuit 510 includes transition detectors 710-1 to 710-n. Each of the transition detectors 710-1 to 710-n has a corresponding detector input terminal 712-1 to 712-n coupled to a corresponding input terminal among the input terminals 122-1 to 122-n of the control circuit 120, and a corresponding detector output terminal 714-1 to 714-n. Each of the transition detectors 710-1 to 710-n is configured to detect a bit transition at the corresponding detector input terminal 712-1 to 712-n, and output a detection pulse at the corresponding detector output terminal 714-1 to 714-n when a bit transition is detected. Since each of the transition detectors 710-1 to 710-n is coupled to a corresponding input terminal of the control circuit 120 122-1 to 122-n, each of the transition detectors 710-1 to 710-n detects the digital control code delay_ctrl. <n-1:0>The bit transitions of the corresponding bits in the n bits. The bit transitions can be from low (logic 0) to high (logic 1) or from high (logic 1) to low (logic 0).

[0046] In this example, when the numeric control code delay_ctrl <n-1:0>When updated, the transition detectors 710-1 to 710-n output one or more detection pulses at their respective detector outputs 714-1 to 714-n. The number of detection pulses output by the transition detectors 710-1 to 710-n depends on the digital control code delay_ctrl. <n-1:0>The number of bits that are changed. For example, when one bit is changed, transition detectors 710-1 to 710-n output one detection pulse. When two bits are changed, transition detectors 710-1 to 710-n output two detection pulses. When three bits are changed, transition detectors 710-1 to 710-n output three detection pulses, and so on.

[0047] exist Figure 7 In the example, the pulse generation circuit 520 includes a combiner 720, a pulse delay circuit 730, and a clock driver 740. The combiner 720 has inputs 722-1 to 722-n and an output 724. Each input of the combiner 720 is coupled to a detector output 714-1 to 714-n of a corresponding transition detector among the transition detectors 710-1 to 710-n. The pulse delay circuit 730 has an input 732 coupled to the output of the combiner 720 and an output 734. The clock driver 740 has an input 742 coupled to the output 734 of the pulse delay circuit 730 and an output 744 coupled to the clock inputs of the flip-flops 320-1 to 320-m.

[0048] In this example, combiner 720 is configured to receive one or more detection pulses from transition detectors 710-1 to 710-n, combine the one or more detection pulses to generate a synchronization pulse, and output the synchronization pulse at output 724. A single detection pulse (i.e., the digital control code delay_ctrl) is output by transition detectors 710-1 to 710-n. <n-1:0>In the case where only one bit in the signal is changed, combiner 720 will pass the detection pulse to output 734 as a synchronization pulse.

[0049] The pulse delay circuit 730 receives a synchronization pulse from the combiner 720 and delays the synchronization pulse to the delay of the pulse delay circuit 730. In this example, the delay setting transition detection circuit 510 of the pulse delay circuit 730 detects the digital control code delay_ctrl. <n-1:0>The delay between the time of at least one bit transition and the time when the synchronization pulse is input to the clock inputs of flip-flops 320-1 to 320-m. In some aspects, the delay of the pulse delay circuit 730 can be configured such that the arrival of the synchronization pulse at the clock inputs of flip-flops 320-1 to 320-m satisfies the setup time requirements of flip-flops 320-1 to 320-m. As used herein, "setup time" can refer to the minimum amount of time required for the update of the m control bits to stabilize at the signal inputs D of flip-flops 320-1 to 320-m before the synchronization pulse arrives at the clock inputs of flip-flops 320-1 to 320-m to synchronize the m control bits.

[0050] Clock driver 740 is configured to receive a synchronization pulse from pulse delay circuit 730 and use this synchronization pulse to drive the clock inputs of flip-flops 320-1 to 320-m. Clock driver 740 may also be referred to as a clock buffer or another term. In specific implementations where pulse delay circuit 730 has sufficient drive strength to drive the clock inputs of flip-flops 320-1 to 320-m, clock driver 740 may be omitted.

[0051] Figure 8 An exemplary specific implementation of transition detectors 710-1 to 710-n according to certain aspects is shown. In this example, each transition detector among transition detectors 710-1 to 710-n includes a corresponding XOR gate 810-1 to 810-n and a corresponding delay circuit 820-1 to 820-n. In each transition detector among transition detectors 710-1 to 710-n, the corresponding XOR gate 810-1 to 810-n has a first input terminal coupled to the corresponding detector input terminals 712-1 to 712-n, a second input terminal coupled to the corresponding detector output terminals 714-1 to 714-n. Additionally, in each transition detector among transition detectors 710-1 to 710-n, the corresponding delay circuit 820-1 to 820-n is coupled between the corresponding detector input terminals 712-1 to 712-n and the second input terminal of the corresponding XOR gate 810-1 to 810-n. It should be understood that the XOR gate can be implemented using a combination of logic gates.

[0052] In this example, each of the transition detectors 710-1 to 710-n is configured to output a detection pulse when a bit transition occurs at the corresponding detector input 712-1 to 712-n, wherein the pulse width of the detection pulse is approximately equal to the delay of the corresponding delay circuits 820-1 to 820-n. Therefore, the pulse width of the detection pulse for each of the transition detectors 710-1 to 710-n can be set by correspondingly setting the delay of the corresponding delay circuits 820-1 to 820-n. For example, the pulse width of the detection pulse for each of the transition detectors 710-1 to 710-n can be set to a pulse width that satisfies the hold time requirement of the flip-flops 320-1 to 320-m. As used herein, "hold time" can refer to the minimum amount of time required for an update of the m control bits to remain stable at the signal input D of the flip-flops 320-1 to 320-m after a synchronization pulse arrives at the clock input of the flip-flops 320-1 to 320-m to synchronize the m control bits.

[0053] Figure 9 An exemplary specific implementation of a combiner 720 according to certain aspects is shown. In this example, the combiner 720 includes an OR gate 910 having multiple inputs and one output. Each input of the OR gate 910 is coupled to the detector outputs 714-1 to 740-n of a corresponding transition detector 710-1 to 710-n, and the output of the OR gate 910 is coupled to the input 732 of a pulse delay circuit 730. In this example, the OR gate 910 combines one or more detection pulses from transition detectors 710-1 to 710-n by performing an OR function on one or more detection pulses. It should be understood that the OR gate 910 may be implemented using a network of multiple individual OR gates and / or other types of logic gates. In general, the OR gate 910 may be implemented using any suitable circuit configured to perform an OR function.

[0054] Figure 10A This is a timing diagram illustrating an example of pulse combination in a combiner 720 according to certain aspects. In this example, the digital control code delay_ctrl <n-1:0>The number of bits in the middle is 8 (i.e., n=8). Figure 10A Examples of the output signals of the transition detectors 710-1 to 710-8 (labeled "detector output 1" to "detector output 8") and the output signal of the combiner 720 are shown.

[0055] In this example, the numeric control code delay_ctrl <n-1:0>Updated, including the numeric control code delay_ctrl <n-1:0>Four of the eight bits are changed. In this example, the changes to the four bits cause the transition detectors 710-1, 710-3, 710-5, and 710-6 to output detection pulses 1010, 1015, 1020, and 1025, respectively. Detection pulses 1010, 1015, 1020, and 1025 overlap and have approximately the same pulse width (assuming that the delay circuits 820-1 to 820-8 in the transition detectors 710-1 to 710-8 have approximately the same delay). In this example, combiner 720 performs an OR function on the output signals of transition detectors 710-1 to 710-8, which combines (i.e., merges) the detection pulses 1010, 1015, 1020, and 1025 into a synchronization pulse 1030 from the output of combiner 720.

[0056] It should be understood that this disclosure is not limited to Figure 10A The example shown. For example, the numeric control code delay_ctrl <n-1:0>Other updates may include varying numbers of bit changes. Generally, when the numeric control code delay_ctrl... <n-1:0>When at least one bit is changed, the combiner 720 outputs a synchronization pulse.

[0057] Combiner 720 does not require the detection pulses to be perfectly aligned or have exactly the same pulse width in order to combine the detection pulses to generate a synchronization pulse. Combiner 720 can tolerate a certain amount of deviation between the detection pulses (i.e., misalignment) and / or a certain amount of mismatch in the detection pulse widths. Figure 10B An example of this situation is illustrated in the example, which shows that the detection pulses 1010, 1015, 1020, and 1025 are due to, for example, the digital control code delay_ctrl. <n-1:0>An example of misalignment due to deviation between corresponding bits. Additionally, in this example, detection pulse 1025 has a wider width than detection pulse 1010. This could be due to, for example... Figure 8 and Figure 9 The exemplary embodiment shown illustrates a mismatch between the delay circuit 820-1's delay for pulse 1010 and the delay circuit 820-6's delay for pulse 1025. In this example, even though there is a discrepancy between the detection pulses 1010, 1015, 1020, and 1025, the combiner 720 can still use the OR function to generate the synchronization pulse 1030 because the detection pulses 1010, 1015, 1020, and 1025 overlap.

[0058] like Figure 10B As shown in the example, combiner 720 can tolerate delay_ctrl due to numeric control codes. <n-1:0>The deviation between corresponding bits causes the deviation between detection pulses 1010, 1015, 1020, and 1025. This is because the combiner 720 can tolerate the digital control code delay_ctrl. <n-1:0>The deviation between the positions can therefore be omitted. Figure 3 The image shown is used for the digital control code delay_ctrl <n-1:0>The bits are de-skewed by flip-flops 310-1 to 310-n, which further reduces power consumption.

[0059] Figure 11 An exemplary embodiment of delay circuit 110 is shown, wherein delay circuit 110 includes: a coarse delay circuit 1110 for providing coarse delay adjustment to delay circuit 110; and a fine delay circuit 1120 for providing fine delay adjustment to delay circuit 110. In this example, coarse delay circuit 1110 and fine delay circuit 1120 are coupled in series between input terminal 112 and output terminal 114 of delay circuit 110. Therefore, in this example, the delay of delay circuit 110 is approximately equal to the sum of the delay of coarse delay circuit 1110 and the delay of fine delay circuit 1120.

[0060] In this example, the m control bits of the m delay control signals include the coarse control bit coarse_ctrl for programming the delay of the coarse delay circuit 1110. <k-1:0>and the fine control bit fine_ctrl used to program the delay of the fine delay circuit 1120 <j-1:0>Where m = k + j. Coarse control bit coarse_ctrl <k-1:0>The delay of the coarse delay circuit 1110 is programmed with a coarse delay step, and the fine control bit fine_ctrl is used. <j-1:0>The delay of the fine delay circuit 1120 is programmed with fine delay steps, where one fine delay step is smaller than a coarse delay step. For example, a coarse delay step may be an integer multiple of a fine delay step.

[0061] Coarse delay circuits and fine delay circuits are known in the art. A coarse delay circuit can be implemented, for example, using a network of logic gates (e.g., NAND gates), where the coarse control bit `coarse_ctrl` is used. <k-1:0>The corresponding logic gates are input to control the delay path of signals in a coarse delay circuit. For example, a fine delay circuit can be implemented using a series-coupled delay buffer, where the fine control bit is fine_ctrl. <j-1:0>The drive strength of the delay buffer is controlled. Therefore, the coarse delay circuit 1110 can be implemented using any suitable coarse delay circuit, and the fine delay circuit 1120 can be implemented using any suitable fine delay circuit that provides finer delay adjustment than the coarse delay circuit.

[0062] exist Figure 11 In the example, control circuit 120 outputs the coarse control bit coarse_ctrl via outputs 124-1 to 124-k. <k-1:0>And fine control bits fine_ctrl are output from output terminals 124-(k+1) to 124-m. <j-1:0>Additionally, the delay circuit 110 receives the coarse control bit coarse_ctrl via control inputs 116-1 to 116-k. <k-1:0>And it receives fine control bits fine_ctrl via control inputs 116-(k+1) to 116-m. <j-1:0>.

[0063] Figure 12 An exemplary specific implementation of the control circuit 120 is shown, wherein flip-flops 320-1 to 320-m include a coarse control bit coarse_ctrl for outputting the coarse control bit. <k-1:0>The first flip-flops 320-1 to 320-k and the fine_ctrl bit for output fine control <j-1:0>The second flip-flops 320-(k+1) to 320-m, where m = k+j. In this example, the signal input terminals D of the first flip-flops 320-1 to 320-k are coupled to the output terminals 334-1 to 334-k of the decoder 330, respectively, and the output terminals Q of the first flip-flops 320-1 to 320-k are coupled to the output terminals 124-1 to 124-k of the control circuit 120. Additionally, in this example, the signal input terminals D of the second flip-flops 320-(k+1) to 320-m are coupled to the output terminals 334-(k+1) to 334-m of the decoder 330, respectively, and the output terminals Q of the second flip-flops 320-(k+1) to 320-m are coupled to the output terminals 124-(k+1) to 124-m of the control circuit 120. As discussed above, the clock input terminals of the flip-flops 320-1 to 320-m are coupled to the pulse generation circuit 520.

[0064] In this example, decoder 330 is configured to use the numeric control code delay_ctrl <n-1:0>Convert to coarse control bit coarse_ctrl <k-1:0>and fine control bit fine_ctrl <j-1:0>The coarse control bit coarse_ctrl is output from terminals 334-1 to 334-k. <k-1:0>The output is sent to the first flip-flops 320-1 to 320-k, and the fine control bit fine_ctrl is transmitted via outputs 334-(k+1) to 334-m. <j-1:0>The output is fed to the second flip-flop 320-(k+1) to 320-m.

[0065] For the numeric control code delay_ctrl <n-1:0>This is an example of binary numeric code; decoder 330 can convert the numeric control code delay_ctrl. <n-1:0>The n bits are divided into a first group of bits and a second group of bits, where the order of the first group of bits is lower than the order of the second group of bits. In this example, the decoder 330 can convert the first group of bits into fine_ctrl bits to provide fine control. <j-1:0>The first thermometer code is converted, and the second set of bits is converted to provide coarse control bits (coarse_ctrl). <k-1:0>The second thermometer code.

[0066] For example, in one example, the numeric control code delay_ctrl <n-1:0>It can include 8 bits (i.e., n=8), where the first group of bits includes the numeric control code delay_ctrl. <n-1:0>The three least significant bits (LSBs), and the second group of bits includes the numeric control code delay_ctrl. <n-1:0>The remaining five higher-order bits. In this example, fine-tuning bits fine_ctrl are provided. <j-1:0>The first thermometer code may include eight bits (i.e., 2). 3 =8), and provides coarse control bit coarse_ctrl <k-1:0>The second thermometer code may include 32 bits (i.e., 2... 5 =32). However, it should be understood that this disclosure is not limited to this example. Generally speaking, the first group of bits may include the numeric control code delay_ctrl. <n-1:0>The set of bits consists of L LSBs, where L is an integer less than n, and the second set of bits may include the numeric control code delay_ctrl. <n-1:0>The remaining higher orders. In this example, decoder 330 may include methods for processing the numeric control code delay_ctrl. <n-1:0>The L LSBs are converted into the first binary to thermometer code by the first thermometer code decoder and the delay_ctrl code used to convert the digital control code. <n-1:0>The remaining high-order bits are converted into the second binary of the second thermometer code and then into the thermometer code decoder.

[0067] In the example discussed above, flip-flops 320-1 to 320-m are used to synchronize the control signal with a synchronization pulse from pulse generation circuit 520. However, it should be understood that control circuit 120 is not limited to flip-flops 320-1 to 320-m. More broadly, control circuit 120 may include samplers 1310-1 to 1310-m for synchronizing the control signal with a synchronization pulse from pulse generation circuit 520, such as... Figure 13 As shown. As used herein, a sampler refers to circuitry that can be configured to sample or capture data, such as a flip-flop, latch, etc. In this example, each of the samplers 1310-1 to 1310-m has a corresponding signal input 1312-1 to 1312-m coupled to a corresponding output of the decoder 330, corresponding outputs 1314-1 to 1314-m coupled to a corresponding output of the control circuit 120, and corresponding clock inputs 1316-1 to 1316-m coupled to the output of the pulse generation circuit 520.

[0068] In this example, each of the samplers 1310-1 to 1310-m is configured to receive a synchronization pulse from the pulse generation circuit 520 at the corresponding clock inputs 1316-1 to 1316-m. Each of the samplers 1310-1 to 1310-m is also configured to sample (i.e., capture) the bit value of a corresponding control signal at the corresponding signal inputs 1312-1 to 1312-m on the edge of the synchronization pulse, and output the sampled bit value at the corresponding outputs 1314-1 to 1314-m. Each of the samplers 1310-1 to 1310-m may hold the corresponding sampled bit value at the corresponding outputs 1314-1 to 1314-m until the next synchronization pulse from the pulse generation circuit 520. The edge of the synchronization pulse used for sampling can be a rising edge or a falling edge. Each of the samplers 1310-1 to 1310-m can be implemented using a flip-flop (e.g., a corresponding flip-flop in flip-flops 320-1 to 320-m) or any other suitable circuit configured to perform the functions described above. For an example where each of the samplers 1310-1 to 1310-m is implemented using a corresponding flip-flop in flip-flops 320-1 to 320-m, the corresponding signal inputs 1312-1 to 1312-m correspond to the corresponding signal inputs D of the corresponding flip-flops in flip-flops 320-1 to 320-m, the corresponding outputs 1314-1 to 1314-m correspond to the corresponding outputs Q of the corresponding flip-flops in flip-flops 320-1 to 320-m, and the corresponding clock inputs 1316-1 to 1316-m correspond to the clock inputs of the corresponding flip-flops in flip-flops 320-1 to 320-m.

[0069] In the example discussed above, control circuit 120 outputs a synchronized control signal to delay circuit 110 to program the delay of delay circuit 110. However, it should be understood that this disclosure is not limited to this example. More broadly, control circuit 120 can output a synchronized control signal to digital control circuit 1320, such as... Figure 13 As shown. In this example, the digital control circuit 1320 has control inputs 1322-1 to 1322-m, each of which is coupled to a corresponding output of the control circuit 120, 124-1 to 124-m, to receive a corresponding synchronized control signal in the synchronized control signals. In this example, the synchronized control signals program (i.e., control) the parameters of the digital control circuit 1320. For example, the digital control circuit 1320 may be a delay circuit (e.g., delay circuit 110), where the control signals program the delay of the delay circuit. In another example, the digital control circuit 1320 may be an oscillator, where the control signals program the output frequency of the oscillator. In yet another example, the digital control circuit 1320 may be a frequency divider, where the control signals program the divider's divider.

[0070] Figure 14 An exemplary method 1400 for synchronizing samplers is shown, according to certain aspects. The samplers may correspond to samplers 1310-1 to 1310-m. In some aspects, each of the samplers 1310-1 to 1310-m may be implemented using a corresponding trigger among triggers 320-1 to 320-m.

[0071] At box 1410, a numeric control code is received. For example, the numeric control code may correspond to the numeric control code delay_ctrl. <n-1:0>.

[0072] At box 1420, the digital control code is converted into a control signal. For example, decoder 330 can convert the digital control code into a control signal. The control signal may correspond to m control signals output from decoder 330 and may include the m control bits discussed above. In some aspects, the digital control code includes binary digital code, and converting the digital control code into a control signal includes converting the binary digital code into one or more thermometer codes.

[0073] At box 1430, each control signal in the control signals is input to the corresponding sampler among samplers 1310-1 to 1310-m. For example, each control signal in the control signals can be input to the signal input terminals 1312-1 to 1312-m of the corresponding sampler among samplers 1310-1 to 1310-m. In the example where each sampler among samplers 1310-1 to 1310-m is implemented using a corresponding flip-flop among flip-flops 320-1 to 320-m, each control signal in the control signals can be input to the input terminal D of the corresponding flip-flop among flip-flops 320-1 to 320-m.

[0074] At box 1440, at least one bit transition in the digital control code is detected. For example, transition detection circuit 510 can detect the digital control code delay_ctrl. <n-1:0>At least one bit transition in the process.

[0075] At block 1450, a synchronization pulse is generated in response to the detection of at least one bit transition in the digital control code. For example, pulse generation circuit 520 can generate a synchronization pulse.

[0076] At block 1460, a synchronization pulse is input to the clock input of the sampler. For example, the clock input may correspond to the clock inputs 1316-1 to 1316-m of samplers 1310-1 to 1310-m. In an example where each of the samplers 1310-1 to 1310-m is implemented using a corresponding flip-flop among flip-flops 320-1 to 320-m, the clock input may correspond to the clock input of flip-flops 320-1 to 320-m.

[0077] In some aspects, method 1400 may further include: outputting a control signal from the sampler to a delay circuit, wherein the delay circuit is configured to set a delay based on the control signal. For example, this delay circuit may correspond to delay circuit 110.

[0078] In some aspects, detecting at least one bit transition in a digital control code includes: detecting multiple bit transitions in the digital control code; and generating a corresponding detection pulse for each of the multiple bit transitions. For example, transition detectors 710-1 to 710-n may generate corresponding detection pulses. In some aspects, generating a synchronization pulse includes combining the corresponding detection pulses. For example, a combiner 720 may combine the corresponding detection pulses.

[0079] In some aspects, method 1400 further includes using a pulse delay circuit to delay the synchronization pulse by a delay to satisfy the setup time. For example, pulse delay circuit 730 can delay the synchronization pulse. In this example, the sampler can be implemented using flip-flops 320-1 to 320-m, and the setup time can correspond to the setup time of flip-flops 320-1 to 320-m.

[0080] Specific implementation examples are described in the following numbered clauses: 1. A system comprising: A decoder having an input and an output, wherein the decoder is configured to receive a digital control code at the input of the decoder, generate a control signal based on the digital control code, and output each of the control signals at a corresponding output of the output of the decoder; A sampler, wherein each sampler has a corresponding signal input, a corresponding clock input, and a corresponding output, the corresponding signal input being coupled to a corresponding output of the output of the decoder; A transition detection circuit, configured to detect at least one bit transition in the digital control code; and A pulse generation circuit coupled to the transition detection circuit and the corresponding clock input of the sampler, wherein the pulse generation circuit is configured to output a synchronization pulse to the corresponding clock input of the sampler when the transition detection circuit detects at least one bit transition in the digital control code.

[0081] 2. The system according to Clause 1, the system further comprising a delay circuit having a control input, wherein the respective output of each sampler in the samplers is coupled to a respective control input of the control input of the delay circuit, and the delay circuit is configured to set the delay of the delay circuit based on the control signal.

[0082] 3. The system according to Clause 1 or 2, wherein the transition detection circuit includes transition detectors, and wherein each transition detector has a corresponding detector input coupled to a corresponding input of the input of the decoder and a corresponding detector output coupled to the pulse generation circuit.

[0083] 4. The system according to Clause 3, wherein each of the transition detectors is configured to: Detecting the bit transition at the input of the corresponding detector; and When the bit transition at the input terminal of the corresponding detector is detected, a corresponding detection pulse is output at the output terminal of the corresponding detector.

[0084] 5. The system according to Clause 4, wherein the pulse generation circuit includes a combiner configured to receive the corresponding detection pulse from the transition detector and combine the corresponding detection pulse to generate the synchronization pulse.

[0085] 6. The system according to Clause 5, wherein the combiner includes an OR gate having an input and an output, and each of the inputs of the OR gate is coupled to the corresponding detector output of the corresponding transition detector in the transition detector.

[0086] 7. The system according to Clause 5 or 6, wherein the pulse generation circuit further includes a pulse delay circuit coupled between the combiner and the respective clock input of the sampler.

[0087] 8. The system according to Clause 7, wherein each sampler in the samplers includes a corresponding trigger, and the pulse delay circuit is configured to delay the synchronization pulse to a delay that satisfies the setup time of the trigger.

[0088] 9. The system according to Clause 7 or 8, wherein the pulse generation circuit further includes a clock driver coupled between the pulse delay circuit and the respective clock input of the sampler.

[0089] 10. The system according to any one of clauses 3 to 9, wherein each of the transition detectors comprises: A corresponding XOR gate, the corresponding XOR gate having a corresponding first input terminal coupled to the input terminal of the corresponding detector, a corresponding second input terminal, and a corresponding output terminal coupled to the output terminal of the corresponding detector; and A corresponding delay circuit is coupled between the input terminal of the corresponding detector and the corresponding second input terminal of the corresponding XOR gate.

[0090] 11. The system according to Clause 10, wherein the pulse generation circuit includes an OR gate having an input and an output, and each input of the OR gate is coupled to the corresponding detector output of the corresponding transition detector in the transition detector.

[0091] 12. The system according to Clause 11, wherein the pulse generation circuit further comprises a pulse delay circuit coupled between the output of the OR gate and the corresponding clock input of the sampler.

[0092] 13. The system according to Clause 12, wherein each sampler in the samplers includes a corresponding trigger, and the pulse delay circuit is configured to delay the synchronization pulse to a delay that satisfies the setup time of the trigger.

[0093] 14. The system according to clause 12 or 13, wherein the pulse generation circuit further includes a clock driver coupled between the pulse delay circuit and the respective clock input of the sampler.

[0094] 15. The system according to any one of Clauses 1 to 14, wherein the digital control code comprises binary digital code.

[0095] 16. The system according to Clause 15, wherein the decoder is configured to convert the binary digital code into one or more thermometer codes, and the control signal includes the one or more thermometer codes.

[0096] 17. The system according to any one of clauses 1 to 16, wherein each of the samplers includes a corresponding trigger.

[0097] 18. A method for synchronization using a sampler, the method comprising: Receive digital control codes; Convert the digital control code into a control signal; Each of the control signals is input to the corresponding sampler in the sampler; Detect at least one bit transition in the digital control code; A synchronization pulse is generated in response to detecting at least one bit transition in the digital control code; and The synchronization pulse is input to the clock input terminal of the sampler.

[0098] 19. The method according to Clause 18, wherein the digital control code comprises a binary digital code, and wherein converting the digital control code into the control signal comprises converting the binary digital code into one or more thermometer codes.

[0099] 20. The method according to clause 18 or 19, further comprising: outputting the control signal from the sampler to a delay circuit, wherein the delay circuit is configured to set a delay based on the control signal.

[0100] 21. The method according to any one of clauses 18 to 20, wherein detecting the at least one bit transition in the digital control code comprises: Detect multiple bit transitions in the digital control code; and A corresponding detection pulse is generated for each of the plurality of bit transitions.

[0101] 22. The method according to Clause 21, wherein generating the synchronization pulse includes combining the corresponding detection pulses.

[0102] 23. The method according to any one of clauses 18 to 23, wherein the sampler includes a trigger.

[0103] 24. The method according to Clause 23, further comprising: delaying the synchronization pulse to a delay that satisfies the setup time of the trigger.

[0104] 25. A system comprising: A decoder configured to receive digital control codes and convert the digital control codes into control signals; A transition detection circuit, configured to detect at least one bit transition in the digital control code; A pulse generation circuit, configured to output a synchronization pulse when the transition detection circuit detects at least one bit transition in the digital control code; and A sampler, wherein each sampler is configured to receive a corresponding control signal in the control signal, capture the bit value of the corresponding control signal in the control signal based on the synchronization pulse, and output the captured bit value of the corresponding control signal in the control signal.

[0105] 26. The system according to Clause 25, wherein each of the samplers is configured to capture the bit value of the corresponding control signal in the control signal on the rising edge of the synchronization pulse.

[0106] 27. The system according to Clause 25, wherein each of the samplers is configured to capture the bit value of the corresponding control signal in the control signal on the falling edge of the synchronization pulse.

[0107] 28. The system according to any one of clauses 25 to 27, the system further comprising a delay circuit having a control input, wherein each sampler in the samplers is configured to output a captured bit value of the corresponding control signal in the control signal to a corresponding control input of the delay circuit, and the delay circuit is configured to set a delay of the delay circuit based on the control signal.

[0108] 29. The system according to any one of clauses 25 to 28, wherein the at least one bit transition in the digital control code includes a plurality of bit transitions in the digital control code, the transition detection circuit is configured to output a corresponding detection pulse for each of the plurality of bit transitions in the digital control code, and the pulse generation circuit is configured to combine the corresponding detection pulses to generate the synchronization pulse.

[0109] 30. The system according to any one of clauses 25 to 29, wherein each sampler in the samplers includes a corresponding trigger.

[0110] 31. The system according to Clause 30, wherein the pulse generation circuit is configured to delay the synchronization pulse to a delay that satisfies the setup time of the trigger.

[0111] 32. The system according to any one of clauses 25 to 31, wherein the digital control code comprises a binary digital code, the decoder is configured to convert the binary digital code into one or more thermometer codes, and the control signal comprises the one or more thermometer codes.

[0112] Within this disclosure, the term "exemplary" is used to mean "serving as an example, instance, or illustration." Any specific implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term "aspect" does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term "coupling" is used herein to refer to direct or indirect electrical coupling between two structures. It should also be understood that the term "grounding" can refer to DC ground or AC ground, and therefore the term "grounding" encompasses both possibilities.

[0113] The use of designations such as "first" and "second" to refer to elements in this document generally does not limit the number or order of those elements. Rather, these designations are used here as a convenient way to distinguish two or more elements or instances of elements. Therefore, a reference to the first element and the second element does not imply that only two elements can be used, or that the first element must precede the second element.

[0114] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Thus, this disclosure is not intended to be limited to the examples described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A system comprising: A decoder having an input and an output, wherein the decoder is configured to receive a digital control code at the input of the decoder, generate a control signal based on the digital control code, and output each of the control signals at a corresponding output of the output of the decoder; A sampler, wherein each sampler has a corresponding signal input, a corresponding clock input, and a corresponding output, the corresponding signal input being coupled to a corresponding output of the output of the decoder; A transition detection circuit, configured to detect at least one bit transition in the digital control code; and A pulse generation circuit coupled to the transition detection circuit and the corresponding clock input of the sampler, wherein the pulse generation circuit is configured to output a synchronization pulse to the corresponding clock input of the sampler when the transition detection circuit detects at least one bit transition in the digital control code.

2. The system of claim 1, further comprising a delay circuit having a control input, wherein the respective output of each sampler in the samplers is coupled to a respective control input of the control input of the delay circuit, and the delay circuit is configured to set a delay based on the control signal.

3. The system of claim 1, wherein the transition detection circuit includes transition detectors, and wherein each transition detector has a corresponding detector input coupled to a corresponding input of the input of the decoder and a corresponding detector output coupled to the pulse generation circuit.

4. The system of claim 3, wherein each of the transition detectors is configured to: Detecting the bit transition at the input of the corresponding detector; and When the bit transition at the input terminal of the corresponding detector is detected, a corresponding detection pulse is output at the output terminal of the corresponding detector.

5. The system of claim 4, wherein the pulse generation circuit includes a combiner configured to receive the corresponding detection pulses of the transition detector and combine the corresponding detection pulses to generate the synchronization pulse.

6. The system of claim 5, wherein the combiner comprises an OR gate having an input and an output, and each of the inputs of the OR gate is coupled to the corresponding detector output of the corresponding transition detector in the transition detector.

7. The system of claim 5, wherein the pulse generation circuit further comprises a pulse delay circuit coupled between the combiner and the respective clock input of the sampler.

8. The system of claim 7, wherein each sampler in the samplers includes a corresponding trigger, and the pulse delay circuit is configured to delay the synchronization pulse to a delay that satisfies the setup time of the trigger.

9. The system of claim 7, wherein the pulse generation circuit further comprises a clock driver coupled between the pulse delay circuit and the corresponding clock input of the sampler.

10. The system of claim 3, wherein each of the transition detectors comprises: A corresponding XOR gate, the corresponding XOR gate having a corresponding first input terminal coupled to the input terminal of the corresponding detector, a corresponding second input terminal, and a corresponding output terminal coupled to the output terminal of the corresponding detector; and A corresponding delay circuit is coupled between the input terminal of the corresponding detector and the corresponding second input terminal of the corresponding XOR gate.

11. The system of claim 10, wherein the pulse generation circuit includes an OR gate having an input and an output, and each input of the OR gate is coupled to the corresponding detector output of the corresponding transition detector in the transition detector.

12. The system of claim 11, wherein the pulse generation circuit further comprises a pulse delay circuit coupled between the output of the OR gate and the corresponding clock input of the sampler.

13. The system of claim 12, wherein each sampler in the samplers includes a corresponding trigger, and the pulse delay circuit is configured to delay the synchronization pulse to a delay that satisfies the setup time of the trigger.

14. The system of claim 12, wherein the pulse generation circuit further comprises a clock driver coupled between the pulse delay circuit and the corresponding clock input of the sampler.

15. The system according to claim 1, wherein the digital control code comprises binary digital code.

16. The system of claim 15, wherein the decoder is configured to convert the binary digital code into one or more thermometer codes, and the control signal includes the one or more thermometer codes.

17. The system of claim 1, wherein each sampler in the samplers includes a corresponding trigger.

18. A method for synchronization using a sampler, the method comprising: Receive digital control codes; Convert the digital control code into a control signal; Each of the control signals is input to the corresponding sampler in the sampler; Detect at least one bit transition in the digital control code; A synchronization pulse is generated in response to detecting at least one bit transition in the digital control code; as well as The synchronization pulse is input to the clock input terminal of the sampler.

19. The method of claim 18, wherein the digital control code comprises a binary digital code, and wherein converting the digital control code into the control signal comprises converting the binary digital code into one or more thermometer codes.

20. The method according to claim 18, further comprising: The control signal from the sampler is output to a delay circuit, wherein the delay circuit is configured to set its delay based on the control signal.

21. The method of claim 18, wherein detecting the at least one bit transition in the digital control code comprises: Detect multiple bit transitions in the digital control code; as well as A corresponding detection pulse is generated for each of the plurality of bit transitions.

22. The method of claim 21, wherein generating the synchronization pulse comprises combining the corresponding detection pulses.

23. The method of claim 18, wherein the sampler comprises a trigger.

24. The method according to claim 23, further comprising: The synchronization pulse is delayed to a delay that satisfies the setup time of the trigger.

25. A system comprising: A decoder configured to receive digital control codes and convert the digital control codes into control signals; A transition detection circuit, configured to detect at least one bit transition in the digital control code; A pulse generation circuit is configured to output a synchronization pulse when the transition detection circuit detects at least one bit transition in the digital control code. and A sampler, wherein each sampler is configured to receive a corresponding control signal in the control signal, capture the bit value of the corresponding control signal in the control signal based on the synchronization pulse, and output the captured bit value of the corresponding control signal in the control signal.

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