Circuit arrangement with transistor-based switches and method for switching transistor-based switches

Abstract

A circuit arrangement is proposed, having an input contact (in) switchably connected to an output contact (out) via two series-connected transistors (T1, T2). Each of the two transistors has a source contact connected to each other, and each of the two transistors has a gate contact connected to each other. The source and gate contacts of the two transistors are connected to at least one current source (I) that is both on and off. The current source is configured to generate source / gate voltages (Vgs_1,2) at the two transistors that are greater than their respective threshold voltages. Furthermore, the source and gate contacts of the two transistors can be connected to circuit units (T4, T5, D5) configured to equalize the gate and source voltages of the two transistors once the current source is disconnected from their respective source and gate contacts. A method for switching transistor-based switches is also proposed. The current source is connected to the high voltage supply voltage (HV) and can be connected via the ON / OFF switch function unit (SE) to the series-connected function unit (T_D1) that causes a voltage drop and to the source-drain path of the third transistor (T3), which is connected to the low voltage supply voltage (LV). The gate contacts of the two transistors are connected to the current source (I) via the ON / OFF switch function unit (SE), and the source contacts of the two transistors are connected to the gate contacts of the third transistor (T3).

Description

Technical Field

[0001] This invention relates to a circuit arrangement having input contacts that are switchably connected to output contacts via two series-connected transistors. Each source contact of one transistor is connected to the other, and each gate contact of one transistor is connected to the other. The source and gate contacts of the two transistors are connected to at least one current source configured to generate source / gate voltages at the two transistors that are greater than their respective threshold voltages. Furthermore, a method for switching the transistor-based switch is described. Background Technology

[0002] Switches with two switching states, such as "closed" and "open" or "on" and "off," are among the most important components in a circuit. In integrated circuits, semiconductor elements are mostly used as switches in the form of transistors, which can implement bidirectional switching functions for current in different circuit configurations, such as as transmission gates. The quality of such components depends particularly on their characteristic of not conducting current in the "off" switching state.

[0003] The "off" switching state is characterized by a semiconductor region in the semiconductor element being reverse-biased; however, a weak current still flows in the reverse direction in that semiconductor region, which is called leakage current. Especially in power semiconductors, such as high-voltage CMOS devices, leakage current can be generated by a variety of reasons, and its intensity increases with increasing temperature.

[0004] Depending on the application of such switches, the significant relevance of leakage current needs to be assessed. In this case, a particularly preferred application area involves implantable electronic devices that treat various types of neurological dysfunctions by stimulating nerves with electrical charges. These implants are based on multifunctional, highly integrated circuits designed with principles of maximum operational safety, maximum energy efficiency, and maximum possible miniaturization. Leakage current flowing through electrodes in contact with biological tissue areas is unacceptable, especially when performing in vivo electrical stimulation of specific body regions, such as nerve fibers. Therefore, leakage current can continuously lead to charge buildup on the electrodes, which must be avoided.

[0005] Document US 4,595,847 A discloses a bidirectional analog high-voltage switch implemented using a pair of depletion-mode MOS transistors, whose source contacts are connected to each other and whose gate contacts are connected to each other. The drain contacts form the high-voltage input connection and the high-voltage output connection. However, leakage current may still flow through a diode connected to the source contacts in reverse.

[0006] Document US 10 517 570 B2 discloses a switching circuit for operating an ultrasonic transducer, in which the switching transistors are shorted in an off-switch state by shorting the gate and source contacts of two switching transistors via the source-drain path of another transistor. In this known switching circuit, leakage current that may occur between the switching transistors in the off-switch state cannot be ruled out due to the electrical connection path between the source contacts of the switching transistors and the supply voltage Vdd. Summary of the Invention

[0007] The objective of this invention is to provide a circuit arrangement having an input contact that is switchably connected to an output contact via two series-connected transistors, wherein a source contact of each of the two transistors is connected to each other, a gate contact of each of the two transistors is connected to each other, and the source and gate contacts of the two transistors are connectably and disconnectably connected to at least one current source configured to generate a source / gate voltage at each transistor greater than its respective associated threshold voltage, wherein the source and gate contacts of the two transistors are also connectable to a circuit unit configured to balance the gate and source voltages of the two transistors once the current source is disconnected from the source and gate contacts of the two transistors. The circuit arrangement is further extended such that no leakage current or only a negligible small leakage current is formed inside the switching arrangement when it is in an "off" state, i.e., the transistors involved in the switching process are turned off. In this case, the resistor R of the transistors involved in the switching process can be... off It should be as large as possible. In addition, it should significantly improve operational safety, energy efficiency, and miniaturization compared to similar circuit arrangements achieved to date.

[0008] The solution to the task upon which this invention is based is described in claim 1. Claim 19 describes a method for switching transistor-based switches according to the solution of this invention. Advantageous further developments of the inventive concept can be derived from the dependent claims and the following description, especially in conjunction with the accompanying drawings.

[0009] The circuit arrangement according to the solution of the present invention, having the features of the preamble of claim 1, is characterized in that the current source is connected to a high-voltage supply voltage and is connected via an ON / OFF switching unit to a series-connected functional unit causing a voltage drop and to the source-drain path of a third transistor, the source-drain path of which is connected to a low-voltage supply voltage. Furthermore, the gate contacts of the two transistors are connected to the current source via the ON / OFF switching unit, and the source contacts of the two transistors are connected to the gate contact of the third transistor.

[0010] Because the two transistors are connected to the rest of the circuit arrangement only via high-impedance paths, such as through their gate contacts—that is, on the one hand, the two transistors are connected to the ON / OFF switching unit via their respective gate contacts, and on the other hand, the source contacts of the two transistors are connected to the gate contact of the third transistor—the two transistors are decoupled from both the high-voltage and low-voltage supply voltages in the OFF switching state. In other words, they are connected via very high-impedance current paths, so the current flowing between the two transistors originates solely or almost solely from the potential existing between the input and output contacts. Therefore, the circuit arrangement has no effect on the two transistors in the OFF switching state, and also in the ON switching state.

[0011] This new switching scheme is particularly useful for realizing high-voltage robust CMOS switches with negligible leakage current, preferably using SOI technology. It is based on active control or regulation of the turn-on and turn-off processes of two transistors that are fundamentally responsible for the switching function and are connected in series between the input and output contacts. Furthermore, it combines several advantages over similar switches known to date: The leakage current that may occur in the off state is only a few picoamperes or even less.

[0012] Because both switching on and off are performed actively, the switching process can be executed reversibly in a deterministic manner and can be executed very quickly, for example, within 10 µs or even less.

[0013] Since at least the two transistors responsible for the switching function are preferably constructed as NMOS transistors, they form a very small resistance in the on state, i.e., the "on" state.

[0014] To achieve the circuit layout, only a small number of space-saving components are required, and these components also have low current consumption or low self-power loss.

[0015] The circuit arrangement is suitable for a wide voltage range, which is determined primarily by selecting the two transistors connected to the circuit unit. Therefore, switching voltages of 200 V and higher can be achieved by appropriately selecting the HV transistor.

[0016] Starting with two transistors connected in series via their source contacts, preferably configured as NMOS transistors, whose drain contacts form both input and output contacts, the transistors connect the input and output contacts as needed (i.e., in an "on" state) or disconnect them (i.e., in an "off" state). The two transistors are driven by current control, independent of the voltage domain applied at the input and output contacts, or the voltage domain applied as operating potentials HV and LV at the circuit unit. Therefore, the source and gate contacts of the two transistors can be connected to at least one current source that is configured to generate source / gate voltages at the two transistors, which are greater than their respective threshold voltages. This current can generate a voltage swing between the gate and source contacts of the two transistors, allowing a low-resistance connection between the input and output contacts, such as R. on =100 Ohm, thus turning the switch to the "on" state.

[0017] For the controlled turn-on process, the current source is connected to the high-voltage supply voltage and, via an ON / OFF switch unit, to a series-connected voltage-dropping functional unit and to the source-drain path of a third transistor. The voltage-dropping functional unit is preferably configured as a diode or similar element. The source-drain path of the third transistor is connected to the low-voltage supply voltage. The gate contacts of the two transistors are connected to the current source via the ON / OFF switch unit, while the source contacts of the two transistors are connected only to the gate contact of the third transistor. This current path can be referred to as the turn-on current path.

[0018] This method ensures that the source contacts of the two transistors are each connected to a high-impedance current path, so that the current appearing inside the circuit unit will not interfere with the signal current applied between the input and output contacts.

[0019] Without additional circuitry, turning off the current source would cause the two transistors to passively discharge due to the parasitic capacitance in the current path and uncontrollably transition to a high-impedance state corresponding to the "off" state. This circuit effectively avoids leakage current, especially since the two transistors responsible for the switching function are connected to the drive device only through their gate contacts—partly through the gate contacts of the two transistors themselves, and partly through the gate contact of a third transistor connected to the source contacts of the two transistors—thus preventing the formation of a leakage current path.

[0020] To expedite and controllably execute the turn-off process, a separate circuit unit is provided. This unit is connected to the source and gate contacts of two transistors and is configured such that disconnecting a large current source from the source and gate contacts of the two transistors balances the gate and source voltages of each transistor. Therefore, the circuit unit is selected to avoid leakage current while keeping the logic levels used to drive the digital circuit components contained within the unit in a low-voltage range.

[0021] In a first design of the circuit unit, a fourth transistor is provided. The source-drain path of the fourth transistor is connected in parallel with the gate and source contacts of the two transistors, and the gate contact of the fourth transistor is connected to the current source in a way that allows it to be turned on and off. The fourth transistor forms a turn-off current path and is connected to the current source via an ON / OFF switch unit, as is the aforementioned turn-on current path. In the turn-off state, the turn-on current path is disconnected from the current source, while the turn-off current path is connected to the current source. In this way, only one current source is needed to activate both current paths, which operate uniformly using a low-voltage range, typically 1.8 V, control signal.

[0022] Once the turn-off current path is connected to the current source, the gate / source voltage required to turn on the fourth transistor is applied to it. This causes the fourth transistor to become low-resistance and balances the voltage between the gate and source contacts of the two transistors responsible for the switching function. This puts the two transistors into a high-resistance state, or "off" state, in which an ohmic resistance greater than 1 GΩ can be formed between the input and output contacts. off .

[0023] Various other design approaches can be envisioned for driving the fourth transistor and for the configuration of the circuit unit that forms the turn-off current path, which will be described below with reference to the accompanying drawings.

[0024] The circuit arrangement according to the solution of the present invention is based on a novel switching method, characterized in that the source contacts and gate contacts of two transistors are respectively connected to the circuit unit via a current-free connection, thereby enabling the two transistors to switch to the off state without leakage current. This is achieved through high-resistance current paths between the source contacts and gate contacts of the two transistors and the circuit unit, respectively, the high-resistance current paths contacting the gate contacts.

[0025] Furthermore, the circuit unit connected to the source and gate contacts of the two transistors can form a floating potential difference dV = V1 - V2, which is applied by the circuit unit between the source and gate contacts of the two transistors, wherein there is a potential V2 at the source contact and a potential V1 at the gate contact.

[0026] The floating potential difference formed between the source and gate contacts of the two transistors is preferably a low-voltage difference, i.e., less than 3 V, and is independent of the high-voltage and low-voltage supply voltages applied to the circuit unit, which can be in the range of ±60 V to ±200 V or higher, depending on the circuit technology employed. This allows the circuit unit to be implemented using low-voltage transistors, thereby enabling the circuit unit to be constructed in an optimized miniaturized form. Attached Figure Description

[0027] The invention will now be described by way of example with reference to the accompanying drawings and an embodiment, without limiting the overall inventive concept. In the drawings: Figure 1 The circuit topology shown has an on-current path and an off-current path that can be actively switched on and off. Figure 2 The circuit topology is shown as described above, but the turn-off current path is an NMOS and PMOS source follower circuit. Figure 3 As shown Figure 1 The circuit topology is the same, but the turn-off current path has a source follower; Figure 4 As shown Figure 1 of Figure 1 However, the shutdown control device has a latch; Figure 5 As shown Figure 1 of Figure 1 However, the shutdown control device has a current mirror; and Figure 6 A general circuit topology is shown for illustrating the method principle of the solution according to the present invention. Detailed Implementation

[0028] Figure 1 A circuit arrangement is shown, having an input contact "in" and an output contact "out," which requires controlled connection ("on") and controlled disconnection ("off") states. For example, it can be assumed that the output contact is connected to an implantable electrode that is in direct contact with an organic structure in the body, such as a bundle of nerve fibers, to electrically stimulate that structure.

[0029] To achieve the switching process between "on" and "off" states, as well as in reverse, two transistors T1 and T2 are arranged in series between the input contact "in" and the output contact "out". The source contacts of each transistor T1 and T2 are connected to each other, and their gate contacts are also connected to each other. Furthermore, each transistor T1 and T2 has a substrate connection terminal (Bulk) connected to the source contact of each transistor T1 and T2. The two transistors T1 and T2 are preferably constructed as high-voltage NMOS transistors.

[0030] To switch transistors T1 and T2 to the "on" state, the circuit arrangement includes a current path Ion, which has a current source I connected to the high-voltage supply voltage HV. This current source I is connected via an ON / OFF switching unit SE to a diode that causes a voltage drop, and to the source-drain path of a third transistor T3. The diode is a diode-connected transistor T_D1. The source-drain path of the third transistor T3 is itself connected to the low-voltage supply voltage LV. A control signal Vctrl controls the ON / OFF switching unit SE to switch between two specific switching states: "on" and "off". Furthermore, the gate contacts of transistors T1 and T2 are connected to the current source I via the ON / OFF switching unit SE, while the source contacts of transistors T1 and T2 are connected to the gate contact of the third transistor T3. The gate contact of the diode-connected transistor T_D1 is connected to the ON / OFF switching unit SE, and therefore is directly connected to the current source I in the "on" state. Because only the gate contacts of two transistors, T1 and T2, are connected to all other components of the circuit arrangement, leakage current can be avoided, especially in the "off" state.

[0031] Once the ON / OFF switch function unit SE is connected to the on current path Ion, such as Figure 1As shown, for example, a current Ion of 20 nA flows through the diode-connected transistor T_D1 and the third transistor T3, which is constructed as a PMOS transistor. Consequently, the gate-source voltages corresponding to these transistors rise above their respective threshold voltages. Due to the voltage drop generated at the diode-connected transistor T_D1 and the third transistor T3, a floating potential difference dV = V1 - V2 is formed between the gate and source contacts of the two transistors T1 and T2. This causes the two transistors T1 and T2 to become conductive, i.e., to achieve the "on" state of a switch, with a small transition resistance Ron of, for example, about 100 Ω.

[0032] To actively and controllably switch transistors T1 and T2 to the "off" state, the circuit arrangement includes a turn-off current path Ioff. A fourth transistor T4 is positioned along this path, with its source-drain path connected in parallel with the gate and source contacts of transistors T1 and T2. The fourth transistor T4 is driven such that, in the "on" state of the circuit arrangement, as previously described, it is not conducting and forms a large resistance. In the "off" state, the fourth transistor T4 becomes conductive, shorting the gate and source contacts of transistors T1 and T2 together, i.e., V1 = V2. Thus, transistors T1 and T2 together present a high-resistance transition resistance Roff greater than 1 GΩ between their input and output contacts.

[0033] To drive the fourth transistor T4, a fifth transistor T5 is connected in the turn-off current path Ioff. The source-drain path of the fifth transistor T5 is connected to the current source I via the ON / OFF switch unit SE, and also to the low-voltage supply voltage LV. Furthermore, the gate contact of the fifth transistor T5 is connected to the source contacts of the two transistors T1 and T2, as well as the source contact of the fourth transistor T4. The gate contact of the fourth transistor T4 is connected to the current source I via the ON / OFF switch unit SE.

[0034] By creating a voltage difference Vgs_5 at the fifth transistor T5 in the "off" state of the circuit arrangement (this voltage difference is also applied to the gate of the fourth transistor T4), the fourth transistor T4 is turned on, thereby generating the aforementioned short-circuiting effect on the two transistors T1 and T2. That is, the voltage potential V1 applied at the gate contact point of the two transistors T1 and T2 is actively pulled to the voltage potential V2, i.e., dV=0 V.

[0035] The diodes D2, D3, D4, and D5, additionally arranged in the circuit arrangement, are primarily used for the protection and operational safety of the individual transistors T3, T4, and T5, for example, ensuring that locally formed potentials do not reverse. Diode D5 also supports the fifth transistor T5 to enter a no-current state during the switching process from "off" to "on" by connecting the gate contact of the fifth transistor T5 to its source contact.

[0036] Figure 2 An alternative circuit layout with a turn-off current path Ioff is shown. In addition to the turn-off current path Ioff, Figure 2 The circuit layout shown is otherwise similar to Figure 1 The circuit layout shown is corresponding, therefore, to avoid repetition, components unrelated to the turn-off current path Ioff will not be described again.

[0037] A circuit unit is arranged along the turn-off current path Ioff, which includes two transistors T6 and T7 connected to the current source I via the ON / OFF switching function unit SE. The two transistors T6 and T7 are connected in the form of NMOS and PMOS source follower circuits, and are configured such that the circuit unit generates a voltage potential V1 applied to the gate contact of the two transistors T1 and T2 when connected to the current source I, which corresponds to the voltage potential V2 applied to the source contact of the two transistors T1 and T2.

[0038] Here, the source-drain path of PMOS transistor T6 is connected to current source I via the ON / OFF switching unit SE, while its gate contact is connected to the source contacts of transistors T1 and T2. The source-drain path of NMOS transistor T7 is connected to the high-voltage supply voltage HV on one hand, and to the gate contacts of transistors T1 and T2 on the other. Furthermore, the gate contact of transistor T7 is connected to current source I via the ON / OFF switching unit SE. The source-drain paths of transistors T6 and T7 are also connected to the low-voltage supply voltage LV via two additional transistors T8 and T9, which are connected as current mirrors. These current mirrors T8 / T9 constitute a current trap.

[0039] When PMOS transistor T6 is powered on, it establishes a gate-source voltage Vgs_6. Simultaneously, NMOS transistor T7 is turned on, its source-drain path connected between a high-voltage potential HV and a low-voltage potential present at current mirrors T8 / T9, and its gate contact connected to current source I (20 nA) via the ON / OFF switching unit SE. The gate voltage of NMOS transistor T7 is boosted to a value V2 + Vgs_6, defining voltage V1, as this voltage corresponds to the source voltage of T7. Ideally, transistors T6 and T7 are coordinated such that their gate-source voltages Vgs_6 and Vgs_7 are equal, i.e., V1 = V2 + Vgs_6 - Vgs_7 and therefore V1 = V2.

[0040] Figure 3 An alternative design for a turn-off current path is shown, the turn-off current path having two current path branches Ioff1 and Ioff2. In addition to the turn-off current path branches Ioff1 and Ioff2, Figure 3 The circuit layout shown is otherwise similar to Figure 1 The circuit layout shown is corresponding, therefore, to avoid repetition, components not included in the turn-off current paths Ioff1 and Ioff2 will not be described again.

[0041] The circuit unit is provided with a fourth transistor T4 along the current-off path branches Ioff1 and Ioff2. The fourth transistor T4 is connected to the third transistor T3 and the gate contacts of the two transistors T1 and T2 in such a way that the voltage potential V2 applied to the source contacts of the two transistors T1 and T2 and the voltage potential V1 applied to the gate contacts of the two transistors T1 and T2 are at least affected by the fourth transistor T4 in such a way that the two voltage potentials V1 and V2 are opposite to each other.

[0042] Therefore, the fourth transistor T4 has the opposite doping type to the third transistor T3. Figure 3 In this configuration, the third transistor T3 is a PMOS transistor, while the fourth transistor T4 is an NMOS transistor. The source-drain path of the fourth transistor T4 is connected to both a high-voltage supply voltage HV and a low-voltage supply voltage LV, which forms a current trap Is and creates a turn-off current path branch Ioff2. Furthermore, the gate contact of the fourth transistor T4 is connected to the current source I and the source-drain path of the third transistor T3 via the ON / OFF switching unit SE.

[0043] Unlike the aforementioned embodiments, in Figure 3In the circuit arrangement shown, current flows through the third transistor T3 in both the "on" and "off" states. In the "off" state, this current causes the third transistor T3 to establish a gate-source voltage Vgs_3. The fourth transistor T4 is configured in coordination with the third transistor T3 such that it establishes a gate-source voltage Vgs_4 corresponding to Vgs_3, thereby generating a control voltage V1 applied to its gate contact. For this control voltage V1, the formula is: V1 = V2 + Vgs_3 - Vgs_4. In this way, ideally, the same voltage, V1 = V2, is applied at the gate contact and source contact of both transistors T1 and T2, resulting in dV = 0.

[0044] Figure 4 A circuit arrangement is shown in which the source-drain path of the third transistor T3 is always connected to the current source I1 and the low-voltage supply voltage LV, regardless of the switching state of the ON / OFF switching functional unit SE. The functional unit that causes the voltage drop and is connected in series with the third transistor T3 is constructed in the form of two diodes connected in parallel, D1 and D1′.

[0045] Diode arrangements D1 and D1' each have two series-connected transistors T_D1 and T10, and T_D1' and T10', where T_D1 and T_D1' are connected as diodes. This diode arrangement is primarily used to generate a voltage drop. Transistors T_D1 and T_D1' have the same doping type, in this case, NMOS, and their source-drain paths are respectively connected to the source-drain path of a third transistor T3. Transistors T10 and T10' also have the same doping type, in this case, PMOS, but with a different doping type than transistors T_D1 and T_D1'. The source contact of transistor T10 is permanently connected to the gate contacts of the first and second transistors T1 and T2. The source contact of another transistor T10' and the gate contact of transistor T_D1' are switchably connected to the current source I1 via an ON / OFF switching unit SE. Conversely, the gate contact of transistor T_D1 is permanently connected to the gate contacts of the first and second transistors T1 and T2.

[0046] The circuit unit that realizes the current-cut-off path has two fourth transistors T4 and T4' connected as latches. Their gate contacts are connected to the drain contacts of the corresponding fourth transistors T4 and T4' via contacts K and K', respectively. The source contacts of the two fourth transistors T4 and T4' are connected to the source contacts of the first and second transistors T1 and T2, respectively.

[0047] Furthermore, the gate contact of transistor T_D1 is connected to the drain contact of the fourth transistor T4, while the gate contact of transistor T_D1′ is connected to the drain contact of another fourth transistor T4′.

[0048] like Figure 4 As shown, in the "on" state of the circuit arrangement, current flows through diode arrangement D1 and third transistor T3. This current causes voltage Vgs_1,2 to be formed at the gate contact and source contact of the two transistors T1 and T2, and turns on the two transistors T1 and T2, that is, switches to the "on" state.

[0049] Since the voltage potential V1 at the gate contact of transistors T1 and T2 is greater than V2 and the voltage potential Voff is less than V1 in the "on" state of the circuit arrangement, transistor T10' is turned off, thereby preventing current from flowing from V1 to V2 via another fourth transistor T4' and T_D1'. Furthermore, the other fourth transistor T4' is in a conducting state (low resistance) due to the control voltage V1 applied to it, which pulls voltage Voff towards V2, thus fully turning on transistor T10 (low resistance), while transistors T10', T_D1, and T4 are turned off (high resistance).

[0050] In the "off" state of the circuit arrangement, current I1 flows through diode arrangement D1′ and third transistor T3. This current causes the gate contacts of two transistors T1 and T2 to be shorted with V2, i.e., V1=V2. As a result, transistors T1 and T2 are high-impedance, i.e., switched to the "off" state.

[0051] The current I1 flowing through diode arrangement D1′ causes voltage Voff to be higher than the threshold voltage V of transistors T10′ and T_D1′. th The voltage Voff is also greater than Von, thereby turning on the diode arrangement D1′ and the third transistor T3. A similar voltage Voff exists at contact point K′, which turns on the fourth transistor T4 and makes V1 = V2, while the other fourth transistor T4′ is turned off.

[0052] Figure 4 One of the advantages of the circuit arrangement shown is that transistors T4, T4′, T_D1, T_D1′, T10, and T10′ are constructed as low-voltage transistors, which is related to the small area requirement of these transistors.

[0053] Figure 5 A circuit arrangement with a current-carrying path is shown, wherein the current-carrying path is... Figures 1 to 3The circuit layout corresponds to the on-current path, that is, the third transistor T3, which is connected in series with diode T_D1, is connected to the gate contact and source contact of the two transistors T1 and T2, so that the two transistors T1 and T2 are turned on in the "on" state. In the "on" switching state, current source I1 provides current along the on-current path, and due to inverter Inv, current sources I2 and I3 are in a no-current state.

[0054] To achieve the current-switching effect, a fourth transistor T4 is provided. The source-drain path of the fourth transistor T4 is connected in parallel with the gate and source contacts of the two transistors T1 and T2, and is connected to another fourth transistor T4' as a current mirror. The gate contacts of the fourth transistor T4 and the other fourth transistor T4' are connected to each other, and the source-drain path of the other fourth transistor T4' is connected to another current source I2 on one hand and to a current sink on the other. In the illustrated embodiment, the current sink is constructed as a current mirror formed by transistors T11 and T11'. Furthermore, the other fourth transistor T4' is connected in a diode manner, meaning its gate contact is connected to its source-drain path, ensuring that no current flows through T4' in the "on" state.

[0055] Transistors T4 and T4′ connected as current mirrors form a floating current mirror because their source and drain voltages vary with the potentials of V1 and V2 and are not fixed in any other way.

[0056] To control the two fourth transistors T4 and T4', a fifth transistor T5 is provided. The source-drain path of the fifth transistor T5 is connected to the gate contacts of the first and second transistors T1 and T2, as well as the gate contacts of the two fourth transistors T4 and T4', which are connected as current mirrors. Furthermore, the gate contact of the fifth transistor T5 is connected to the source contacts of the two transistors T1 and T2.

[0057] In the "off" state, current source I1 is turned off, while current sources I2 and I3 are turned on. The source contact of transistor T4', which acts as a diode, shares a potential V1 with the source contact of the fourth transistor T4. This means it is connected to the gate contacts of transistors T1 and T2, and also to current sinks T11 and T11'. Transistor T4' is turned on via the common gate connection between T4 and T4', thereby achieving potential balance between V1 and V2, i.e., dV = 0. In this situation, the fifth transistor T5 becomes high-resistance.

[0058] Figure 6A circuit topology is illustrated, which is used to explain the switching method concept based on the solution of the present invention upon which all the aforementioned circuit topologies are based. The source and gate contacts of two transistors T1 and T2 are respectively connected to circuit unit S via a current-free connection path OA. Circuit unit S is otherwise connected between a high-voltage supply voltage HV and a low-voltage supply voltage LV. The high-voltage supply voltage HV is connected to circuit unit S via an ON / OFF switching function unit SE, which can be turned on and off. Whether the switching function unit SE is in the ON or OFF state, no current flows through the connection path OA between circuit unit S and the two transistors T1 and T2.

[0059] Circuit unit S can create a floating potential difference dV = V1 - V2 between connection path 0A connecting the gate contacts of two transistors T1 and T2 and connection path 0A connecting the source contacts of two transistors T1 and T2. Here, potential V2 exists at the source contacts of two transistors T1 and T2, while potential V1 exists at the gate contacts of two transistors T1 and T2. The floating potential dV varies to match the potential V2 at the source contacts of two transistors T1 and T2. In the ON state of the switching function unit SE, V1 is always greater than V2; in the OFF state of the switching function unit SE, V1 = V2.

[0060] The floating potential difference dV formed between the source and gate contacts of the two transistors T1 and T2 is preferably a low-voltage potential difference, i.e., preferably less than 3V, and this is independent of the high-voltage supply voltage HV and the low-voltage supply voltage LV applied to the circuit unit S. This allows the circuit unit S to be implemented using low-voltage transistors, thereby enabling the circuit unit S to be optimally constructed in a miniaturized form, i.e., with small area requirements.

[0061] List of reference numerals

Claims

1. A circuit arrangement having an input contact (in) that is switchably connected to an output contact (out) via two transistors (T1, T2) connected in series, wherein, Each of the two transistors (T1, T2) has a source contact connected to each other, and each of the two transistors (T1, T2) has a gate contact connected to each other. The source and gate contacts of the two transistors (T1, T2) are connected to at least one current source (I) that is operable to turn on and off. The current source (I) is configured to generate source / gate voltages at the two transistors (T1, T2) that are greater than their respective threshold voltages (V). th In this circuit, the source and gate contacts of two transistors (T1, T2) are connectable to a circuit unit configured to: balance the gate and source voltages of the two transistors (T1, T2) once the current source (I) is disconnected from the source and gate contacts of the two transistors (T1, T2), characterized in that... The current source (I) is connected to the high-voltage supply voltage (HV) and, via an ON / OFF switching function unit, can be connected in series with a function unit that causes a voltage drop and to the source-drain path of the third transistor (T3), whose source-drain path is connected to the low-voltage supply voltage (LV); and The gate contacts of the two transistors (T1, T2) are connected to the current source (I) via the ON / OFF switching function unit, and the source contacts of the two transistors (T1, T2) are connected to the gate contact of the third transistor (T3).

2. The circuit arrangement according to claim 1, characterized in that, The functional unit has at least one of the following elements: resistor, diode, transistor with substrate connection terminal, latch.

3. The circuit arrangement according to claim 1 or 2, characterized in that, The circuit unit has a fourth transistor (T4), the source-drain path of which is connected in parallel with the gate contact and source contact of the two transistors (T1, T2), and the gate contact of the fourth transistor (T4) is connected to the current source (I) via the ON / OFF switch function unit.

4. The circuit arrangement according to claim 3, characterized in that, The circuit unit has a fifth transistor (T5), whose source-drain path is connected to the current source (I) via the ON / OFF switch function unit and to the low-voltage supply voltage (LV) on the other hand. The gate contact of the fifth transistor (T5) is connected to the source contact of the two transistors (T1, T2) and the source contact of the fourth transistor (T4).

5. The circuit arrangement according to claim 4, characterized in that, A diode is connected between the gate contacts of the fourth transistor (T4) and the fifth transistor (T5).

6. The circuit arrangement according to claim 1 or 2, characterized in that, The circuit unit is connected to the current source (I) via the ON / OFF switch function unit and has two additional transistors (T6, T7), which are connected to each other in the form of NMOS and PMOS source follower circuits and are appropriately constructed such that the circuit unit, when connected to the current source (I), generates a voltage potential (V2) applied to the source contacts of the two transistors (T1, T2), which corresponds to the voltage potential (V1) applied to the gate contacts of the two transistors (T1, T2).

7. The circuit arrangement according to claim 6, characterized in that, In the NMOS and PMOS source follower circuit, the source-drain path of the PMOS transistor (T6) is connected to the current source (I) via the ON / OFF switching unit, and the gate contact of the PMOS transistor (T6) is connected to the source contacts of the two transistors (T1, T2). The source-drain path of the NMOS transistor (T7), one of the two additional transistors (T6, T7) in the NMOS and PMOS source follower circuits, is connected to the high voltage supply voltage (HV) on one hand and to the gate contact of the two transistors (T1, T2) on the other hand. The gate contact of the NMOS transistor (T7) can be connected to the current source (I) via the ON / OFF switching function unit.

8. The circuit arrangement according to claim 6 or 7, characterized in that, The source-drain paths of the two additional transistors (T6, T7) in the NMOS and PMOS source follower circuits are connected to the low-voltage supply voltage (LV) via two additional transistors (T8, T9) connected as current mirrors.

9. The circuit arrangement according to claim 1 or 2, characterized in that, The source-drain path of the third transistor (T3) is always connected to the current source (I) regardless of the switching state of the ON / OFF switching function unit. The circuit unit has a fourth transistor (T4) that is connected to the third transistor (T3) and to the gate contacts of the two transistors (T1, T2) such that the voltage potential (V2) applied at the source contacts of the two transistors (T1, T2) is affected at least by the third transistor (T3) and the voltage potential (V1) applied at the gate contacts of the two transistors (T1, T2) is affected at least by the fourth transistor (T4) such that the two voltage potentials (V1, V2) correspond to each other.

10. The circuit arrangement according to claim 9, characterized in that, The fourth transistor (T4) is doped in the opposite way to the third transistor (T3). The source-drain path of the fourth transistor (T4) is connected to the high-voltage supply voltage (HV) on one hand, and can be switched to the low-voltage supply voltage (LV) on the other hand. The gate contact of the fourth transistor (T4) is connected to the current source (I) via the ON / OFF switch function unit, and is also connected to the source-drain path of the third transistor (T3).

11. The circuit arrangement according to any one of claims 1 to 10, characterized in that, The functional unit that causes the voltage drop is configured as a diode-connected transistor (T_D1), the source-drain path of which is connected in series with the source-drain path of the third transistor (T3) and connected to the gate contact of the first and second transistors (T1, T2), and the diode-connected transistor (T_D1) has a substrate connection terminal connected to the source contact of the first and second transistors (T1, T2).

12. The circuit arrangement according to claim 1 or 2, characterized in that, The source-drain path of the third transistor (T3) is always connected to the current source (I) and the low-voltage supply voltage (LV) regardless of the switching state of the ON / OFF switching function unit. The circuit unit has two fourth transistors (T4, T4') connected as latches. The gate contacts of the fourth transistors are respectively connected to the source and drain paths of the corresponding other fourth transistor (T4, T4') via contact portions. Relative to the contact portions, the source-drain paths of the two fourth transistors (T4, T4') are connected to the source contact points of the first and second transistors, and... The functional unit that causes the voltage drop has two diode arrangements (D1, D1′) connected in parallel, in which one diode arrangement (D1) is connected to one of the two fourth transistors (T4, T4′) (T4) and the other diode arrangement (D1′) is connected to the other of the two fourth transistors (T4, T4′) (T4′).

13. The circuit arrangement according to claim 12, characterized in that, The diode arrangement (D1, D1′) each has two transistors (T10, T_D1; T10′, T_D1′) connected in series. The two transistors connected in series are respectively doped with a first doping and a second doping. The source and drain paths of the transistors (T_D1, T_D1′) with the first doping are respectively connected to the source and drain paths of the third transistor (T3). The source contact of the second-doped transistor (T10) and the gate contact of the first-doped transistor (T_D1) in one of the two diode arrangements (T_D1, T_D1′) are permanently connected to the gate contacts of the first and second transistors (T1, T2), respectively. The gate contact of the transistor (T_D1′) with first doping and the source contact of the transistor (T10′) with second doping in the other diode arrangement of the two diode arrangements (T_D1, T_D1′) can be connected to the current source (I1) via the ON / OFF switching function unit SE.

14. The circuit arrangement according to claim 13, characterized in that, A transistor with the first doping is an NMOS transistor, and a transistor with the second doping is a PMOS transistor.

15. The circuit arrangement according to claim 13 or 14, characterized in that, The gate contact of one of the transistors in the first doped transistor is connected to the source-drain path of one of the two fourth transistors (T4, T4′), and the gate contact of the other transistor in the first doped transistor is connected to the source-drain path of the other transistor (T4′) in the two fourth transistors (T4, T4′).

16. The circuit arrangement according to claim 1 or 2, characterized in that, The circuit unit has a fourth transistor (T4), whose source-drain path is connected in parallel with the gate and source contacts of the two transistors (T1, T2) and is connected to another fourth transistor (T4′) as a current mirror. The source-drain path of the fifth transistor (T5) is connected to the gate contacts of the first and second transistors (T1, T2) and the gate contacts of the two fourth transistors (T4, T4′) connected as current mirrors.

17. The circuit arrangement according to claim 16, characterized in that, The gate contact of the fifth transistor (T5) is connected to the source contacts of the first and second transistors (T1, T2).

18. The circuit arrangement according to claim 16 or 17, characterized in that, The other fourth transistor (T4′) is connected as a diode and its gate contact is connected to its source-drain path.

19. A method for switching two series-connected transistors (T1, T2) in a circuit arrangement according to any one of claims 1 to 18, characterized in that, The circuit unit (S) connected to the source and gate contacts of the two transistors (T1, T2) is connected to the two transistors (T1, T2) in a current-free manner.

20. The method according to claim 19, characterized in that, The circuit unit (S) connected to the source and gate contacts of the two transistors (T1, T2) forms a floating potential difference (dV=V1-V2), which is applied by the circuit unit (S) between the source and gate contacts of the two transistors (T1, T2), wherein there is a potential (V2) at the source contact and a potential (V1) at the gate contact.

21. The method according to claim 20, characterized in that, The floating potential difference (dV=V1-V2) is adapted to the potential (V2) applied at the source contact point of the two transistors (T1, T2).

22. The method according to claim 20 or 21, characterized in that, The floating potential difference (dV=V1-V2) is formed as a low-voltage potential difference and is independent of the high-voltage supply voltage (HV) and low-voltage supply voltage (LV) applied to the circuit unit (S).

23. The method according to any one of claims 20 to 22, characterized in that, The high-voltage supply voltage (HV) is connected to the circuit unit (S) in a way that can be turned on and off, and when it is on, the potential (V1) is greater than the potential (V2), while when it is off, V1 = V2.

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