Area efficient power detection subsystem for phased array transmitters

Abstract

In some aspects, an apparatus can include a plurality of power coupling circuits each coupled between a respective power amplifier and a respective antenna element in a phased array, each power coupling circuit configured to generate a current proportional to an output power of the respective power amplifier. The apparatus can include a shared transimpedance amplifier (TIA) coupled to the plurality of power coupling circuits, where the shared TIA includes: an input to receive the respective generated currents from the plurality of power coupling circuits; and an output to provide an analog signal indicative of values of the respective generated currents received from the plurality of power coupling circuits. The apparatus can include an analog-to-digital converter (ADC) including an input coupled to the output from the shared TIA and an output configured to provide a digital signal indicative of the output power from the power amplifier. Numerous other aspects are described.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to U.S. Patent Application No. 18 / 610,461, filed March 20, 2024, entitled “AREA-EFFICIENT POWERDETECTION SUBSYSTEM FOR PHASED ARRAY TRANSMITTER”, which is assigned to the assignee of this application. The disclosure of the earlier application is considered part of this patent application and is incorporated herein by reference. Technical Field

[0003] All aspects of this disclosure relate in general to wireless transmitters, and, for example, to an area-efficient power detection subsystem for a phased array transmitter. Background Technology

[0004] Wireless communication devices typically include transceivers or transmitters to transmit radio frequency (RF) signals to another wireless communication device, such as a network node or user equipment (UE). To improve transmission gain, the transceiver or transmitter may include a series of transmission chains coupled to a corresponding set of antennas (e.g., an antenna array). The transmission chains can be configured to achieve beamforming via the antenna array, resulting in a significant increase in transmission gain in a specific direction and a significant decrease in transmission gain in other directions. For example, the direction in which transmission gain is maximized may be substantially directed towards a target wireless communication device intended to receive the transmitted RF signal. Summary of the Invention

[0005] In some embodiments, an apparatus includes a plurality of power coupling circuits, each coupled between a corresponding power amplifier and a corresponding antenna element in a phased array, each power coupling circuit being configured to generate a current proportional to the output power of the corresponding power amplifier; a shared transimpedance amplifier (TIA) coupled to the plurality of power coupling circuits, wherein the shared TIA includes: an input for receiving a corresponding generated current from the plurality of power coupling circuits; and an output for providing an analog signal indicating the value of the corresponding generated current received from the plurality of power coupling circuits; and an analog-to-digital converter (ADC) including an input coupled to the output of the shared TIA and an output configured to provide a digital signal indicating the output power from the power amplifier.

[0006] In some specific implementations, a method includes: generating a current proportional to the output power of the respective power amplifier through each of a plurality of power coupling circuits coupled between a respective power amplifier and a respective antenna element in a phased array; receiving the corresponding generated current at an input of a shared TIA coupled to the plurality of power coupling circuits; providing an analog signal indicating the value of the corresponding generated current received from the plurality of power coupling circuits through the shared TIA; and providing a digital signal indicating the output power from the power amplifier based on the analog signal provided by the shared TIA through an ADC coupled to the output of the shared TIA.

[0007] In some specific embodiments, an apparatus includes: a plurality of power coupling components, each disposed between a respective power amplifier and a respective antenna element in a phased array, for generating a current proportional to the output power of the respective power amplifier; a component for providing an analog signal indicating the value of the corresponding generated current, wherein the component for providing the analog signal is shared by the plurality of power coupling components; and a component for providing a digital signal indicating the output power from the power amplifier based on the analog signal.

[0008] The aspects generally include apparatus, methods, systems, wireless communication devices, transceivers, transmitters, and / or circuits as fully described with reference to the accompanying drawings and description, and illustrated as illustrated in the accompanying drawings and description.

[0009] The features and technical advantages of the examples according to this disclosure have been summarized rather extensively above in order to better understand the detailed description below. Additional features and advantages will be described below. The disclosed concepts and specific examples can be readily utilized as the basis for modifying or designing other structures for achieving the same purpose of this disclosure. Such equivalent constructions do not depart from the scope of the appended claims. The characteristics of the concepts disclosed herein (both their organization and manner of operation) and the associated advantages will be better understood from the following description when considered in conjunction with the accompanying drawings. Each figure in the drawings is provided for illustrative and descriptive purposes and not as a limitation of the definitions in the claims. Attached Figure Description

[0010] To gain a full understanding of the foregoing features of this disclosure, a more specific description of the invention, briefly outlined above, can be obtained by referring to various aspects, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only certain typical aspects of this disclosure and are therefore not to be considered as limiting its scope, as other equally valid aspects are permissible in this description. The same reference numerals in different drawings may identify the same or similar elements.

[0011] Figure 1This is a diagram illustrating an example transceiver architecture supporting beamforming according to this disclosure.

[0012] Figure 2 This is a diagram illustrating an example of a power detector circuit according to the present disclosure, which generates a signal indicating the power level of the transmitting element in the phased array of a wireless transceiver.

[0013] Figures 3 to 5 This is a diagram illustrating an example of a power detection topology according to the present disclosure, wherein one or more power detection hardware elements are shared among multiple transmission paths.

[0014] Figures 6A to 6B This is a diagram illustrating an example of an area-efficient power detection subsystem for a phased array transmitter according to the present disclosure.

[0015] Figure 7 This is a flowchart illustrating an example process associated with an area-efficient power detection subsystem for a phased array transmitter according to the present disclosure. Detailed Implementation

[0016] Various aspects of this disclosure are described more fully below with reference to the accompanying drawings. However, this disclosure may be embodied in many different forms and should not be construed as limited to any particular structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be comprehensive and complete, and will fully convey the scope of protection of this disclosure to those skilled in the art. Those skilled in the art will appreciate that the scope of this disclosure is intended to cover any aspect of this disclosure disclosed herein, whether implemented independently or in combination with any other aspect of this disclosure. For example, any number of aspects set forth herein may be used to implement an apparatus or method of practice. Furthermore, the scope of this disclosure is intended to cover such apparatuses or methods implemented using structures, functions, or structures and functions other than or different from the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure herein may be embodied by one or more elements of the claims.

[0017] In a wireless transceiver or transmitter comprising multiple antenna elements (e.g., to support beamforming to maximize gain in a particular direction and / or minimize gain in other directions), each transmit chain typically includes a power amplifier to amplify the power of the signal to be transmitted by the corresponding antenna element, enabling a target wireless communication device to successfully receive and process the transmitted signal. However, the power of the transmitted signal at the output of the power amplifier is typically subject to one or more limitations (e.g., to prevent damage to the power amplifier). Furthermore, in some cases, there may be government or regulatory constraints (e.g., maximum permissible exposure (MPE) limits that restrict the maximum total output signal power of the transmitter for safety and / or interference control purposes. Therefore, to protect the power amplifier from damage and / or meet government or regulatory constraints, the wireless transceiver or transmitter may include a power detection subsystem to measure and control the total radiated power (TRP) of the wireless transceiver or transmitter.

[0018] For example, in a wireless transceiver or transmitter, a power detection subsystem typically includes various power detectors that measure and adjust the TRP (e.g., in a servo manner) of the wireless transceiver or transmitter, as well as one or more processors, controllers, circuitry, or other devices. For instance, in a wireless transceiver or transmitter with multiple antenna elements, each driven (e.g., powered) by a corresponding power amplifier, a typical power detection subsystem includes a corresponding power detector coupled between each power amplifier and its corresponding antenna element. Each power detector (e.g., implemented using a diode detector, logarithmic detector, peak detector, or other suitable circuitry) samples a portion of the radio frequency (RF) signal delivered from the power amplifier (e.g., via a coupler or other suitable technique) to the antenna element and converts the sampled portion of the RF signal into a voltage or current that indicates or otherwise represents the power level of the RF signal (e.g., by rectifying and filtering the sampled RF signal to generate a corresponding analog signal, which may be a voltage or current proportional to the power level of the RF signal). The detected power level information can then be used by the wireless transceiver or transmitter to control or adjust one or more aspects of its operation, such as adjusting the gain of the power amplifier to prevent damage to the power amplifier or to meet government or regulatory constraints, enabling automatic gain control (AGC), or managing the power level to ensure efficient transmission and reception. However, because the power detection subsystem typically includes power detection hardware replicated for each antenna element and corresponding power amplifier, the power detection hardware tends to occupy a large area in the wireless communication device, and the large number of components required to implement the power detection subsystem increases the device cost.

[0019] Various aspects relate to power sensing topologies, where one or more power sensing hardware elements, typically replicated for each power amplifier and corresponding antenna element, are shared among multiple power amplifiers and corresponding antenna elements. For example, in some aspects, a wireless transceiver or transmitter may include one or more modules or integrated circuits (ICs), each module or IC including multiple power amplifiers, each coupled to a corresponding antenna element in a phased array. Therefore, for each of these modules or ICs, the power sensing topology may include multiple power coupling circuits, each coupled between a corresponding power amplifier and a corresponding antenna element. In some aspects, as described herein, each power coupling circuit may be configured to generate a current proportional to the output power of the corresponding power amplifier (e.g., using a squared or filtered circuit). Furthermore, for each module or IC, the power sensing topology may include a shared transimpedance amplifier (TIA) coupled to the multiple power coupling circuits, wherein the shared TIA receives the current generated by the multiple power coupling circuits and outputs an analog signal indicating the value of the generated current received from the multiple power coupling circuits (e.g., a summation value when more than one current is received from the power coupling circuits). Therefore, the analog-to-digital converter (ADC) receives analog signals from the shared TIA and outputs a digital signal indicating the output power from the power amplifier. This digital signal can then be provided to a processor, circuitry, or other device that measures and adjusts the TRP of the wireless transceiver or transmitter based on the digital signal output by the ADC associated with each module or IC.

[0020] Specific aspects of the subject matter described in this disclosure can be implemented to achieve one or more of the following potential advantages. In some examples, by sharing one or more hardware components of the power detection subsystem among multiple transmission paths (e.g., multiple power amplifiers and corresponding antenna elements), the area occupied by the power detection subsystem within the wireless transceiver or transmitter can be significantly reduced. In this way, the described techniques can increase the available area in the wireless transceiver or transmitter, where the available area can then be used for other efficiency enhancement techniques, such as antenna tuning, power combining, etc. Furthermore, by sharing one or more hardware components of the power detection subsystem among multiple transmission paths, the total number of hardware components forming the power detection subsystem is significantly reduced, which lowers the device cost.

[0021] Figure 1 This is an illustration of an example transceiver architecture 100 supporting beamforming (e.g., for millimeter-wave (mmW) communication) according to this disclosure. In some aspects, architecture 100 may be implemented in a transmitting device (e.g., a first wireless communication device, user equipment (UE), or network node) and / or a receiving device (e.g., a second wireless communication device, UE, or network node).

[0022] In a broad sense, Figure 1 Example hardware components of a wireless communication device according to certain aspects of this disclosure are illustrated. The illustrated components can be used for antenna element selection and / or for beamforming to transmit wireless signals. Numerous architectures exist for antenna element selection and phase shift implementation. Figure 1 Only one example is shown. Architecture 100 includes a modem (modulator / demodulator) 102, a digital-to-analog converter (DAC) 104, a first mixer 106, a second mixer 108, and a splitter 110. Architecture 100 also includes multiple first amplifiers 112, multiple phase shifters 114, multiple second amplifiers 116, and an antenna array 118 including multiple antenna elements 120.

[0023] The diagram illustrates transmit lines or other waveguides, wires, and / or traces connecting various components to illustrate how signals to be transmitted travel between components. Reference numerals 122, 124, 126, and 128 indicate areas in architecture 100 where different types of signals travel or are processed. Specifically, reference numeral 122 indicates the area where digital baseband signals travel or are processed, reference numeral 124 indicates the area where analog baseband signals travel or are processed, reference numeral 126 indicates the area where analog intermediate frequency (IF) signals travel or are processed, and reference numeral 128 indicates the area where analog RF signals travel or are processed. Architecture 100 also includes local oscillator A 130, local oscillator B 132, and controller / processor 134. It should be understood that this configuration is merely an example. As another example, signals may be directly converted between baseband and RF (e.g., frequencies used for transmitting or receiving signals over the air).

[0024] Each antenna element 120 may include one or more sub-elements for radiating or receiving RF signals. For example, a single antenna element 120 may include a first sub-element cross-polarized with a second sub-element, which can be used to independently transmit the cross-polarized signal. Antenna elements 120 may include patch antennas, dipole antennas, or other types of antennas arranged in a linear pattern, a two-dimensional pattern, or another pattern. The spacing between antenna elements 120 may allow signals transmitted individually by antenna elements 120 at desired wavelengths to interact or interfere (e.g., to form a desired beam). For example, given a desired wavelength or frequency range, the spacing may provide a quarter wavelength, half wavelength, or other fraction of the wavelength of the spacing between adjacent antenna elements 120 to allow interaction or interference of signals transmitted by individual antenna elements 120 within that desired range.

[0025] Modem 102 processes and generates digital baseband signals and also controls the operation of DAC 104, first mixer 106 and second mixer 108, splitter 110, first amplifier 112, phase shifter 114 and / or second amplifier 116 to transmit signals via one or more of the antenna elements 120. Modem 102 may process signals and control operations according to communication standards, such as the wireless standards discussed herein. DAC 104 converts the digital baseband signals received from (and to be transmitted) by modem 102 into analog baseband signals. First mixer 106 uses local oscillator A 130 to upconvert the analog baseband signal to an analog IF signal within the IF. For example, first mixer 106 may mix the signal with an oscillation signal generated by local oscillator A 130 to “shift” the baseband analog signal to the IF. In some cases, some processing or filtering (not shown) may occur at the IF. The second mixer 108 uses a local oscillator B 132 to upconvert the analog IF signal to an analog RF signal. Similar to the first mixer, the second mixer 108 can mix the signal with an oscillating signal generated by the local oscillator B 132 to “move” the IF analog signal to the frequency of the RF or transmitted / received signal. The modem 102 and / or controller / processor 134 can adjust the frequencies of local oscillators A 130 and / or B 132 to produce desired IF and / or RF frequencies and use them to facilitate signal processing and transmission within a desired bandwidth. The controller / processor 134 is exemplified as being coupled to local oscillators C 170 and D 172, for example, to adjust the frequencies of local oscillators C 170 and / or D 172, but the controller / processor 134 may additionally or alternatively be coupled to local oscillators A 130, B 132, C 170, and / or D 172. In other examples, modem 102 is coupled to local oscillator A 130 and / or local oscillator B 132, and / or connections from controller / processor 134 to local oscillator A 130, local oscillator B 132, local oscillator C 170 and / or local oscillator D 172 are omitted.

[0026] In the illustrated architecture 100, the signal up-converted by the second mixer 108 is split or replicated into multiple signals by the splitter 110. The splitter 110 in architecture 100 separates the RF signal into multiple identical or nearly identical RF signals. In other examples, the splitting can occur for any type of signal, including baseband signals, baseband analog, or IF analog signals. Each of these signals may correspond to an antenna element 120, and the signal travels through amplifiers 112, 116, phase shifters 114, and / or other elements corresponding to the respective antenna element 120 and is processed by these components to provide power to the corresponding antenna element 120 of the antenna array 118 for transmission by that corresponding antenna element. In one example, the splitter 110 may be an active splitter connected to a power supply and providing some gain such that the RF signal leaving the splitter 110 is at a power level equal to or greater than that of the signal entering the splitter 110. In another example, splitter 110 is a passive splitter not connected to a power source, and the RF signal leaving splitter 110 may be at a lower power level than the RF signal entering splitter 110.

[0027] After separation by splitter 110, the resulting RF signal can enter an amplifier, such as first amplifier 112 or phase shifter 114 corresponding to antenna element 120. First amplifier 112 and second amplifier 116 are illustrated with dashed lines because in some respects, one or both of amplifiers 112 and 116 may not be necessary. In some respects, both first amplifier 112 and second amplifier 116 are present. In some respects, neither first amplifier 112 nor second amplifier 116 is present. In some respects, one of the two amplifiers 112 and 116 is present, but the other is not. By way of example, if splitter 110 is an active splitter, first amplifier 112 may not be used. By another example, if phase shifter 114 is an active phase shifter that provides gain, second amplifier 116 may not be used.

[0028] Amplifiers 112 and 116 can provide a desired level of positive or negative gain. Positive gain (positive dB) can be used to increase the amplitude of the signal radiated by a particular antenna element 120. Negative gain (negative dB) can be used by a particular antenna element to reduce the amplitude of that signal and / or suppress the radiation of that signal. Each of amplifiers 112 and 116 can be independently controlled (e.g., by modem 102 or controller / processor 134) to provide independent control over the gain of each antenna element 120. For example, modem 102 and / or controller / processor 134 may have at least one control line connected to each of splitter 110, first amplifier 112, phase shifter 114, and / or second amplifier 116, which can be used to configure the gain to provide the desired amount of gain for each component and therefore each antenna element 120.

[0029] Phase shifter 114 can provide a configurable phase shift or phase offset to the corresponding RF signal to be transmitted. Phase shifter 114 can be a passive phase shifter that is not directly connected to a power source. Passive phase shifters may introduce some insertion loss. Second amplifier 116 can amplify the signal to compensate for the insertion loss. Phase shifter 114 can also be an active phase shifter connected to a power source, such that an active phase shifter provides a certain amount of gain or prevents insertion loss. The settings of each phase shifter in phase shifter 114 are independent, meaning that each phase shifter can be independently set to provide a desired amount of phase shift, the same amount of phase shift, or some other configuration. Modem 102 and / or controller / processor 134 may have at least one control line connected to each phase shifter in phase shifter 114, and this at least one control line can be used to configure phase shifter 114 to provide a desired amount of phase shift or phase offset between antenna elements 120.

[0030] In the illustrated architecture 100, the RF signal received by antenna element 120 is provided to one or more first amplifiers 156 to enhance the signal strength. The first amplifiers 156 may be connected to the same antenna array 118 (e.g., for time division duplex (TDD) operation). The first amplifiers 156 may be connected to different antenna arrays 118. The enhanced RF signal is input to one or more phase shifters 154 to provide a configurable phase shift or phase offset to the corresponding received RF signal to achieve reception via one or more Rx beams. The phase shifters 154 may be active or passive phase shifters. The configuration of the phase shifters 154 is independent, meaning that each phase shifter can be independently configured to provide the desired amount of phase shift, the same amount of phase shift, or some other configuration. The modem 102 and / or controller / processor 134 may have at least one control line connected to each phase shifter in the phase shifter 154, and the at least one control line may be used to configure the phase shifter 154 to provide a desired amount of phase shift or phase offset between the antenna elements 120 to achieve reception via one or more Rx beams.

[0031] The output of phase shifter 154 can be input to one or more second amplifiers 152 for signal amplification of the phase-shifted received RF signal. Second amplifiers 152 can be individually configured to provide a configured amount of gain. Second amplifiers 152 can be individually configured to provide a certain amount of gain to ensure that signals input to combiner 150 have the same amplitude. Amplifiers 152 and / or 156 are illustrated with dashed lines because in some respects they may not be necessary. In some respects, both amplifiers 152 and 156 are present. In other respects, neither amplifiers 152 nor 156 are present. In still other respects, one of amplifiers 152 and 156 is present, but the other is absent.

[0032] In the illustrated architecture 100, the signals output from phase shifter 154 (via amplifier 152 (when present)) are combined in combiner 150. Combiner 150 in architecture 100 combines RF signals into a single signal. Combiner 150 can be a passive combiner (e.g., not connected to a power source), which may result in some insertion loss. Combiner 150 can be an active combiner (e.g., connected to a power source), which may result in some signal gain. When combiner 150 is an active combiner, it can provide different (e.g., configurable) amounts of gain for each input signal, such that the input signals have the same amplitude when combined. When combiner 150 is an active combiner, combiner 150 may not require a second amplifier 152, as the active combiner provides signal amplification.

[0033] The output of combiner 150 is input to mixers 148 and 146. Mixers 148 and 146 typically use inputs from local oscillators 172 and 170, respectively, to down-convert the received RF signals to generate intermediate or baseband signals carrying encoded and modulated information. The outputs of mixers 148 and 146 are input to ADC 144 for conversion to a digital signal. The digital signal output from ADC 144 is input to modem 102 for baseband processing, such as decoding, deinterleaving, or similar operations.

[0034] Architecture 100 is given by way of example only to illustrate an architecture for transmitting and / or receiving signals. In some cases, architecture 100 and / or each part of architecture 100 may be repeated multiple times within the architecture to accommodate or provide any number of RF chains, antenna elements, and / or antenna panels. Furthermore, numerous alternative architectures are possible and contemplated. For example, although only a single antenna array 118 is shown, two, three, or more antenna arrays may be included, each having its own corresponding amplifier, phase shifter, splitter, mixer, DAC, ADC, and / or modem, one or more of these. For example, a single UE may include two, four, or more antenna arrays for transmitting or receiving signals at different physical locations on the UE, in different directions, or at different frequencies.

[0035] Furthermore, mixers, splitters, amplifiers, phase shifters, and other components may be located in different signal type regions in different implementation architectures (e.g., indicated by different reference numerals in figures 122, 124, 126, 128). For example, in different examples, splitting the signal to be transmitted into multiple signals may occur at analog RF, analog IF, analog baseband, or digital baseband frequencies. Similarly, amplification and / or phase shifting may also occur at different frequencies. For example, in some aspects, one or more of splitter 110, amplifiers 112, 116, or phase shifter 114 may be located between DAC 104 and first mixer 106 or between first mixer 106 and second mixer 108. In one example, the functionality of one or more components may be combined into one component. For example, phase shifter 114 may perform amplification to include or replace first amplifier 112 and / or second amplifier 116. By another example, phase shifting may be implemented by second mixer 108 to eliminate the need for a separate phase shifter 114. This technique is sometimes referred to as local oscillator (LO) phase shifting. In some aspects of this configuration, multiple IF-RF mixers may exist within the second mixer 108 (e.g., for each antenna element chain), and the local oscillator B 132 may supply a different local oscillator signal (with different phase shifts) to each IF-RF mixer.

[0036] Modem 102 and / or controller / processor 134 can control one or more of other components 104 to 172 to select one or more antenna elements 120 and / or form a beam for transmitting one or more signals. For example, antenna element 120 can be individually selected or deselected for signal transmission by controlling the amplitude of one or more corresponding amplifiers, such as first amplifier 112 and / or second amplifier 116. Beamforming involves generating a beam using multiple signals on different antenna elements, wherein one or more of the multiple signals are phase-shifted relative to each other. The formed beam can carry physical or higher-level reference signals or information. Since each of the multiple signals is radiated from a corresponding antenna element 120, the radiated signals interact, interfere (constructive and destructive interference), and amplify each other to form the resulting beam. Shape (such as amplitude, width, and / or the presence of sidelobes) and orientation (such as the angle of the beam relative to the surface of antenna array 118) can be dynamically controlled by modifying the phase shift or phase offset applied by phase shifter 114 and the amplitudes applied by amplifiers 112, 116 of multiple signals relative to each other. The controller / processor 134 may be partially or wholly located within one or more other components of architecture 100. For example, in some aspects, the controller / processor 134 may be located within modem 102.

[0037] As indicated above, Figure 1This is provided as an example. Other examples are available with reference to [the relevant information]. Figure 1 The examples described are different.

[0038] Figure 2 This is a diagram illustrating example 200 of a power detector circuit according to the present disclosure, which generates a signal indicating the power level of the transmitting elements in the phased array of a wireless transceiver. For example, as Figure 2 As shown, each transmitting element in the phased array includes a power amplifier 210 that drives the corresponding antenna element 220 in the phased array, and a power detector circuit 230 is coupled to the output of the power amplifier 210. In some aspects, as described herein, the power detector circuit 230 is configured to generate a signal indicating or representing how much power the power amplifier 210 is outputting, such that information related to the power output by the power amplifier can be provided back to the modem to servo-increase or decrease the TRP of the wireless transceiver (e.g., to prevent damage to the power amplifier 210, to meet government or regulatory constraints, to improve beamforming gain, etc.).

[0039] For example, to detect and control the output signal power of power amplifier 210, power detector circuit 230 can receive samples of the RF transmitted signal provided from power amplifier 210 (e.g., via a coupler or other suitable circuitry) to corresponding antenna element 220. Power detector circuit 230 can rectify and filter the sampled RF transmitted signal to generate an analog signal, which can be a voltage or current proportional to or otherwise indicating the power level of the sampled RF signal at the output of power amplifier 210. For example, as... Figure 2 As shown, the power detector circuit 230 can generate a first voltage Vout, which is proportional to or otherwise indicates the power level of the sampled RF signal at the output of the power amplifier 210. Therefore, the first voltage, together with a second (reference) voltage Vref, can be provided to the ADC 240, enabling the ADC 240 to generate a digital signal indicating the output power from the power amplifier 210. The digital signal generated by the ADC 240 can then be provided to a processor, controller, beamforming assembly, modem, or other suitable device or circuitry that can accordingly measure and adjust the TRP of the phased array system.

[0040] For example, a phased array system may include multiple power amplifiers 210, each driving a corresponding antenna element 220, wherein each power amplifier 210 may have a power detector circuit 230 and an ADC 240 coupled to its output. Therefore, in a phased array system, one or more transmitters can be simultaneously activated within a transmission time interval (TTI) (such as a symbol, time slot, etc.), and the TRP of the phased array system can be configured based on the average output power across all transmitting elements within the TTI (e.g., configured by a processor, controller, modem, etc.). For example, in a system with… N In a phased array system with a power amplifier 210, there may be N A power detector circuit 230 and N Each of the N ADCs 240 generates an analog signal proportional to the power level of the sampled RF transmitted signal from the corresponding output of each power amplifier 210, and the N ADCs generate a corresponding digital signal indicating the corresponding power level output from each power amplifier 210. Therefore, by N The digital signal generated by the ADC 240 can be provided to a processor, controller, modem, etc., which can generate a TRP (Transcription Point Reference) for the phased array system (e.g., within a TTI). N The average output power on each power amplifier 210 or the detected power signal that is otherwise associated with the TRP.

[0041] In some respects, the detected power signal can then be used (e.g., by a processor, controller, modem, etc.) for control. N The corresponding gain of each amplifier 210 and / or the corresponding phase shift of a set of phase shifters (e.g., Tx phase shifter 114). For example, the gain and phase shift can be adjusted (e.g., increased or decreased) to control the TRP of the phased array system in order to prevent damage to the power amplifier 210, comply with government or other regulatory constraints, and / or beamform the radiation pattern produced by the phased array system such that the gain in a particular direction is substantially maximized or greater and / or the gain in other directions is substantially minimized. However, in Figure 2In the power detection topology shown, full power detection hardware is replicated for each power amplifier 210 and corresponding antenna element 220. Therefore, the output voltage from the ADC 240 (e.g., its value is proportional to, equivalent to, indicates, or otherwise represents the voltage or current generated by the power detector circuit 230) is averaged across all power amplifiers 210 and corresponding antenna elements 220 to set the transceiver's or transmitter's TRP (e.g., reducing power if the measured TRP might damage one or more power amplifiers 210 or fail to comply with government or regulatory restrictions). Therefore, because the power detection hardware (e.g., power detector circuit 230, ADC 240, and any associated circuitry, such as couplers for sampling the RF transmitted signal at the output of power amplifier 210 and / or grounding devices associated with optimal resistance) is fully replicated for each transmit path, the power detection hardware is significantly reduced. Figure 2 As shown in Zopt), in addition to increasing equipment costs due to the large number of hardware components required to implement the power detection subsystem, power detection hardware also tends to occupy a large area in the wireless transceiver or transmitter.

[0042] Therefore, the various aspects described herein relate to a power detection topology where one or more power detection hardware elements (e.g., multiple power amplifiers and corresponding antenna elements) typically replicated in each transmit path are shared across multiple transmit paths. In this way, the area occupied by the power detection subsystem within the wireless transceiver or transmitter can be significantly reduced, thereby increasing the area of ​​hardware elements within the wireless transceiver or transmitter that can be used to support other efficiency enhancement techniques, such as antenna tuning, power combining, etc. Furthermore, because the power detection hardware is typically located adjacent to or near the input / output (I / O) hardware, the reduction in the area of ​​the power detection hardware allows for a smaller chip size that includes both the power detection hardware and the I / O hardware. Moreover, by sharing one or more hardware elements across multiple transmit paths, the total number of hardware elements forming the power detection subsystem is significantly reduced, which lowers device costs.

[0043] As indicated above, Figure 2 This is provided as an example. Other examples are available with reference to [the relevant information]. Figure 2 The examples described are different.

[0044] Figure 3 This is a diagram illustrating Example 300 of a power detection topology according to this disclosure, wherein one or more power detection hardware elements are shared among multiple transmission paths. As described herein, Figure 3 The power detection topology in the image is provided for use in the phased array. N There are 1 transmission path, where each transmission path includes a corresponding power amplifier ( Figure 3Antenna elements 310 (shown as antenna elements 310-1 to 310-N, not explicitly shown herein) are driven by antenna elements 310. For example, each antenna element 310 may be coupled to a corresponding power amplifier via an antenna connection path, which may include on-chip antenna signal lines (or antenna leads), off-chip antenna feeds, or combinations thereof (e.g., depending on the position of the corresponding antenna element 310 relative to the power amplifier). Each power amplifier receives an RF transmit signal to be amplified for transmission, wherein the RF transmit signal may be a phase-shifted version of the transmit signal that has been phase-shifted by a corresponding phase shifter. Furthermore, each transmit path includes a corresponding coupler 320 (shown as couplers 320-1 to 320-N), wherein each coupler 320 senses the power of the RF transmit signal along the antenna connection path. Therefore, as described herein, the power detector circuitry 350 may be shared among the multiple antenna elements 310, rather than being replicated at the output of each power amplifier.

[0045] For example, when coupler 320 senses the transmit power level of the corresponding antenna element 310, the sensed power level can be provided to power combiner 340 as a sensed power indication signal. Power combiner 340 can combine the sensed power indication signals from each of the couplers 320-1 to 320-N and generate a combined power indication provided to power detector circuit 350. For example, as Figure 3 As shown, the power detector circuit 350 is coupled to the power combiner 340 via one or more lines. Therefore, the power detector circuit 350 receives a combined power indication from the power combiner 340 (e.g., a Wilkinson power combiner), wherein the combined power indication represents the power output of the driving antenna elements 310-1 to 310-N. N The total output power associated with each power amplifier. Furthermore, as... Figure 3 As shown, the power detection topology includes additional phase shifters 330 (shown as phase shifters 330-1 to 330-N) located between the power combiner 340 and the coupler 320 in each transmit path. For example, additional phase shifters 330-1 to 330-N may be provided to compensate for any phase shift applied to the RF transmit signals sampled by the respective couplers 320 (e.g., to keep the various RF transmit signals in phase so that the power combiner 340 can appropriately combine power levels).

[0046] Therefore, although Figure 3 The power detection topology shown can be used to share the power detector circuit 350 among multiple transmit paths, but due to the addition of the power combiner 340 and phase shifters 330-1 to 330-N, Figure 3The power sensing topology shown has a significant area cost. Furthermore, implementing the power combiner 340 near the transmit output convex point, which provides connection points for antenna elements 310-1 to 310-N, presents a significant challenge, as the area near the transmit output convex point is typically one of the most congested areas in the wireless transceiver or transmitter.

[0047] As indicated above, Figure 3 This is provided as an example. Other examples are available with reference to [the relevant information]. Figure 3 The examples described are different.

[0048] Figure 4 This is a diagram illustrating Example 400 of a power detection topology according to this disclosure, wherein one or more power detection hardware elements are shared among multiple transmission paths. As described herein, Figure 4 The power detection topology in the image is provided for use in the phased array. N Each transmission path includes a corresponding connection path 405 originating from the corresponding power amplifier driving the corresponding antenna element (for...). N Each transmission path is shown as connection paths 405-1 to 405-N. For example, as shown, each connection path 405 connects the power amplifier to the corresponding bump (for...). N Each transmission path is shown as bumps 410-1 to 410-N, which represent connection points or transitions between integrated circuits implementing the depicted components and corresponding antenna elements. Figure 4 (Not explicitly shown in the text).

[0049] like Figure 4 As further shown, each transmission path also includes a coupler 415 (for...). N Each transmission path is shown as couplers 415-1 to 415-N. For example, in some aspects, each coupler 415 is a directional coupler or other suitable device that can tap or sample a portion of the output power supplied from the power amplifier to the antenna element along the respective connection path 405. As further shown, each transmission path includes a squaring (or filtering) device 420 (for...). N A transmit path, shown as squaring devices 420-1 to 420-N, wherein a coupler 415 in each transmit path provides a tapped or sampled portion of the output power to the squaring device 420 in the corresponding transmit path along a corresponding connection path 405. For example, in some aspects, the squaring device 420 may include one or more elements commonly biased according to a threshold, such that the squaring device 420 can generate a current proportional to the output power of the power amplifier in the corresponding transmit path. For example, as Figure 4As shown, the square device 420 in each transmission path includes a resistor coupled between a capacitor and a field-effect transistor (FET), which is coupled between ground and a corresponding current source 425 (for...). N One transmission path is shown, illustrating current sources 425-1 to 425-N.

[0050] Therefore, as Figure 4 As further shown, the current generated by the square device 420 in each transmission path can be supplied to the TIA 430 (for...). N A transmission path, shown as TIA 430-1 to 430-N, enables low-pass transmission of the current supplied by the square device 420. For example, as Figure 4 As shown, each transmit path's TIA 430 includes an operational amplifier having: a negative input terminal coupled between the current source 425 and the FET included in the square device 420; and a positive input terminal connectable to a reference voltage generator. Figure 4 (not shown in the image); and a resistor-capacitor (RC) feedback circuit, which includes a feedback capacitor and a feedback resistor, both coupled in parallel between the negative input terminal and the output terminal of the operational amplifier. As further shown, the TIA 430 includes: a resistor having a first end coupled to the output terminal of the operational amplifier; and a capacitor coupled between ground and a second end of the resistor. Therefore, as described herein, the TIA 430 is configured to generate an analog signal (e.g., voltage) indicating the power level of the RF transmitted signal of the associated transmit path based on the current supplied by the square device 420.

[0051] like Figure 4 As further shown, each transmission path includes switch 435 (for...). N There are several transmission paths (shown as switches 435-1 to 435-N), which can be used to sequentially sample each transmission path within a transmission time slot or TTI. For example, the power detection topology includes an ADC 440, which can be used with... Figure 4The other components illustrated are implemented in the same integrated circuit or in different integrated circuits. In either case, ADC 440 can be configured to sequentially scan all transmission paths and convert the analog signal generated by each transmission path into a digital signal. For example, within a transmission time slot or TTI, switch 435-1 can be opened and switches 435-2, 435-3, ..., 435-N can be closed, allowing ADC 440 to sample the analog signal generated by the first TIA 430-1, then switch 435-2 can be opened and switches 435-1 and 435-3, ..., 435-N can be closed, allowing ADC 440 to sample the analog signal generated by the first TIA 430-2, and so on. Thus, ADC 440 can sequentially sample various analog signals within a transmission time slot or TTI, and then average the analog signals in the digital domain to generate a digital signal that is estimated to be analog to... N Each sending path is associated with a TRP. However, Figure 4 The power detection topology shown presents various challenges, including the need for an anti-aliasing filter 450 before the ADC 440 (e.g., to achieve sequential sampling and averaging of various analog signals in the digital domain). Furthermore, Figure 4 The power sensing topology shown is associated with other limitations, such as increased latency (e.g., due to digital averaging) and limited power accuracy.

[0052] As indicated above, Figure 4 This is provided as an example. Other examples are available with reference to [the relevant information]. Figure 4 The examples described are different.

[0053] Figure 5 This is a diagram illustrating Example 500 of a power detection topology according to this disclosure, wherein one or more power detection hardware elements are shared among multiple transmission paths. As described herein, Figure 5 The power detection topology in the image is provided for use in the phased array. N Each transmission path includes a corresponding connection path 505 originating from the corresponding power amplifier driving the corresponding antenna element (for...). N Each transmission path is shown as connection paths 505-1 to 505-N. For example, as shown, each connection path 505 connects the power amplifier to the corresponding bump (for...). N Each transmission path is shown as bumps 510-1 to 510-N, which represent connection points or transitions between integrated circuits implementing the depicted components and corresponding antenna elements. Figure 5 (Not explicitly shown in the text).

[0054] like Figure 5As further shown, each transmission path also includes a coupler 515 (for...). N Each transmission path is shown as couplers 515-1 to 515-N. For example, in some aspects, each coupler 515 is a directional coupler or other suitable device that can tap or sample a portion of the output power supplied from the power amplifier to the antenna element along the respective connection path 505. As further shown, each transmission path includes a squaring (or filtering) device 520 (for...). N A transmission path, shown as squaring devices 520-1 to 520-N, wherein a coupler 515 in each transmission path provides a tapped or sampled portion of the output power to the squaring device 520 in the corresponding transmission path along a corresponding connection path 505. For example, in some aspects, the squaring device 520 may include one or more elements commonly biased according to a threshold, such that the squaring device 520 can generate a current proportional to the output power of the power amplifier in the corresponding transmission path. For example, as Figure 5 As shown, the square device 520 in each transmission path includes a resistor coupled between a capacitor and a FET, which is coupled between ground and a corresponding current source 525 (for...). N One transmission path is shown, illustrating current sources 525-1 to 525-N.

[0055] Therefore, as Figure 5 As further shown, the current generated by the square device 520 in each transmission path can be provided to the TIA 530 (for...). N A transmission path, shown as TIA 530-1 to 530-N, enables low-pass transmission of the current supplied by the square device 520. For example, as Figure 5 As shown, each transmit path's TIA 530 includes an operational amplifier having: a negative input terminal coupled between the current source 525 and the FET included in the square device 520; and a positive input terminal connectable to a reference voltage generator. Figure 5 (not shown in the diagram) and an RC feedback circuit, which includes a feedback capacitor and a feedback resistor, both coupled in parallel between the negative input terminal and the output terminal of the operational amplifier. As further shown, the TIA 530 includes: a resistor having a first end coupled to the output terminal of the operational amplifier; and a capacitor coupled between ground and a second end of the resistor. Therefore, as described herein, the TIA 530 is configured to generate an analog signal (e.g., voltage) indicating the power level of the RF transmitted signal of the associated transmit path based on the current supplied by the square device 520.

[0056] like Figure 5As further shown, each transmission path includes a switch pair 535 (for...). N Each transmit path (shown as switch pairs 535-1 to 535-N) includes a first switch closed and coupled to a reference voltage Vref, and a second switch open, when the corresponding antenna element is turned off. Alternatively, when the corresponding antenna element is turned on, the second switch closes and is coupled to the input terminal of the ADC 540, and the first switch is open. In this way, each switch pair 535 always includes a closed switch and an open switch, where the closed switch depends on whether the corresponding antenna element is turned on or off. In this way, the ADC 540 can sample only once per transmit time slot or TTI the waveform representing the current generated by the TIA 530 associated with the multiple transmit paths to obtain the TRP from all transmit elements coupled to the ADC 540 (e.g., by performing analog averaging), which the ADC can then use in conjunction with... Figure 5 The other components illustrated are implemented in the same integrated circuit or in different integrated circuits. In either case, relative to Figure 4 For the power sensing topology shown, adding a first switch coupled to the reference voltage and using an always-on technique for the switch pair 535 associated with each transmit path reduces the power estimation delay because the ADC 540 only needs to sample the waveform once to obtain the TRP for all transmit paths, and the ADC 540 does not need to perform digital averaging. However, by Figure 5 The power sensing topology shown offers area savings relative to Figure 4 The power detection topology shown is extremely small because Figure 5 The power sensing topology shown eliminates the need for an anti-aliasing filter before the ADC 540.

[0057] As indicated above, Figure 5 This is provided as an example. Other examples are available with reference to [the relevant information]. Figure 5 The examples described are different.

[0058] Figures 6A to 6B These are illustrations of examples 600A and 600B associated with an area-efficient power detection subsystem for a phased array transmitter according to this disclosure. As described herein, Figures 6A to 6B Examples are provided for use in phased arrays. N A power detection topology for each transmit path, wherein each transmit path includes a corresponding connection path 605 originating from a corresponding power amplifier (e.g., amplifier 116) driving the corresponding antenna element (e.g., antenna element 120). NEach transmission path is shown as connection paths 605-1 to 605-N. For example, as shown, each connection path 605 connects the power amplifier to the corresponding bump (for...). N Each transmission path is shown as bumps 610-1 to 610-N, which represent connection points or transitions between integrated circuits implementing the depicted components and corresponding antenna elements. Figures 6A to 6B (Not explicitly shown in the text).

[0059] Therefore, as Figures 6A to 6B As shown and described herein, each transmit path includes a power coupling circuit that couples between a corresponding power amplifier and a corresponding antenna element in the phased array. For example, as... Figures 6A to 6B As shown, the power coupling circuit in each transmission path includes a coupler 615 (for...). N Each transmission path is shown as couplers 615-1 to 615-N. For example, in some aspects, each coupler 615 is a directional coupler or other suitable device that can tap or sample a portion of the output power supplied from the power amplifier to the antenna element along the respective connection path 605. As further shown, each transmission path includes a squaring (or filtering) device 620 (for...). N A transmit path, shown as squaring devices 620-1 to 620-N, wherein a coupler 615 in each transmit path provides a tapped or sampled portion of the output power to the squaring device 620 in the corresponding transmit path along a corresponding connection path 605. For example, in some aspects, the squaring device 620 may include one or more elements commonly biased according to a threshold, such that the squaring device 620 can generate a current proportional to the output power of the power amplifier in the corresponding transmit path. For example, as Figures 6A to 6B As shown, the square device 620 in each transmission path includes a resistor coupled between a capacitor and a FET, which is coupled between ground and a corresponding current source 625 (for...). N Each transmission path is shown, illustrating current sources 625-1 to 625-N. (e.g., [example]). Figures 6A to 6B As further shown, each transmission path includes switch 630 (for...). N A transmission path, shown as switches 630-1 to 630-N, wherein each switch 630 can be closed when the corresponding antenna element is turned on, or opened when the corresponding antenna element is turned off.

[0060] Therefore, as Figures 6A to 6B As further shown, the current generated by the square device 620 in each transmission path can be provided to a shared TIA 640, which is common to multiple transmission paths, and coupled to the antenna element when the corresponding antenna element is turned on. NEach transmit path in the transmit path is associated with a power coupling circuit. For example, as described herein, a shared TIA 640 can enable power coupling circuitry for each transmit path. N The square device 620 associated with each transmission path provides a low-pass current and can provide or otherwise output an indication from the current supplied by the transmission path. N The analog signal received by the power coupling circuit associated with each transmission path is the sum of the corresponding generated currents. For example, as Figures 6A to 6B As shown, the shared TIA 640 includes an operational amplifier having a negative input terminal coupled to a source from... N The output terminal of the power coupling circuit associated with the transmission path; the positive input terminal, which can be connected to the reference voltage generator ( Figures 6A to 6B (not shown in the diagram) and an RC feedback circuit, the RC feedback circuit including a feedback capacitor and a feedback resistor, both coupled in parallel between the negative input terminal and the output terminal of the operational amplifier. As further shown, the shared TIA 640 includes: a resistor having a first end coupled to the output terminal of the operational amplifier; and a capacitor coupled between ground and a second end of the resistor. Therefore, as described herein, the shared TIA 640 is configured to generate an analog signal (e.g., voltage) indicating the sum of corresponding generated currents received from multiple power coupling circuits, the analog signal being provided to an ADC 650, the ADC being configured to provide an indication of the current from the input terminal and the output terminal of the operational amplifier based on the analog signal output by the shared TIA 640. N The digital signal represents the output power of the power amplifier associated with each transmission path. In some respects, the ADC 650 can be used with... Figures 6A to 6B The other components illustrated are implemented in the same integrated circuit or in different integrated circuits. Furthermore, because the squaring device 620 in each transmit path is configured to output a current proportional to the output power of the corresponding power amplifier, the phase of the sampled signal does not affect the value of the current, which can be easily low-pass filtered using a shared TIA 640.

[0061] Therefore, relative to Figures 4 to 5 Regarding the power detection topology shown, Figures 6A to 6B The power sensing topology shown extends power sensing hardware sharing to another level. For example, Figures 4 to 5 The power detection topologies shown each include a TIA per transmit path, where each TIA includes an operational amplifier and associated circuitry (e.g., one or more resistors and one or more capacitors). In this way, in which... Figures 6A to 6B The power sensing topology shown is implemented multiple times (e.g., for each quadrant in the mmW IC, and / or such that each combination of frequency range and polarization is associated with...). Figures 6A to 6B The corresponding topology shown is associated with (and in this example) N In an example implementation where four transmit paths share a single TIA 640, each quadrant or combination eliminates three operational amplifiers, associated circuitry, and associated registers and calibration devices. In other examples, N It is five or another number. Furthermore, in a wireless transceiver or transmitter that includes multiple circuits (e.g., quadrant circuits), where each circuit implements... Figures 6A to 6B The power detection topology shown can multiply hardware savings depending on the number of circuits. For example, in a wireless transceiver or transmitter with eight circuits, where each circuit includes a power detection topology for four transmit paths, the following can be achieved: Figures 4 to 5 The power detection topology shown would require 32 operational amplifiers and associated circuitry, along with associated registers and calibration devices, all housed in a single die. Conversely, assuming a wireless transceiver or transmitter with the same configuration and eight circuits, each including a power detection topology for four transmit paths, the following implementation... Figures 6A to 6B The power sensing topology shown would require only eight operational amplifiers and associated circuitry (e.g., all implemented on a single die or IC, where each circuit on that die or IC has a shared TIA 640), eliminating the need for 24 operational amplifiers and associated circuitry, along with associated registers and calibration devices, all located on a single die. Furthermore, Figures 6A to 6B The power sensing topology shown can be implemented using a front-end IC (FEIC) configuration, for example, enabling... Figures 6A to 6B All the components illustrated are implemented on a single FEIC (such as an mmW IC). In another example, in some respects, the shared TIA 640 can be implemented in the FEIC, and the ADC 650 can be implemented in an intermediate frequency integrated circuit (IFIC) coupled to the FEIC. In this case, the output from the power coupling circuit coupled to the shared TIA 640 can generate only an analog output, which will be fed to a matching IFIC or upconverter chip carrying mixed-signal circuitry (e.g., the ADC 650, etc.).

[0062] In some respects, when only one antenna element is turned on within a transmit time slot or TTI, only one current is generated and supplied to the shared TIA 640. However, when multiple antenna elements are turned on within a transmit time slot or TTI, multiple corresponding currents are generated and supplied to the shared TIA 640. In other words, the current through the shared TIA 640 is proportional to or related to the number of antenna elements turned on within the transmit time slot or TTI. For example, if a single antenna element is turned on, the value of the current through the shared TIA 640 can be expressed as I1, and if... MIf multiple components are simultaneously turned on within a transmission time slot or TTI, the current flowing through the shared TIA 640 can be expressed as follows: M ×I1. In many cases, in mmW transceivers or transmitters that support beamforming, multiple antenna elements may be simultaneously activated to maximize gain in a specific direction (e.g., towards a wireless communication device intended to receive the transmitted signal). Therefore, in order to maintain the output voltage from the shared TIA 640 within a suitable dynamic range, Figure 6B One or more examples of devices and / or technologies are described that can be used to scale the current of the shared TIA 640 per antenna element based on the number of antenna elements turned on in the transmit time slot or TTI.

[0063] For example, as indicated by reference numeral 660, the gain of the shared TIA 640 can be dynamically adjusted by an RC feedback circuit comprising a feedback resistor and a feedback capacitor coupled between the input and output of the operational amplifier. For example, when one antenna element is turned on, the feedback resistor may have a first resistance, and the feedback capacitor may have a first capacitance value. Alternatively, when multiple antenna elements are turned on, the feedback resistor may have a second (e.g., lower) resistance, and / or the capacitance of the feedback capacitor may be adjusted accordingly to regulate the voltage value at the output of the shared TIA 640. For example, in some aspects, the feedback resistor and / or feedback capacitor may be adjustable, such that the resistance and capacitance can be set to appropriate values ​​(e.g., depending on the number of antenna elements turned on). In another example, the feedback resistor may be included in a resistor bank, and / or the feedback capacitor may be included in a capacitor bank, such that a feedback resistor and / or feedback capacitor with appropriate resistance and / or capacitance values ​​can be selected from the resistor bank and / or capacitor bank. Additionally or alternatively, the power coupling circuitry associated with each transmission path may include an input attenuator 662 (for...). N Each transmit path, shown as input attenuators 662-1 to 662-N, can be configured within a corresponding square device 620 to scale the current from the corresponding antenna element. For example, in some aspects, a processor, controller, or other device can determine the number of antenna elements turned on or off in the current transmit time slot or TTI, and can configure the corresponding input attenuator 662 based on the number of antenna elements turned on or off in the current transmit time slot or TTI to add several decibels (dB) of attenuation. Additionally or alternatively, the power coupling circuitry associated with each transmit path may include device 664 (for... NEach transmit path (shown as FETs 664-1 to 644-N) can be configured to discharge current from the respective antenna element (e.g., discharge to Vdd) based on the number of antenna elements turned on or off in the current transmit time slot or TTI to reduce the current supplied to the shared TIA 640.

[0064] As indicated above, Figures 6A to 6B This is provided as an example. Other examples are available with reference to [the relevant information]. Figures 6A to 6B The examples described are different.

[0065] Figure 7 This is a flowchart of an example process 700 associated with an area-efficient power detection subsystem for a phased array transmitter. In some specific implementations, the power detection subsystem (e.g., Figures 6A to 6B The power detection subsystem shown may be executed or configured to perform process 700. In some embodiments, another device or group of devices (e.g., a processor, controller, etc.) separate from or including the power detection subsystem may be executed or configured to perform process 700. Additionally or alternatively, one or more components of the power detection subsystem may be executed or configured to perform process 700. Therefore, components for performing process 700 may include the power detection subsystem and / or one or more components of the power detection subsystem.

[0066] like Figure 7 As shown, process 700 may include: generating a current proportional to the output power of the respective power amplifier (box 710) through each of a plurality of power coupling circuits coupled between the respective power amplifier and the respective antenna element in the phased array. Figure 7 As further shown, process 700 may include receiving the corresponding generated current at the input of the shared TIA coupled to the plurality of power coupling circuits (block 720). Figure 7 As further shown, process 700 may include: providing an analog signal (block 730) via a shared TIA indicating the value of the corresponding generated current received from the plurality of power coupling circuits. Figure 7 As further shown, process 700 may include providing a digital signal indicating the output power from the power amplifier based on an analog signal provided by the shared TIA via an ADC including an input coupled to the output of the shared TIA (box 740).

[0067] Process 700 may include additional aspects, such as any single aspect or any combination of aspects described in conjunction with one or more other processes or operations described below and / or elsewhere herein.

[0068] In a first aspect, each of the plurality of power coupling circuits includes a coupler comprising a first output coupled to an input of a respective power amplifier, a first output coupled to a respective antenna element associated with the power coupling circuit, and a second output coupled to a shared TIA.

[0069] In a second aspect, either alone or in combination with the first aspect, each of the plurality of power coupling circuits further includes a square device coupled between the shared TIA and the second output of the coupler to output a current proportional to the output power of the respective power amplifier.

[0070] In a third aspect, either alone or in combination with one or more of the first and second aspects, each of the plurality of power coupling circuits further includes a switching device coupled between the shared TIA and the square device, which closes when the corresponding antenna element is turned on, such that the current output from the square device is provided to the shared TIA.

[0071] In the fourth aspect, the TIA is shared in the FEIC, either alone or in combination with one or more of the first to third aspects, and the ADC is implemented in the IFIC coupled to the FEIC.

[0072] In the fifth aspect, either alone or in combination with one or more of the first to fourth aspects, the current of the shared TIA is proportional to the number of antenna elements turned on.

[0073] In the sixth aspect, either alone or in combination with one or more of the first to fifth aspects, process 700 includes: adjusting the gain of the shared TIA by means of an RC feedback circuit coupled between the input and output of the shared TIA.

[0074] In the seventh aspect, either alone or in combination with one or more of the first to sixth aspects, process 700 includes scaling the current from the respective antenna element through the respective input attenuators included in the plurality of power coupling circuits.

[0075] In the eighth aspect, either alone or in combination with one or more of the first to seventh aspects, process 700 includes: the plurality of power coupling circuits discharging current from the respective antenna elements to reduce the current supplied to the shared TIA.

[0076] although Figure 7 An example block diagram of process 700 is shown, but in some specific implementations, process 700 may include... Figure 7The boxes depicted may be fewer, different, or arranged differently compared to additional boxes, boxes, or boxes in a different manner. Additionally or alternatively, two or more of the boxes in process 700 may be executed in parallel. Process 700 is an example of a process that can be executed by one or more devices described herein. These one or more devices may perform one or more other processes based on the operations described herein, or may be configured to perform one or more other processes based on the operations described herein.

[0077] The following provides an overview of some aspects of this disclosure:

[0078] Aspect 1: An apparatus comprising: a plurality of power coupling circuits, each power coupling circuit being coupled between a respective power amplifier and a respective antenna element in a phased array, each power coupling circuit being configured to generate a current proportional to the output power of the respective power amplifier; a shared TIA coupled to the plurality of power coupling circuits, wherein the shared TIA includes: an input for receiving a corresponding generated current from the plurality of power coupling circuits; and an output for providing an analog signal indicating the value of the corresponding generated current received from the plurality of power coupling circuits; and an ADC including an input coupled to the output from the shared TIA and an output configured to provide a digital signal indicating the output power from the power amplifier.

[0079] Aspect 2: The apparatus according to Aspect 1, wherein each of the plurality of power coupling circuits includes a coupler, the coupler including a first output coupled to an input of the respective power amplifier, a first output coupled to a respective antenna element associated with the power coupling circuit, and a second output coupled to the shared TIA.

[0080] Aspect 3: The apparatus according to Aspect 2, wherein each of the plurality of power coupling circuits further includes a squaring device coupled between the shared TIA and the second output of the coupler to output a current proportional to the output power of the respective power amplifier.

[0081] Aspect 4: The apparatus according to aspect 3, wherein each of the plurality of power coupling circuits further includes a switching device coupled between the shared TIA and the square device, wherein when the respective antenna element is turned on, the switching device is closed such that the current output by the square device is provided to the shared TIA.

[0082] Aspect 5: The apparatus according to any one of aspects 1 to 4, wherein the shared TIA is implemented in the FEIC, and wherein the ADC is implemented in the IFIC coupled to the FEIC.

[0083] Aspect 6: The apparatus according to any one of aspects 1 to 5, wherein the current through the shared TIA is proportional to the number of the antenna elements that are turned on.

[0084] Aspect 7: The apparatus according to any one of aspects 1 to 6, the apparatus further comprising: an RC feedback circuit coupled between an input terminal of the shared TIA and an output terminal of the shared TIA to adjust the gain of the shared TIA.

[0085] Aspect 8: The apparatus according to any one of aspects 1 to 7, wherein each of the plurality of power coupling circuits includes an input attenuator for scaling the current from the respective antenna element.

[0086] Aspect 9: The apparatus according to any one of aspects 1 to 8, wherein each of the plurality of power coupling circuits includes one or more devices for discharging current from the respective antenna element to reduce the current supplied to the shared TIA.

[0087] Aspect 10: A method comprising: generating a current proportional to the output power of the respective power amplifier through each of a plurality of power coupling circuits coupled between a respective power amplifier and a respective antenna element in a phased array; receiving the corresponding generated current at an input of a shared TIA coupled to the plurality of power coupling circuits; providing an analog signal through the shared TIA indicating the value of the corresponding generated current received from the plurality of power coupling circuits; and providing a digital signal indicating the output power from the power amplifier based on the analog signal provided by the shared TIA through an ADC coupled to an output of the shared TIA.

[0088] Aspect 11: According to the method of aspect 10, each of the plurality of power coupling circuits includes a coupler, the coupler including a first output coupled to an input of the respective power amplifier, a first output coupled to a respective antenna element associated with the power coupling circuit, and a second output coupled to the shared TIA.

[0089] Aspect 12: According to the method of aspect 11, each of the plurality of power coupling circuits further includes a squaring device coupled between the shared TIA and the second output of the coupler to output a current proportional to the output power of the respective power amplifier.

[0090] Aspect 13: According to the method of aspect 12, each of the plurality of power coupling circuits further includes a switching device coupled between the shared TIA and the square device, wherein when the respective antenna element is turned on, the switching device closes such that the current output by the square device is provided to the shared TIA.

[0091] Aspect 14: The method according to any one of aspects 10 to 13, wherein the shared TIA is implemented in the FEIC, and wherein the ADC is implemented in the IFIC coupled to the FEIC.

[0092] Aspect 15: The method according to any one of aspects 10 to 14, wherein the current through the shared TIA is proportional to the number of the antenna elements that are turned on.

[0093] Aspect 16: The method according to any one of aspects 10 to 15, the method further comprising: adjusting the gain of the shared TIA by means of an RC feedback circuit coupled between the input terminal of the shared TIA and the output terminal of the shared TIA.

[0094] Aspect 17: The method according to any one of aspects 10 to 16, the method further comprising: scaling the current from the respective antenna element by means of a respective input attenuator included in the plurality of power coupling circuits.

[0095] Aspect 18: The method according to any one of aspects 10 to 17, the method further comprising: the plurality of power coupling circuits discharging current from the respective antenna elements to reduce the current supplied to the shared TIA.

[0096] Aspect 19: An apparatus comprising: a plurality of power coupling components, each disposed between a respective power amplifier and a respective antenna element in a phased array, for generating a current proportional to the output power of the respective power amplifier; a component for providing an analog signal indicating the value of the corresponding generated current, wherein the component for providing the analog signal is shared by the plurality of power coupling components; and a component for providing a digital signal indicating the output power from the power amplifier based on the analog signal.

[0097] Aspect 20: The apparatus according to aspect 19 further includes a component for adjusting the gain of the component for providing the analog signal.

[0098] Aspect 21: A system configured to perform one or more of the operations stated in one or more of aspects 1 to 20.

[0099] Aspect 22: An apparatus comprising components for performing one or more of the operations described in one or more of aspects 1 to 20.

[0100] Aspect 23: A non-transitory computer-readable medium storing an instruction set comprising one or more instructions that, when executed by a device, cause the device to perform one or more operations stated in one or more of aspects 1 to 20.

[0101] Aspect 24: A computer program product comprising instructions or code for performing one or more of the operations stated in one or more of aspects 1 to 20.

[0102] While the foregoing disclosure provides examples and descriptions, it is not intended to be exhaustive or to limit all aspects to the precise form disclosed. Modifications and variations may be made based on the foregoing disclosure, or from various forms of practice.

[0103] As used herein, the term "component" is intended to be interpreted broadly as hardware and / or a combination of hardware and software. Whether referred to as software, firmware, middleware, microcode, hardware description language, or other names, "software" should be interpreted broadly as meaning instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, and / or functions, etc. As used herein, a "processor" is implemented in hardware and / or a combination of hardware and software. It will be apparent that the systems and / or methods described herein can be implemented through various forms of hardware and / or combinations of hardware and software. The actual dedicated control hardware or software code used to implement these systems and / or methods is not limiting in any way. Therefore, no specific software code is referred to in this document to describe the operation and behavior of the systems and / or methods, as those skilled in the art will understand that the software and hardware can be designed, at least in part, based on the descriptions herein, to implement the systems and / or methods.

[0104] As used in this article, depending on the context, "meeting the threshold" can mean a value greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, equal to the threshold, not equal to the threshold, etc.

[0105] Although specific combinations of features are set forth in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of various aspects. Many of these features may be combined in ways not specifically set forth in the claims and / or not disclosed in the specification. The disclosure of various aspects includes each dependent claim in combination with each other claim in the claim set. As used herein, the phrase “at least one of” in the list of items refers to any combination of these entries, including a single member. As an example, “at least one of: a, b, or c” is intended to cover: a, b, c, a+b, a+c, b+c, and a+b+c, as well as any combination having multiple identical elements (e.g., a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c, and c+c+c, or any other ordering of a, b, and c).

[0106] No element, action, or instruction used herein should be construed as essential or necessary unless explicitly stated otherwise. Furthermore, as used herein, the articles “a” and “an” are intended to include one or more items and are used interchangeably with “one or more.” Similarly, as used herein, the article “described” is intended to include one or more items mentioned in connection with the article “described” and is used interchangeably with “one or more.” Furthermore, as used herein, the terms “set” and “group” are intended to include one or more items and are used interchangeably with “one or more.” If only one item is desired, the phrase “only one” or similar terminology will be used. Additionally, as used herein, the terms “having” and the like are intended to be open-ended terms that do not limit the elements they modify (e.g., an element “having” A may also have B). Furthermore, the phrase “based on” is intended to mean “at least partially based on” unless otherwise explicitly stated. Additionally, as used herein, the term “or” is intended to be open-ended when used in a series and is interchangeable with “and / or” unless otherwise explicitly stated (e.g., if used in conjunction with “any” or “only one”).

Claims

1. An apparatus, the apparatus comprising: Multiple power coupling circuits, each coupled between a corresponding power amplifier and a corresponding antenna element in a phased array, wherein each power coupling circuit is configured to generate a current proportional to the output power of the corresponding power amplifier; A shared transimpedance amplifier (TIA) coupled to the plurality of power coupling circuits, wherein the shared TIA includes: The input terminal is used to receive the corresponding generated current from the plurality of power coupling circuits; and The output terminal is used to provide an analog signal indicating the value of the corresponding generated current received from the plurality of power coupling circuits; and An analog-to-digital converter (ADC) includes an input coupled to the output of the shared TIA and an output configured to provide a digital signal indicating the output power from the power amplifier.

2. The apparatus of claim 1, wherein each of the plurality of power coupling circuits includes a coupler, the coupler including a first output coupled to an input of the respective power amplifier, a first output coupled to a respective antenna element associated with the power coupling circuit, and a second output coupled to the shared TIA.

3. The apparatus of claim 2, wherein each of the plurality of power coupling circuits further comprises a squaring device coupled between the shared TIA and the second output of the coupler to output a current proportional to the output power of the respective power amplifier.

4. The apparatus of claim 3, wherein each of the plurality of power coupling circuits further comprises a switching device coupled between the shared TIA and the square device, wherein when the respective antenna element is turned on, the switching device closes such that the current output by the square device is provided to the shared TIA.

5. The apparatus of claim 1, wherein the shared TIA is implemented in a front-end integrated circuit (FEIC), and wherein the ADC is implemented in an intermediate frequency integrated circuit (IFIC) coupled to the FEIC.

6. The apparatus of claim 1, wherein the current through the shared TIA is proportional to the number of the antenna elements that are turned on.

7. The apparatus according to claim 1, further comprising: A resistor-capacitor (RC) feedback circuit is coupled between the input and output of the shared TIA to adjust the gain of the shared TIA.

8. The apparatus of claim 1, wherein each of the plurality of power coupling circuits includes an input attenuator for scaling the current from the respective antenna element.

9. The apparatus of claim 1, wherein each of the plurality of power coupling circuits includes one or more devices for discharging current from the respective antenna element to reduce the current supplied to the shared TIA.

10. A method, the method comprising: A current proportional to the output power of the corresponding power amplifier is generated by each of a plurality of power coupling circuits coupled between the corresponding power amplifier and the corresponding antenna element in the phased array. The generated current is received at the input of the shared transimpedance amplifier (TIA) coupled to the plurality of power coupling circuits; The shared TIA provides an analog signal indicating the value of the corresponding generated current received from the plurality of power coupling circuits; as well as An analog-to-digital converter (ADC) coupled to the output of the shared TIA provides a digital signal indicating the output power from the power amplifier based on the analog signal provided by the shared TIA.

11. The method of claim 10, wherein each of the plurality of power coupling circuits includes a coupler, the coupler including a first output coupled to an input of the respective power amplifier, a first output coupled to a respective antenna element associated with the power coupling circuit, and a second output coupled to the shared TIA.

12. The method of claim 11, wherein each of the plurality of power coupling circuits further comprises a squaring device coupled between the shared TIA and the second output of the coupler to output a current proportional to the output power of the respective power amplifier.

13. The method of claim 12, wherein each of the plurality of power coupling circuits further comprises a switching device coupled between the shared TIA and the square device, wherein when the respective antenna element is turned on, the switching device closes such that the current output by the square device is provided to the shared TIA.

14. The method of claim 10, wherein the shared TIA is implemented in a front-end integrated circuit (FEIC), and wherein the ADC is implemented in an intermediate frequency integrated circuit (IFIC) coupled to the FEIC.

15. The method of claim 10, wherein the current through the shared TIA is proportional to the number of the antenna elements that are turned on.

16. The method according to claim 10, further comprising: The gain of the shared TIA is adjusted by a resistor-capacitor (RC) feedback circuit coupled between the input and output of the shared TIA.

17. The method according to claim 10, further comprising: The current from the respective antenna element is scaled by the corresponding input attenuators included in the plurality of power coupling circuits.

18. The method according to claim 10, further comprising: The plurality of power coupling circuits discharge current from the respective antenna elements to reduce the current supplied to the shared TIA.

19. An apparatus comprising: Multiple power coupling components, each disposed between a corresponding power amplifier and a corresponding antenna element in a phased array, are used to generate a current proportional to the output power of the corresponding power amplifier; A component for providing an analog signal indicating the value of the corresponding generated current, wherein the component for providing the analog signal is shared by the plurality of power coupling components; and A component for providing a digital signal indicating the output power from the power amplifier based on the analog signal.

20. The apparatus of claim 19, further comprising: A component used to adjust the gain of the component used to provide the analog signal.

Images