Switching architecture

Abstract

A switch fabric comprising: an input column array (110) comprising a plurality of input switch cells (110a-d); an output column array (160) comprising a plurality of output switch cells (160a-d); a plurality of additional switch cells and a plurality of interconnect channels directly connecting pairs of the plurality of additional switch cells. The plurality of additional switch cells are arranged in a plurality of columns (120-150) between the input column array (110) and the output column array (160) and comprising an input adjacent column (120) closest to the input column array (110), an output adjacent column (150) closest to the output column array (160), and a plurality of intermediate columns (130, 140) between the input adjacent column (120) and the output adjacent column (150). A first input switch cell (110a) is directly connected to a first switch cell (120a) of the input adjacent column (120) and a second input switch cell (110d) is directly connected to a first intermediate switch cell (140d) of one of the intermediate columns (140a-d). A first output switch cell (160d) is directly connected to a second switch cell (150d) of the output adjacent column (150) and a second output switch cell (160a) is directly connected to a second intermediate switch cell of one of the intermediate columns (130a).

Description

Technical Field

[0001] This invention relates to a highly scalable, high-cardinality switching architecture for use in large-scale photonic processors for modern data center applications, computing clusters, and artificial intelligence infrastructure. Background Technology

[0002] Artificial intelligence (AI) innovation is experiencing rapid and global growth. The widespread deployment of AI technology across multiple industries is a major catalyst for unprecedented increases in power consumption within data centers. This sudden surge in power demand means that data centers will need to significantly improve their efficiency and scalability. Traditional systems consisting of only a few general-purpose processing units (GPUs) are insufficient to process and compute recently programmed AI models, and these systems also suffer from significant scalability limitations.

[0003] In this context, there is an unprecedented need for a highly scalable, high-cardinality switching architecture that will be integrated into network devices to connect computing resources across multiple data center architectures.

[0004] Currently, the limitations of network switching for data centers remain significant. In particular, there are no solutions yet for high-cardinality, high-capacity switching architectures (whose performance and scalability can meet the new demands of applications requiring large data transfer volumes due to heavy usage).

[0005] This invention aims to alleviate these problems and provide a scalable high-cardinality switching architecture suitable for future data centers, artificial intelligence infrastructure, and high-performance computing. Summary of the Invention

[0006] According to a first aspect of the present invention, a switching architecture is provided, comprising: an input column array including a plurality of input switching cells; an output column array including a plurality of output switching cells; a plurality of additional switching cells; and a plurality of interconnect channels directly connecting pairs of the plurality of additional switching cells. The plurality of additional switching cells may be arranged in a plurality of columns, wherein the plurality of columns are located between the input column array and the output column array. The plurality of columns may include an input adjacent column closest to the input column array and an output adjacent column closest to the output column array. The plurality of columns may include a plurality of intermediate columns, wherein the intermediate columns are located between the input adjacent columns and the output adjacent columns. A first input switching cell may be directly connected to a first switching cell in an input adjacent column. A second input switching cell may be directly connected to a first intermediate switching cell in one of the intermediate columns. A first output switching cell may be directly connected to a second switching cell in an output adjacent column. A second output switching cell may be directly connected to a second intermediate switching cell in one of the intermediate columns.

[0007] In some examples, each of the first input switching cell and the second input switching cell can be selectively coupled to any output switching cell via one or more interconnect channels. In some examples, each of the first output switching cell and the second output switching cell can be selectively coupled to any input switching cell via one or more interconnect channels.

[0008] A switching architecture can be used within a network system, i.e., to provide links between multiple servers or nodes. For example, a switching architecture can be used within a device for internal data connectivity, i.e., to route multiple signals (e.g., data streams modulated by optical signals) between different components (e.g., servers, racks, GPUs, or other nodes in the data center) that are respectively connected to either a first or second input switching cell and either a first or second output switching cell. This can be provided by selectively coupling each of at least the first / second input switching cells to any output switching cell via one or more interconnect channels. This can be further provided by selectively coupling each of at least the first / second output switching cells to any input switching cell via one or more interconnect channels.

[0009] Due to the specific arrangement of switching cells and interconnect channels within the switching architecture, this invention provides a layout design applicable to large-scale, high-cardinality switching architectures. Advantageously, this invention provides a high-cardinality switching architecture within high-density and low-loss devices. In this case, the cardinality of the switching architecture is defined as the number of input / output ports of the switching architecture. Therefore, a high-cardinality switching architecture is ideal, enabling signal switching from / to a large number of ports. However, to achieve a scalable and high-cardinality switching architecture, the architecture needs to be designed with a high-density layout to ensure that a large number of switching cells can be constructed within a relatively small space.

[0010] More specifically, high-density integration is achieved through the arrangement of multiple additional swap cells in the intermediate columns between the input and output column arrays and in the adjacent input / output columns, as well as the way in which various swap cells in different columns are connected to each other.

[0011] Specifically, high-density integration is provided by arranging multiple additional switch cells in a plurality of column arrangements between the input column array and the output column array, wherein the input adjacent column is the column closest to the input column array, and the output adjacent column is the column closest to the output column array, and finally, there are multiple intermediate columns between the input adjacent column and the output adjacent column; and by directly connecting at least a first input switch cell and at least a second input switch cell of the input column array to a first switch cell of the input adjacent column (which is the column closest to the input column array) and a first intermediate switch cell of one of the multiple intermediate columns, respectively. The specific arrangement of these switch cells is mirrored with respect to the output switch cells of the output column array by directly connecting at least a first output switch cell and a second output switch cell to a second switch cell of the output adjacent column (which is the column closest to the output column array) and a second intermediate switch cell of one of the intermediate columns, respectively. However, it is worth noting that the layout of the connection channels connecting the input switch cells and the additional switch cells may differ from the layout of the connection channels connecting the output switch cells and the additional switch cells. For example, the number of crossovers between the connection channels connecting the input exchange cell and the corresponding additional exchange cell may differ from the number of channels connecting the output exchange cell and the corresponding additional exchange cell.

[0012] In this way, selective coupling between the first / second input (output) switching cell and the corresponding output (input) switching cell is provided in a compact layout, which is easier to manufacture and integrate with other components, such as switching network devices.

[0013] In some arrangements, each input switching cell has a first output port and a second output port, the first output port being directly connected to the switching cell in the adjacent input column, and the second output port being directly connected to a corresponding intermediate switching cell in one of the intermediate columns. In some arrangements, each output switching cell has a first input port and a second input port, the first input port being directly connected to the switching cell in the adjacent output column, and the second input port being directly connected to a corresponding intermediate switching cell in one of the intermediate columns.

[0014] In this way, each input switching cell and / or each output switching cell is directly connected via a port to one of the switching cells arranged in the column, which is placed between the input column array and the output column array.

[0015] In some arrangements, the additional swap cell includes an input layer of swap cells, wherein the input layer includes all swap cells directly connected to any input swap cell. In some examples, the additional swap cell also includes an output layer, which includes all swap cells directly connected to any output swap cell. In some examples, the input layer may include swap cells from at least two intermediate columns. In some examples, the output layer may include swap cells from at least two intermediate columns.

[0016] In existing systems, each cell layer is typically arranged in a single column. Therefore, in existing systems, the additional columns between the input and output column arrays are much longer than the input and output column arrays themselves, or at least have more cells. This results in wider gaps between the switching cells within the input and output columns, or gaps at the ends of the input and output columns, increasing the device footprint and reducing scalability. Some embodiments of the present invention allow all or most of the switching cells to be arranged in a rectangular array of switching cells such that the spacing between most of them does not exceed the spacing required to avoid crosstalk or excessive losses and to reduce the overall system footprint aspect ratio (i.e., the difference between the vertical and horizontal dimensions of the layout).

[0017] In some arrangements, multiple additional switching cells are arranged in multiple sub-cells, wherein each sub-cell includes NxN switching networks, each NxN switching network is a switching cell network and includes N input ports and N output ports, and each input port of each sub-cell can be selectively connected to any output port of the sub-cell through the switching cell network.

[0018] In this way, one or more input switching cells of the input column array can be selectively connected to one or more output switching cells of the output column array via one or more sub-units. For example, this can be achieved by directly connecting an input switching cell to one of the N input ports of a specific switching network for a particular sub-unit, while one or more of the N output ports of the same switching network are connected to one or more output switching cells of the output column array. Thus, an input switching cell connected to one of the N ports of the switching network can be selectively connected via a sub-unit to any one or more of the N output ports of the switching architecture, and therefore can be selectively connected to any one or more output switching cells connected to one or more of the N output ports of the switching architecture.

[0019] In some arrangements, the second output port of the input switching cell of the input column array can be directly connected to the corresponding intermediate switching cell via a first connection channel, wherein the first connection channel does not intersect with any of the multiple sub-cells. The first connection channel may be part of an interconnection channel.

[0020] In some arrangements, the second input port of the output switching cell of the output column array can be directly connected to the corresponding intermediate switching cell via a second connection channel, wherein the second connection channel does not intersect with any of the multiple sub-cells. The second connection channel may be part of an interconnect channel.

[0021] In this way, the channels connecting the corresponding input / output switching cells to the corresponding intermediate cells neither intersect nor overlap with any of the switching networks of the multiple sub-cells. For example, if the switching architecture is an optical switching architecture and the connecting channels are waveguides, then by not intersecting with any sub-cells, the waveguides will not intersect with any waveguides of the various switching cells of the NxN switching network connecting the sub-cells. Thus, crosstalk between the connecting channels and the switching network is minimized, or even zero.

[0022] In some arrangements, the swap cells of adjacent input columns and the swap cells of the corresponding middle columns belong to two different sub-cells. In some arrangements, the swap cells of adjacent output columns and the swap cells of the corresponding middle output columns belong to two different sub-cells.

[0023] In this way, the input exchange cell can be directly connected to two exchange cells located in different sub-cells (i.e., the exchange cell of the adjacent column and the exchange cell of the corresponding middle column).

[0024] In some arrangements, multiple sub-units can be divided into a first group of sub-units and a second group of sub-units, wherein the first group is arranged in columns adjacent to the input column array, and the second group is arranged in columns adjacent to the output column array. Thus, the switching network within each sub-unit can be arranged in a square or rectangular layout where the width-to-height ratio is closer to 1 than in a layout where all sub-units are arranged in a single column. Advantageously, the shape of this switching architecture layout is easy to manufacture and integrate with other devices.

[0025] In some arrangements, the input exchange cells of adjacent columns belong to the first sub-cell of a first group, and the corresponding intermediate exchange cells of intermediate columns belong to the second sub-cell of a second group. In this example, the first connection channel may extend around the first sub-cell without intersecting with it. For example, the first connection channel may be designed to run along one side of the first sub-cell.

[0026] In some arrangements, the output exchange cells of adjacent columns belong to the third sub-cell of the second group, and the corresponding intermediate exchange cells of the middle columns belong to the fourth sub-cell of the first group. In this example, the second connection channel can extend around the fourth sub-cell without intersecting with it. For example, the second connection channel can be designed to be positioned along one side of the first sub-cell.

[0027] In some arrangements, each input switching cell can be selectively connected to any output switching cell via one or more intermediate switching cells, and any output switching cell can be selectively connected to any input switching cell.

[0028] In some configurations, the switching architecture is non-blocking, allowing any of the multiple input switching cells to selectively connect to any output switching cell via a minimum possible number of switching cells and interconnects. Therefore, the number of unused interconnects and switching cells is minimized. In this case, "unused" means not used at any given time to connect an input switching cell to its corresponding output switching cell.

[0029] In some arrangements, the switching architecture is bidirectional. In this way, a signal (e.g., an optical signal in the case of an optical switching architecture) can propagate along the same path within the switching architecture from an input switching cell to a specific output switching cell, and vice versa.

[0030] In some arrangements, each of the multiple sub-units includes one of the following: a dilated Banyan switching network, a switch and selectswitching network, a double-layer switching network, a Benes switching network, or a dilated Benes switching network. The sub-units preferably include the same type of switching network (e.g., each sub-unit is a dilated Banyan switching network). The type of switching architecture chosen for the sub-unit depends on which attributes are preferred.

[0031] In some arrangements, the switching architecture is an optical switching architecture, such that each of the switching cells includes an optical switch, and each connection channel between the switching cells includes a waveguide. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of a switching architecture according to an embodiment of the present invention;

[0033] Figure 2 yes Figure 1 A schematic diagram of the switching architecture shown;

[0034] Figure 3 This is a schematic diagram of a switching architecture according to an embodiment of the present invention;

[0035] Figure 4 This is a schematic diagram of a switching architecture according to an embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram of various types of optical switches that form part of a switching architecture according to an embodiment of the present invention;

[0037] Figure 6 This is a schematic diagram of a switching architecture according to an embodiment of the present invention;

[0038] Figure 7 This is a schematic diagram of a switching architecture including a nested switching architecture with a low cardinality, according to an embodiment of the present invention; and

[0039] Figure 8 This is a schematic diagram of a switching architecture according to an embodiment of the present invention. Detailed Implementation

[0040] Reference Figure 1 The switching architecture 100 includes: an input column array 110 with four input switching cells 110a-d; an output column array 160 with four output switching cells 160a-d; and multiple additional switching cells arranged in multiple columns 120, 130, 140, and 150. The switching architecture 100 also includes multiple interconnect channels (such as 40, 41, 42, and 43) that directly connect pairs of additional switching cells. For simplicity, in... Figure 1 In this example, only four interconnects 40 to 43 are labeled. Multiple columns are located between the input column array 110 and the output column array 160. More specifically, the multiple columns include the input adjacent column 120 closest to the input column array 110 (i.e., adjacent to the input column array), the output adjacent column 150 closest to the output column array 160 (i.e., adjacent to the output column array), and two intermediate columns 130 and 140 positioned between the input adjacent column 120 and the output adjacent column 150. Each column includes multiple swap cells. More specifically, intermediate columns 130 and 140 include multiple intermediate swap cells 130a-d and 140a-d, respectively; the input adjacent column includes four (input adjacent) swap cells 120a-d; and the output adjacent column includes four (output adjacent) swap cells 150a-d. In this example, each column includes four swap cells, but other numbers of swap cells and intermediate columns are also possible.

[0041] Each input switching cell 110a-d is selectively coupled to one of the output switching cells 160a-d via one or more interconnect channels of the switching architecture 100. Each output switching cell 160a-d is selectively coupled to one of the input switching cells 110a-d via one or more interconnect channels of the switching architecture 100.

[0042] The switching architecture 100 has an extended banyan tree architecture, the structure of which is described in this paper.

[0043] Each switching cell in the switching architecture 100 can be in one of two switching states: parallel switching and cross-connect switching. The functional effects of the parallel switching and cross-connect switching states depend on which port of the switching cell is idle. For example, refer to... Figure 2 Switching cell 120a has an idle input port, but both output ports are in use. When switching cell (e.g., switching cell 120a) is in parallel switching state, the used (or "first") input port of switching cell 120a (e.g., 120a-11 in this case) is connected to the first output port (120a-21) of switching cell 120a. The second input port of switching cell is idle (i.e., not connected to anything, therefore unused). When switching cell 120a is in cross-switching state, the first input port 120a-11 of switching cell 120a is connected to the second output port 120a-22 of switching cell 120a. The second input port of switching cell remains idle. Similarly, switching cell (e.g., 150a) has an idle output port, but both input ports are in use. In this case, the parallel state of switching cell 150a is provided when the first input port is connected to the first (and not idle) output port. When the second input port is connected to the first (and non-idle) output, it provides the crossover state of the switching cell 150a.

[0044] Each swap cell can switch between parallel and cross states, and vice versa. When one of the input ports is idle, the swap cell operates as a 1x2 swap cell and can be defined as such. When one of the output ports is idle, the swap cell operates as a 2x1 swap cell and can be defined as such. In each case, these can be replaced by other forms of 1x2 or 2x1 swap cells.

[0045] For example, if the switching architecture is optical, then the switching cell can be as follows: Figure 5 The examples shown are programmable unit cells (PUCs) with optical switches. In this case, each PUC can be controlled by external circuitry to switch the corresponding optical switch from one state to another. In some examples, one of the input ports and / or one of the output ports of a particular switching cell may not be used (i.e., it may not be connected to any other ports). For example, see reference... Figure 2 (shown) Figure 1The same switching architecture 100 applies to input switching cell 110a, which has two input ports 110a-11 and 110a-12, and two output ports 110a-21 and 110a-22. When input switching cell 110a is in parallel mode, input port 110a-11 is directly connected to output port 110a-21, and input port 110a-12 is connected to output port 110a-22. In crossover mode, input port 110a-11 is connected to output port 110a-22, and input port 110a-12 is connected to output port 110a-21. In this example, input port 110a-12 is not used (i.e., it is not connected to any other port and therefore does not receive or transmit any signals). The detailed description of switching cell 110a also applies to any other switching cell in switching architecture 100.

[0046] Reference Figure 1 and Figure 2 Input switching cell 110a has a first output port 110a-21 and a second output port 110a-22. The first output port 110a-21 is directly connected to the first input port 120a-11 of the switching cell 120a in the adjacent column 120, and the second output port 110a-22 is directly connected to the first input port 120c-11 of the corresponding intermediate switching cell 120c. Input switching cell 110b has a first output port 120c-21 and a second output port 120c-22. The first output port 120c-21 is directly connected to the first input port 120b-11 of switching cell 120b, and the second output port 120c-22 is directly connected to the first input port 120d-11 of intermediate switching cell 120d. Two other input switching cells 110c-d are directly connected to the corresponding intermediate switching cells in the intermediate column 140, similar to the detailed description of switching cells above. More specifically, the input switching cell 110c has a first output port 110c-21 and a second output port 110c-22. The first output port 110c-21 is directly connected to the first input port 140a-11 of the intermediate switching cell 140a, and the second output port 110c-22 is connected to the first input port 140c-11 of the intermediate switching cell 140c.

[0047] Output switching cell 160a has a first input port 160a-11 and a second input port 160a-12. The first input port 160a-11 is directly connected to the first output port 130a-21 of intermediate switching cell 130a, and the second input port 160a-12 is directly connected to the first output port 150a-21 of switching cell 150a. Output switching cell 160b has a first input port 160b-11 and a second input port 160b-12. The first input port 160b-11 is directly connected to the first output port 130b-21 of intermediate switching cell 130b, and the second input port 160b-12 is directly connected to the first output port 150b-21 of switching cell 150b. Output switching cell 160c has a first input port 160c-11 and a second output port 160c-21. The first input port 160c-11 is directly connected to the first output port 130c-21 of switching cell 130c, and the second output port 160c-21 is directly connected to the first output port 150c-11 of switching cell 150c. Finally, output switching cell 160d has a first input port 160d-11 and a second input port 160d-12. The first input port 160d-11 is directly connected to the first output port 130d-21 of switching cell 130d, and the second input port 160d-12 is connected to the second output port 150d-22 of switching cell 150d.

[0048] Reference Figure 1 and Figure 2 The switching cells arranged in columns 120 to 150 are also arranged within four sub-units 122, 124, 126, and 128. In this case, each sub-unit includes a 2x2 switching network. Each switching network includes two input switching cells and two output switching cells. Each input / output switching cell includes two input ports and two output ports. As will be described in more detail later, one of the two input ports of the input switching cell in each sub-unit is idle. As will be described in more detail later, one of the two output ports of the output switching cell in each sub-unit is idle. Therefore, in this case, each sub-unit has four input ports and four output ports. Two of the four input / output ports are idle, as will be described in more detail later. For example, as... Figure 2As shown, subunit 122 has two input switching cells 120a and 120b, and two output switching cells 130a and 130b. In subunit 122, only two of the four input ports (120a-11 and 120b-11) are used, i.e., connected to the other output port of another switching cell. The same applies to the output ports: only two output ports (130a-21 and 130b-21) are used, i.e., connected to the other input port of another switching cell. Each of the two input ports (120a-11 and 120b-11) of the input switching cells 120a and 120b of subunit 122 can be selectively connected to any one of the two output ports (130a-21 and 130b-21) of the output switching cells 130a and 130b of subunit 122. A similar description applies to all other subunits 124, 126, and 128. In this example, each switching network is a 2x2 dilated banyan, but other network architectures are possible. For individual switching cells, each sub-cell 122 to 128 can be in one of two states: a parallel sub-cell state and a cross-sub-cell state. For example, when sub-cell 122 is in the parallel sub-cell state, input switching cell 120a is connected to output switching cell 130a, and input switching cell 120b is connected to output switching cell 130b. However, when in the cross-sub-cell state, input switching cell 120a is connected to output switching cell 130b, and input switching cell 120b is connected to output switching cell 130a. Each sub-cell can switch from the parallel sub-cell state to the cross-sub-cell state, and vice versa. Thus, the switching architecture 100 has multiple switching states. In each of these switching states, each of the input switching cells 110a-d is connected to a corresponding one of the output switching cells 160a-d through a specific combination of sub-cells in a specific sub-cell state (crossed, parallel, or a mixture of both), and each individual switching cell is in one of the parallel or crossed states. In other words, the specific switching state of the switching architecture 100 is determined by the specific state of each switching cell and each sub-cell.

[0049] The advantage of providing multiple switching states through sub-cells 122 to 128 is a significant reduction in first-order crosstalk. These sub-cells are arranged as a 2x2 extended banyan tree, rather than using a 2x2 cell where all ports are used and there is no free space. First-order crosstalk occurs between signals simultaneously input to two ports of the same switching cell and has the effect of power leakage from one port to the other. By leaving one of the input / output ports of the switching cell free, first-order crosstalk is reduced, and therefore, the undesirable mixing of two signals input to two different ports is also reduced.

[0050] In this example, such as Figure 1 and Figure 2 As shown, four sub-units 122 to 128 are divided into a first group and a second group. Sub-units 122 and 126 belong to the first group, while sub-units 124 and 128 belong to the second group. The first group, containing sub-units 122 and 126, is arranged in a column adjacent to the input column array 110, and the second group, containing sub-units 124 and 128, is arranged in a column adjacent to the output column array 160. In this particular example, each input switching cell 110a-d is adjacent to a switching cell of one of sub-units 122 and 126. Each output switching cell 160a-d is adjacent to a switching cell of one of sub-units 124 and 128. For example, sub-unit 122 includes switching cells 120a, 120b, 130a, and 130b. Input switching cell 110a is adjacent to switching cell 120a, and input switching cell 110b is adjacent to switching cell 120b. A similar description applies to all other input / output switching cells 110c-d and 160a-d.

[0051] refer to Figure 2 This illustrates an example of how switching architecture 100 operates to selectively connect input switching cell 110a to output switching cell 160a or output switching cell 160b. A signal 101 received at a first input port 110a-11 of input switching cell 110a can be routed via path 1 to output port 160a-21 of output switching cell 160a, or via path 2 to output port 160b-21 of output switching cell 160b. If switching architecture 100 is an optical switching architecture, signal 101 can be an optical signal.

[0052] Both Path 1 and Path 2 are formed by specific state combinations of the various exchange cells and sub-units involved.

[0053] Path 1 in Figure 2The diagram is shown with dotted lines. Path 1 includes multiple interconnect channels that directly connect pairs of switch cells. For example, one interconnect channel is one that directly connects the first output port 110a-21 of input switch cell 110a to the first input port 120a-11 of switch cell 120a. In Path 1, input switch cell 110a is in a parallel state because the first input port 110a-11 is connected to the first output port 110a-21. In Path 1, the first output port 110a-21 of input switch cell 110a is directly connected to the input port 120a-11 of switch cell 120a in sub-unit 122. Switch cell 120a is also part of the input adjacent column 120. In this configuration, switch cell 120a is in a parallel state because the input port 120a-11 is connected to the first output port 120a-21. The first output port 120a-21 of switch cell 120a is directly connected to the first input port 130a-11 of switch cell 130a. Switch cell 130a is in a parallel state because the first input port 130a-11 is directly connected to the output port 130a-21. Switch cell 130a is one of the intermediate switch cells in intermediate column 130. The output port of intermediate switch cell 130a is directly connected to the first input port 160a-11 of output switch cell 160a via first connection channel 10. First connection channel 10 does not intersect with any of sub-cells 122 to 128. First connection channel 10 does not intersect with any component of switch architecture 100. First connection channel 10 is designed to extend around sub-cell 124 along one side of sub-cell 124. Switch cell 160a is in a parallel state because the first input port 160a-11 is connected to the first output port 160a-21.

[0054] Through path 1, signal 101 propagates from the first input port 110a-11 of input switching cell 110a to the first output port 160a-21 of output switching cell 160a. Path 1 is obtained by programming each switching cell (i.e., 120a and 130a) involved in forming this connection into a parallel state. Similarly, subcell 122 is programmed into a parallel subcell state because the first input switching cell 120a of subcell 122 is connected to the first output switching cell 130a of subcell 122.

[0055] Path 2 in Figure 2The path shown in dashed lines is an alternative to path 1. Path 2 is obtained by programming the swap cell into different states, as described in detail below. In path 2, input swap cell 110a is in a parallel state, as in path 1. The first output port 110a-21 of input swap cell 110a is directly connected to the input port 120a-21 of swap cell 120a in sub-unit 122. Swap cell 120a is also part of the input adjacent column 120. In this configuration, swap cell 120a is in a crossover state because the input port 120a-21 of swap cell 120a is connected to the second output port 120a-22 of swap cell 120a. The second output port 120a-22 of swap cell 120a is directly connected to the first input port 130b-11 of swap cell 130b. Switching cell 130b is in a parallel state because its first input port 130b-11 is connected to its first output port 130b-21. Switching cell 130b is one of the intermediate switching cells in intermediate column 130. The first output port 130b-21 of intermediate switching cell 130b is directly connected to the first input port 160b-11 of output switching cell 160b via second connection channel 20. Second connection channel 20 does not intersect with any of sub-cells 122 to 128. Second connection channel 20 does not intersect with any component of switching architecture 100. Second connection channel 20 is designed to extend around sub-cell 124 along one side of sub-cell 124. Second connection channel 20 is arranged parallel to first connection channel 10, and its length extends along one side of sub-cell 124. The output switching cell 160b is in a parallel state because the first input port 160b-11 of the output switching cell 160b is connected to the first output port 160b-21 of the output switching cell 160b.

[0056] Through path 2, signal 101 propagates from the first input port 110a-11 of input switching cell 110a to the first output port 160-21 of output switching cell 160b. Path 2 is obtained by programming each switching cell (i.e., 120a and 130b) involved in forming this connection to a specific state. In particular, unlike path 1, switching cell 120a is programmed to a crossover state instead of a parallel state. Similarly, sub-cell 122 is programmed to be in a crossover sub-cell state because the first input switching cell 120a of sub-cell 122 is connected to the second output switching cell 130b of sub-cell 122.

[0057] The switching architecture 100 is bidirectional because each signal can propagate in opposite directions via a corresponding path. For example, signal 101 can propagate along path 1 from the first input port 110a-11 of input switching cell 110a to the first output port 160a-21 of output switching cell 160a, but it can also propagate along path 1 from the first output port 160a-21 of output switching cell 160a to the first input port 110a-11 of input switching cell 110a (in this case, the input port is used as the output port, and the output port is used as the input port). This also applies to any other path including path 2 and... Figure 2 Any other paths not detailed in the text.

[0058] Despite Figure 2 Only two possible paths are highlighted and described in detail, but many alternative paths can selectively connect different input switching cells 110a-d to any output switching cell 160a-d. A particular path is determined by the configuration of each switching cell involved and can be changed by altering the configuration of one or more of the switching cells involved in forming the path, as described in the example above.

[0059] exist Figure 1 and Figure 2 In the example, each of the output ports of input switching cells 110c and 110d is directly connected to one of the intermediate switching cells (in this case, belonging to intermediate switching column 140). Each connection is via a connection channel that does not overlap (intersect) with any other switching cell in the adjacent input column 120 or intermediate column 130. The various connection channels are arranged along one side of sub-cell 126, neither overlapping nor intersecting with said sub-cell 126. Some connection channels intersect each other. The number of intersection points between different connection channels is minimized to minimize crosstalk between connection channels.

[0060] The switching cell of the switching architecture 100 includes an input layer and an output layer.

[0061] The input layer includes all switching cells directly connected to any input switching cells 110a-d. The input layer includes all input switching cells of all sub-units of the switching architecture 100. More specifically, the input layer includes input adjacent switching cells 120a-d of input adjacent columns 120, where 120a-b belong to sub-unit 122, and 120c-d belong to sub-unit 126 (see reference). Figure 1 and Figure 2 The input layer also includes intermediate exchange cells 140a-d of intermediate column 140, where 140a-b belong to sub-cell 124 and 140c-d belong to sub-cell 128.

[0062] The output layer includes all switch cells directly connected to any output switch cells 160a-d. The output layer includes all output switch cells forming all sub-units of the switching architecture 100. More specifically, the output layer includes output adjacent switch cells 150a-d of output adjacent columns 150, where 150a-b belong to sub-unit 124, and 150c-d belong to sub-unit 128 (see reference). Figure 1 and Figure 2 The output layer also includes intermediate exchange cells 130a-d, where 130a-b belong to sub-cell 122 and 130c-d belong to sub-cell 126.

[0063] The switching architecture 100 is a 4x4 switching network architecture (i.e., having 4 input cells and 4 output cells), and it is formed by 4 2x2 switching network architectures, which are grouped such that the switching cells of the switching architecture 100 are arranged in a rectangular matrix.

[0064] Reference Figure 3 An embodiment of a switching architecture 200 is illustrated. The switching architecture 200 is arranged in a two-tier architecture, which will be described herein. The switching architecture 200 includes an input column array 210 of eight input switching cells 210a-h, an output column array 260 of eight output switching cells 260a-h, and multiple additional switching cells arranged in multiple columns. The switching architecture also includes multiple interconnect channels that directly connect pairs of additional switching cells, similar to... Figure 1 and Figure 2 The interconnection channels of the switching architecture 100 are shown. Multiple columns are located between the input column array 210 and the output column array 260. More specifically, the multiple columns include the input adjacent column 220 closest to the input column array 210 (i.e., adjacent to the input column array), the output adjacent column 250 closest to the output column array 260 (i.e., adjacent to the output column array), and four intermediate columns 130, 132, 134, and 140 disposed between the input adjacent column 220 and the output adjacent column 250. Each column includes multiple switching cells. Each switching cell can be in a parallel or crossover state, similar to the detailed description of the switching architecture 100. Intermediate columns 230 to 140 each include multiple intermediate switching cells 130a-h to 140a-h, the input adjacent column includes eight (input adjacent) switching cells 220a-h, and the output adjacent column includes eight (output adjacent) switching cells 250a-h. In this example, each column includes eight switching cells.

[0065] Each of the input switching cells 210a-h is selectively coupled to one of the output switching cells 260a-h via one or more interconnect channels of the switching architecture 200. Each of the output switching cells 260a-h is selectively coupled to one of the input switching cells 210a-h via one or more interconnect channels of the switching architecture 200.

[0066] The switching cells arranged in columns 220 to 250 are also arranged within four sub-units 222, 224, 226, and 228. In this case, each sub-unit includes a 4x4 switching network. Each 4x4 switching network includes four input switching cells and four output switching cells. Each input / output switching cell includes two input ports and two output ports. Therefore, in this case, the sub-unit has eight input ports and eight output ports. However, similar to the sub-units of switching architecture 100, not all input / output ports of sub-units 222 to 228 are used, i.e., not directly connected to any other port. For example, sub-unit 222 only has four input ports (220a-11 to 220d-11) and four output ports (232a-21 to 232d-21) in use. More specifically, the first input ports (220a-11 to 220d-11) of the input switching cells 220a-d and the first output ports (232a-21 to 232d-21) of the output switching cells 232a-d of column 220 are in use, while the second input ports (not labeled for simplicity) of the input switching cells 220a-d and the second output ports (not labeled for simplicity) of the output switching cells 232a-d of column 220 are not in use.

[0067] Some of the switching cells in this arrangement are 2x2 switching cells. For example, switching cells 230a-h are 2x2 switching cells. This means that both inputs and outputs are in use. In other words, these switching cells have no free input / output ports. On the other hand, switching cells 220a-h are examples of 1x2 switching cells (i.e., they have free input ports and both output ports are in use). Switching cells 232a-h are examples of 2x1 switching cells (i.e., they have free output ports and both input ports are in use).

[0068] Each input switching cell of each subunit can be selectively connected to any one of the four output switching cells of the subunit. For example, each of the first input ports 220a-11 to 220d-11 of the respective input switching cells 220a-d of subunit 222 can be selectively connected to any one of the first output ports 232a-21 to 232d-21 of the respective output switching cells 232a-d of intermediate columns 230 and 232, respectively. In this example, each switching network is a 4x4 two-layer architecture, but other network architectures are also possible. Similar to that described for subunits 122 to 128 of switching architecture 100, subunits 222 to 228 can also be in different subunit states. Each subunit state corresponds to a specific combination of switching cells forming a subunit in a parallel or cross state. Each subunit state corresponds to a specific input port of an input switching cell coupled to a specific corresponding output port of an output switching cell of the subunit.

[0069] In this example, each input switching cell 210a-d has a first output port 210a-21-210d-11 of the corresponding input switching cell 220a-11 to 220d-11, which is directly connected to the corresponding first input port of the corresponding switching cell 220a-11 of the adjacent column 220. Each of the same input switching cells 210a-d also has a second output port (not labeled for simplicity), which is directly connected via a corresponding connection channel to the corresponding input port (also not labeled for simplicity) of the intermediate switching cell of the intermediate column 234. This connection channel extends between sub-cells 222 and 226 without overlapping or intersecting with any switching cell of sub-cells 222 and 226. The corresponding connection channels are arranged parallel to each other along the sides of sub-cells 222 and 226 without overlapping each other. The connection channels further extend toward the corresponding intermediate switching cell to which they are connected. The above configuration is mirrored for input switching cells 210e-h. Each input switching cell 210e-h has a first output port, which is directly connected to the corresponding intermediate switching cell 234e-h of the intermediate column 234 via a corresponding connection channel that does not intersect, overlap, or intersect with any sub-cells. These corresponding connection channels are arranged parallel to each other between the sides of sub-cells 222 and 226. Each input switching cell 210e-h has a second output port, which is directly connected to the switching cell 220e-h of the input adjacent column 220. A similar arrangement is shown for the output switching cells 160a-h. In this case, at some points, there is overlap between the connection channel connecting the intermediate switching cell 232a-h of the intermediate column 232 to the output switching cell 160a-h and the connection channel directly connecting the switching cell 250a-h of the output adjacent column 250 to the output switching cell 260a-h.

[0070] Sub-units 222 and 226 are part of a first group arranged in columns adjacent to the input column array. Sub-units 224 and 228 are part of a second group arranged in columns adjacent to the output column array 228.

[0071] Each input switching cell 210a-h can be selectively connected to any output switching cell 260a-h via one or more intermediate switching cells distributed in the switching network within sub-units 222 to 228, and any output switching cell 260a-h can be selectively connected to any input switching cell 210a-h.

[0072] The switching cells of switching architecture 200 also include an input layer for the switching cells. The input layer includes all switching cells directly connected to any input switching cells 210a-h. The input layer includes all input switching cells of all sub-units of switching architecture 200. In this particular case, the input layer includes all eight switching cells 220a-h of the adjacent column 220, where 220a-d belong to sub-unit 222 and 220e-h belong to sub-unit 226. The input layer also includes intermediate switching cells 234a-h of the intermediate column 234, where 234a-d are input switching cells of sub-unit 224 and 234e-h are input switching cells of sub-unit 228.

[0073] The switching cells of switching architecture 200 also include an output layer. The output layer includes all switching cells directly connected to any output switching cells 260a-h. The output layer includes all output switching cells forming all sub-units of switching architecture 200. In this particular case, the output layer includes all eight switching cells 250a-h of the output adjacent column 250, where 250a-d are the output switching cells of sub-unit 224, and 250e-h are the output switching cells of sub-unit 228. The output layer also includes intermediate switching cells 232a-h of the intermediate column 232, where 232a-d are the output switching cells of sub-unit 222, and 232e-h are the output switching cells of sub-unit 226.

[0074] The switching architecture 200 is non-blocking, allowing any one of the multiple input switching cells 220a-h to be selectively connected to any output switching cell 260a-h, with the fewest possible switching cells and interconnect channels. Therefore, the number of unused interconnect channels and switching cells is minimized. In this case, "unused" means not used at any given time to connect an input switching cell to its corresponding output switching cell.

[0075] Furthermore, the switching architecture 200 is bidirectional because each signal can propagate in the opposite direction through a corresponding path, as shown in the switching architecture 100, and more specifically, as... Figure 2 The paths 1 and 3 are shown.

[0076] The switching architecture described in this article can be a building block for creating larger switching architectures with a higher cardinality (i.e., more input / output switching cells). For example, Figure 1 The switching architecture 100 can be a building block for sub-units of a switching architecture similar to switching architecture 200 (e.g., each of sub-units 222 to 228 can be formed by switching architecture 100). Thus, the switching architecture can be formed by a nested structure of switching networks that iteratively repeat in a scalable manner to form higher cardinality architectures.

[0077] Figure 4 An example of a switching architecture 300 is shown, which is designed as an extended banyan tree switching architecture. Switching architecture 300 is an optical switching architecture. The switching cells include optical switches, and the connection channels between different optical switches are waveguides. The arrangement of the various switching cells and their interconnections has a [specific characteristic / relevance]. Figure 3 The structural components of the shown switching architecture 200 are similar (but not identical). Advantageously, the optical switching architecture 300 can be used within an all-optical network system, i.e., to provide optical links between multiple servers or nodes. For example, the optical switching architecture 300 can be used for intra-data center connectivity, i.e., to selectively route multiple optical signals between different elements within the data center (such as servers, racks, GPUs, or other nodes in the data center). This can be achieved by controlling multiple optical switching cells to route optical signals from any input switching cell to any output switching cell. Each of the input and output switching cells can be (directly or indirectly) coupled to an optical fiber or other type of connector that connects to different servers or other nodes in the data center. Thus, optical signals can be routed through corresponding processing channels from a first server within the data center to a first receiving server, a second receiving server, or another network element within the data center.

[0078] Same reference Figure 5 The optical switches used in the switching architecture can be any suitable optical switches in the art, and in particular Figure 5 One of the examples 35a-d shown. Examples of optical switches may be 2x2 Mach-Zehnder interferometers (MZI) 35a, 1x2 MZI 35b, nested 2x2 MZI 35c, or double parallel 2x2 MZI 35d. Figure 4 The switching architecture shown includes Figure 5 The 2x2 MZI 35a functions as an optical switch. The 2x2 MZI includes a splitter 351a with two inputs and two outputs, two phase shifters 352'a and 352''a, and a combiner 354a with two inputs and two outputs. The output of each splitter is connected to the corresponding phase shifter input, and the output of each phase shifter is connected to the corresponding input of the combiner 354a. When the switching cell used in a particular switching architecture is a 1x2 or 2x1 cell (such as the extended banyan tree architecture previously described associated with switching architecture 100), it can be used... Figure 5 The same MZI, with an unused input or output port.

[0079] In other embodiments, it is also possible to use Figure 5The alternative optical switches are shown. The 1x2 MZI 35b is similar to the 2x2 MZI 35a, but the splitter 351b has only one input instead of two. The nested MZI 35c is a 2x2 MZI 35a, where one of the inputs of the splitter 351a and one of the outputs of the combiner 354a are coupled to the output and input ports of the other two combiners 351c and 354c, respectively. The dual-parallel 2x2 MZI 35d is formed by two 2x2 MZI 35a that receive optical signals from the “input” combiner 351d in parallel and send the optical signals to the “output” combiner 354d in parallel. Multiple combinations of optical switches are possible within the switching network in different sub-units (more generally, within the switching architecture 300). The state of the optical switches can be controlled and changed using standard techniques of programmable photonics.

[0080] Return to reference Figure 4 The waveguides connecting the pairs of optical switches can be silicon waveguides. Advantageously, silicon waveguides are characterized by high integration density and can provide more compact chip designs. At some points, two different waveguides may overlap, such as intersections 36 and 37. An intersection (or cross) is the point where two waveguides intersect at a 90-degree angle. Crosses are designed to minimize losses and crosstalk between the two waveguides. This is typically achieved by designing a specific width and shape for the cross.

[0081] Figure 6An optical switching architecture 400 is illustrated. The switching architecture 400 has an input column array and an output column array, each with 16 input switching cells (input optical switches) and 16 output switching cells (output optical switches), respectively. The switching architecture 400 also includes multiple columns arranged between the input and output column arrays. In this embodiment, some of the switching cells in the multiple columns are not aligned with the input and output switching cells (i.e., by treating the switching cells as part of a matrix, some switching cells are not in the same row as any input / output switching cells). The multiple columns are arranged in a switching network, which is arranged in sub-units characterized by a nested structure. In this example, the switching architecture includes four sub-units 422, 424, 426, and 428. Each sub-unit includes an 8x8 switching network comprising eight input switching cells and eight output switching cells. Sub-units 422 to 428 are arranged in a column between the input and output column arrays. Each sub-unit is also divided into sub-sub-units. More specifically, each subunit 422 to 428 comprises four sub-subunits. For example, subunit 422 comprises four sub-subunits 422a-d. Each sub-subunit comprises a 4x4 switching network, including four input switching cells and four output switching cells. The four subunits of each subunit are arranged in two groups: a first group comprising the columns of the two sub-subunits closest to the input adjacent columns; and a second group comprising the columns of the two sub-subunits closest to the output adjacent columns.

[0082] The interconnections between the switching cells of switching architecture 400 are similar to those described for switching architectures 100 to 300.

[0083] exist Figure 7 The optical switching architecture 600 is shown in the figure. The switching architecture 600 includes four switching architectures 500a-d, each of which has four input switching cells and four output switching cells. Figure 7 The diagram at the bottom shows the layout of each of the four switching architectures 500a-d. The nested switching architectures 500a-d are connected to the input array column 610 of the eight input switching cells 610a-h. The nested switching architectures 500a-d are also connected to the output array column 660 of the eight input switching cells 660a-h.

[0084] exist Figure 8The diagram illustrates two switching networks with alternative architectures different from the extended Benedictine network. More specifically, switching architecture 500 is a 4x4 Benedictine switching architecture, comprising an input column array of four switching cells and an output column array of four switching cells. Furthermore, each of the six columns of the two switching cells is arranged between the input and output column arrays. The six columns of the switching cells are divided into two sub-units, each sub-unit comprising a 2x2 Benedictine switching network. Switching architecture 600 is an extended Benedictine switching architecture. Each sub-unit is an extended Benedictine switching network.

[0085] Switching architectures can be created using varying numbers of input and output switching cells, as well as an increasing number of switching networks arranged in nested sub-cells. Although already described... Figures 1 to 4 and Figures 6 to 8 The switching network shown has a specific architecture (e.g., switching architecture 100 is an extended banyan tree), but alternative architectures for similar switching networks can be considered.

Claims

1. A switching architecture, comprising: An input column array, which comprises multiple input exchange cells; An output column array, which includes multiple output exchange cells; Multiple additional exchange cells and multiple interconnect channels, wherein the multiple interconnect channels are directly connected to pairs of the multiple additional exchange cells; in The plurality of additional exchange cells are arranged in a plurality of columns, the plurality of columns being located between the input column array and the output column array, and the plurality of columns including an input adjacent column closest to the input column array, an output adjacent column closest to the output column array, and a plurality of intermediate columns, wherein the intermediate columns are located between the input adjacent column and the output adjacent column; The first input swap cell is directly connected to the first swap cell of the adjacent input column, and the second input swap cell is directly connected to the first intermediate swap cell of one of the intermediate columns; The first output swap cell is directly connected to the second swap cell in the adjacent column of the output, and the second output swap cell is directly connected to the second intermediate swap cell in one of the intermediate columns.

2. The switching architecture according to claim 1, wherein, Each of the first input switching cell and the second input switching cell is arranged to be selectively coupled to any of the output switching cells via one or more of the interconnect channels; and Each of the first output switching cell and the second output switching cell is arranged to be selectively coupled to any of the input switching cells via one or more of the interconnect channels.

3. The switching architecture according to claim 1, wherein, Each input switching cell has a first output port and a second output port, the first output port being directly connected to the switching cell of the adjacent column of the input, and the second output port being directly connected to the corresponding intermediate switching cell of one of the intermediate columns.

4. The switching architecture according to any one of the preceding claims, wherein, Each output switching cell has a first input port and a second input port, the first input port being directly connected to the switching cell in the adjacent column of the output, and the second input port being directly connected to the corresponding intermediate switching cell in one of the intermediate columns.

5. The switching architecture according to any one of the preceding claims, wherein, The additional swap cell includes an input layer for the swap cell, wherein the input layer includes all swap cells directly connected to any of the input swap cells; Furthermore, the additional switching cell also includes an output layer, which comprises all switching cells directly connected to any of the output switching cells; The input layer includes swap cells from at least two of the intermediate columns; and The output layer includes swapped cells from at least two of the intermediate columns.

6. The switching architecture according to any one of the preceding claims, wherein, The plurality of additional switching cells are arranged in a plurality of sub-units, wherein each sub-unit includes an NxN switching network, wherein each NxN switching network is a switching cell network and includes N input ports and N output ports, wherein each input port of each sub-unit can be selectively connected to any output port of the sub-unit through the switching cell network.

7. The switching architecture according to claim 6 when subordinate to claim 3, wherein, The second output port is directly connected to the corresponding intermediate switching cell through the first connection channel, wherein the first connection channel is one of the interconnect channels; and The first connection channel does not intersect with any of the plurality of sub-units.

8. The switching architecture according to claim 6 or 7 when subordinate to claim 4, wherein the second input port is directly connected to the corresponding intermediate switching cell via a second connection channel, wherein the second connection channel is one of the interconnect channels; and in, The second connection channel does not intersect with any of the plurality of sub-units.

9. The switching architecture according to any one of claims 6 to 8, wherein: (i) When subordinate to claim 2, the exchange cell of the adjacent input column and the exchange cell of the corresponding intermediate column belong to two different sub-units; (ii) When subordinate to claim 3, the swap cell of the adjacent output column and the swap cell of the corresponding intermediate column belong to two different sub-units.

10. The switching architecture according to any one of claims 6 to 9, wherein, The plurality of sub-units are divided into a first group of sub-units and a second group of sub-units, wherein the first group is arranged in a column adjacent to the input column array, and the second group is arranged in a column adjacent to the output column array.

11. The switching architecture of claim 10 when subordinate to claim 9 (i), wherein the input switching cells of the adjacent input columns belong to the first sub-unit of the first group, and the corresponding intermediate switching cells of the intermediate columns belong to the second sub-unit of the second group; and wherein the first connection channel extends around the first sub-unit without intersecting the first sub-unit.

12. The switching architecture of claim 10 when subordinate to claim 9 (ii), wherein the output switching cells of the adjacent output columns belong to the third sub-unit of the second group, and the corresponding intermediate switching cells of the intermediate columns belong to the fourth sub-unit of the first group; and wherein the second connection channel extends around the fourth sub-unit without intersecting the fourth sub-unit.

13. The switching architecture according to any one of the preceding claims, wherein, Each input switching cell can be selectively connected to any output switching cell via one or more of the intermediate switching cells, and any output switching cell can be selectively connected to any input switching cell.

14. The switching architecture according to any one of the preceding claims, wherein, The switching architecture is non-blocking, enabling any of the plurality of input switching cells to be selectively connected to any output switching cell via a minimum possible number of switching cells and interconnect channels.

15. The switching architecture according to any one of the preceding claims, wherein the switching architecture is bidirectional.

16. The switching architecture according to any one of the preceding claims, wherein, Each of the plurality of sub-units includes one of the following: an extended banyan tree exchange network, an exchange and selection exchange network, a Benes exchange network, or an extended Benes exchange network.

17. The switching architecture according to any one of the preceding claims, wherein, The switching architecture is an optical switching architecture, such that each of the switching cells includes an optical switch, and each connection channel between the switching cells includes a waveguide.

Images