Semiconductor memory device

Abstract

The SRAM cell includes an active region (N3) and a power supply wiring (13). A readout drive transistor (RPD) is formed in the active region (N3), and the power supply wiring (13) is formed in a back surface wiring layer, has an overlapping portion with the active region (N3) in plan view, and supplies a power supply voltage VSS. A wiring (63) corresponding to a readout bit line (RBL) is formed in a metal wiring layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor memory device including a nanosheet FET (Field Effect Transistor), and more particularly to a layout structure of a dual-port SRAM (Static Random Access Memory) cell (hereinafter, appropriately referred to as a cell) using a nanosheet FET. Background Technology

[0002] SRAM is widely used in semiconductor integrated circuits. Two-port SRAM exists, which has one write port and one read port.

[0003] Furthermore, scaling down the gate length of transistors, a fundamental component of LSI (Liquid Crystal Interchange), has increased the integration density of semiconductor integrated circuits, reduced operating voltage, and improved operating speed. However, in recent years, excessive scaling has led to off-state leakage current, which in turn causes a significant increase in power consumption. To address this issue, researchers have begun actively studying three-dimensional transistors, which are obtained by changing the transistor structure from the existing planar type to a three-dimensional type. Nanosheet FETs, as one type of three-dimensional transistor, have attracted considerable attention.

[0004] A layout of a dual-port SRAM cell using nanosheet FETs is disclosed in Patent Documents 1 to 3.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: U.S. Patent Application Publication No. 2022 / 0328499

[0008] Patent Document 2: U.S. Patent Application Publication No. 2023 / 0017584

[0009] Patent Document 3: International Publication No. 2023 / 171452 Summary of the Invention

[0010] -The technical problem the invention aims to solve-

[0011] Here, Patent Documents 1 and 2 disclose the following technical content: Because the read bit line and write bit line are disposed on the same wiring layer, the wiring width of the bit line cannot be increased. As a result, the wiring resistance of the bit line increases, and the operating speed of the semiconductor memory device decreases. Furthermore, because the bit line and power wiring are disposed on the same wiring layer, the wiring width of the power wiring cannot be increased. Consequently, the wiring resistance of the power wiring increases, the power supply voltage drop increases, leading to a decrease in the operating speed and stability of the semiconductor memory device. Additionally, because the distance between the bit line and the power wiring becomes closer, the parasitic capacitance increases, further reducing the operating speed of the semiconductor memory device.

[0012] Furthermore, Patent Document 3 discloses the following technique: by separating the read bit lines, write bit lines, and power supply wiring into a buried wiring layer and an upper wiring layer, the wiring width of the wiring in the upper wiring layer is increased. However, since the wiring in the buried wiring layer cannot overlap with the transistor (nanosheet), the wiring width formed in the buried wiring layer cannot be increased. As a result, the wiring resistance increases, and the operating speed of the semiconductor memory device decreases.

[0013] The purpose of this disclosure is to improve the operating speed of a semiconductor memory device in a layout structure where wiring is arranged on the back side of a transistor in an SRAM cell.

[0014] - Technical solutions used to solve technical problems -

[0015] A first aspect of this disclosure is a semiconductor memory device comprising an SRAM cell. The SRAM cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The source of the first transistor is connected to a first power supply providing a first power supply voltage. The drain of the first transistor is connected to a first node. The gate of the first transistor is connected to a second node. The source of the second transistor is connected to the first power supply. The drain of the second transistor is connected to a second node. The gate of the second transistor is connected to the first node. The source of the third transistor is connected to a second power supply providing a second power supply voltage. The drain of the third transistor is connected to the... The first node is connected, the gate of the third transistor is connected to the second node, wherein the second power supply voltage is different from the first power supply voltage, the source of the fourth transistor is connected to the second power supply, the drain of the fourth transistor is connected to the second node, and the gate of the fourth transistor is connected to the first node, the source of the fifth transistor is connected to the first write bit line, the drain of the fifth transistor is connected to the first node, and the gate of the fifth transistor is connected to the write word line, the source of the sixth transistor is connected to the second write bit line, the drain of the sixth transistor is connected to the second node, and the gate of the sixth transistor is connected to the first write bit line. The SRAM cells are connected to write word lines, wherein the second write bit line and the first write bit line form a complementary bit line pair. The source of the seventh transistor is connected to the second power supply, and the gate of the seventh transistor is connected to the second node. The source of the eighth transistor is connected to the read bit line, and the drain of the eighth transistor is connected to the drain of the seventh transistor. The gate of the eighth transistor is connected to the read word line. The read bit line includes a first wiring layer formed on a metal wiring layer above the first transistor to the eighth transistor, extending in a first direction and connected to the source of the eighth transistor. The SRAM cell includes a first active region. The first power supply wiring and the first via are provided. The first active region constitutes the channel, source, and drain of the seventh transistor and contains a seventh nanosheet extending in the first direction as the channel. The first power supply wiring is formed on the back side of the wiring layer (i.e., the back wiring layer) of the first transistor to the eighth transistor, extends in the first direction, overlaps with the first active region when viewed from above, and is connected to the second power supply. The first via is formed in the region of the first active region that is the source of the seventh transistor and overlaps with the first power supply wiring, and connects the source of the seventh transistor in the first active region to the first power supply wiring.

[0016] According to this disclosure, a first power supply wiring connected to a second power supply is formed on a back wiring layer. A first wiring corresponding to a read bit line is formed on a metal wiring layer. This increases the wiring width of the first wiring formed on the metal wiring layer. As a result, wiring resistance of the bit line can be suppressed, thus improving the operating speed of the semiconductor memory device. Furthermore, the wiring width of the first power supply wiring formed in the buried wiring layer can be increased. As a result, wiring resistance of the power supply wiring can be suppressed, thereby suppressing power supply voltage drop, thus improving the operating speed and stability of the semiconductor memory device. Additionally, since the bit line and power supply wiring are formed on different wiring layers, the distance between the bit line and the power supply wiring can be increased. As a result, parasitic capacitance between the bit line and the power supply wiring can be suppressed, thus improving the operating speed of the semiconductor memory device. Furthermore, by forming the first power supply wiring connected to the second power supply on the back wiring layer, transistors constituting an SRAM cell and the first power supply wiring can be arranged overlappingly. This increases the wiring width of the first power supply wiring formed on the back wiring layer. As a result, wiring resistance of the wiring formed on the back wiring layer can be suppressed, thus improving the operating speed and stability of the semiconductor memory device.

[0017] A second aspect of this disclosure is a semiconductor memory device that includes an SRAM cell. The SRAM cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The source of the first transistor is connected to a first power supply providing a first power voltage; the drain of the first transistor is connected to a first node; and the gate of the first transistor is connected to a second node. The source of the second transistor is connected to the first power supply; the drain of the second transistor is connected to the second node; and the gate of the second transistor is connected to the first node. The source of the third transistor is connected to a second power supply providing a second power voltage; the drain of the third transistor is connected to the first node; and the gate of the third transistor is connected to the second node. The second power supply voltage is different from the first power supply voltage. The source of the fourth transistor is connected to the second power supply; the drain of the fourth transistor is connected to the second node; and the gate of the fourth transistor is connected to the first node. The source of the fifth transistor is connected to a first write bit line; the drain of the fifth transistor is connected to the first node; and the gate of the fifth transistor is connected to a write word line. The source of the sixth transistor is connected to a second write bit line; and the drain of the sixth transistor is connected to the second node. The gate of the sixth transistor is connected to the write word line, wherein the second write bit line and the first write bit line form a complementary bit line pair. The source of the seventh transistor is connected to the second power supply, and the gate of the seventh transistor is connected to the second node. The source of the eighth transistor is connected to the read bit line, and the drain of the eighth transistor is connected to the drain of the seventh transistor. The gate of the eighth transistor is connected to the read word line. A first power supply wiring is formed on a metal wiring layer above the first transistor to the eighth transistor. The first power supply wiring extends in a first direction and connects to the second power supply and the seventh transistor. The source of the SRAM is connected to the read bit line, which includes a first wiring layer. The first wiring layer is formed on the back side of the wiring layer from the first transistor to the eighth transistor, i.e., the back wiring layer, and extends in the first direction. The SRAM cell includes a first active region and a first via. The first active region constitutes the channel, source, and drain of the eighth transistor and contains an eighth nanosheet extending in the first direction as the channel. The first via is formed in the region of the first active region that becomes the source of the eighth transistor and overlaps with the first power wiring, and connects the source of the eighth transistor in the first active region to the first power wiring.

[0018] According to this disclosure, a first wiring corresponding to a read bit line is formed on the back wiring layer. A first power supply wiring connected to a second power supply is formed on the metal wiring layer. This increases the wiring width of the first wiring formed on the back wiring layer. As a result, the wiring resistance of the bit line can be suppressed, thus improving the operating speed of the semiconductor memory device. Furthermore, the wiring width of the first power supply wiring formed on the metal wiring layer can also be increased. As a result, the wiring resistance of the power supply wiring can be suppressed, thereby suppressing power supply voltage drop, thus improving the operating speed and stability of the semiconductor memory device. Additionally, since the bit line and power supply wiring are formed on different wiring layers, the distance between the bit line and the power supply wiring can be increased. As a result, parasitic capacitance between the bit line and the power supply wiring can be suppressed, thus improving the operating speed of the semiconductor memory device. Furthermore, by forming first wirings corresponding to read bit lines on the back wiring layer, transistors constituting an SRAM cell and the first wirings can be stacked overlapping. This increases the wiring width of the first wiring formed on the back wiring layer. As a result, the wiring resistance of the wiring formed on the back wiring layer can be suppressed, thus improving the operating speed and stability of the semiconductor memory device.

[0019] -The effects of the invention-

[0020] According to this disclosure, in the layout structure of SRAM cells with wiring arranged on the back side of transistors, the operating speed and stability of semiconductor memory devices are improved. Attached Figure Description

[0021] Figure 1 This is a top view showing an example of the layout structure of the SRAM cell according to the first embodiment.

[0022] Figure 2 This is a cross-sectional view showing an example of the layout structure of the SRAM cell according to the first embodiment.

[0023] Figure 3 This is a cross-sectional view showing an example of the layout structure of the SRAM cell according to the first embodiment.

[0024] Figure 4 This is a circuit diagram showing the structure of the SRAM cell according to the first embodiment.

[0025] Figure 5 These are other structural examples of the semiconductor integrated circuit device involved in the first embodiment.

[0026] Figure 6 This is a top view showing another example of the layout structure of the SRAM cell according to the first embodiment.

[0027] Figure 7This is a top view showing another example of the layout structure of the SRAM cell according to the first embodiment.

[0028] Figure 8 This is a top view showing another example of the layout structure of the SRAM cell according to the first embodiment.

[0029] Figure 9 This is a top view showing an example of the layout structure of the SRAM cell according to the second embodiment. Detailed Implementation

[0030] The embodiments will now be described with reference to the accompanying drawings. In the following embodiments, the semiconductor memory device includes a plurality of SRAM cells, at least a portion of which includes a nanosheet FET. A nanosheet FET is a FET that uses a thin sheet (nanosheet) for current flow. The nanosheet is formed, for example, from silicon. It should be noted that, in this disclosure, the transistors included in the SRAM cells are not limited to nanosheet FETs.

[0031] Additionally, in this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. Furthermore, expressions such as "same wiring width" indicating equal widths include manufacturing variations.

[0032] (First Implementation)

[0033] (Structure of an SRAM cell)

[0034] Figures 1 to 3 This is a diagram illustrating an example of the layout structure of the SRAM cell according to the first embodiment. Figure 1 (a) Figure 1 (b) is a top view. Figure 2 (a) to Figure 2 (c) and Figure 3 (a) Figure 3 (b) is a sectional view taken from a top-down perspective, showing a transverse section. Specifically, Figure 1 (a) shows the upper part of the cell in the M1 and M2 wiring layers. Figure 1 (b) shows the lower part of the cell, which is a layer below the M1 and M2 wiring layers and includes the nanosheet FET. Figure 2 (a) is a cross-section taken along line X1-X1'. Figure 2 (b) is a cross-section taken along line X2-X2'. Figure 2 (c) is a cross-section taken along line X3-X3'. Figure 3 (a) is a cross-section taken along line X4-X4'. Figure 3 (b) is a cross section taken along line X5-X5'.

[0035] It should be noted that in the following explanation, in Figure 1 In the top view, the vertical direction of the attached drawing is set as the Y direction (first direction), the horizontal direction of the attached drawing is set as the X direction (second direction), and the direction perpendicular to the substrate surface is set as the Z direction.

[0036] Figure 4 This is a circuit diagram illustrating the structure of the dual-port SRAM cell according to the first embodiment. (As shown...) Figure 4 As shown, a dual-port SRAM cell contains a dual-port memory cell circuit, which consists of load transistors PU1 and PU2, drive transistors PD1 and PD2, access transistors PG1 and PG2, read drive transistor RPD, and read access transistor RPG. Load transistors PU1 and PU2 are P-type FETs, while drive transistors PD1 and PD2, access transistors PG1 and PG2, read drive transistor RPD, and read access transistor RPG are N-type FETs.

[0037] Load transistor PU1 is positioned between the power supply voltage VDD and the first node NA, and drive transistor PD1 is positioned between the first node NA and the power supply VSS. The gates of both load transistor PU1 and drive transistor PD1 are connected to the second node NB, forming inverter INV1. Load transistor PU2 is positioned between the power supply voltage VDD and the second node NB, and drive transistor PD2 is positioned between the second node NB and the power supply VSS. The gates of both load transistor PU2 and drive transistor PD2 are connected to the first node NA, forming inverter INV2. In other words, the output of one inverter is connected to the input of another inverter, thus forming a latch.

[0038] Access transistor PG1 is positioned between write bit line WBL and the first node NA, and its gate is connected to write word line WWL. Access transistor PG2 is positioned between write bit line WBLB and the second node NB, and its gate is connected to write word line WWL. It should be noted that write bit lines WBL and WBLB form a complementary write bit line pair.

[0039] The source of the read drive transistor RPD is connected to the power supply VSS, the gate of the read drive transistor RPD is connected to the second node NB, and the drain of the read drive transistor RPD is connected to the source of the read access transistor RPG. The gate of the read access transistor RPG is connected to the read word line RWL, and the drain of the read access transistor RPG is connected to the read bit line RBL.

[0040] exist Figure 4In the memory cell circuit, when the write bit lines WBL and WBLB, which constitute a complementary write bit line pair, are driven to high and low levels respectively, and the write word line WWL is driven to high level, the high level is written to the first node NA, and the low level is written to the second node NB. On the other hand, when the write bit lines WBL and WBLB are driven to low and high levels respectively, and the write word line WWL is driven to high level, the low level is written to the first node NA, and the high level is written to the second node NB. Subsequently, when the write word line WWL is driven to low level after data has been written to both the first node NA and the second node NB, the latch state is determined, maintaining the data already written to the first node NA and the second node NB unchanged.

[0041] Furthermore, when the read bit line RBL is pre-charged to a high level and the read word line RWL is driven to a high level, the state of the read bit line RBL is determined based on the data written to the second node NB, thus enabling data to be read from the memory cell. Specifically, if the second node NB is high, the read bit line RBL is discharged to a low level. On the other hand, if the second node NB is low, the read bit line RBL remains high.

[0042] As described above, the dual-port SRAM cell has the functions of writing data to the dual-port SRAM cell, keeping the data in the dual-port SRAM cell unchanged, and reading data from the dual-port SRAM cell by controlling the write bit line WBL, WBLB, read bit line RBL, write word line WWL, and read word line RWL.

[0043] It should be noted that in the following explanation, in Figure 1 The dashed lines extending horizontally and vertically in the top view, and in Figure 2 In the isometric view, the dashed lines extending longitudinally represent a grid used for component placement during design. The grid is evenly spaced in both the X and Y directions. It should be noted that the grid spacing in the X and Y directions can be the same or different. Furthermore, it is acceptable for the grid spacing to vary between each layer. Also, components do not necessarily have to be placed on the grid.

[0044] In addition, Figure 1 In the top view, the dashed lines shown in a way that surrounds the cells represent the cell frame (outer edge of the SRAM cell). The SRAM cell is arranged such that its cell frame is connected to the cell frame of the cell adjacent to it in the X or Y direction.

[0045] In addition, Figure 1In the top view, cells with their X-direction inversions are arranged on both sides of the SRAM cell. Cells with their Y-direction inversions are also arranged on both sides of the SRAM cell.

[0046] like Figure 1 As shown in (b), a BM0 (Backside Metal 0) wiring layer and a BM1 (Backside Metal 1) wiring layer are formed on the back side of the semiconductor chip, and a transistor is formed on the semiconductor chip. The BM1 wiring layer is located below the BM0 wiring layer, i.e., at a distance from the transistor. It should be noted that both the BM0 and BM1 wiring layers are equivalent to backside wiring layers.

[0047] In the BM0 wiring layer, power traces 11-13 are formed extending in the Y direction to the top and bottom ends of the cell in the attached drawing. Power trace 11 supplies power voltage VDD. Power trace 12 is formed in the X direction at the left end of the attached drawing, supplying power voltage VSS. Power trace 13 is formed in the X direction at the right end of the attached drawing, supplying power voltage VSS. Power trace 12 is shared with other cells arranged on the left side of the attached drawing. Power trace 13 is shared with other cells arranged on the right side of the attached drawing.

[0048] In the BM1 wiring layer, power wiring 121 is formed extending to the left and right ends of the cell in the X direction. Power wiring 121 supplies power supply voltage VSS. Power wiring 121 is connected to power wiring 12 via via 131 and to power wiring 13 via via 132.

[0049] Multiple active regions constituting the channel, source, and drain of the N-type transistor are formed on the P-type substrate (PSub) (illustration omitted). Specifically, active regions N1-N3 are formed in the N-type transistor region. Active region N1 overlaps with power line 12 when viewed from above. Active region N3 overlaps with power line 13 when viewed from above.

[0050] In the N-type transistor region, drive transistors PD1 and PD2, access transistors PG1 and PG2, readout drive transistor RPD, and readout access transistor RPG are formed. Access transistor PG2, drive transistors PD2 and PD1, access transistor PG1, readout drive transistor RPD, and readout access transistor RPG each have nanosheets 21-26 serving as channels. Nanosheets 21-26 are composed of three overlapping layers when viewed from above and extend in the Y direction.

[0051] In the active region N1, the portion that becomes the source of the driving transistor PD2 is connected to the power supply wiring 12 via a via 91 located at a position overlapping with the power supply wiring 12 when viewed from above. In the active region N3, the portion that becomes the source of the readout driving transistor RPD is connected to the power supply wiring 13 via a via 92 located at a position overlapping with the power supply wiring 13 when viewed from above.

[0052] On the N-well (illustration omitted), multiple active regions constituting the channel, source, and drain of the P-type transistor are formed in the P-type transistor region. Specifically, active regions P1 and P2 are formed in the P-type transistor region. Active regions P1 and P2 overlap with power supply wiring 11 when viewed from above.

[0053] Load transistors PU1 and PU2 are formed in the P-type transistor region. Load transistors PU1 and PU2 each have nanosheets 27 and 28 that serve as channels. Nanosheets 27 and 28 are composed of three overlapping layers when viewed from above and extend in the Y direction. In other words, load transistors PU1 and PU2 are nanosheet FETs.

[0054] It should be noted that the width of nanosheets 21-26 in the X direction is twice the width of nanosheets 27 and 28 in the X direction.

[0055] In the active region P1, the portion of the load transistor PU1 that becomes the source is connected to the power wiring 11 via a via 93 located at a position overlapping the power wiring 11 when viewed from above. In the active region P2, the portion of the load transistor PU2 that becomes the source is connected to the power wiring 11 via a via 94 located at a position overlapping the power wiring 11 when viewed from above.

[0056] It should be noted that, regarding the active region, the portions located on both sides of the nanosheet that become the source and drain are formed, for example, by epitaxial growth starting from the nanosheet.

[0057] like Figure 1As shown in (b), gate wirings 31-35 extending in the X direction are formed. Gate wiring 31 surrounds nanosheet 21 in both the X and Z directions. Gate wiring 32 surrounds nanosheets 27, 23, and 25 in both the X and Z directions. Gate wiring 33 surrounds nanosheets 22 and 28 in both the X and Z directions. Gate wiring 34 surrounds nanosheet 24 in both the X and Z directions. Gate wiring 35 surrounds nanosheet 26 in both the X and Z directions. Gate wiring 31 corresponds to the gate of access transistor PG2. Gate wiring 32 corresponds to the gate of load transistor PU1, drive transistor PD1, and readout drive transistor RPD. Gate wiring 33 corresponds to the gate of drive transistor PD2 and load transistor PU2. Gate wiring 34 corresponds to the gate of access transistor PG1. Gate wiring 35 corresponds to the gate of readout access transistor RPG.

[0058] In the local wiring layer, local wiring (LI: Local Interconnect) 41-50 extending in the X direction is formed. Local wiring 41 is connected to the portion in active region N1 that becomes the source of access transistor PG2. Local wiring 42 is connected to the portion in active region P1 that becomes the source of load transistor PU1. Local wiring 43 is connected to the portion in active region N2 that becomes the source of drive transistor PD1 and the portion in active region N3 that becomes the source of readout drive transistor RPD. Local wiring 44 is connected to the portions in active region N1 that become the drain of access transistor PG2, the portion in active region N1 that becomes the drain of drive transistor PD2, and the portion in active region P2 that becomes the drain of load transistor PU2. Local wiring 45 is connected to the portions in active region P1 that become the drain of load transistor PU1, the portion in active region N2 that becomes the drain of drive transistor PD1, and the portion in active region N2 that becomes the drain of access transistor PG1. Local wiring 46 is connected to the drain of the read drive transistor RPD and the drain of the read access transistor RPG in active region N3. Local wiring 47 is connected to the source of the drive transistor PD2 in active region N1. Local wiring 48 is connected to the source of the load transistor PU2 in active region P2. Local wiring 49 is connected to the source of the access transistor PG1 in active region N2. Local wiring 50 is connected to the source of the read access transistor RPG in active region N3.

[0059] Local wiring 44 is connected to gate wiring 32 via shared contact 51. Local wiring 45 is connected to gate wiring 33 via shared contact 52. It should be noted that gate wiring 33, local wiring 45, and shared contact 52 correspond to the first node NA. Gate wiring 32, local wiring 44, and shared contact 51 correspond to the second node NB.

[0060] like Figure 1 As shown in (a), in the metal wiring layer above the local wiring layer, namely the M1 wiring layer, wirings 61-63 extending in the Y direction to the upper and lower ends of the cell are formed. Wirings 64-66 are also formed. Wirings 61-63 correspond to write bit lines WBLB, WBL, and read bit line RBL, respectively. Wiring 61 overlaps with active region N1 and power wiring 12 when viewed from above. Wiring 62 overlaps with active regions P1, N2 and power wiring 11 when viewed from above. Wiring 63 overlaps with active region N3 and power wiring 13 when viewed from above.

[0061] Router 61 is connected to local routing 41 via via 53. Router 62 is connected to local routing 49 via via 54. Router 63 is connected to local routing 50 via via 55.

[0062] Above the M1 wiring layer, namely the M2 wiring layer, wirings 71 and 72 are formed extending in the X direction to the left and right ends of the cell. Wirings 71 and 72 correspond to the write word line WWL and the read word line RWL, respectively. Wiring 71 is connected to the gate wiring 31 via via 81, wiring 64, and via 56. Wiring 71 is connected to the gate wiring 34 via via 82, wiring 65, and via 57. Wiring 72 is connected to the gate wiring 35 via via 83, wiring 66, and via 58.

[0063] Based on the above structure, on the back of the transistor, the BMO wiring layer, power supply wiring 11 for supplying power supply voltage VDD and power supply wirings 12 and 13 for supplying power supply voltage VSS are formed. On the upper metal wiring layer of the transistor, the M1 wiring layer, wirings 61-63 are formed, which correspond to write bit lines WBLB and WBL, and read bit line RBL, respectively. Therefore, the wiring formed on the M1 wiring layer consists only of bit lines, thus increasing the width of wirings 61-63. As a result, the wiring resistance of the bit lines can be suppressed, thereby improving the operating speed of the semiconductor memory device. Furthermore, since the wiring formed on the BMO wiring layer consists only of power supply wirings for supplying power supply voltages VDD and VSS, the width of power supply wirings 11-13 can be increased. As a result, the wiring resistance of the power supply wiring can be suppressed, thereby suppressing power supply voltage drop, thus improving the operating speed and stability of the semiconductor memory device. Additionally, since the bit lines and power supply wirings are formed on different wiring layers, the distance between the bit lines and power supply wirings can be increased. As a result, parasitic capacitance between bit lines and power supply lines can be suppressed, thus improving the operating speed of the semiconductor memory device. Furthermore, by forming power supply lines 11 supplying power supply voltage VDD and power supply lines 12 and 13 supplying power supply voltage VSS on the back-side wiring layer, i.e., the BMO wiring layer, the transistors constituting the SRAM cell and the power supply lines 11-13 can be stacked overlappingly. This increases the width of the power supply lines 11-13 formed on the BMO wiring layer. As a result, the wiring resistance of the wiring formed on the BMO wiring layer can be suppressed. Additionally, by connecting the power supply lines 11-13 and the transistors constituting the SRAM cell via vias provided in the overlapping area of ​​the power supply lines 11-13 and the transistors constituting the SRAM cell, the resistance from the power supply lines to the transistors can be reduced. Therefore, the operating speed of the semiconductor memory device can be improved. Furthermore, by increasing the width of the power supply lines 11-13, the wiring resistance of the wiring supplying power supply voltages VDD and VSS can be suppressed, thus improving operating stability, particularly improving the retention characteristics (static noise margin) of the SRAM cell.

[0064] (Other structural examples)

[0065] Figure 5 (a) Shows other structural examples of the semiconductor integrated circuit device according to the first embodiment. Figure 5 The semiconductor integrated circuit device 100 shown in (a) is constructed by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B). SRAM cells, etc., are arranged on chip A. Power wiring is formed on a wiring layer disposed on the surface of chip B. Chip B is attached to the back side of chip A using bumps or the like.

[0066] Figure 5 (b) shows the structure example in this example. Figure 1 The cross-section at line X1-X1' of the SRAM cell. (Example) Figure 5 As shown in (b), power supply wiring 11 for supplying VDD and power supply wirings 12 and 13 for supplying VSS are formed on the wiring layer disposed on the surface of chip B. Power supply wiring 11 is connected to the active region P1 of chip A via via 93. Power supply wiring 13 is connected to the active region N3 of chip A via via 92. It should be noted that, although the diagram is omitted, power supply wiring 12 is connected to the active region N1 of chip A via via 91. Power supply wiring 11 is connected to the active region P2 of chip A via via 94.

[0067] (Variation Example 1)

[0068] Figure 6 This is a top view illustrating another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Figure 6 (a) shows the upper part of the unit, Figure 6 (b) shows the lower part of the unit.

[0069] and Figure 1 In comparison, Figure 6 In the above view, the width of power supply wiring 13 increases in the X direction. Specifically, power supply wiring 13 overlaps with wirings 62, 63 and active regions N2, N3 when viewed from above. In addition, power supply wiring 13 is connected to the portion of active region N2 that becomes the source of driving transistor PD1 via a via 95 provided at the overlapping position when viewed from above.

[0070] exist Figure 6 In this structure, the width of the power supply wiring 13 in the X direction is increased, thus enhancing the power supply voltage VSS supplied to the SRAM cell. This, in turn, improves the operating speed of the semiconductor memory device.

[0071] In addition, it is also possible to receive and Figure 1 Same effect.

[0072] It should be noted that in this modified example, the via 95 can be omitted.

[0073] (Variation Example 2)

[0074] Figure 7 This is a top view illustrating another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Figure 7 (a) shows the upper part of the unit, Figure 7 (b) shows the lower part of the unit.

[0075] and Figure 1 In comparison, Figure 7In the BM0 wiring layer, power wiring 14 is formed that extends in the Y direction to the upper and lower ends of the cell.

[0076] Specifically, power supply wiring 14 is arranged between power supply wirings 11 and 13. Power supply wiring 14 supplies power supply voltage VSS. Power supply wiring 14 overlaps with active region N2 and wiring 62 when viewed from above. Power supply wiring 14 is connected to the portion of active region N2 that becomes the source of driving transistor PD1 via a via 96 provided at the overlapping position when viewed from above.

[0077] In addition, the power lines 11-14 have the same width (width L) in the X direction. Furthermore, the power lines 11-14 are arranged at equal intervals (spacing P) in the X direction.

[0078] exist Figure 7 In the structure, the power supply wiring 11-14 has the same width in the X direction and the spacing between the wirings is equal, thus improving the manufacturability and product yield of the semiconductor memory device.

[0079] In addition, it is also possible to receive and Figure 1 Same effect.

[0080] It should be noted that power wiring 11-14 can be either the same width in the X direction or the same spacing between the wirings.

[0081] (Variation Example 3)

[0082] Figure 8 This is a top view illustrating another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Figure 8 (a) shows the upper part of the unit, Figure 8 (b) shows the lower part of the unit.

[0083] and Figure 1 In comparison, Figure 8 In the M1 wiring layer, power supply wiring 68 is formed that extends in the Y direction to the upper and lower ends of the cell.

[0084] Specifically, power supply wiring 68 is formed between wirings 61 and 62. Power supply wiring 68 overlaps with power supply wiring 11 when viewed from above. Power supply wiring 68 is connected to the source portion of the active region P1 that becomes the load transistor PU1 via via 59 and local wiring 42. Power supply wiring 68 is connected to the source portion of the active region P2 that becomes the load transistor PU2 via via 60 and local wiring 48.

[0085] exist Figure 8In this structure, the power supply wiring 68, which supplies the power supply voltage VDD, suppresses crosstalk noise between wirings 61 and 62, which correspond to the write bit lines WBLB and WBL, respectively. This enables the stabilization of the semiconductor memory device's operation.

[0086] In addition, it is also possible to receive and Figure 1 Same effect.

[0087] It should be noted that in this variant, the power supply wiring 11 formed on the BMO wiring layer and supplying the power supply voltage VDD can also be omitted.

[0088] (Second Implementation)

[0089] Figure 9 This is a top view illustrating another example of the layout structure of the SRAM cell according to the second embodiment. Specifically, Figure 9 (a) shows the upper part of the unit. Figure 9 (b) shows the lower part of the unit.

[0090] and Figure 1 In comparison, Figure 9 In the BM0 wiring layer, wiring 111-113 is formed to replace power wiring 11-13. In addition, power wiring 161-164 is formed in the M1 wiring layer to replace wiring 61-63. Furthermore, power wiring 121 in the BM1 wiring layer and vias 131 and 132 connecting the power wiring in the BM0 wiring layer and the power wiring in the BM1 wiring layer are omitted.

[0091] like Figure 9 As shown in (b), wiring 111-113 extending in the Y direction to the top and bottom ends of the cell are formed in the BM0 wiring layer. Wiring 111-113 correspond to write bit lines WBLB, WBL, and read bit line RBL, respectively. Wiring 111 overlaps with active region N1 when viewed from above. Wiring 112 overlaps with active region N2 when viewed from above. Wiring 113 overlaps with active region N3 when viewed from above.

[0092] Wiring 111 is connected to the portion of active region N1 that becomes the source of access transistor PG2 via via 191 located at an overlapping position when viewed from above. Wiring 112 is connected to the portion of active region N2 that becomes the source of access transistor PG1 via via 192 located at an overlapping position when viewed from above. Wiring 113 is connected to the portion of active region N3 that becomes the source of readout access transistor RPG via via 193 located at an overlapping position when viewed from above.

[0093] like Figure 9As shown in (a), power supply wirings 161-164 are formed in the M1 wiring layer, extending in the Y direction to the upper and lower ends of the cell. Power supply wiring 161 supplies power supply voltage VDD. Power supply wirings 162-164 supply power supply voltage VSS. Power supply wiring 161 overlaps with active regions P1 and P2 when viewed from above. Power supply wiring 162 overlaps with active region N1 and wiring 111 when viewed from above. Power supply wiring 163 overlaps with active region N2 and wiring 112 when viewed from above. Power supply wiring 164 overlaps with active region N3 and wiring 113 when viewed from above.

[0094] Power supply wiring 161 is connected to the source of load transistor PU1 in active region P1 via via 151 and partial wiring 42. Power supply wiring 161 is connected to the source of load transistor PU2 in active region P2 via via 152 and partial wiring 48. Power supply wiring 162 is connected to the source of drive transistor PD2 in active region N1 via via 153 and partial wiring 47. Power supply wirings 163 and 164 are connected to the sources of drive transistor PD1 in active region N2 and the source of readout drive transistor RPD in active region N3 via vias 154 and 155 and partial wiring 43.

[0095] exist Figure 9In the transistor, on the back side wiring layer, namely the BMO wiring layer, wirings 111-113 are formed, corresponding to write bit lines WBLB, WBL, and read bit line RBL, respectively. On the upper metal wiring layer of the transistor, namely the M1 wiring layer, power supply wirings 161 supplying power supply voltage VDD and power supply wirings 162-164 supplying power supply voltage VSS are formed. Therefore, the wirings formed on the BMO wiring layer are only bit lines, thus increasing the wiring width of wirings 111-113. As a result, the wiring resistance of the bit lines can be suppressed, thereby improving the operating speed of the semiconductor memory device. Furthermore, since bit lines are not required for wiring formed on the M1 wiring layer, the wiring width of power supply wirings 161-164 can be increased. As a result, the wiring resistance of the power supply wiring can be suppressed, thereby suppressing power supply voltage drop, thus improving the operating speed and stability of the semiconductor memory device. Additionally, since the bit lines and power supply wirings are formed on different wiring layers, the distance between the bit lines and power supply wirings can be increased. As a result, parasitic capacitance between bit lines and power supply lines can be suppressed, thus improving the operating speed of the semiconductor memory device. Furthermore, by forming lines 111-113 corresponding to write bit lines WBLB, WBL, and read bit line RBL respectively on the back-side wiring layer, i.e., the BMO wiring layer, transistors constituting the SRAM cell and wiring 111-113 can be stacked overlappingly. This increases the wiring width of the power supply lines 111-113 formed on the BMO wiring layer. As a result, wiring resistance of the wiring formed on the BMO wiring layer can be suppressed. Additionally, by connecting wiring 111-113 and the transistors constituting the SRAM cell via vias provided in the areas where wiring 111-113 overlaps with the transistors constituting the SRAM cell, the resistance from the bit lines to the transistors can be reduced. Therefore, the operating speed of the semiconductor memory device can be improved. Furthermore, the wiring width of power supply lines 161-164 can be increased, suppressing the wiring resistance of the lines supplying power supply voltages VDD and VSS, thus improving operating stability, particularly improving the retention characteristics (static noise margin) of the SRAM cell.

[0096] It should be noted that, in this embodiment, either of the power supply wiring 163 or 164 supplying the power supply voltage VSS can be omitted.

[0097] In addition, in this embodiment, such as Figure 8 As shown, power supply wiring for supplying power voltage VDD can also be formed on the BM0 wiring layer. In this case, the power supply wiring 161 for supplying power voltage VDD formed on the M1 wiring layer can also be omitted.

[0098] It should be noted that in the above embodiments and variations, each transistor includes three layers of nanosheets, but a portion or all of the transistors may include one, two, or four or more layers of nanosheets.

[0099] Furthermore, in the above embodiments and variations, the cross-sectional shape of the nanosheet is set to rectangular, but it is not limited to this. For example, it can also be square, circular, elliptical, etc.

[0100] Furthermore, in the above-described embodiments and modifications, the width of nanosheets 21-26 in the X direction is twice the width of nanosheets 27 and 28 in the X direction, but this is not a limitation. The width of each of nanosheets 21-28 in the X direction can be determined by considering factors such as the operational stability of the SRAM circuit.

[0101] Alternatively, in the first embodiment and its variations described above, a power supply line for supplying power supply voltage VDD can be formed in the BM1 wiring layer to replace the power supply line 121 for supplying power supply voltage VSS. In this case, vias are formed in the area where the power supply line overlaps with the power supply line 11 for supplying power supply voltage VDD in the BM0 wiring layer, and the power supply lines are connected to each other.

[0102] Furthermore, in the above-described embodiments and variations, the common contacts 51 and 52, the gate-contact, and the local wiring can be manufactured in the same process step or in different process steps.

[0103] Furthermore, in the above-described embodiments and variations, the power supply voltage VDD supplied to the source of the load transistors PU1 and PU2 is not limited to a power supply supplied from outside the semiconductor integrated circuit, but may also be a power supply generated inside the semiconductor integrated circuit or a power supply generated inside the semiconductor memory device.

[0104] -Industry Applicability-

[0105] This disclosure improves the operating speed of semiconductor memory devices by arranging the wiring in the SRAM cells on the back side of the transistor.

[0106] - Symbol Explanation -

[0107] Power cabling 11-14, 68, 161-164

[0108] Vias 91-96, 191-193

[0109] 21-28 nanosheets

[0110] 31-35 Gate wiring

[0111] Wiring 61-63, 111-113

[0112] PU1 and PU2 load transistors

[0113] PD1 and PD2 driving transistors

[0114] PG1 and PG2 access transistors

[0115] RPD readout drive transistor

[0116] RPG readout access transistor

[0117] WBL, WBLB write bit lines

[0118] RBL readout bit line

[0119] WWL write word line

[0120] RWL reads out word lines.

Claims

1. A semiconductor memory device comprising SRAM cells, characterized in that: The SRAM cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The source of the first transistor is connected to a first power supply that provides a first power supply voltage, the drain of the first transistor is connected to a first node, and the gate of the first transistor is connected to a second node. The source of the second transistor is connected to the first power supply, the drain of the second transistor is connected to the second node, and the gate of the second transistor is connected to the first node. The source of the third transistor is connected to a second power supply voltage, the drain of the third transistor is connected to the first node, and the gate of the third transistor is connected to the second node, wherein the second power supply voltage is different from the first power supply voltage. The source of the fourth transistor is connected to the second power supply, the drain of the fourth transistor is connected to the second node, and the gate of the fourth transistor is connected to the first node. The source of the fifth transistor is connected to the first write bit line, the drain of the fifth transistor is connected to the first node, and the gate of the fifth transistor is connected to the write word line. The source of the sixth transistor is connected to the second write bit line, the drain of the sixth transistor is connected to the second node, and the gate of the sixth transistor is connected to the write word line, wherein the second write bit line and the first write bit line form a complementary bit line pair. The source of the seventh transistor is connected to the second power supply, and the gate of the seventh transistor is connected to the second node. The source of the eighth transistor is connected to the read bit line, the drain of the eighth transistor is connected to the drain of the seventh transistor, and the gate of the eighth transistor is connected to the read word line. The readout bit line includes a first wiring layer formed on a metal wiring layer above the first transistor to the eighth transistor, extending in a first direction and connected to the source of the eighth transistor. The SRAM cell includes a first active region, a first power supply wiring, and a first via. The first active region constitutes the channel, source, and drain of the seventh transistor, and contains a seventh nanosheet extending in the first direction as the channel. The first power supply wiring is formed on the back side of the wiring layer (i.e., the back wiring layer) of the first transistor to the eighth transistor, extends in the first direction, overlaps with the first active region in a top view, and is connected to the second power supply. The first via is formed in the region of the first active region where the region that becomes the source of the seventh transistor overlaps with the first power supply wiring, and connects the source of the seventh transistor in the first active region to the first power supply wiring.

2. The semiconductor memory device according to claim 1, characterized in that: The first active region constitutes the channel, source, and drain of the eighth transistor, and contains an eighth nanosheet extending in the first direction as the channel. The seventh nanosheet and the eighth nanosheet are arranged in the first direction.

3. The semiconductor memory device according to claim 1, characterized in that: The SRAM cell includes a second active region, a second power supply wiring, and a second via. The second active region constitutes the channel, source, and drain of the sixth transistor, and contains a sixth nanosheet extending in the first direction as the channel. The second active region also constitutes the channel, source, and drain of the fourth transistor, and contains a fourth nanosheet extending in the first direction as the channel. The second power supply wiring is formed on the back wiring layer, extends in the first direction, overlaps with the second active area in a top view, and is connected to the second power supply. The second via is formed in the region of the second active region where the region that becomes the source of the fourth transistor overlaps with the second power supply wiring, and connects the source of the fourth transistor in the second active region to the second power supply wiring. The fourth nanosheet and the sixth nanosheet are arranged in the first direction.

4. The semiconductor memory device according to claim 1, characterized in that: The first write bit line includes a second wiring formed in the metal wiring layer, extending in the first direction and connected to the source of the fifth transistor. The second write bit line includes a third wiring formed in the metal wiring layer, extending in the first direction and connected to the source of the sixth transistor.

5. The semiconductor memory device according to claim 1, characterized in that: The SRAM cell includes a third active region, a fourth active region, a third power supply wiring, a third via, and a fourth via. The third active region constitutes the channel, source, and drain of the first transistor, and contains a first nanosheet extending in the first direction as the channel. The fourth active region constitutes the channel, source, and drain of the second transistor, and contains a second nanosheet extending in the first direction as the channel. The third power supply wiring is formed on the back wiring layer, extends in the first direction, overlaps with the third active region and the fourth active region when viewed from above, and is connected to the first power supply. The third via is formed in the region of the third active region where the region that becomes the source of the first transistor overlaps with the third power supply wiring, and connects the source of the first transistor in the third active region to the third power supply wiring. The fourth via is formed in the region of the fourth active region where the region that becomes the source of the second transistor overlaps with the third power supply wiring, and connects the source of the second transistor in the fourth active region to the third power supply wiring.

6. The semiconductor memory device according to claim 1, characterized in that: A fourth power supply line is formed in the metal wiring layer, the fourth power supply line extends in the first direction and is connected to the first power supply. The fourth power supply wiring is connected to the source of the first transistor and the source of the second transistor.

7. The semiconductor memory device according to claim 1, characterized in that: The SRAM cell includes a fifth active region. The fifth active region constitutes the channel, source, and drain of the third transistor, and contains a third nanosheet extending in the first direction as the channel. The fifth active region also constitutes the channel, source, and drain of the fifth transistor, and contains a fifth nanosheet extending in the first direction as the channel. The third nanosheet and the fifth nanosheet are arranged in the first direction.

8. The semiconductor memory device according to claim 7, characterized in that: The first power supply wiring overlaps with the fifth active region when viewed from above. The SRAM cell includes a fifth via formed in the fifth active region where the region that serves as the source of the third transistor overlaps with the first power supply wiring, and connects the source of the third transistor in the fifth active region to the first power supply wiring.

9. The semiconductor memory device according to claim 7, characterized in that: The SRAM cell includes a fifth power supply wiring and a sixth via. The fifth power supply wiring is formed on the back wiring layer, extends in the first direction, overlaps with the fifth active region in a top view, and is connected to the second power supply. The sixth via is formed in the region of the fifth active region where the region that becomes the source of the third transistor overlaps with the fifth power supply wiring, and connects the source of the third transistor in the fifth active region to the fifth power supply wiring.

10. The semiconductor memory device according to claim 9, characterized in that: The SRAM cell includes a second active region, a third active region, a fourth active region, a second power supply wiring, a third power supply wiring, a second via, a third via, and a fourth via. The second active region constitutes the channel, source, and drain of the sixth transistor, and contains a sixth nanosheet extending in the first direction as the channel. The second active region also constitutes the channel, source, and drain of the fourth transistor, and contains a fourth nanosheet extending in the first direction as the channel. The third active region constitutes the channel, source, and drain of the first transistor, and contains a first nanosheet extending in the first direction as the channel. The fourth active region constitutes the channel, source, and drain of the second transistor, and contains a second nanosheet extending in the first direction as the channel. The second power supply wiring is formed on the back wiring layer, extends in the first direction, overlaps with the second active area in a top view, and is connected to the second power supply. The third power supply wiring is formed on the back wiring layer, extends in the first direction, overlaps with the third active region and the fourth active region when viewed from above, and is connected to the first power supply. The second via is formed in the region of the second active region where the region that becomes the source of the fourth transistor overlaps with the second power supply wiring, and connects the source of the fourth transistor in the second active region to the second power supply wiring. The third via is formed in the region of the third active region where the region that becomes the source of the first transistor overlaps with the third power supply wiring, and connects the source of the first transistor in the third active region to the third power supply wiring. The fourth via is formed in the region of the fourth active region where the region that serves as the source of the second transistor overlaps with the third power supply wiring, and connects the source of the second transistor in the fourth active region to the third power supply wiring. The first power supply wiring, the second power supply wiring, the third power supply wiring, and the fifth power supply wiring have the same width in a second direction perpendicular to the first direction.

11. The semiconductor memory device according to claim 9, characterized in that: The SRAM cell includes a second active region, a third active region, a fourth active region, a second power supply wiring, a third power supply wiring, a second via, a third via, and a fourth via. The second active region constitutes the channel, source, and drain of the sixth transistor, and contains a sixth nanosheet extending in the first direction as the channel. The second active region also constitutes the channel, source, and drain of the fourth transistor, and contains a fourth nanosheet extending in the first direction as the channel. The third active region constitutes the channel, source, and drain of the first transistor, and contains a first nanosheet extending in the first direction as the channel. The fourth active region constitutes the channel, source, and drain of the second transistor, and contains a second nanosheet extending in the first direction as the channel. The second power supply wiring is formed on the back wiring layer, extends in the first direction, overlaps with the second active area in a top view, and is connected to the second power supply. The third power supply wiring is formed on the back wiring layer, extends in the first direction, overlaps with the third active region and the fourth active region when viewed from above, and is connected to the first power supply. The second via is formed in the region of the second active region where the region that becomes the source of the fourth transistor overlaps with the second power supply wiring, and connects the source of the fourth transistor in the second active region to the second power supply wiring. The third via is formed in the region of the third active region where the region that becomes the source of the first transistor overlaps with the third power supply wiring, and connects the source of the first transistor in the third active region to the third power supply wiring. The fourth via is formed in the region of the fourth active region where the region that serves as the source of the second transistor overlaps with the third power supply wiring, and connects the source of the second transistor in the fourth active region to the third power supply wiring. The first power supply wiring, the second power supply wiring, the third power supply wiring, and the fifth power supply wiring are arranged at the same spacing in a second direction perpendicular to the first direction.

12. A semiconductor memory device comprising SRAM cells, characterized in that: The SRAM cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The source of the first transistor is connected to a first power supply that provides a first power supply voltage, the drain of the first transistor is connected to a first node, and the gate of the first transistor is connected to a second node. The source of the second transistor is connected to the first power supply, the drain of the second transistor is connected to the second node, and the gate of the second transistor is connected to the first node. The source of the third transistor is connected to a second power supply voltage, the drain of the third transistor is connected to the first node, and the gate of the third transistor is connected to the second node, wherein the second power supply voltage is different from the first power supply voltage. The source of the fourth transistor is connected to the second power supply, the drain of the fourth transistor is connected to the second node, and the gate of the fourth transistor is connected to the first node. The source of the fifth transistor is connected to the first write bit line, the drain of the fifth transistor is connected to the first node, and the gate of the fifth transistor is connected to the write word line. The source of the sixth transistor is connected to the second write bit line, the drain of the sixth transistor is connected to the second node, and the gate of the sixth transistor is connected to the write word line, wherein the second write bit line and the first write bit line form a complementary bit line pair. The source of the seventh transistor is connected to the second power supply, and the gate of the seventh transistor is connected to the second node. The source of the eighth transistor is connected to the read bit line, the drain of the eighth transistor is connected to the drain of the seventh transistor, and the gate of the eighth transistor is connected to the read word line. A first power supply line is formed on a metal wiring layer above the first to eighth transistors. The first power supply line extends in a first direction and is connected to the second power supply and the source of the seventh transistor. The readout bit line includes a first wiring layer, which is formed on the back side of the wiring layer (i.e., the back wiring layer) of the first transistor to the eighth transistor and extends in the first direction. The SRAM cell includes a first active region and a first via. The first active region constitutes the channel, source, and drain of the eighth transistor, and contains an eighth nanosheet extending in the first direction as the channel. The first via is formed in the region of the first active region where the region that becomes the source of the eighth transistor overlaps with the first power supply wiring, and connects the source of the eighth transistor in the first active region to the first power supply wiring.

13. The semiconductor memory device according to claim 12, characterized in that: The first write bit line includes a second wiring formed on the back wiring layer and extending in the first direction. The SRAM cell includes a fifth active region and a second via. The fifth active region constitutes the channel, source, and drain of the third transistor, and contains a third nanosheet extending in the first direction as the channel. The second via is formed in the region of the fifth active region where the region that becomes the source of the fifth transistor overlaps with the second wiring, and connects the source of the fifth transistor in the fifth active region to the second wiring.

14. The semiconductor memory device according to claim 12, characterized in that: The second write bit line includes a third wiring formed on the back wiring layer and extending in the first direction. The SRAM cell includes a second active region and a third via. The second active region constitutes the channel, source, and drain of the sixth transistor, and contains a sixth nanosheet extending in the first direction as the channel. The third via is formed in the region of the second active region where the region that becomes the source of the sixth transistor overlaps with the third wiring, and connects the source of the sixth transistor in the second active region to the third wiring.

15. The semiconductor memory device according to claim 12, characterized in that: The SRAM cell includes a third active region, a fourth active region, a second power supply wiring, a fourth via, and a fifth via. The third active region constitutes the channel, source, and drain of the first transistor, and contains a first nanosheet extending in the first direction as the channel. The fourth active region constitutes the channel, source, and drain of the second transistor, and contains a second nanosheet extending in the first direction as the channel. The second power supply wiring is formed on the back wiring layer, extends in the first direction, overlaps with the third and fourth active regions when viewed from above, and is connected to the first power supply. The fourth via is formed in the region of the third active region where the region that becomes the source of the first transistor overlaps with the second power supply wiring, and connects the source of the first transistor in the third active region to the second power supply wiring. The fifth via is formed in the region in the fourth active region where the region that becomes the source of the second transistor overlaps with the second power supply wiring, and connects the source of the second transistor in the fourth active region to the second power supply wiring.

16. The semiconductor memory device according to claim 12, characterized in that: A third power supply line is formed in the metal wiring layer, the third power supply line extends in the first direction and is connected to the first power supply. The third power supply wiring is connected to the source of the first transistor and the source of the second transistor.

17. The semiconductor memory device according to claim 12, characterized in that: A fourth power supply line is formed in the metal wiring layer, the fourth power supply line extends in the first direction and is connected to the second power supply. A fifth power supply line is formed in the metal wiring layer, the fifth power supply line extends in the first direction and is connected to the second power supply. The fourth power supply wiring is connected to the source of the fourth transistor. The fifth power supply wiring is connected to the source of the third transistor.

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