Semiconductor device, electronic device, and method for manufacturing semiconductor device

Abstract

A semiconductor device according to an embodiment of the present disclosure includes a plurality of wiring layers each including a wiring, a plurality of contacts respectively provided between the plurality of wirings, and an element of a resistance change type or a capacitance change type provided between any of the plurality of wirings. The plurality of contacts includes a lower contact located below the element and configured to connect the element and a first lower layer wiring that is a wiring in a layer located below the element. A total thickness of the lower contact and the element is greater than a thickness of a first lower layer contact that is a contact connected to the first lower layer wiring in a layer located below the first lower layer wiring.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, electronic devices, and methods for manufacturing semiconductor devices. Background Technology

[0002] Storage devices are examples of semiconductor devices, and due to the increasing number of pixels provided in image sensors such as CMOS image sensors (CIS), there is a need for storage devices with large capacities. Furthermore, storage devices need to achieve low error rates. For example, static random access memory (SRAM) is used as a storage element, but SRAM has a large area and it is difficult to ensure the necessary capacity. Therefore, magnetic random access memory (MRAM) with a small area is used as a storage element (e.g., see PTL1). As storage elements, for example, resistive or capacitive changing elements are used.

[0003] Reference List

[0004] Patent documents

[0005] PTL 1: WO2018 / 221114 Summary of the Invention

[0006] Technical issues

[0007] However, in semiconductor devices that include the aforementioned resistance-varying or capacitance-varying components, parts other than the component itself (e.g., wiring, contacts, etc.) may be damaged during component handling, and this can lead to quality degradation. For example, the resistance of parts other than the component may increase due to damage, and this can affect other components.

[0008] Therefore, this disclosure provides semiconductor devices, electronic devices, and methods for manufacturing semiconductor devices that can suppress quality degradation.

[0009] Solution to the problem

[0010] A semiconductor device according to an embodiment of the present disclosure includes a plurality of wiring layers, a plurality of contacts, and a resistance-varying or capacitance-varying element. Each wiring layer includes wiring, and the plurality of contacts are disposed between the plurality of wirings. The resistance-varying or capacitance-varying element is disposed between any of the plurality of wirings. The plurality of contacts include a lower contact located below the element, the lower contact being configured to connect the element to a first lower layer wiring, the first lower layer wiring being a wiring in the layer below the element. The total thickness of the lower contact and the element is greater than the thickness of the first lower layer contact in the layer below the first lower layer wiring, the first lower layer contact being a contact connected to the first lower layer wiring.

[0011] An electronic device according to embodiments of the present disclosure includes a semiconductor device. The semiconductor device includes multiple wiring layers, multiple contacts, and a resistance-varying or capacitance-varying element. Each wiring layer includes wiring, and the multiple contacts are disposed between the multiple wirings. The resistance-varying or capacitance-varying element is disposed between any of the multiple wirings. The multiple contacts include a lower contact located below the element, configured to connect the element to a first lower layer wiring. The first lower layer wiring is a wiring in the layer below the element. The total thickness of the lower contact and the element is greater than the thickness of the first lower layer contact in the layer below the first lower layer wiring. The first lower layer contact is a contact connected to the first lower layer wiring.

[0012] A method for manufacturing a semiconductor device according to embodiments of the present disclosure includes generating a plurality of wiring layers, disposing a plurality of contacts between the plurality of wiring layers, and disposing a resistance-varying or capacitance-varying element between any of the plurality of wiring layers, each wiring layer having wiring. The plurality of contacts includes a lower contact located below an element, the lower contact being configured to connect the element to a first lower layer wiring, the first lower layer wiring being a wiring in the layer below the element, the total thickness of the lower contact and the element being greater than the thickness of the first lower layer contact in the layer below the first lower layer wiring, the first lower layer contact being a contact connected to the first lower layer wiring. Attached Figure Description

[0013] Figure 1 This is a diagram illustrating a configuration example of a storage device according to the first embodiment.

[0014] Figure 2 This is a diagram illustrating a configuration example of the main parts of a storage device according to a first embodiment.

[0015] Figure 3 This is a diagram used to describe how, according to the first embodiment, damage to parts other than the element is suppressed during the processing of the element.

[0016] Figure 4 This is a diagram illustrating an example configuration of the main portion (bit unit) of the memory section according to the first embodiment.

[0017] Figure 5 This is a diagram illustrating a first layout example of a bit cell according to the first embodiment.

[0018] Figure 6 This is a diagram used to describe the electrical connections of a first layout example according to the first embodiment.

[0019] Figure 7 This is a diagram illustrating a second layout example of a bit cell according to the first embodiment.

[0020] Figure 8 This is a diagram illustrating a third layout example of a bit cell according to the first embodiment.

[0021] Figure 9 This is a diagram used to describe the electrical connections of a third layout example according to the first embodiment.

[0022] Figure 10 This is a diagram illustrating an example of the relationship between the planar area of ​​the through-hole and the planar area of ​​the metal film according to the first embodiment.

[0023] Figure 11 This is a diagram illustrating an example of the relationship between the planar area of ​​the through-hole and the planar area of ​​the metal film according to the first embodiment.

[0024] Figure 12 This is a diagram illustrating an example of the relationship between the planar area of ​​the through-hole and the planar area of ​​the metal film according to the first embodiment.

[0025] Figure 13 This is a diagram illustrating the relationship between the resistance of the storage element according to the first embodiment and the resistance of the via disposed directly below the storage element.

[0026] Figure 14 This is a diagram illustrating an example configuration of through holes according to the first embodiment, excluding the through hole located directly below the storage element.

[0027] Figure 15 This is a diagram illustrating an example configuration of through holes according to the first embodiment, excluding the through hole located directly below the storage element.

[0028] Figure 16 This is a diagram illustrating a first configuration example of a through-hole in a connection layer including a storage element according to a first embodiment.

[0029] Figure 17 This is a diagram illustrating a second configuration example of a through-hole in a connection layer including a storage element according to the first embodiment.

[0030] Figure 18 This is a diagram illustrating a third configuration example of a through-hole in a connection layer including a storage element according to the first embodiment.

[0031] Figure 19 This is a diagram illustrating a fourth configuration example of a through-hole in a connection layer including a storage element according to the first embodiment.

[0032] Figure 20 This is a diagram illustrating a fifth configuration example of a through-hole in a connection layer including a storage element according to the first embodiment.

[0033] Figure 21This is a diagram illustrating the manufacturing steps of the storage device according to the first embodiment.

[0034] Figure 22 This is a diagram illustrating the manufacturing steps of the storage device according to the first embodiment.

[0035] Figure 23 This is a diagram illustrating the manufacturing steps of the storage device according to the first embodiment.

[0036] Figure 24 This is a diagram illustrating the manufacturing steps of the storage device according to the first embodiment.

[0037] Figure 25 This is a diagram illustrating the manufacturing steps of the storage device according to the first embodiment.

[0038] Figure 26 This is a plan view showing an example configuration of a storage device according to a second embodiment.

[0039] Figure 27 This is a cross-sectional view showing an example configuration of the annular portion according to the second embodiment (along... Figure 26 (The sectional view taken by line A1-A1 in the diagram).

[0040] Figure 28 This is a first modified cross-sectional view showing the configuration of the annular portion according to the second embodiment.

[0041] Figure 29 This is a second modified cross-sectional view showing the configuration of the annular portion according to the second embodiment.

[0042] Figure 30 This is a cross-sectional view showing a third modification to the configuration of the annular portion according to the second embodiment.

[0043] Figure 31 This is a cross-sectional view showing a fourth modification to the configuration of the annular portion according to the second embodiment.

[0044] Figure 32 This is a fifth modified cross-sectional view showing the configuration of the annular portion according to the second embodiment.

[0045] Figure 33 This is a plan view showing a sixth modification to the configuration of the annular portion according to the second embodiment.

[0046] Figure 34 This is a sixth modified cross-sectional view showing the configuration of the annular portion according to the second embodiment (along...). Figure 33 (The cross-sectional view taken by line A2-A2 in the middle).

[0047] Figure 35This is a diagram illustrating an example of the circuit configuration of a storage device according to a third embodiment.

[0048] Figure 36 This is a diagram illustrating an example of the circuit configuration of a bit unit according to the third embodiment.

[0049] Figure 37 It is a graph showing the relationship between the resistance value of the storage element according to the third embodiment and the degree of change in the resistance value.

[0050] Figure 38 This is a diagram illustrating a first layout example of a bit cell according to a third embodiment.

[0051] Figure 39 This is a diagram used to describe the electrical connections of a first layout example according to the third embodiment.

[0052] Figure 40 This is a diagram illustrating a second layout example of a bit cell according to a third embodiment.

[0053] Figure 41 This is a diagram used to describe the electrical connections of a second layout example according to the third embodiment.

[0054] Figure 42 This is a diagram illustrating a third layout example of a bit cell according to a third embodiment.

[0055] Figure 43 This is a diagram used to describe the electrical connections of a third layout example according to the third embodiment.

[0056] Figure 44 This is a diagram illustrating a fourth layout example of a bit cell according to the third embodiment.

[0057] Figure 45 This is a diagram used to describe the electrical connections of a fourth layout example according to the third embodiment.

[0058] Figure 46 This is a diagram illustrating an application example of the aforementioned storage device.

[0059] Figure 47 This is a diagram illustrating an example configuration of an imaging device based on an application example.

[0060] Figure 48 This is a diagram illustrating a configuration example of a distance measurement device based on an application example. Detailed Implementation

[0061] Embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. Embodiments include examples, variations, etc. It should be noted that the apparatuses, devices, methods, etc., relating to this disclosure are not limited to the embodiments of this disclosure. Furthermore, in the following embodiments, redundant descriptions are substantially omitted by assigning the same reference numerals to substantially the same components.

[0062] This disclosure will be described in the following order.

[0063] 1. First Embodiment

[0064] 1-1. Storage Device Configuration Example

[0065] 1-2. Layout example of bit unit

[0066] 1-3. Example of the relationship between the planar area of ​​the through-hole and the metal film

[0067] 1-4. Configuration examples of the connection layer including storage elements

[0068] 1-5. Configuration examples of vias in the interconnect layer of storage elements

[0069] 1-6. Examples of manufacturing steps for storage devices

[0070] 2. Second Embodiment

[0071] 2-1. Storage Device Configuration Example

[0072] 2-2. Variations of the ring-shaped portion

[0073] 3. Third embodiment

[0074] 3-1. Storage Device Configuration Example

[0075] 3-2. Example of bit cell layout

[0076] 4. Overview of each embodiment

[0077] 5. Other embodiments

[0078] 6. Application Examples

[0079] 6-1. Various equipment

[0080] 6-2. Imaging equipment

[0081] 6-3. Distance measuring equipment

[0082] 7. Supplementary Explanation

[0083] 1. Example

[0084] 1-1. Example of a first configuration for a storage device

[0085] Reference Figures 1 to 3 A configuration example of storage device 1 according to this embodiment is described. Figure 1 This is a diagram illustrating a configuration example of storage device 1 according to this embodiment. Figure 2 This is a diagram illustrating a configuration example of the main parts of the storage device 1 according to this embodiment. Figure 3 This is a diagram used to illustrate the suppression of damage to parts other than the component during the processing of the component according to this embodiment. Figures 1 to 3 The example shown schematically illustrates the cross-sectional structure of storage device 1 and its main components. Storage device 1 is an example of a semiconductor device.

[0086] like Figure 1 As shown, the storage device 1 according to this embodiment is configured such that storage element 50 is integrated with logic circuit 100. The logic circuit 100 has a multilayer wiring structure with wiring layers and connection layers stacked alternately multiple times. Each of the plurality of wiring layers includes wiring (e.g., each of metal films M1 to M8). Each of the plurality of connection layers includes a contact (e.g., each of vias V1 to V8).

[0087] The logic circuit 100 includes a logic section 110 and a memory section 120. The logic section 110 includes circuitry for performing logical operations, etc. The memory section 120 includes storage elements 50. For example, the logic section 110 and the memory section 120 have a common multilayer wiring structure. For example, the logic section 110 and the memory section 120 have a multilayer wiring structure formed with the same wiring spacing in the stacking direction.

[0088] A multi-layer cabling structure has a configuration in which multiple layers with different wiring spacings are stacked. For example, a multi-layer cabling structure includes a first cabling layer group 10 in which multiple cabling layers with narrow wiring spacing are stacked, and a second cabling layer group 20 in which multiple cabling layers with wide wiring spacing are stacked. Figure 1 In the example shown, the first wiring layer group 10 and the second wiring layer group 20 are stacked on the substrate 30 in the order described. The substrate 30 is, for example, a semiconductor substrate.

[0089] The first routing layer group 10 includes, for example, five routing layers and five connection layers. Furthermore, the second routing layer group 20 includes, for example, three routing layers and three connection layers. That is, the multi-layer routing structure has eight routing layers and eight connection layers.

[0090] Specifically, the logic circuit 100, starting from the substrate 30 side, sequentially includes eight wiring layers: a wiring layer including a metal film M1, a wiring layer including a metal film M2, a wiring layer including a metal film M3, a wiring layer including a metal film M4, a wiring layer including a metal film M5, a wiring layer including a metal film M6, a wiring layer including a metal film M7, and a wiring layer including a metal film M8. Each of the metal films M1 to M8 is formed embedded in an insulating film (interlayer insulating layer). Each of the metal films (metal layers) M1 to M8 serves as wiring.

[0091] Furthermore, the logic circuit 100, starting from the substrate 30 side, sequentially includes eight connection layers: a connection layer including via V1, a connection layer including via V2, a connection layer including via V3, a connection layer including via V4, a connection layer including via V5, a connection layer including via V6, a connection layer including via V7, and a connection layer including via V8. Each of vias V1 to V8 is formed embedded in an insulating film (interlayer insulating layer). Each of vias V1 to V8 is formed, for example, by metal. Each of vias V1 to V8 serves as a contact.

[0092] The substrate 30 and the metal film M1 are connected through a through-hole V1. It should be noted that... Figure 1 In the example shown, a plurality of transistors 31 are formed on a substrate 30. Each of the transistors 31 includes a first diffusion layer 31a, a second diffusion layer 31b, and an electrode 31c. Each of the transistors 31 is, for example, a field-effect transistor (FET). Each of the first diffusion layer 31a, the second diffusion layer 31b, and the electrode 31c of the transistor 31 is connected to a metal film M1 via a via V1.

[0093] Metal films M1 and M2 are connected via through hole V2. Similarly, metal films M2 and M3 are connected via through hole V3. Metal films M3 and M4 are connected via through hole V4. Metal films M4 and M5 are connected via through hole V5. Metal films M5 and M6 are connected via through hole V6. Metal films M6 and M7 are connected via through hole V7. Metal films M7 and M8 are connected via through hole V8.

[0094] exist Figure 1 In the example shown, the first wiring layer group 10 comprises a plurality of wiring layers including metal films M1 to M5 and a plurality of connection layers including vias V1 to V5. Each of the wiring layers in the first wiring layer group 10 is formed, for example, according to a common wiring rule (e.g., wiring spacing). Furthermore, the second wiring layer group 20 comprises a plurality of wiring layers including metal films M6 to M8 and a plurality of connection layers including vias V6 to V8. Each of the wiring layers in the second wiring layer group 20 is formed, for example, according to a common wiring rule. It should be noted that... Figure 1The configuration of the logic circuit 100 shown is an example, and the configuration is not limited thereto.

[0095] like Figure 1 and Figure 2 As shown, the storage element 50 is formed in the interlayer insulating layer between the metal film M5 and the metal film M6 in the memory section 120. Figure 1 In the example shown, the via V6 and the storage element 50 are stacked on the metal film M5 in the order described. The storage element 50 is connected to the metal film M5 located below the storage element 50 via the via V6, and is also directly connected to the metal film M6 located above the storage element 50. The via V6 is located below the storage element 50 and connects the storage element 50 and the metal film M5.

[0096] The total thickness D1 of the storage element 50 and the via V6 (total thickness D1 = thickness of storage element 50 + thickness of via V6) is greater than the thickness D2 of the via V5. The total thickness D1 of the storage element 50 and the via V6 is the thickness of the interlayer insulating layer between metal films M5 and M6. The thickness of the via V5 is the thickness of the interlayer insulating layer between metal films M4 and M5. Therefore, it can be said that the thickness of the interlayer insulating layer between metal films M5 and M6 (total thickness D1) is greater than the thickness of the interlayer insulating layer between metal films M4 and M5 (thickness D2). Thickness is the length in the stacking direction of each layer. Figure 1 and Figure 2 (Length in the vertical direction).

[0097] It should be noted that the total thickness D1 (the thickness of the interlayer insulating layer between metal films M5 and M6) of the storage element 50 and the via V6 is preferably equal to or less than 10 times the thickness of the via V6. For example, when the via V6 is circular in the plan view, the total thickness D1 is preferably equal to or less than 10 times the diameter of the via V6. The width (e.g., diameter) is the length in a direction orthogonal to the stacking direction of each layer. Figure 1 and Figure 2 (Length in the left and right directions).

[0098] Storage element configuration example

[0099] like Figure 2 As shown, the storage element 50 is, for example, a magnetoresistive variable element (magnetoresistive effect element). The storage element 50 includes a reference layer 51, a barrier layer 52, and a storage layer 53. Figure 2 In the example shown, reference layer 51, barrier layer 52 and storage layer 53 are stacked in this order to form storage element 50.

[0100] The storage element 50 is provided with a lower electrode 54 and an upper electrode 55. The lower electrode 54 and the upper electrode 55 are arranged to sandwich the storage element 50. The lower electrode 54 is connected to a through-hole V6, and the upper electrode 55 is connected to a metal film M6. The lower electrode 54 and the upper electrode 55 are conductive layers for supplying voltage to the storage element 50. Voltage (current) is supplied to the storage element 50 via the lower electrode 54 and the upper electrode 55. Note that the storage element 50 may include a lower electrode 54 and an upper electrode 55.

[0101] The reference layer 51 is a ferromagnetic layer with magnetic anisotropy and an invariant magnetization direction. For example, the magnetization direction of the reference layer 51 is controlled by magnetic anisotropy to be perpendicular to the layer surface (film surface). The reference layer 51 may contain at least one element selected from, for example, Fe, Co, Ni, and Mn. Furthermore, in order to adjust saturation magnetization, control magnetocrystalline anisotropy energy, and adjust grain size and inter-grain coupling, the reference layer 51 may contain at least one element selected from, for example, B, C, Mg, Y, Si, Al, Ta, Zr, Hf, Pt, Pd, and rare earth elements. The reference layer 51 is also referred to, for example, as a fixed layer, a magnetized fixed layer, etc.

[0102] A barrier layer 52 is disposed between the reference layer 51 and the storage layer 53. The barrier layer 52 applies an electric field to the storage layer 53 to provide voltage-controlled magnetic anisotropy effects, for example. The barrier layer 52 may contain at least one of, for example, oxides, nitrides, and fluorides, wherein the oxide contains at least one element selected from Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Sc, La, Ta, Eu, Cu, Ba, Mo, W, V, Y, Ni, Co, Mn, Cr, Fe, B, and C, the nitride contains at least one element, and the fluoride contains at least one element. Furthermore, the barrier layer 52 can be formed by stacking at least two or more types of elements selected from the above-mentioned element groups. The barrier layer 52 is also referred to as, for example, a tunnel barrier layer, an insulating layer, etc.

[0103] The storage layer 53 is a ferromagnetic layer with magnetic anisotropy and a variable magnetization direction. For example, the magnetization direction of the storage layer 53 is controlled by magnetic anisotropy to be perpendicular to the layer surface (film surface). The storage layer 53 may contain at least one or more elements selected from, for example, Fe, Co, Ni, and Mn. Furthermore, in order to increase VCMA efficiency, control the interface magnetic anisotropy energy, adjust saturation magnetization, control the magnetocrystalline anisotropy energy, and adjust grain size and inter-grain coupling, the storage layer 53 may contain at least one or more elements selected from, for example, Hf, Zr, Ti, Ta, W, Au, Mo, Ru, Pd, Y, V, Sc, Gd, Tb, La, Mg, Al, Ag, Cu, Cr, B, C, Si, Ga, and Ge. The storage layer 53 is also referred to as, for example, a free layer.

[0104] It should be noted that, in addition to the layers described above, the storage element 50 may also include other layers, such as a magnetic field generating layer (magnetic field generating layer) used as a bias layer. The magnetic field generating layer generates a magnetic field to be applied in the in-plane direction (horizontal direction), for example, a direction orthogonal to, for example, the stacking direction of the aforementioned layers. Furthermore, techniques other than the magnetic field generating layer can also be used to generate the magnetic field. For example, techniques such as providing a magnetic layer above or below the storage element 50, or arranging permanent magnets around the storage element 50, can be used.

[0105] Data (e.g., 0 or 1) is written to the storage element 50 (e.g., a memory cell including the storage element 50) by switching the resistance state (resistance value) of the storage element 50 between a low resistance state (low resistance value) and a high resistance state (high resistance value). A low resistance state is a state where the magnetization of the reference layer 51 and the magnetization of the storage layer 53 are parallel to each other, and a high resistance state is a state where the magnetization of the reference layer 51 and the magnetization of the storage layer 53 are antiparallel to each other. For example, the resistance state of the storage element 50 switches between a low resistance state and a high resistance state by reversing the magnetization direction of the storage layer 53 between the upward and downward directions in the stacking direction. For example, the data corresponding to the low resistance state is 0, and the data corresponding to the high resistance state is 1.

[0106] As described above, the basic structure of the memory element 50 is a sandwich structure consisting of a non-magnetic thin film made of an insulator sandwiched between two magnetic layers, both formed of magnetic thin films. This structure is called a magnetic tunnel junction (MTJ). Because the thickness of the non-magnetic thin film is very small, approximately a few nanometers, tunneling current flows when a voltage is applied across the element. The magnitude of the tunneling current depends on the relative angle of magnetization of the two magnetic layers. This is called the tunneling magnetoresistance (TMR) effect. In MRAM, the magnetization of one of the two magnetic layers (reference layer 51) is fixed, and the magnetization of the other magnetic layer (memory layer 53) is controlled by an external field. For example, methods using magnetic anisotropy control through a voltage exist as external fields for controlling the magnetization direction. The TMR effect is used to read the state.

[0107] It should be noted that, in addition to the aforementioned magnetoresistive changing element, other resistance changing elements, capacitance changing elements, etc., are also used as storage element 50. The resistance changing element is a resistance-changing type element, and the capacitance changing element is a capacitance-changing type element. Besides magnetic tunnel junction (MTJ) elements, resistive random access memory (ReRAM), nanotube RAM (NRAM), etc., are also used as resistance changing elements. Examples of MTJ elements include spin-torque-magnetoresistive random access memory (MRAM) and voltage-controlled (VC) MRAM. Furthermore, ferroelectric random access memory (FeRAM), dynamic random access memory (DRAM), etc., are also used as capacitance changing elements. Such resistance changing elements or capacitance changing elements can be provided in semiconductor devices as functional elements other than storage element 50.

[0108] Damage suppression

[0109] like Figure 3 As shown, in one step of the manufacturing process of storage device 1, a plurality of through holes V5 and a plurality of metal films M5 are formed in insulating layer 201, and an insulating layer 202 is stacked on insulating layer 201 in which each of the through holes V5 and each of the metal films M5 is formed. Figure 3 The insulating layer 202 on the left is formed of two layers, and Figure 3 The insulating layer 202 on the right side is formed by a single layer. Multiple vias V6 are formed in the insulating layer 202. A multilayer element layer 203 for forming the memory element 50 is formed in the insulating layer 202 in which each of the vias V6 is formed. Then, an upper electrode layer 204, each having a predetermined pattern shape, and two hard mask layers 205 are stacked on top of this layer. Subsequently, etching is performed on the element layer 203 on which the upper electrode layer 204 and hard mask layers 205, each having a predetermined pattern shape, are stacked. Thus, multiple memory elements 50 and the insulating layer 206 are formed.

[0110] exist Figure 3 In the example shown, the insulating layer 201 including each of the through holes V5 serves as a connection layer. Furthermore, the insulating layer 201 including each of the metal films M5 serves as a wiring layer. The insulating layer 202 including each of the through holes V6 serves as a connection layer. In this way, the insulating layer including the through holes (contacts) serves as a connection layer, and the insulating layer including the metal layers (wiring) serves as a wiring layer.

[0111] Here, Figure 3 The thickness D11 of the through hole V6 on the left is greater than Figure 3 The thickness D21 of the through-hole V6 on the right. Thickness D11 is set such that the total thickness D1 of the through-hole V6 and the storage element 50 is greater than the thickness D2 of the through-hole V5 (see...). Figure 1 and Figure 2 ).

[0112] When the thickness of the through hole V6 is Figure 3 When the thickness D21 of the via V6 on the right side is thin and the processing allowance is insufficient, parts other than the storage element 50 (e.g., wiring, contacts, components, etc.) may be damaged during the etching of the element layer 203. On the other hand, when the thickness of the via V6 is... Figure 3 When the thickness D11 of the via V6 on the left is large and has sufficient processing allowance, damage to parts other than the memory element 50 can be suppressed during the etching of the element layer 203. In other words, if the total thickness D1 of the via V6 and the memory element 50 is greater than the thickness D2 of the via V5, the aforementioned damage can be suppressed, thus suppressing quality degradation.

[0113] It should be noted that the total thickness D1 of the through-hole V6 and the storage element 50 is greater than the thickness D2 of the through-hole V5 (see [reference]). Figure 1 and Figure 2 However, the configuration is not limited to this, and for example, the thickness D11 of the through-hole V6 can be greater than the thickness D2 of the through-hole V5. Therefore, the aforementioned damage can be further suppressed, and thus, quality degradation can be reliably suppressed. Alternatively, the total thickness D1 of the storage element 50 and the through-hole V6 can be greater than the total thickness of the through-hole V5 and the metal film M5.

[0114] In addition, the planar area of ​​through hole V6 can be larger than that of through hole V5 (see...). Figure 2 Therefore, the resistance of via V6 can be suppressed, and thus the quality degradation caused by increased resistance can be suppressed. Planar area is the area in a direction orthogonal to the stacking direction of each layer (planar direction).

[0115] Furthermore, the thickness of metal film M6 can be greater than that of metal film M5. Additionally, the linewidth of metal film M6 can be wider than that of metal film M5 (see [link to relevant documentation]). Figure 1 and Figure 2 Therefore, the resistance of the wiring of the metal film M6 can be suppressed, and thus the quality degradation caused by the increase in resistance can be suppressed.

[0116] 1-2. Layout example of bit unit

[0117] Reference Figures 4 to 9 A layout example of bit unit B1 according to this embodiment is described. Figure 4 This is a diagram showing an example of the configuration of the main part (bit unit B1) of the memory section 120 according to this embodiment. Figure 5 and Figure 6 This is a diagram used to describe a first layout example according to this embodiment. Figure 7 This is a diagram used to describe a second layout example according to this embodiment. Figure 8 and Figure 9 This is a diagram used to describe a third layout example according to this embodiment.

[0118] First layout example

[0119] like Figure 4 and Figure 5 As shown, bit unit B1 includes the aforementioned transistor 31. Bit unit B1, for example, together with storage element 50, constitutes a memory cell. That is, in Figure 4 and Figure 5 In the example shown, the layout of bit cell B1 is a 1Tr-1E1 (one transistor 31 - one storage element 50) layout. Figure 5 In the example shown, transistors 31 are electrically isolated from each other via their gates (word lines WL). Additionally, for example, each of the source lines SL is not positioned between specific adjacent gates (word lines WL).

[0120] Multiple bit units B1, i.e., memory cells, constitute a memory cell array, for example, having a cross-point array structure. For example, memory element 50 is disposed at the intersection between a word line WL extending in a predetermined direction and a bit line BL extending in a direction different from the word line WL (e.g., perpendicular to the word line WL). Source line SL extends, for example, in the same direction as bit line BL.

[0121] exist Figure 4 In the example shown, metal film M4 serves as the source line SL, and is connected to the first diffusion layer 31a of transistor 31 via vias V1 to V4 and metal films M1 to M3. Metal film M6 serves as the word line WL, and is connected to the second diffusion layer 31b of transistor 31 via vias V1 to V6, metal films M1 to M5, and memory element 50. Metal film M2 serves as the word line WL, and is connected to the electrode 31c of transistor 31 via vias V1 to V2 and metal film M1.

[0122] like Figure 6 As shown, storage element 50 and transistor 31 are disposed between bit line BL and source line SL. Figure 6 In the example shown, one terminal of the storage element 50 is connected to the bit line BL, and the other terminal is connected to the source line SL via transistor 31. The gate terminal of transistor 31 is connected to the word line WL.

[0123] Transistor 31 is an example of a selection element used to select a target storage element 50 (memory cell) from which data is to be read and written. Any of a variety of transistors, such as the field-effect transistor described above, can be used as transistor 31.

[0124] Second layout example

[0125] like Figure 7 As shown, transistors 31 are electrically isolated from each other by shallow trench isolation (STI) isolation method K1. Figure 7 Isolation method K1 and Figure 5 The isolation methods used in transistor 31 differ. It should be noted that, in addition to methods such as STI, various other isolation methods can be used for the electrical isolation of transistor 31.

[0126] Third layout example

[0127] like Figure 8 As shown, bit unit B1 includes two transistors 31. Bit unit B1, for example, together with storage element 50, constitutes a memory cell. That is, in Figure 8 In the example shown, the layout of bit cell B1 is a 2Tr-1E1 (two transistors 31 - one storage element 50) layout.

[0128] like Figure 9 As shown, storage element 50 and two transistors 31 are positioned between bit line BL and source line SL. Figure 9 In the example shown, one terminal of the storage element 50 is connected to the bit line BL, and the other terminal is connected to the source line SL via two transistors 31. The gate terminal of each of the two transistors 31 is connected to the word line WL.

[0129] 1-3. Example of the relationship between the planar area of ​​the through-hole and the metal film

[0130] Reference Figures 10 to 12 An example illustrating the relationship between the planar area of ​​the through hole (contact) and the planar area of ​​the metal film (wiring) according to this embodiment. Figure 10 This is a diagram illustrating an example of the relationship between the planar areas of the through-hole V7 and the metal film M6 according to this embodiment. Figure 11 This is a diagram illustrating an example of the relationship between the planar areas of the through-hole V5 and the metal films M4 and M5 according to this embodiment. Figure 12 This is a diagram illustrating an example of the relationship between the planar areas of the through-hole V5 and the metal film M5 according to this embodiment.

[0131] like Figure 10 As shown, via V7 and metal film M7 are stacked on metal film M6 in the order described. Metal film M7 serves as bit line BL. The planar area of ​​metal film M6 is larger (wider) than the planar area of ​​via V7. Therefore, the resistance of the wiring on metal film M6 can be suppressed, and thus the quality degradation due to increased resistance can be suppressed.

[0132] like Figure 11As shown, the planar area of ​​each of the metal films M4 and M5 is larger (wider) than the planar area of ​​the through hole V5. Figure 11 In the example shown, metal films M4 and M5 have the same planar area. Therefore, the resistance of the wiring in each of metal films M4 and M5 can be suppressed, and thus the quality degradation due to increased resistance can be suppressed. Note that metal film M6 is used as bit line BL.

[0133] like Figure 12 As shown, the planar area of ​​the metal film M5 is larger (wider) than the planar area of ​​the via V5. Therefore, the wiring resistance of the metal film M5 can be suppressed, and thus the quality degradation due to increased resistance can be suppressed. Note that, as Figure 11 As in the example, the metal film M6 is used as the bit line BL.

[0134] 1-4. Configuration examples of the connection layer including storage elements

[0135] The following will refer to Figures 13 to 15 A configuration example of a connection layer including storage element 50 according to this embodiment is described. Figure 13 This is a diagram illustrating the relationship between the resistance R1 of the storage element 50 according to this embodiment and the resistance R2 of the through hole V6 directly below the storage element 50. Figure 14 and Figure 15 Each of the above figures shows an example configuration of the via V6 according to this embodiment, excluding the via V6 directly below the storage element 50.

[0136] like Figure 13 As shown, the resistance R1 of the storage element 50 is, for example, 4.5 kΩ. In contrast, the resistance R2 of the via V6 of W is, for example, 50 Ω. Therefore, the resistance R2 of the via V6 of W is approximately 1% of the resistance R1 of the storage element 50. In this case, the via V6 directly below the storage element 50 is formed by W. Therefore, the resistance R2 of the via V6 of W has a negligible effect on the resistance R1 of the storage element 50, and W can be used as the material for the via V6 directly below the storage element 50.

[0137] like Figure 14 and Figure 15 As shown, multiple vias V6 (other vias V6 existing in the same interconnect layer as the via V6 directly below the storage element 50) can be provided for the metal film M6. Each via V6 is formed by W. Figure 14 In the example shown, there are nine through holes V6, and the planar shape of through hole V4 is square. Figure 15 In the example shown, there are three vias V6, and the planar shape of via V4 is rectangular. The planar shape is the shape in a direction orthogonal to the stacking direction of each layer (planar direction).

[0138] As described above, since multiple vias V6 are provided to the metal film M6, the total resistance can be reduced to approximately a few Ω compared to the case where a single via V6 with the same planar area as each of the vias V6 is provided to the metal film M6. Therefore, the total resistance of each of the vias V6 has a small effect on the resistance of the metal film M6, and W can be used as the material for the vias V6 except for the via V6 directly below the storage element 50.

[0139] For the metal film M6, the number and planar shape of the vias V6 are unrestricted. The number of vias V6 can be, for example, two, four, five, etc. Furthermore, the planar shape of the vias V6 does not have to be square or rectangular, but can be, for example, circular, elliptical, triangular, etc.

[0140] 1-5. Configuration examples of vias in the interconnect layer including storage elements

[0141] Reference Figures 16 to 20 The first to fifth configuration examples of the through-hole V6 of the connection layer including the storage element 50 according to this embodiment are described. Figures 16 to 20 This is a diagram illustrating configuration examples (first to fifth configuration examples) of a through-hole V6 in a connection layer including a storage element 50 according to this embodiment.

[0142] First configuration example

[0143] like Figure 16 As shown, in the logic section 110, a plurality of through holes V6 are provided between the metal film M5 and the metal film M6. Figure 16 In the example shown, there are two through holes V6. In the memory section 120, through holes V6 and memory element 50 are provided between metal film M5 and metal film M6.

[0144] The metal film M6 of the logic section 110 has multiple protrusions M6a (in) Figure 16 The example shown has two protrusions M6a. The thickness of each protrusion M6a is the same as the thickness of the storage element 50. Figure 16 In the example shown, each metal film M6 is formed of Cu, and each through-hole V6 is formed of W.

[0145] It should be noted that each protrusion M6a of the logic section 110 can serve as part of each via V6. In this case, the thickness of the W layer in each via V6 of the logic section 110 is greater than the thickness of the Cu layer.

[0146] Second configuration example

[0147] like Figure 17As shown, in the logic section 110, a plurality of through holes V6 are provided between the metal film M5 and the metal film M6. Figure 17 The example shown has two through holes (V6). However, Figure 17 Each via V6 of the logic section 110 on the left is formed by two W layers (processed twice). On the other hand, Figure 17 Each via V6 in the logic section 110 on the right is formed by one W layer (processed once). In the memory section 120, via V6, memory element 50, and via V6a are disposed between metal film M5 and metal film M6. Memory element 50 is sandwiched between via V6 and via V6a. Figure 17 In the example shown, each metal film M6 and each via V6 and V6a are formed by W.

[0148] Third Configuration Example

[0149] like Figure 18 As shown, in the logic section 110, the metal film M6 has a plurality of protrusions M6a (in Figure 18 The example shown has two protrusions (M6a), such as... Figure 16 As shown in the diagram. In the memory section 120, the metal film M6 has a protrusion M6a. The protrusion M6a of the memory section 120 is connected to the memory element 50. The thickness of each protrusion M6a in the logic section 110 is the same as the total thickness of the through-hole V6 and the protrusion M6a of the memory section 120. Figure 18 In the example shown, each metal film M6 is formed of Cu, and each through-hole V6 is formed of W.

[0150] Each protrusion M6a of the logic section 110 can serve as part of each via V6, and the protrusion M6a of the memory section 120 can serve as via V6a. In each via V6 of the logic section 110, the thickness of the Cu layer is greater than the thickness of the W layer.

[0151] Fourth configuration example

[0152] like Figure 19 As shown, in the logic section 110, the metal film M6 is integrated with multiple vias V6. However, Figure 19 Each via V6 of the logic section 110 on the left is formed by two Cu layers (processed twice). On the other hand, Figure 19 Each via V6 of the logic section 110 on the right is formed by a Cu layer (processed once). The memory section 120 has... Figure 18 The memory section 120 has the same configuration, but the through-hole V6 is formed of Cu. Figure 19 In the example shown, each metal film M6 and each through-hole V6 are formed of Cu.

[0153] Fifth configuration example

[0154] like Figure 20 As shown, the logic unit 110 has a relationship with Figure 19 The logic section 110 on the right has the same configuration. The memory section 120 has the same... Figure 19 The memory sections 120 on the right and left sides have the same configuration, but the through-hole V6 is formed by W.

[0155] As described above, in the logic section 110 and the memory section 120, the through-hole V6 of the connection layer including the storage element 50 is implemented by the various configurations described above (e.g., the first to fifth configuration examples), but is not limited thereto, and can be implemented by other configurations.

[0156] 1-6. Examples of manufacturing processes for storage devices

[0157] Reference Figures 21 to 25 An example of the manufacturing process of storage device 1 according to this embodiment is described. Figures 21 to 25 Each of these figures is a diagram used to describe the manufacturing process (manufacturing method) of the storage device 1 according to this embodiment. Figures 21 to 25 The main parts of the storage device 1 according to this embodiment are shown in the order of steps (e.g., the interconnection layer including storage element 50: see [link]). Figure 17 The manufacturing process of ).

[0158] like Figure 21 As shown, a plurality of through-holes V5 and a plurality of metal films M5 are formed in the insulating layer 201, and two insulating layers 202 are stacked on the insulating layer 201 in which each through-hole V5 and each metal film M5 are formed. As a wiring method, for example, wiring techniques using a conventional damascene method can be used. Note that a barrier metal film can be formed around each through-hole V5 and each metal film M5.

[0159] In the photolithography and etching steps, photolithography and etching are performed on the two insulating layers 202 on the insulating layer 201 on which each of the vias V5 and each of the metal films M5 are formed. Therefore, a plurality of openings H1 are formed reaching each metal film M5. These openings H1 are formed in a predetermined pattern shape. Note that the depth of the openings H1 is set such that the total thickness D1 of the vias V6 and the memory element 50 is greater than the thickness D2 of the vias V5 (see [link to image]). Figure 1 and Figure 2 ).

[0160] In the W-chemical vapor deposition (CVD) step, a W layer 211 is stacked on two insulating layers 202 in which each of the openings H1 is formed. Thus, each opening H1 is filled with W. Note that materials other than W can be used.

[0161] like Figure 22As shown, in the W-chemical mechanical polishing (CMP) step, the W layer 211 (see [reference]) stacked on the multilayer insulating layer 202 is polished by CMP. Figure 21 The surface is planarized, and multiple through holes V6 are formed in the two insulating layers 202.

[0162] In the element and upper electrode film formation step, a multilayer element layer 203 and an upper electrode layer 204 for forming the storage element 50 are stacked on two insulating layers 202 in which each of the vias V6 is formed. Note that the multilayer element layer 203 includes a lower electrode layer. Note that the thickness of the element layer 203 is set such that the total thickness D1 of the vias V6 and the storage element 50 is greater than the thickness D2 of the via V5 (see [link to documentation]). Figure 1 and Figure 2 ).

[0163] In the hard mask film formation step, two hard mask layers 205 are stacked on the upper electrode layer 204, which is stacked on two insulating layers 202, via the element layer 203. The hard mask layers 205 are used to process multiple memory elements 50.

[0164] like Figure 23 As shown, in the hard mask edge step, the upper electrode layer 204 and the hard mask layer 205 (see [reference]) are stacked on the component layer 203. Figure 22 Etching is performed, and the upper electrode layer 204 and the hard mask layer 205 are formed in a predetermined pattern shape.

[0165] In the element etching and interlayer film formation steps, firstly, the element layer 203, on which the upper electrode layer 204 and the hard mask layer 205 having a predetermined pattern shape are stacked, is etched to form a plurality of memory elements 50 and an insulating layer 206. Subsequently, an insulating layer 212 serving as an interlayer film is stacked on the two insulating layers 202 on which each of the memory elements 50 is formed.

[0166] In the interlayer film CMP step, the insulating layer 212, which is an interlayer film stacked on the two insulating layers 202 on which each of the storage elements 50 is formed, is planarized by CMP.

[0167] like Figure 24 As shown, in the contact formation step, the planarized insulating layer 212 is etched. This forms a plurality of openings H2 that respectively reach the via V6 and the storage element 50. These openings H2 are formed in a predetermined pattern shape.

[0168] In the W film formation step, a W layer 213 is stacked on the insulating layer 212 in which each of the openings H2 is formed. Therefore, each opening H2 is filled with W. Note that materials other than W can be used.

[0169] In the W-CMP process, the surface of the W layer 213 stacked on the insulating layer 212 is planarized by CMP. As a result, multiple through-holes V6a are formed in the insulating layer 212.

[0170] like Figure 25 As shown, in the wiring formation step, an insulating layer 214 is stacked on top of an insulating layer 212 in which each of the through-holes V6a is formed, and a plurality of metal films M6 are formed in the insulating layer 214. As a wiring method, for example, wiring techniques using a conventional damascene method can be used as described above.

[0171] The various layers described above can be formed using methods such as physical vapor deposition (PVD), represented by sputtering, ion beam deposition, and vacuum deposition, and chemical vapor deposition (CVD), represented by atomic layer deposition (ALD). Furthermore, these layers can be patterned using reactive ion etching (RIE) or ion milling. Preferably, the various layers are formed continuously in a vacuum apparatus, and can then be patterned.

[0172] 2. Second Embodiment

[0173] 2-1. Storage Device Configuration Example

[0174] Reference Figure 26 and Figure 27 A configuration example of storage device 1A according to this embodiment is described. Note that storage device 1A is substantially the same as storage device 1 described above, and therefore the differences between them will be described. Figure 26 This is a diagram illustrating a configuration example of storage device 1A according to this embodiment. Figure 27 This is a cross-sectional view showing an example configuration of the annular portion 520 according to this embodiment (along... Figure 26 (The cross-sectional view taken by line A1-A1 in the diagram). Figure 26 and Figure 27 The example shown schematically illustrates storage device 1A and its cross-sectional configuration.

[0175] like Figure 26 As shown, the storage device 1A includes a main body portion 510, an annular portion 520, and a scribing portion 530. The main body portion 510 is, for example, a chip region including the aforementioned logic circuit 100. The annular portion 520 is, for example, an annular region formed in a ring shape to surround the main body portion 510 in a plan view. The scribing portion 530 is, for example, an outer peripheral region for which cutting is performed (e.g., an outer peripheral region cut by a tool or blade).

[0176] like Figure 27As shown, the annular portion 520 is composed of a plurality of rings 521. Each ring 521 is composed of a multi-layer wiring structure, which alternately includes wiring layers and connection layers, for example, composed of each of metal films M1 to M8 and each of vias V1 to V8. Each of the vias V6 is, for example, composed of two W layers (processed twice) (W / W stack: see the second configuration example above and Figure 17 )form.

[0177] Each ring 521 is arranged to surround the main body 510 sequentially in a plan view. That is, the outer ring 521 surrounds the inner ring 521, and each ring 521 forms multiple layers around the main body 510 while surrounding the main body 510 in a plan view. Each ring 521 serves as a wall portion to prevent moisture, gases (e.g., corrosive gases), etc., from entering the main body 510. Therefore, moisture, gases, etc., can be prevented from entering the main body 510, and cracks in the main body 510 caused by cutting, etc., can also be suppressed. Therefore, quality deterioration can be suppressed.

[0178] It should be noted that, Figure 27 In the example shown, multiple rings 521 are provided, but the number of rings 521 can be only one. The frame widths of the individual rings 521 can be the same or different from each other. For example, the frame width of each ring 521 can become narrower or wider as the ring 521 is positioned further inward. The frame width of the annular portion 520 (annular region) is preferably in the range of, for example, tens to hundreds of micrometers. Furthermore, the multilayer wiring structures of the individual rings 521 can be the same or different from each other.

[0179] 2-2. Variations of the annular portion

[0180] Reference Figures 28 to 34 The first to sixth variations of the annular portion 520 according to this embodiment are described. Figures 28 to 32 These are cross-sectional views showing variations (first to fifth variations) of the configuration of the annular portion 520 according to this embodiment. Figure 33 This is a plan view showing a sixth variation of the annular portion 520 according to this embodiment. Figure 34 This is a cross-sectional view showing a sixth variation of the arrangement of the annular portion 520 according to this embodiment (along...). Figure 33 (Cross-section view taken from line A2-A2 in the diagram).

[0181] First variant

[0182] like Figure 28 As shown, in the first variant, each of the metal films M6 includes a protrusion M6a. Each of the metal films M6 and each of the protrusions M6a are formed of a Cu layer, and each of the vias V6 is formed of a W layer (Cu / W stack: see the first configuration example above and...). Figure 16 ).

[0183] Second variant

[0184] like Figure 29 As shown, in the second variant, each of the metal films M6 is formed of a Cu layer, and each of the vias V6 is formed of two Cu layers (Cu / Cu stack: see the fourth configuration example above). Figure 19 ).

[0185] Third variant

[0186] like Figure 30 As shown, in the third variation, the metal films M8 of ring 521 are integrated by coupling with each other. This metal film M8 is, for example, an AL layer. Note that the configuration of each of the vias V6 is the same as that of the second variation (see [link to second variation]). Figure 29 ).

[0187] Fourth variant

[0188] like Figure 31 As shown, in the fourth variant, the metal films M8 of ring 521 are integrated by coupling with each other, and the metal films M7 of ring 521 are integrated by coupling with each other. The metal films M8 are, for example, AL layers. Note that the configuration of each of the vias V6 is the same as the configuration example described above (see...). Figure 27 ).

[0189] Fifth variant

[0190] like Figure 32 As shown, in the fifth variant, each of the through-holes V6 is formed by a Cu layer.

[0191] Sixth variant

[0192] like Figure 33 and Figure 34 As shown, in the sixth variation, the annular portion 520 is formed as a mesh. For example, the annular portion 520 is formed as a mesh in one or both of the planar direction (planar view) and the stacking direction (vertical view). The stacking direction is the direction of the stacked layers, and the planar direction is the direction orthogonal to the stacking direction.

[0193] The rings 521 are coupled to each other, and the annular portions 520 are formed in a mesh pattern. For example, the individual metal films M6 of the rings 521 are coupled to each other. The coupling portions between them serve as coupling films (coupling layers). Furthermore, the individual vias V6 of the rings 521 are coupled to each other. The coupling portions between them serve as coupling vias (coupling layers).

[0194] It should be noted that in each ring 521, metal films M1 to M5 (excluding metal film M6) and metal films M7 and M8 can be coupled to each other between films of the same layer. Furthermore, in each ring 521, vias V1 to V5 (excluding via V6) and vias V7 and V8 can be coupled to each other between vias of the same layer. In each ring 521, it is desirable that one or both of the films and vias are coupled to each other.

[0195] According to the first to sixth modifications, as in the above configuration example, each ring 521 surrounds the main portion 510 in a planar view while forming multiple layers around the main portion 510. Therefore, moisture, gas, etc., can be prevented from entering the main portion 510, and the occurrence of cracks in the main portion 510 due to cutting, etc., can also be suppressed. Therefore, quality degradation can be suppressed. Furthermore, according to the sixth modification, since the ring portion 520 is formed in a mesh shape, moisture, gas, etc., can be reliably prevented from entering the main portion 510, and the occurrence of cracks in the main portion 510 due to cutting, etc., can also be reliably suppressed.

[0196] 3. Third embodiment

[0197] 3-1. Storage Device Configuration Example

[0198] Reference Figures 35 to 37 A configuration example of storage device 1B according to this embodiment is described. It should be noted that storage device 1B is substantially the same as storage device 1 described above; therefore, the differences between them will be described. Figure 35 This is a diagram illustrating an example of the circuit configuration of the storage device 1B according to this embodiment. Figure 36 This is a diagram illustrating an example configuration of bit unit B1 according to this embodiment. Figure 37 This is a graph showing the relationship between the resistance value of the storage element 50 according to this embodiment and the degree of change in the resistance value.

[0199] like Figure 35 As shown, the storage device 1B according to this embodiment includes a write circuit 610, a read circuit 620, a reference circuit 630, and a comparator 640. The write circuit 610, the read circuit 620, the reference circuit 630, and the comparator 640 are provided in either the logic unit 110 or the memory unit 120 described above.

[0200] like Figure 35 and Figure 36As shown, the write circuit 610 is a circuit that writes data to the storage element 50. Specifically, the write circuit 610 changes the resistance state of the storage element 50. The write circuit 610 includes a transistor 31 and a high-voltage transistor 611. For example, one terminal of the transistor 31 is connected to the storage element 50, and one terminal of the high-voltage transistor 611 is connected to the storage element 50. The high-voltage transistor 611 is directly connected to, for example, the power supply VCC (VSS).

[0201] Storage element 50 is a one-time programmable memory (OTP) and, for example, a magnetoresistive variable element. Storage element 50 includes at least a reference layer 51, a barrier layer 52, and a storage layer 53 (see [link to documentation]). Figure 36 When the barrier layer 52 is broken down, the resistance of the storage element 50 becomes very small. Therefore, the storage element 50 uses the difference in resistance before and after the barrier layer 52 is broken down to store data (e.g., 0 or 1). For example, when the barrier layer 52 is MgO, the breakdown of the barrier layer 52 is also called MgO breakdown.

[0202] The high-voltage transistor 611 can apply a high voltage to the storage element 50. This high voltage is a voltage capable of breaking down the barrier layer 52 of the storage element 50. For example, the high-voltage transistor 611 can apply a voltage in the range of 1.8V to 3.3V, with a median value of about 2.5V. By applying the high voltage, the barrier layer 52 of the storage element 50 is broken down. Therefore, for example, the resistance value of the storage element 50 decreases from 4kΩ to 1kΩ or less.

[0203] It should be noted that when a voltage higher than 3.3V is applied to the storage element 50, the portion of the storage element 50 other than the barrier layer 52 may be broken down. Therefore, it is desirable to apply a voltage equal to or less than 3.3V to the storage element 50. Furthermore, due to the use of the high-voltage transistor 611, the breakdown time of the barrier layer 52 used to break down the storage element 50 is relatively short. For example, when the applied voltage is 2.5V, the breakdown time is 100ns. For example, the breakdown time is 100ns or less.

[0204] Here, for reference Figure 37 It can be seen that before the barrier layer 52 of the storage element 50 is broken down, the low resistance value RL of the storage element 50 in its low resistance state and the high resistance value RH of the storage element 50 in its high resistance state are both sufficiently greater than 1kΩ. In contrast, it can be seen that after the barrier layer 52 of the storage element 50 is broken down, the resistance value of the storage element 50 is sufficiently less than 1kΩ. Since, for example, the resistance value of the storage element 50 is 1kΩ or less after breakdown, 1kΩ is set as the resistance value Rth1 used as the threshold. That is, the resistance value Rth1 used as the threshold is used to generate the reference voltage Vref (see...). Figure 35 ).

[0205] Refer again Figure 35 The read circuit 620 is a circuit that reads data from the storage element 50. Specifically, the read circuit 620 reads the resistance state (resistance value) of the storage element 50, i.e., generates a read voltage Vm corresponding to the resistance state. The read circuit 620 includes a plurality of transistors 621 and 622. For example, one terminal of transistor 621 is connected to the power supply VDD, and another terminal of transistor 621 is connected to the connection point P1. Furthermore, for example, one terminal of transistor 622 is connected to each of the storage element 50 and the high-voltage transistor 611, and another terminal of transistor 622 is connected to the connection point P1.

[0206] Reference circuit 630 generates a reference voltage Vref that is supplied to comparator 640. Reference circuit 630 includes multiple transistors 631, 632, and 633 and a resistor 634. For example, one terminal of transistor 631 is connected to resistor 634, and another terminal of transistor 631 is connected to connection point P2. Furthermore, for example, one terminal of transistor 632 is connected to power supply VDD, and another terminal of transistor 632 is connected to connection point P2. For example, one terminal of transistor 633 is connected to resistor 634. Resistor 634 is set to a resistance value Rth1, for example, used as a threshold.

[0207] Comparator 640 compares the read voltage Vm with the reference voltage Vref. Specifically, comparator 640 compares the read voltage Vm input from read circuit 620 with the reference voltage Vref input from reference circuit 630 and determines whether the data stored in storage element 50 is 0 or 1. A sense amplifier, for example, is used as comparator 640.

[0208] With this configuration, a high-voltage transistor 611 is placed in the write circuit 610. Therefore, the breakdown time required to break down the barrier layer 52 of the storage element 50 can be suppressed. Furthermore, a charge pump is not required, and thus the rise time of the applied voltage can be suppressed. It should be noted that a charge pump is, for example, an electronic circuit that increases the voltage by combining a capacitor and a switch.

[0209] 3-2. Example of bit cell layout

[0210] Reference Figures 38 to 45 A layout example of bit unit B1 according to this embodiment is described. Figure 38 and Figure 39 This is a diagram used to describe a first layout example according to this embodiment. Figure 40 and Figure 41 This is a diagram used to describe a second layout example according to this embodiment. Figure 42 and Figure 43This is a diagram used to describe a third layout example according to this embodiment. Figure 44 and Figure 45 This is a diagram used to describe a fourth layout example according to this embodiment.

[0211] First layout example

[0212] like Figure 38 As shown, bit unit B1 includes two transistors 31. Bit unit B1, together with storage element 50, constitutes, for example, a memory cell. That is, in Figure 38 In the example shown, the layout of bit cell B1 is a 2Tr-1E1 layout (two transistors 31 - one storage element 50).

[0213] exist Figure 38 In the example shown, nine storage elements 50 are arranged in bit cell B1, but only the storage element 50 located in the center of the storage element 50 is connected to the bit line BL. Therefore, the eight storage elements 50 other than the central storage element 50 are dummy elements. This also applies to other layout examples, namely the second layout example, the third layout example, and the fourth layout example.

[0214] Each transistor 31 is an NMOS transistor (N-type metal-oxide-semiconductor field-effect transistor). Cell isolation in the X-axis direction is performed by the gate (word line WL). Cell isolation in the Y-axis direction is performed by isolation section 650. Isolation section 650 isolates each bit cell B1 from each other. As isolation section 650, shallow trench isolation (STI) is used, for example.

[0215] like Figure 39 As shown, the storage element 50 and two transistors 31 are positioned between the bit line BL and the source line SL. Figure 39 In the example shown, one terminal of the storage element 50 is connected to the bit line BL, and the other terminal is connected to the source line SL via two transistors 31. The gate terminal of each of the two transistors 31 is connected to the word line WL.

[0216] It should be noted that, for example, the wiring width connected to the gate (e.g., electrode 31c) of the word line WL is wide, and the oxide film of the gate is thick. Furthermore, for example, in bit cell B1, the width of the planar mounting space (cell width) of each contact (e.g., metal film M4) connected to the source line SL is wider than the wiring width connected to the gate (e.g., electrode 31c) of the word line WL. Additionally, for example, in the memory cell array, the area (planar area) of the upper surface of substrate 30 (excluding isolation portion 650) is greater than the total area of ​​the upper surface of isolation portion 650 (total area of ​​the recess openings). This also applies to the second layout example, the third layout example, and the fourth layout example.

[0217] Second layout example

[0218] like Figure 40 As shown, the second layout example is essentially the same as the first layout example (see...). Figure 38 However, one of the transistors 31 is an NMOS transistor, and the other is a PMOS transistor (P-type metal-oxide-semiconductor field-effect transistor). The N-well (NW) and P-well (PW) are adjacent to each other. Cell isolation in the X-axis direction is performed by the gate (word line WL), and cell isolation in the Y-axis direction is performed by an isolation section 650 such as an STI.

[0219] like Figure 41 As shown, two of the storage element 50 and transistor 31 are positioned between the bit line BL and the source line SL. Figure 41 In the example shown, one terminal of the storage element 50 is connected to the bit line BL, and the other terminal is connected to the source line SL via two transistors 31. The gate terminals of the two transistors 31 (an NMOS transistor and a PMOS transistor) are connected to the word line WL, respectively.

[0220] Third layout example

[0221] like Figure 42 As shown, bit unit B1 includes a transistor 31. For example, bit unit B1, together with storage element 50, constitutes a memory cell. That is, in Figure 42 In the example shown, the layout of bit cell B1 is a 1Tr-1E1 (one transistor 31 - one storage element 50) layout. Transistor 31 is an NMOS transistor, and cell isolation in both the X-axis and Y-axis directions is performed by an isolation section 360 such as STI.

[0222] like Figure 43 As shown, storage element 50 and transistor 31 are disposed between bit line BL and source line SL. Figure 43 In the example shown, one terminal of storage element 50 is connected to bit line BL, and the other terminal is connected to source line SL via transistor 31. The gate terminal of transistor 31 is connected to word line WL.

[0223] Fourth layout example

[0224] like Figure 44 As shown, layout example 4 is basically the same as the second layout example (see Figure 40 As in the second layout example, one of the transistors 31 is an NMOS transistor, and the other is a PMOS transistor. The N-well (NW) and P-well (PW) are adjacent to each other. However, cell isolation in both the X-axis and Y-axis directions is performed by an isolation section 360 such as STI.

[0225] like Figure 45 As shown, two of the storage element 50 and transistor 31 are positioned between the bit line BL and the source line SL. Figure 45 In the example shown, one terminal of the storage element 50 is connected to the bit line BL, and the other terminal is connected to the source line SL via two transistors 31. The gate terminals of the two transistors 31 (an NMOS transistor and a PMOS transistor) are connected to the word line WL, respectively.

[0226] 4. Overview of each embodiment

[0227] As described above, each of the storage devices 1, 1A, or 1B according to each embodiment (which are all examples of semiconductor devices) includes multiple wiring layers (e.g., a first wiring layer group 10 and a second wiring layer group 20). Each wiring layer includes wiring (e.g., each of metal films M1 to M8), multiple contacts (e.g., each of vias V1 to V8) respectively disposed between the multiple wirings, and resistance-varying or capacitance-varying elements (e.g., storage element 50) disposed between any of the multiple wirings. The multiple contacts include a lower contact (e.g., via V6) located below the element and connecting the element to a first lower layer wiring (e.g., metal film M5), which is a wiring in a layer located below the element. The total thickness D1 of the lower contact and the element is greater than the thickness D2 of the first lower layer contact (e.g., via V5), which is located below the first lower layer wiring and is a contact connected to the first lower layer wiring (see [link to documentation]). Figure 1 and Figure 2 Therefore, the processing margin of components with varying resistance or capacitance can be increased, thereby suppressing quality degradation.

[0228] Furthermore, the thickness D11 of the lower contact (e.g., through-hole V6) can be greater than the thickness D2 of the first lower layer wiring (e.g., metal film M5) (see [reference]). Figures 1 to 3 Therefore, the processing margin of resistance-varying or capacitance-varying components can be reliably increased, thereby reliably suppressing quality degradation.

[0229] Furthermore, the planar area of ​​the lower contact (e.g., through-hole V6) can be larger than the planar area of ​​the first lower contact (e.g., through-hole V5) (see [reference]). Figure 2 Therefore, the resistance of the lower contact parts can be suppressed, thereby suppressing quality degradation.

[0230] Furthermore, the component (e.g., storage component 50) can be connected to a first upper layer wiring (e.g., metal film M6), which is wiring in a layer above the component, and the thickness of the first upper layer wiring can be greater than the thickness of the first lower layer wiring (e.g., metal film M5) (see [reference]). Figure 1 and Figure 2 Therefore, the resistance of the first upper layer wiring can be suppressed, thereby suppressing quality degradation.

[0231] Furthermore, a component (e.g., storage component 50) can be connected to a first upper layer wiring (e.g., metal film M6), which is a wiring in a layer above the component, and the linewidth of the first upper layer wiring can be wider than the linewidth of the first lower layer wiring (e.g., metal film M5) (see [reference]). Figure 1 and Figure 2 Therefore, the resistance of the first upper layer wiring can be suppressed, and thus the degradation of quality can be suppressed.

[0232] Furthermore, the multiple wirings may include a first lower layer wiring (e.g., metal film M5) and a second lower layer wiring (e.g., metal film M4), the second lower layer wiring being connected to the first lower layer wiring via a first lower layer contact (e.g., via V5), and the multiple contacts may include a first lower layer contact (e.g., via V5) and a second lower layer contact (e.g., via V4), the second lower layer contact being located in a layer below the second lower layer wiring (e.g., metal film M4) and connected to the second lower layer wiring (see [link to documentation]). Figure 1 (etc.). Therefore, quality degradation can be reliably suppressed.

[0233] In addition, the lower contact element (e.g., through-hole V6) may include a W layer or a Cu layer (see Figures 16 to 25 Therefore, the resistance of the lower contact can be suppressed, and thus the degradation of quality can be reliably suppressed.

[0234] In addition, the first lower contact (e.g., through-hole V5) may include a W layer (see Figures 21 to 25 Therefore, the resistance of the first lower contact can be suppressed, and thus the degradation of quality can be reliably suppressed.

[0235] Furthermore, the multiple contacts may include multiple second contacts (e.g., through-hole V6) located in the same layer as the lower contact and respectively connecting wiring pairs (e.g., metal films M5 and M6) in layers above and below this layer (see...). Figures 14 to 20 Therefore, the total resistance of each second contact can be reduced compared to the resistance obtained when only one second contact is provided, and thus the degradation of quality can be reliably suppressed.

[0236] Furthermore, each of the plurality of second contacts (e.g., through-hole V6) may include multiple layers (see [link to documentation]). Figures 16 to 19 Therefore, the resistance of the second contact can be suppressed, and thus the degradation of quality can be reliably suppressed.

[0237] Furthermore, each of the above layers may include a Cu layer and a W layer (see [link to documentation]). Figures 16 to 19 Therefore, the resistance of the second contact can be suppressed, and thus the degradation of quality can be reliably suppressed.

[0238] Furthermore, the thickness of the W layer can be greater than the thickness of the Cu layer (see [reference]). Figure 16 Therefore, the resistance of the second contact can be suppressed, and thus the degradation of quality can be reliably suppressed.

[0239] Furthermore, each of the above layers may include a first W layer and a second W layer (see...). Figure 17 Therefore, the resistance of the second contact can be suppressed, and thus the degradation of quality can be reliably suppressed.

[0240] Furthermore, the multiple wiring layers may include a first wiring layer group 10 and a second wiring layer group 20, wherein multiple wiring layers having a predetermined wiring spacing are stacked in the first wiring layer group 10, and multiple wiring layers having a wiring spacing wider than the predetermined wiring spacing of the first wiring layer group 10 are stacked in the second wiring layer group 20, and components (e.g., storage element 50) may be disposed in the second wiring layer group 20 (see [link]). Figure 1 Even with this configuration, quality degradation can be suppressed.

[0241] Furthermore, storage device 1, storage device 1A, or storage device 1B may also include a logic section 110 and a memory section 120. The logic section 110 and the memory section 120 each include multiple wiring layers. The components may be storage elements 50, and the memory section 120 may include storage elements 50, a first lower layer wiring (e.g., a metal film M5), and a lower contact (e.g., a via V6) (see...). Figure 1 Even with this configuration, quality degradation can be suppressed.

[0242] In addition, storage element 50 may be a magnetic tunnel junction (MTJ) element (see [link]). Figure 2 Even with this configuration, quality degradation can be suppressed.

[0243] In addition, the MTJ element can be a spin-transfer torque (STT)-magnetic random access memory (MRAM) or a voltage-controlled (VC)-MRAM (see [link]). Figure 2 Even with this configuration, quality degradation can be suppressed.

[0244] Furthermore, storage element 50 may be ferroelectric random access memory (FeRAM) (see [link]). Figure 2 Even with this configuration, quality degradation can be suppressed.

[0245] Furthermore, the storage device 1A may include a main body portion 510 and an annular portion 520. The main body portion 510 includes multiple wiring layers (e.g., a first wiring layer group 10 and a second wiring layer group 20), multiple contacts (e.g., each of vias V1 to V8), and elements (e.g., storage element 50). The annular portion 520 is formed in an annular shape to surround the main body portion 510 in a plan view (see [reference]). Figure 26 Therefore, the main body 510 can be protected, and thus quality deterioration can be suppressed.

[0246] Furthermore, the annular portion 520 can be formed by a plurality of rings 521 sequentially surrounding the main portion 510 in a plan view (see [reference]). Figure 27 Therefore, quality degradation can be reliably suppressed.

[0247] Furthermore, the annular portion 520 can be formed into a mesh (see...). Figure 33 and Figure 34 Therefore, quality degradation can be reliably suppressed.

[0248] Furthermore, the element (e.g., storage element 50) may include two magnetic layers (e.g., reference layer 51 and storage layer 53) and a non-magnetic layer (e.g., barrier layer 52) sandwiched between the two magnetic layers, and the storage device 1B may include a high-voltage transistor 611 that applies a voltage to the element to break down the non-magnetic layer (see [link to storage device 1B]). Figures 35 to 37 Therefore, the breakdown time required to break down the barrier layer 52 can be suppressed. Furthermore, no charge pump is required, thus suppressing the rise time of the applied voltage.

[0249] Furthermore, the resistance of the element (e.g., storage element 50) in which the non-magnetic layer (e.g., barrier layer 52) is broken down can be 1 kΩ or less (see [reference]). Figures 35 to 37 Therefore, accurate reading can be achieved.

[0250] 5. Other embodiments

[0251] Each configuration, process, etc., according to the above embodiments (including examples and modifications) can be implemented in various forms other than those described above. For example, the configuration and process are not limited to the examples described above, but can take various modes. Furthermore, for example, unless otherwise specified, the configurations, processes, specific names, or information including various data and parameters explained in the above description and drawings can be arbitrarily modified.

[0252] Furthermore, each configuration, process, etc., according to the above embodiments (including examples and modifications) does not necessarily need to be physically configured as shown in the figure. That is, the specific form of distribution or integration of each configuration, process, etc. is not limited to the examples shown, and can be functionally or physically distributed or integrated in any unit, in whole or in part, according to various loads, usage conditions, etc.

[0253] Furthermore, each configuration, process, etc., according to the above embodiments (including examples and modifications) can be appropriately combined. For example, at least a portion of one embodiment can be appropriately combined with at least a portion of another embodiment. Moreover, the effects in the embodiments are merely illustrative and not limiting, and other effects may also be obtained.

[0254] 6. Application Examples

[0255] 6-1. Various devices

[0256] Reference Figure 46 This describes application examples of storage device 1, storage device 1A, or storage device 1B according to the above embodiments (including examples and modifications). Figure 46 This is a diagram illustrating an application example of the aforementioned storage device 1, storage device 1A, or storage device 1B.

[0257] For example, storage device 1, storage device 1A, or storage device 1B can be applied to various sensing light conditions such as visible light, infrared light, ultraviolet light, and X-rays. For example, storage device 1, storage device 1A, or storage device 1B can be applied to various devices (electronic devices), electronic devices installed on various devices, etc., as described below.

[0258] For example, such as Figure 46As shown, storage device 1, storage device 1A, or storage device 1B is used for "an apparatus for imaging images for viewing, such as a digital camera or a mobile device with camera functionality", "an apparatus for transportation, such as an onboard sensor for imaging the front, rear, surroundings, and interior of a vehicle to facilitate safe driving (such as automatic stop, driver status recognition, etc.), a surveillance camera for monitoring moving vehicles or roads, or a distance measuring sensor for measuring the distance between vehicles", "an apparatus for household appliances (such as a TV, refrigerator, or air conditioner) that images the user's posture and performs device operation based on the posture", "an apparatus for medical or healthcare purposes, such as an endoscope or an apparatus for performing angiography by receiving infrared light", "an apparatus for security purposes, such as a surveillance camera for crime prevention or a camera for personal authentication", "an apparatus for beauty purposes, such as a skin measuring instrument for imaging the skin or a microscope for imaging the scalp", "an apparatus for sports purposes, such as an action camera or wearable camera for sports applications", "an apparatus for agriculture, such as a camera for monitoring the condition of fields or crops", etc.

[0259] The technology disclosed herein can be applied to a variety of products. For example, the technology disclosed herein can be used to implement electronic devices mounted on any type of mobile body, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility vehicles, aircraft, drones, ships, robots, construction machinery, or agricultural machinery (tractors). Furthermore, for example, the technology disclosed herein can be used to implement electronic devices mounted on endoscopic surgical systems or microsurgical systems. Additionally, the technology disclosed herein can be used to implement magnetic sensors as an example of electronic devices.

[0260] 6-2. Imaging equipment

[0261] Reference Figure 47 Description of imaging device 300 based on application example. Figure 47 This diagram illustrates a configuration example of an imaging device 300 according to an application example. The imaging device 300 is an example of an electronic device that incorporates storage device 1, storage device 1A, or storage device 1B. Examples of the imaging device 300 include digital still cameras, video cameras, and electronic devices with imaging capabilities, such as smartphones or mobile phones.

[0262] like Figure 47 As shown, the imaging device 300 includes an optical system 301, a shutter device 302, an imaging element 303 (solid-state imaging device), a control circuit (drive circuit) 304, a signal processing circuit 305, a monitor 306, and a memory 307. The imaging device 300 can capture still images and moving images.

[0263] The optical system 301 includes one or more lenses. The optical system 301 guides light (incident light) from the subject to the imaging element 303 and forms an image on the light-receiving surface of the imaging element 303.

[0264] The shutter device 302 is disposed between the optical system 301 and the imaging element 303. Under the control of the control circuit 304, the shutter device 302 controls the light illumination period and the light blocking period of the imaging element 303.

[0265] Imaging element 303 accumulates signal charge over a certain period of time based on light formed as an image via optical system 301 and shutter device 302. The signal charge accumulated in imaging element 303 is transferred according to a drive signal (timing signal) supplied from control circuit 304. Imaging element 303 can be, for example, a solid-state imaging device such as an image sensor.

[0266] The control circuit 304 outputs a drive signal for controlling the transmission operation of the imaging element 303 and the shutter operation of the shutter device 302, and drives the imaging element 303 and the shutter device 302.

[0267] The signal processing circuit 305 performs various signal processing operations on the signal charge output from the imaging element 303. The image (image data) obtained through the signal processing of the signal processing circuit 305 is supplied to the monitor 306 and the memory 307.

[0268] Based on image data supplied from signal processing circuitry 305, monitor 306 displays moving or still images imaged by imaging element 303. Examples of monitor 306 include panel display devices such as liquid crystal panels and organic electroluminescent (EL) panels.

[0269] The memory 307 stores image data supplied from the signal processing circuit 305, namely, image data of moving or still images captured by the imaging element 303. The memory 307 may be the aforementioned storage device 1, storage device 1A, or storage device 1B.

[0270] In the imaging device 300 configured as described above, by using the storage device 1, storage device 1A or storage device 1B as the memory 307, the same effect as in the above embodiment can be obtained.

[0271] 6-3. Distance measuring equipment

[0272] Reference Figure 48 Description of distance measuring device 400 based on application example. Figure 48This is a diagram illustrating a configuration example of a distance measuring device 400 according to an application example. The distance measuring device 400 is an example of an electronic device that incorporates storage device 1, storage device 1A, or storage device 1B.

[0273] like Figure 48 As shown, the distance measuring device (distance image sensor) 400 includes a light source unit 401, an optical system 402, an imaging element (solid-state imaging device) 403, a control circuit (drive circuit) 404, a signal processing circuit 405, a monitor 406, and a memory 407. The distance measuring device 400 can acquire a distance image corresponding to the distance to the subject by emitting light from the light source unit 401 to the subject and receiving light (modulated light or pulsed light) reflected from the surface of the subject.

[0274] The light source unit 401 emits light toward the subject. Examples of the light source unit 401 include a vertical-cavity surface-emitting laser (VCSEL) array that emits laser light as a surface light source, or a laser diode array in which laser diodes are arranged along a line. Note that the laser diode array is supported by a predetermined driving unit (not shown) and scanned in a direction perpendicular to the arrangement direction of the laser diodes.

[0275] The optical system 402 includes one or more lenses. The optical system 402 guides light (incident light) from the subject to the imaging element 403 and forms an image on the light-receiving surface (sensor unit) of the imaging element 403.

[0276] Imaging element 403 accumulates signal charge based on light formed as an image via optical system 402. A distance signal, indicating the distance determined from the light received signal (APD OUT) output by imaging element 403, is supplied to signal processing circuit 405. Imaging element 403 may be, for example, a solid-state imaging device such as an image sensor.

[0277] The control circuit 404 outputs a drive signal (control signal) for controlling the operation of the light source unit 401, the imaging element 403, etc., and drives the light source unit 401, the imaging element 403, etc.

[0278] The signal processing circuit 405 performs various signal processing operations on the distance signal supplied from the imaging element 403. For example, the signal processing circuit 405 performs image processing (such as histogram processing and peak detection processing) to construct a distance image based on the distance signal. The image (image data) obtained by the signal processing performed by the signal processing circuit 405 is supplied to the monitor 406 and the memory 407.

[0279] Based on image data supplied from signal processing circuitry 405, monitor 406 displays a distance image imaged by imaging element 403. Examples of monitor 406 include panel display devices such as liquid crystal panels and organic EL panels.

[0280] The memory 407 stores image data supplied from the signal processing circuit 405, namely, image data of the distance image image captured by the imaging element 403. The memory 407 may be, for example, the storage device 1, storage device 1A, or storage device 1B described above.

[0281] In the distance measuring device 400 configured as described above, the same effect as in the above embodiment can be obtained by using the storage device 1, storage device 1A or storage device 1B as the memory 407.

[0282] As described above, storage device 1, storage device 1A, or storage device 1B can be installed in various electronic devices. For example, in addition to imaging device 300 and distance measuring device 400, storage device 1, storage device 1A, or storage device 1B can also be installed in various electronic devices such as hard disk drives (HDDs), notebook personal computers (PCs), mobile devices (e.g., smartphones or tablet PCs), personal digital assistants (PDAs), wearable devices, gaming devices, and music devices. For example, storage device 1, storage device 1A, or storage device 1B can be used as various types of memory, such as RAM.

[0283] 7. Supplementary Explanation

[0284] It should be noted that this technology can be configured as follows.

[0285] (1) A semiconductor device includes: a plurality of wiring layers, each wiring layer including wiring; a plurality of contacts disposed between the plurality of wirings; and a resistance-varying or capacitance-varying element disposed between any of the plurality of wirings. The plurality of contacts includes a lower contact located below the element and configured to connect the element to a first lower layer wiring (which is a wiring in a layer below the element), and the total thickness of the lower contact and the element is greater than the thickness of the first lower layer contact, the first lower layer contact being located in a layer below the first lower layer wiring and being a contact connected to the first lower layer wiring.

[0286] (2) In the semiconductor device described in (1) above, the thickness of the lower contact is greater than the thickness of the first lower contact.

[0287] (3) In the semiconductor device described in (2) above, the planar area of ​​the lower contact is greater than the planar area of ​​the first lower contact.

[0288] (4) In any one of (1) to (3) above, the element is connected to a first upper layer wiring (the first upper layer wiring is a wiring in a layer above the element), and the thickness of the first upper layer wiring is greater than the thickness of the first lower layer wiring.

[0289] (5) In any one of (1) to (4) above, the element is connected to a first upper layer wiring (the first upper layer wiring is a wiring in a layer above the element), and the line width of the first upper layer wiring is greater than the line width of the first lower layer wiring.

[0290] (6) In any one of (1) to (5) above, the plurality of wirings include a first lower layer wiring and a second lower layer wiring (the second lower layer wiring is a wiring connected to the first lower layer wiring via a first lower layer contact). The plurality of contacts include a first lower layer contact and a second lower layer contact (the second lower layer contact is a contact located in a layer below the second lower layer wiring and connected to the second lower layer wiring).

[0291] (7) In any one of (1) to (6) above, the lower contact includes a W layer or a Cu layer.

[0292] (8) In any one of (1) to (7) above, the first lower contact includes a W layer.

[0293] (9) In any one of (1) to (8) above, the plurality of contacts include a plurality of second contacts located in the same layer as the lower contacts and configured to connect wiring pairs located in layers above and below the layer respectively.

[0294] (10) In the semiconductor device described in (9) above, each of the plurality of second contacts includes a plurality of layers.

[0295] (11) In the semiconductor device described in (10) above, the multiple layers include a Cu layer and a W layer.

[0296] (12) In the semiconductor device described in (11) above, the thickness of the W layer is greater than the thickness of the Cu layer.

[0297] (13) In the semiconductor device described in (10) above, the plurality of layers include a first W layer and a second W layer.

[0298] (14) In any one of (1) to (13) above, the plurality of wiring layers include: a first wiring layer group, wherein a plurality of wiring layers having a predetermined wiring spacing are stacked; and a second wiring layer group, wherein a plurality of wiring layers having a wiring spacing wider than the predetermined wiring spacing of the first wiring layer group are stacked, and an element is disposed in the second wiring layer group.

[0299] (15) The semiconductor device described in any one of (1) to (14) above further includes a logic section and a memory section, each of which includes multiple wiring layers, the elements being storage elements, and the memory section including storage elements, a first lower layer wiring layer and a lower contact.

[0300] (16) The semiconductor device described in (1) above further includes a main part, the main part including a plurality of wiring layers, a plurality of contacts and elements; and a ring part formed in a ring shape to surround the main part in a plan view.

[0301] (17) In the semiconductor device described in (16) above, the ring portion is formed by a plurality of rings that sequentially surround the main portion in a plan view.

[0302] (18) In the semiconductor device described in (16) or (17) above, the ring portion is formed in a grid shape.

[0303] (19) In any of the above (1) to (18), the element comprises two magnetic layers and a non-magnetic layer sandwiched between the two magnetic layers, and the semiconductor device comprises a high-voltage transistor that applies a voltage to the element to break down the non-magnetic layer.

[0304] (20) In the semiconductor device described in (19) above, the resistance of the element in which the non-magnetic layer is broken down is 1 kΩ or less.

[0305] (21) In any of the semiconductor devices described in (1) to (20) above, the element is a magnetic tunnel junction (MTJ) element.

[0306] (22) In the semiconductor device described in (21) above, the MTJ element is a spin-transfer torque (STT) magnetic random access memory (MRAM) or a voltage-controlled (VC) MRAM.

[0307] (23) In any of the semiconductor devices described in (1) to (20) above, the element is a ferroelectric random access memory (FeRAM).

[0308] (24) An electronic device includes a semiconductor device, and the semiconductor device includes: a plurality of wiring layers, each wiring layer including wiring; a plurality of contacts disposed between the plurality of wirings; and a resistance-varying or capacitance-varying element disposed between any of the plurality of wirings. The plurality of contacts includes a lower contact located below the element, the lower contact configured to connect the element to a first lower layer wiring, the first lower layer wiring being a wiring in a layer below the element; and the total thickness of the lower contact and the element is greater than the thickness of the first lower layer contact in a layer below the first lower layer wiring, the first lower layer contact being a contact connected to the first lower layer wiring.

[0309] (25) A method of manufacturing a semiconductor device includes: generating a plurality of wiring layers, each wiring layer having wiring; disposing a plurality of contacts between the plurality of wirings; and disposing a resistance-varying or capacitance-varying element between any of the plurality of wirings. The plurality of contacts includes a lower contact located below the element, the lower contact configured to connect the element to a first lower layer wiring, the first lower layer wiring being a wiring in a layer below the element; and the total thickness of the lower contact and the element is greater than the thickness of the first lower layer contact in a layer below the first lower layer wiring, the first lower layer contact being a contact connected to the first lower layer wiring.

[0310] (26) An electronic device includes the semiconductor device described in any one of (1) to (23) above.

[0311] (27) A method of manufacturing a semiconductor device manufactures the semiconductor device described in any one of (1) to (23) above.

[0312] List of reference numerals

[0313] 1. Storage device

[0314] 1A Storage Device

[0315] 1B storage device

[0316] 10 First wiring layer group

[0317] 20 Second wiring layer group

[0318] 30 substrate

[0319] 31 transistors

[0320] 31a First diffusion layer

[0321] 31b Second diffusion layer

[0322] 31C electrode

[0323] 50 storage elements

[0324] 51 Reference Layer

[0325] 52 Barrier Layer

[0326] 53 Storage Layer

[0327] 54 Lower electrode

[0328] 55 Upper electrode

[0329] 100 Logic Circuits

[0330] 110 Logic Department

[0331] 120 Memory Section

[0332] 201 Insulation Layer

[0333] 202 Insulation Layer

[0334] 203 Component Layer

[0335] 204 Upper electrode layer

[0336] 205 Hard Mask Layer

[0337] 206 Insulation Layer

[0338] 211 W Floor

[0339] 212 Insulation layer

[0340] 213 W floor

[0341] 214 Insulation layer

[0342] 300 Imaging Equipment

[0343] 307 Memory

[0344] 400 Distance Measuring Equipment

[0345] 407 Memory

[0346] 510 Main Department

[0347] 520 Ring Road

[0348] 521 rings

[0349] 530 Marked section

[0350] 610 Write Circuit

[0351] 611 High Voltage Transistor

[0352] 620 Reading Circuit

[0353] 621 transistors

[0354] 622 transistors

[0355] 630 Reference Circuit

[0356] 631 transistors

[0357] 632 transistors

[0358] 633 transistors

[0359] 634 resistor

[0360] 640 comparator

[0361] B1 bit unit

[0362] D1 Total Thickness

[0363] D2 thickness

[0364] D11 thickness

[0365] D21 thickness

[0366] H1 opening

[0367] H2 opening

[0368] M1 Metal Film

[0369] M2 Metal Film

[0370] M3 Metallic Film

[0371] M4 Metallic Film

[0372] M5 Metallic Film

[0373] M6 Metallic Film

[0374] M7 Metallic Film

[0375] M8 Metallic Film

[0376] M6a protrusion

[0377] V1 Through Hole

[0378] V2 through hole

[0379] V3 through hole

[0380] V4 through hole

[0381] V5 through hole

[0382] V6 through hole

[0383] V6a through hole

[0384] V7 through hole

[0385] V8 through hole

Claims

1. A semiconductor device, comprising: Multiple routing layers, each routing layer including routing; Multiple contacts are respectively arranged between multiple wires; as well as A resistance-changing element or a capacitance-changing element disposed between any of the plurality of wirings, wherein The plurality of contacts includes a lower contact located below the element and configured to connect the element to a first lower layer wiring, the first lower layer wiring being wiring in a layer located below the element, and The total thickness of the lower contact and the element is greater than the thickness of the first lower contact in the layer below the first lower wiring, the first lower contact being a contact connected to the first lower wiring.

2. The semiconductor device according to claim 1, wherein The thickness of the lower contact element is greater than the thickness of the first lower contact element.

3. The semiconductor device according to claim 2, wherein The planar area of ​​the lower contact element is greater than the planar area of ​​the first lower contact element.

4. The semiconductor device according to claim 1, wherein The component is connected to a first upper-layer wiring, which is wiring in a layer located above the component. The thickness of the first upper layer wiring is greater than the thickness of the first lower layer wiring.

5. The semiconductor device according to claim 1, wherein The component is connected to a first upper-layer wiring, which is wiring in a layer located above the component. The width of the first upper layer routing is greater than the width of the first lower layer routing.

6. The semiconductor device according to claim 1, wherein The plurality of wirings includes First lower-level wiring, and The second lower-layer wiring is wiring that is connected to the first lower-layer wiring via the first lower-layer contact, and The plurality of contacts include First lower layer contact component, and The second lower layer contact is a contact located in the layer below the second lower layer wiring and connected to the second lower layer wiring.

7. The semiconductor device according to claim 1, wherein The lower contact element includes a W layer or a Cu layer.

8. The semiconductor device according to claim 1, wherein The first lower-level contact element includes the W layer.

9. The semiconductor device according to claim 1, wherein The plurality of contacts include A plurality of second contacts are located in the same layer as the lower contact and are configured to connect wiring pairs located in layers above and below the lower contact, respectively.

10. The semiconductor device according to claim 9, wherein Each of the plurality of second contacts comprises multiple layers.

11. The semiconductor device of claim 10, wherein The multiple layers include a Cu layer and a W layer.

12. The semiconductor device according to claim 11, wherein The thickness of the W layer is greater than the thickness of the Cu layer.

13. The semiconductor device of claim 10, wherein The plurality of layers includes a first W layer and a second W layer.

14. The semiconductor device according to claim 1, wherein The plurality of wiring layers include The first wiring layer group, wherein multiple wiring layers with predetermined wiring spacing are stacked, and The second wiring layer group includes multiple wiring layers stacked together, each having a wiring spacing wider than the predetermined wiring spacing of the first wiring layer group. The element is disposed in the second wiring layer group.

15. The semiconductor device according to claim 1, further comprising: Each includes a logic section and a memory section with multiple wiring layers, wherein The element is a storage element, and The memory unit includes The storage element, First lower-level wiring, and The lower contact element.

16. The semiconductor device according to claim 1, further comprising: The main part includes the plurality of wiring layers, the plurality of contacts, and the elements; as well as The annular portion is formed as an annular shape to surround the main portion in a plan view.

17. The semiconductor device of claim 16, wherein The annular portion is formed by multiple rings that sequentially surround the main portion in a plan view.

18. The semiconductor device of claim 16, wherein The annular portion is formed into a mesh.

19. The semiconductor device according to claim 1, wherein The element includes Two magnetic layers, and The non-magnetic layer sandwiched between the two magnetic layers, and The semiconductor device includes a high-voltage transistor that applies a voltage to the element that breaks down the non-magnetic layer.

20. The semiconductor device of claim 19, wherein The resistance of the element in which the non-magnetic layer is broken down is 1 kΩ or less.

21. An electronic device comprising: Semiconductor equipment, among which The semiconductor device includes Multiple routing layers, each routing layer includes routing. Multiple contacts are respectively arranged between multiple wires; as well as A resistance-changing element or a capacitance-changing element disposed between any of the plurality of wirings. The plurality of contacts includes a lower contact configured to connect the element to a first lower layer wiring, the first lower layer wiring being wiring in a layer located below the element, and The total thickness of the lower contact and the element is greater than the thickness of the first lower contact in the layer below the first lower wiring, the first lower contact being a contact connected to the first lower wiring.

22. A method for manufacturing a semiconductor device, the method comprising: Generate multiple routing layers, each with routing; Multiple contacts are set between multiple wirings; as well as A resistance-changing or capacitance-changing element is placed between any of the plurality of wirings, wherein The plurality of contacts include a lower contact configured to connect the element to a first lower layer wiring, the first lower layer wiring being wiring in a layer located below the element, and The total thickness of the lower contact and the element is greater than the thickness of the first lower contact in the layer below the first lower wiring, the first lower contact being a contact connected to the first lower wiring.

Images