TVS diode

Abstract

The semiconductor chip of the TVS diode includes a first pin junction of a first polarity direction and a second pin junction, and a diode pair region disposed apart from both the first pin junction and the second pin junction in a plan view. The diode pair region includes a first reverse pin junction of a second polarity direction and a second reverse pin junction, and a pn junction of the first polarity direction disposed at a position overlapping the first reverse pin junction and the second reverse pin junction in the plan view and forming a diode pair with the first reverse pin junction and the second reverse pin structure. The diode pair region is disposed between the first pin junction and the second pin junction in the plan view.

Description

Technical Field

[0001] This disclosure relates to TVS diodes. Background Technology

[0002] Patent document 1 discloses a diode chip that includes a TVS (Transient Voltage Suppressor) circuit. Existing technical documents Patent documents

[0003] Patent Document 1: Japanese Patent Application Publication No. 2021-57490. Summary of the Invention

[0004] (summary) Improvements in the electrical characteristics of TVS diodes are desired.

[0005] A TVS diode according to the present disclosure includes a semiconductor chip having a first side and a second side located on the side opposite to the first side. The semiconductor chip includes: a first pin junction and a second pin junction with a first polarity direction, disposed in a region of the semiconductor chip biased towards the first side; and a diode pair region including a first reverse pin junction, a second reverse pin junction, and a pn junction with a first polarity direction. The first reverse pin junction and the second reverse pin junction are disposed in the region of the semiconductor chip biased towards the first side. The pn junction with the first polarity direction is disposed at a position overlapping the first reverse pin junction and the second reverse pin junction in a top view viewed from the thickness direction of the semiconductor chip, and forms a diode pair with the first reverse pin junction and the second reverse pin junction. The diode pair region is separated from the first pin junction and the second pin junction in the top view, and the diode pair region is disposed between the first pin junction and the second pin junction in the top view. Attached Figure Description

[0006] Figure 1 This is a simplified top view of an exemplary TVS diode of the first embodiment. Figure 2 It is Figure 1 A simplified cross-sectional view obtained by cutting a TVS diode along the F2-F2 line. Figure 3 It is Figure 1 A simplified cross-sectional view obtained by cutting a TVS diode along line F3-F3. Figure 4 This is a simplified top view of a semiconductor chip. Figure 5 It is Figure 3A simplified cross-sectional view obtained by cutting a TVS diode along the F5-F5 line. Figure 6 It is Figure 5 A partially enlarged, simplified sectional view. Figure 7 This is a simplified top view of the first to third connecting electrodes and wiring on a semiconductor chip. Figure 8 This is a simplified circuit diagram of a TVS diode. Figure 9 This is a simplified cross-sectional view illustrating an exemplary manufacturing process of the TVS diode according to the first embodiment. Figure 10 It means to continue Figure 9 A simplified cross-sectional view of the manufacturing process shown. Figure 11 It means to continue Figure 10 A simplified cross-sectional view of the manufacturing process shown. Figure 12 It means to continue Figure 11 A simplified cross-sectional view of the manufacturing process shown. Figure 13 It means to continue Figure 12 A simplified cross-sectional view of the manufacturing process shown. Figure 14 It means to continue Figure 13 A simplified cross-sectional view of the manufacturing process shown. Figure 15 It means to continue Figure 14 A simplified cross-sectional view of the manufacturing process shown. Figure 16 It means to continue Figure 15 A simplified cross-sectional view of the manufacturing process shown. Figure 17 It means to continue Figure 16 A simplified cross-sectional view of the manufacturing process shown. Figure 18 It means to continue Figure 17 A simplified cross-sectional view of the manufacturing process shown. Figure 19 It means to continue Figure 18 A simplified cross-sectional view of the manufacturing process shown. Figure 20 It means to continue Figure 19 A simplified cross-sectional view of the manufacturing process shown. Figure 21 It means to continue Figure 20 A simplified cross-sectional view of the manufacturing process shown. Figure 22 It means to continue Figure 21 A simplified cross-sectional view of the manufacturing process shown. Figure 23 It means to continue Figure 22 A simplified cross-sectional view of the manufacturing process shown. Figure 24 It means to continue Figure 23 A simplified cross-sectional view of the manufacturing process shown. Figure 25 It means to continue Figure 24 A simplified cross-sectional view of the manufacturing process shown. Figure 26 It is Figure 2 A simplified cross-sectional view of the diode area and its surroundings, magnified. Figure 27 This is a simplified cross-sectional view of the second pin junction, the third pin junction, and their surroundings. Figure 28 This is a simplified cross-sectional view of the TVS diode according to the second embodiment. Figure 29 Is with Figure 28 Brief cross-sectional views of TVS diodes at different locations. Figure 30 It is Figure 28 A partially enlarged, simplified sectional view. Figure 31 It is a graph showing the relationship between the position of a semiconductor chip in the thickness direction and the impurity concentration. Figure 32 This is a simplified cross-sectional view illustrating the exemplary manufacturing process of the TVS diode according to the second embodiment. Figure 33 It means to continue Figure 32 A simplified cross-sectional view of the manufacturing process shown. Figure 34 This is a simplified top view of the semiconductor chip in the TVS diode according to the third embodiment. Figure 35 It is Figure 34 A simplified cross-sectional view obtained by cutting a TVS diode along the F35-F35 line. Figure 36 It is Figure 34 A simplified cross-sectional view obtained by cutting a TVS diode along the F36-F36 line. Figure 37 This is a simplified cross-sectional view illustrating an exemplary manufacturing process of the TVS diode according to the third embodiment. Figure 38 It means to continue Figure 37 A simplified cross-sectional view of the manufacturing process shown. Figure 39It means to continue Figure 38 A simplified cross-sectional view of the manufacturing process shown. Figure 40 This is a simplified top view of the semiconductor chip in the TVS diode according to the fourth embodiment. Figure 41 This is a simplified top view of the first to third connecting electrodes and wiring on a semiconductor chip. Figure 42 It is Figure 40 A simplified cross-sectional view obtained by cutting a TVS diode along the F42-F42 line. Figure 43 This is a simplified top view of a TVS diode. Figure 44 This is a simplified top view of the semiconductor chip in the TVS diode according to the fifth embodiment. Figure 45 It is a simplified top view of the first connecting electrode, the second connecting electrode, and the wiring disposed on the semiconductor chip. Figure 46 This is a simplified top view of a TVS diode. Figure 47 This is a simplified top view of the semiconductor chip in the TVS diode according to the sixth embodiment. Figure 48 It is a simplified top view of the first connecting electrode, the second connecting electrode, and the wiring disposed on the semiconductor chip. Figure 49 This is a simplified top view of a TVS diode. Figure 50 This is a simplified top view of the semiconductor chip in the TVS diode according to the seventh embodiment. Figure 51 It is Figure 50 A simplified cross-sectional view obtained by cutting a TVS diode along the F51-F51 line. Figure 52 This is a simplified top view of the first to fourth connecting electrodes and wiring on a semiconductor chip. Figure 53 This is a simplified top view of a TVS diode. Figure 54 This is a simplified top view of the semiconductor chip in the TVS diode according to the eighth embodiment. Figure 55 It is a simplified top view of the first connecting electrode, the second connecting electrode, and the wiring disposed on the semiconductor chip. Figure 56 This is a simplified top view of a TVS diode. Figure 57 This is a simplified cross-sectional view of a modified TVS diode. Figure 58This is a simplified cross-sectional view of a modified TVS diode. Figure 59 This is a simplified top view of the first to third connecting electrodes and wiring on the semiconductor chip in a modified TVS diode. Figure 60 It is Figure 59 A simplified cross-sectional view obtained by cutting a TVS diode along the F60-F60 line. Figure 61 This is a simplified top view of a modified TVS diode. Figure 62 It is Figure 61 A simplified cross-sectional view obtained by cutting a TVS diode along the F62-F62 line. Figure 63 It is Figure 61 A simplified cross-sectional view obtained by cutting a TVS diode along the F63-F63 line. Detailed Implementation

[0007] (Detailed explanation) Hereinafter, several embodiments of the TVS diode in this disclosure will be described with reference to the accompanying drawings. Furthermore, to simplify and clarify the description, the constituent elements shown in the drawings are not necessarily drawn to a fixed scale. Additionally, for ease of understanding, shading lines are sometimes omitted in sectional views. The drawings are merely illustrative of embodiments of this disclosure and should not be considered as limiting the scope of this disclosure.

[0008] The following detailed description includes apparatus, systems, and methods that embody exemplary embodiments of the present disclosure. These detailed descriptions are merely illustrative and are not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0009] As used in this disclosure, the expression "at least one" means "more than one" of the desired options. As an example, when the number of options is two, the expression "at least one" means "only one option" or "both options". As another example, when the number of options is three or more, the expression "at least one" means "only one option" or "a combination of any two or more options".

[0010] The phrase "the dimensions (depth, width, length) of A are equal to the dimensions (depth, width, length) of B" or "the dimensions (depth, width, length) of A and B are equal to each other" as used in this disclosure also includes a relationship where the difference between the dimensions (depth, width, length) of A and B is, for example, within 10% of the dimensions (depth, width, length) of A. Similarly, the phrase "the concentration of A is equal to the concentration of B" or "the concentration of A and B are equal to each other" as used in this disclosure also includes a relationship where the difference between the concentrations of A and B is, for example, within 10% of the concentration of A.

[0011] (First Implementation) (Structure of a TVS diode) Reference Figures 1-3 The structure of the TVS diode 10 in the first embodiment will be described. Figure 1 The top view of the TVS diode 10 is shown schematically. Figure 2 schematically shown Figure 1 The cross-sectional structure at line F2-F2. Figure 3 schematically shown Figure 1 The cross-sectional structure at line F3-F3.

[0012] like Figure 1 As shown, TVS diode 10 includes TVS circuit 200 (see reference). Figure 8 The diode chip, wherein the TVS circuit 200 is used to protect electrical circuits from ESD (Electro-Static Discharge). Further details regarding the TVS circuit 200 will be provided using... Figure 8 This will be described later. Such a TVS diode 10 is used, for example, for the protection of interfaces in electronic devices such as wearable devices and smartphones.

[0013] The TVS diode 10 includes a cuboid semiconductor chip 20. The semiconductor chip 20 is made of a material containing, for example, silicon (Si). Alternatively, the semiconductor chip 20 can be described as a flat plate with the Z-direction as its thickness direction. From now on, viewing the TVS diode 10 from the Z-direction will be referred to as "top view." Furthermore, directions orthogonal to each other among directions orthogonal to the Z-direction will be designated as the "X-direction" and the "Y-direction." Here, the X-direction is an example of a "second direction," and the Y-direction is an example of a "first direction."

[0014] Semiconductor chip 20 includes a first surface 20S and a second surface 20R located on the side opposite to the first surface 20S (see reference). Figure 2The semiconductor chip 20 comprises four sides, namely the first to fourth sides 20A to 20D, connecting the first surface 20S and the second surface 20R. In one example, the first surface 20S and the second surface 20R are formed by planes orthogonal to the Z direction. The first side 20A and the second side 20B constitute the two end faces of the semiconductor chip 20 in the X direction. The third side 20C and the fourth side 20D constitute the two end faces of the semiconductor chip 20 in the Y direction.

[0015] (Cross-sectional view of a TVS diode) like Figure 2 and Figure 3 As shown, the semiconductor chip 20 includes a semiconductor substrate 21 and a semiconductor layer 22 disposed on the semiconductor substrate 21.

[0016] The semiconductor substrate 21 is made of a material containing Si (silicon). In one example, a Si substrate is used for the semiconductor substrate 21. Alternatively, a SiC (silicon carbide) substrate can also be used for the semiconductor substrate 21. The semiconductor substrate 21 is a flat plate with the Z-direction as its thickness direction. The thickness of the semiconductor substrate 21 can be set to 10 μm or more and 800 μm or less. In one example, the thickness of the semiconductor substrate 21 is 30 μm or more and 400 μm or less.

[0017] The semiconductor substrate 21 contains p-type impurities. In one example, the semiconductor substrate 21 has a generally certain p-type impurity concentration throughout its entire area. The p-type impurity concentration of the semiconductor substrate 21 can be set to 1 × 10⁻⁶. 19 cm -3 Above and 1×10 21 cm -3 Below. In one example, the p-type impurity concentration of semiconductor substrate 21 is 1 × 10⁻⁶. 19 cm -3 Above and 1×10 20 cm -3 the following.

[0018] The semiconductor layer 22 is formed by an epitaxial layer disposed on the semiconductor substrate 21. In one example, the semiconductor layer 22 is formed by a stacked structure of a first semiconductor layer 23, a second semiconductor layer 24, and a third semiconductor layer 25. Furthermore, in... Figure 2 and Figure 3 In the diagram, the boundaries between the first semiconductor layer 23 and the second semiconductor layer 24, as well as the boundaries between the second semiconductor layer 24 and the third semiconductor layer 25, are shown with dashed lines.

[0019] The first semiconductor layer 23 is formed by a p-type epitaxial layer disposed on the upper surface of the semiconductor substrate 21. The thickness of the first semiconductor layer 23 can be set to 5 μm or more and 20 μm or less. In one example, the thickness of the first semiconductor layer 23 is 10 μm or more and 18 μm or less. In another example, the thickness of the first semiconductor layer 23 is about 15 μm.

[0020] The p-type impurity concentration of the first semiconductor layer 23 is lower than that of the semiconductor substrate 21. The first semiconductor layer 23 has a concentration gradient in which the p-type impurity concentration gradually decreases from the semiconductor substrate 21 toward the crystal growth direction. That is, the p-type impurity concentration of the first semiconductor layer 23 includes a portion that decreases in the Z direction as it moves away from the semiconductor substrate 21. The degree of decrease in the p-type impurity concentration of the first semiconductor layer 23 increases as it moves away from the semiconductor substrate 21. The p-type impurity concentration of the first semiconductor layer 23 gradually decreases until it reaches a minimum value of 1 × 10⁻⁶. 15 cm -3 Above and 1×10 17 cm -3 The following range. The minimum value of the p-type impurity concentration of the first semiconductor layer 23 can be set, for example, to 1 × 10⁻⁶. 16 cm -3 Above and 1×10 17 cm -3 The following range.

[0021] The second semiconductor layer 24 is formed by an n-type epitaxial layer disposed on the upper surface of the first semiconductor layer 23. The thickness of the second semiconductor layer 24 can be set to 1 μm or more and 10 μm or less. In one example, the thickness of the second semiconductor layer 24 is 5 μm or more and 8 μm or less. In another example, the thickness of the second semiconductor layer 24 is about 7 μm. Here, n-type is an example of a "first conductivity type". Alternatively, the second semiconductor layer 24 may also be formed by a p-type epitaxial layer.

[0022] The peak value of the n-type impurity concentration in the second semiconductor layer 24 can be set to 5 × 10⁻⁶. 14 cm -3 Above and 1×10 15 cm -3 Below. In one example, the peak concentration of the n-type impurity in the second semiconductor layer 24 is approximately 1 × 10⁻⁶. 15 cm -3 In one example, the n-type impurity concentration of the second semiconductor layer 24 gradually increases from the center of the first semiconductor layer 23 toward the center of the second semiconductor layer 24 in the Z direction. Furthermore, the n-type impurity concentration of the second semiconductor layer 24 gradually decreases from the center of the second semiconductor layer 24 toward the third semiconductor layer 25 in the Z direction.

[0023] The third semiconductor layer 25 is formed by an n-type epitaxial layer disposed on the upper surface of the second semiconductor layer 24. The third semiconductor layer 25 includes the first surface 20S of the semiconductor chip 20. The thickness of the third semiconductor layer 25 can be set to 5 μm or more and 20 μm or less. In one example, the thickness of the third semiconductor layer 25 is 8 μm or more and 15 μm or less. In another example, the thickness of the third semiconductor layer 25 is about 13 μm. Thus, the thickness of the third semiconductor layer 25 can be thicker than the thickness of the second semiconductor layer 24. The thickness of the third semiconductor layer 25 can also be thinner than the first semiconductor layer 23.

[0024] The n-type impurity concentration of the third semiconductor layer 25 can be set to 1×10. 13 cm -3 Above and 1×10 15 cm -3 Below. In one example, the n-type impurity concentration of the third semiconductor layer 25 is 5 × 10⁻⁶. 13 cm -3 Above and 5×10 14 cm -3 Below. In one example, the n-type impurity concentration of the third semiconductor layer 25 is 1 × 10⁻⁶. 14 cm -3 Above and less than 1×10 15 cm -3 The n-type impurity concentration in the third semiconductor layer 25 gradually decreases in the Z direction as it moves away from the second semiconductor layer 24. That is, the third semiconductor layer 25 reaches its peak n-type impurity concentration in the region where it is in contact with the second semiconductor layer 24 in the Z direction. The n-type impurity concentration becomes minimum in the region of the third semiconductor layer 25 biased towards the first surface 20S. In one example, the minimum n-type impurity concentration in the third semiconductor layer 25 is 1 × 10⁻⁶. 14 cm -3 Thus, the minimum n-type impurity concentration of the third semiconductor layer 25 is less than the minimum n-type impurity concentration of the second semiconductor layer 24. In one example, the n-type impurity concentration of the third semiconductor layer 25 is less than the n-type impurity concentration of the second semiconductor layer 24.

[0025] The second semiconductor layer 24 and the third semiconductor layer 25 are constructed as high-resistivity n-type layers with relatively low n-type impurity concentrations. The second semiconductor layer 24 and the third semiconductor layer 25 can have a resistivity of 50 Ω·cm or more and 150 Ω·cm or less. In one example, the second semiconductor layer 24 and the third semiconductor layer 25 can have a resistivity of 80 Ω·cm or more and 120 Ω·cm or less.

[0026] (pin knot) like Figure 2 and Figure 3As shown, the semiconductor chip 20 includes a first pin (p-intrinsic-n) junction 30, a second pin junction 40, and a third pin junction 50. The first pin junction 30, the second pin junction 40, and the third pin junction 50 are respectively disposed on the surface layer of the semiconductor chip 20 (including the region of the first surface 20S of the semiconductor chip 20 and offset from the first surface 20S in the Z direction). The first pin junction 30, the second pin junction 40, and the third pin junction 50 are regions in the semiconductor chip 20 that constitute pin diodes with a first polarity direction. Here, the first polarity direction refers to the direction in which forward current flows from the second surface 20R of the semiconductor chip 20 towards the first surface 20S.

[0027] like Figure 2 As shown, the first pin junction 30 includes a high-concentration region 31 on the first terminal side, a low-concentration region 32 on the first terminal side, a contact region 33 on the first terminal side, and a first defined region 34. The first terminal-side high-concentration region 31 is a p-type region disposed in the Z direction covering the first semiconductor layer 23, the second semiconductor layer 24, and the third semiconductor layer 25. The first terminal-side high-concentration region 31 is disposed in a portion of the first semiconductor layer 23 in the Z direction, the entire second semiconductor layer 24 in the Z direction, and a portion of the third semiconductor layer 25 in the Z direction. Therefore, the first terminal-side high-concentration region 31 is separated from the first surface 20S of the semiconductor chip 20 by being biased towards the second surface 20R. The first terminal-side high-concentration region 31 is separated from the semiconductor substrate 21 in the Z direction. The first terminal-side high-concentration region 31 can be defined in the Z direction as a first region 31A, a second region 31B, and a third region 31C. Here, p-type is an example of a "second conductivity type".

[0028] A first region 31A is disposed on the surface portion of the first semiconductor layer 23 (a region in the first semiconductor layer 23 including the upper surface and biased towards the second semiconductor layer 24). The first region 31A is configured to suppress the decrease in the p-type impurity concentration of the first semiconductor layer 23. That is, the first region 31A is configured to maintain a predetermined p-type impurity concentration. The p-type impurity concentration of the first region 31A can be set to 1 × 10⁻⁶. 17 cm -3 Above and 1×10 19 cm -3 Below. In one example, the p-type impurity concentration in the first region 31A is 1 × 10⁻⁶. 18 cm -3 .

[0029] The second region 31B is integrally disposed on the first region 31A along the Z-direction of the second semiconductor layer 24. In one example, the second region 31B includes a region configured such that the p-type impurity concentration gradually decreases in the Z-direction as it moves away from the first region 31A. Therefore, the p-type impurity concentration of the second region 31B is below the minimum value of the p-type impurity concentration of the first region 31A.

[0030] The third region 31C is disposed on the second region 31B in the third semiconductor layer 25, biased towards the second semiconductor layer 24. In one example, the p-type impurity concentration of the third region 31C gradually decreases in the Z direction as it moves away from the second region 31B. Therefore, the p-type impurity concentration of the third region 31C is lower than the p-type impurity concentration of the second region 31B.

[0031] The first terminal-side low-concentration region 32 is disposed in a region that is offset from the first terminal-side high-concentration region 31 towards the first surface 20S, at a position overlapping with the first terminal-side high-concentration region 31 when viewed from above. In one example, the first terminal-side low-concentration region 32 is disposed on the third region 31C. The first terminal-side low-concentration region 32 is an n-type region formed by the third semiconductor layer 25. The first terminal-side low-concentration region 32 is exposed from the first surface 20S of the semiconductor chip 20. Therefore, the n-type impurity concentration of the first terminal-side low-concentration region 32 is equal to the n-type impurity concentration of the third semiconductor layer 25. Therefore, the n-type impurity concentration of the first terminal-side low-concentration region 32 can be set to 1×10⁻⁶. 14 cm -3 Above and 1×10 15 cm -3 the following.

[0032] The first terminal-side contact region 33 is an n-shaped region disposed on the surface layer of the first terminal-side low-concentration region 32. The first terminal-side contact region 33 is exposed from the first surface 20S of the semiconductor chip 20. The first terminal-side contact region 33 is separated from the first terminal-side high-concentration region 31 in the Z direction.

[0033] The concentration of n-type impurities in the first terminal-side contact region 33 is higher than that in the low-concentration region 32 on the first terminal side. The peak value of the n-type impurity concentration in the first terminal-side contact region 33 can be set to 1×10⁻⁶. 18 cm -3 Above and 1×10 21 cm -3 Below. In one example, the peak concentration of n-type impurities in the first terminal-side contact region 33 is 5 × 10⁻⁶. 18 cm -3 Above and 1×10 20 cm -3 the following.

[0034] Thus, in the first pin junction 30, the p-type high-concentration region 31 on the first terminal side constitutes the P layer of the pin diode, the n-type low-concentration region 32 on the first terminal side constitutes the I layer of the pin diode, and the n-type first terminal side contact region 33 constitutes the N layer of the pin diode. That is, the first terminal side high-concentration region 31, the first terminal side low-concentration region 32, and the first terminal side contact region 33 form a pin junction in the Z direction. Therefore, in the first pin junction 30, a pin diode (diode 201) with a first polarity direction is formed by the first terminal side high-concentration region 31, the first terminal side low-concentration region 32, and the first terminal side contact region 33.

[0035] The first defined region 34 is a p-type region that, when viewed from above, surrounds the low-concentration region 32 on the first terminal side. The first defined region 34 delineates the low-concentration region 32 on the first terminal side from the third semiconductor layer 25 outside the first pin junction 30. The first defined region 34 is located in a region offset from the first surface 20S compared to the high-concentration region 31 on the first terminal side, and overlaps with the high-concentration region 31 on the first terminal side when viewed from above. The first defined region 34 is separated from the first terminal side contact region 33 when viewed from above. The first defined region 34, when viewed from above, surrounds the first terminal side contact region 33.

[0036] The p-type impurity concentration in the first defined region 34 can be higher than the p-type impurity concentration in the third region 31C of the high-concentration region 31 on the first terminal side. In one example, the p-type impurity concentration in the first defined region 34 can be set to 1 × 10⁻⁶. 17 cm -3 Above and 1×10 18 cm -3 Furthermore, the p-type impurity concentration of the first delineated region 34 can be arbitrarily varied within a range that allows the low-concentration region 32 on the first terminal side to be delineated from the third semiconductor layer 25.

[0037] In the first pin junction 30, a pin diode is formed by a first defined region 34, a first terminal-side low-concentration region 32, and a first terminal-side contact region 33. Thus, the first pin junction 30 has a first current path in which forward current flows in the order of the first terminal-side high-concentration region 31, the first terminal-side low-concentration region 32, and the first terminal-side contact region 33, and a second current path in which forward current flows in the order of the first defined region 34, the first terminal-side low-concentration region 32, and the first terminal-side contact region 33.

[0038] like Figure 3As shown, the second pin junction 40 includes a p-type second terminal-side high-concentration region 41, an n-type second terminal-side low-concentration region 42, an n-type second terminal-side contact region 43, and a p-type second delineated region 44. The second terminal-side high-concentration region 41 is separated from the first surface 20S of the semiconductor chip 20 by being biased towards the second surface 20R. The second terminal-side high-concentration region 41 is separated from the first terminal-side high-concentration region 31 when viewed from above. The second terminal-side low-concentration region 42 is located in a region biased towards the first surface 20S than the second terminal-side high-concentration region 41, and overlaps with the second terminal-side high-concentration region 41 when viewed from above. The second terminal-side contact region 43 is located on the surface of the second terminal-side low-concentration region 42. The second delineated region 44 is located in a region biased towards the first surface 20S than the second terminal-side high-concentration region 41, and overlaps with the second terminal-side high-concentration region 41 when viewed from above. The second delineated region 44 is arranged to surround the second terminal-side low-concentration region 42 when viewed from above. In the second pin junction 40, a pin diode (diode 202) is formed by a high-concentration region 41 on the second terminal side, a low-concentration region 42 on the second terminal side, and a contact region 43 on the second terminal side. Additionally, in the second pin junction 40, a pin diode is formed by a second defined region 44, a low-concentration region 42 on the second terminal side, and a contact region 43 on the second terminal side.

[0039] Here, the structures of the second terminal side high concentration region 41, the second terminal side low concentration region 42, the second terminal side contact region 43, and the second demarcation region 44 are the same as those of the first terminal side high concentration region 31, the first terminal side low concentration region 32, the first terminal side contact region 33, and the first demarcation region 34 of the first pin junction 30, so detailed descriptions of them are omitted.

[0040] like Figure 2As shown, the third pin junction 50 includes a p-type third terminal-side high-concentration region 51, an n-type third terminal-side low-concentration region 52, an n-type third terminal-side contact region 53, and a p-type third delineation region 54. The third terminal-side high-concentration region 51 is separated from the first surface 20S of the semiconductor chip 20 by being biased towards the second surface 20R. The third terminal-side high-concentration region 51 is separated from both the first terminal-side high-concentration region 31 and the second terminal-side high-concentration region 41 when viewed from above. The third terminal-side low-concentration region 52 is located in a region biased towards the first surface 20S than the third terminal-side high-concentration region 51, and overlaps with the third terminal-side high-concentration region 51 when viewed from above. The third terminal-side contact region 53 is located on the surface of the third terminal-side low-concentration region 52. The third delineation region 54 is located in a region biased towards the first surface 20S than the third terminal-side high-concentration region 51, and overlaps with the third terminal-side high-concentration region 51 when viewed from above. The third defined region 54, when viewed from above, is arranged to surround the low-concentration region 52 on the third terminal side. In the third pin junction 50, a pin diode (diode 203) is formed by the high-concentration region 51 on the third terminal side, the low-concentration region 52 on the third terminal side, and the contact region 53 on the third terminal side. Furthermore, in the third pin junction 50, a pin diode is formed by the third defined region 54, the low-concentration region 52 on the third terminal side, and the contact region 53 on the third terminal side.

[0041] Here, the high-concentration region 51, low-concentration region 52, contact region 53, and demarcation region 54 on the third terminal side are the same as the contact region 33 and the demarcation region 34 on the first terminal side, so detailed descriptions of them are omitted.

[0042] (Diode pair area) like Figure 2 and Figure 3 As shown, the semiconductor chip 20 includes diode pair regions 60 that are separated from the first pin junction 30, the second pin junction 40, and the third pin junction 50 when viewed from above. The diode pair regions 60 are disposed on the surface layer of the semiconductor chip 20.

[0043] The diode pair region 60 includes a first reverse pin junction 60A, a second reverse pin junction 60B, a third reverse pin junction 60C, and a pn junction 60E. The first reverse pin junction 60A, the second reverse pin junction 60B, and the third reverse pin junction 60C are regions in the semiconductor chip 20 that constitute a pin diode with a second polarity direction. Here, the second polarity direction refers to the direction in which forward current flows from the first surface 20S of the semiconductor chip 20 towards the second surface 20R. That is, the second polarity direction is the opposite of the first polarity direction.

[0044] The diode pair region 60 includes a high-concentration region 61, a first low-concentration region 62A, a second low-concentration region 62B, a third low-concentration region 62C, a first contact region 63A, a second contact region 63B, a third contact region 63C, an internal region 64, and a separation region 65. The high-concentration region 61, the first low-concentration region 62A, the second low-concentration region 62B, the third low-concentration region 62C, the first contact region 63A, the second contact region 63B, the third contact region 63C, the internal region 64, and the separation region 65 form a first reverse pin junction 60A, a second reverse pin junction 60B, a third reverse pin junction 60C, and a pn junction 60E.

[0045] The high-concentration region 61 is an n-shaped region located at a position separated from the first surface 20S of the semiconductor chip 20 by the second surface 20R. The high-concentration region 61 is separated from the first semiconductor layer 23 by the first semiconductor layer 23 by the first surface 20S in the Z direction. The high-concentration region 61 is distributed throughout the second semiconductor layer 24 and the third semiconductor layer 25 in the Z direction. The high-concentration region 61 is located in a portion of the third semiconductor layer 25 in the Z direction.

[0046] The n-type impurity concentration in high-concentration region 61 is higher than that in the second semiconductor layer 24. The n-type impurity concentration in high-concentration region 61 is also higher than that in the third semiconductor layer 25. The peak value of the n-type impurity concentration in high-concentration region 61 can be set to 1 × 10⁻⁶. 18 cm -3 Above and 1×10 21 cm -3 Below. In one example, the peak concentration of n-type impurities in the high-concentration region 61 is 5 × 10⁻⁶. 18 cm -3 Above and 1×10 20 cm -3 the following.

[0047] The first to third low-concentration regions 62A to 62C are n-type regions located in a region closer to the first surface 20S than the high-concentration region 61. The first to third low-concentration regions 62A to 62C are separated from each other when viewed from above. The first to third low-concentration regions 62A to 62C are respectively located at positions overlapping with the high-concentration region 61 when viewed from above. The first to third low-concentration regions 62A to 62C are exposed from the first surface 20S of the semiconductor chip 20. The first to third low-concentration regions 62A to 62C are constituted by the third semiconductor layer 25. Therefore, the n-type impurity concentration of each of the first to third low-concentration regions 62A to 62C can be equal to the n-type impurity concentration of the third semiconductor layer 25. Therefore, the n-type impurity concentration of each of the first to third low-concentration regions 62A to 62C can be set to 1 × 10⁻⁶.14 cm -3 Above and 1×10 15 cm -3 Below. In one example, the n-type impurity concentration in each of the first to third low-concentration regions 62A to 62C is 1 × 10⁻⁶. 14 cm -3 .

[0048] The first contact region 63A is a p-type region disposed on the surface portion of the first low-concentration region 62A. The first contact region 63A is exposed from the first surface 20S of the semiconductor chip 20. The first contact region 63A is separated from the high-concentration region 61 in the Z direction. The p-type impurity concentration of the first contact region 63A is higher than the n-type impurity concentration of the first low-concentration region 62A.

[0049] The second contact region 63B is a p-type region disposed on the surface portion of the second low-concentration region 62B. The second contact region 63B is exposed from the first surface 20S of the semiconductor chip 20. The second contact region 63B is separated from the high-concentration region 61 in the Z direction. The p-type impurity concentration of the second contact region 63B is higher than the n-type impurity concentration of the second low-concentration region 62B. The p-type impurity concentration of the second contact region 63B is equal to the p-type impurity concentration of the first contact region 63A.

[0050] The third contact region 63C is a p-type region disposed on the surface layer of the third low-concentration region 62C. The third contact region 63C is exposed from the first surface 20S of the semiconductor chip 20. The third contact region 63C is separated from the high-concentration region 61 in the Z direction. The p-type impurity concentration of the third contact region 63C is higher than the n-type impurity concentration of the third low-concentration region 62C. The p-type impurity concentration of the third contact region 63C is equal to the p-type impurity concentration of the first contact region 63A.

[0051] The peak value of the p-type impurity concentration in each of the first to third contact regions 63A to 63C can be set to 1×10⁻⁶. 18 cm -3 Above and 1×10 21 cm -3 Below. In one example, the peak concentration of p-type impurities in the first to third contact regions 63A to 63C is 5 × 10⁻⁶. 18 cm -3 Above and 1×10 20 cm -3 the following.

[0052] Thus, in the first reverse pin junction 60A, the first contact region 63A of the p-type type constitutes the P layer of the pin diode, the first low-concentration region 62A of the n-type type constitutes the I layer of the pin diode, and the high-concentration region 61 of the n-type type constitutes the N layer of the pin diode. That is, the first contact region 63A, the first low-concentration region 62A, and the high-concentration region 61 form a pin junction in the Z direction. Therefore, in the first reverse pin junction 60A, the high-concentration region 61, the first low-concentration region 62A, and the first contact region 63A form a pin diode (diode 204) with a second polarity direction.

[0053] In the second reverse pin junction 60B, the p-type second contact region 63B constitutes the P-layer of the pin diode, the n-type second low-concentration region 62B constitutes the I-layer of the pin diode, and the n-type high-concentration region 61 constitutes the N-layer of the pin diode. That is, the second contact region 63B, the second low-concentration region 62B, and the high-concentration region 61 form a pin junction in the Z-direction. Therefore, in the second reverse pin junction 60B, a pin diode (diode 205) with a second polarity direction is formed by the high-concentration region 61, the second low-concentration region 62B, and the second contact region 63B.

[0054] In the third reverse pin junction 60C, the p-type third contact region 63C constitutes the P-layer of the pin diode, the n-type third low-concentration region 62C constitutes the I-layer of the pin diode, and the n-type high-concentration region 61 constitutes the N-layer of the pin diode. That is, the third contact region 63C, the third low-concentration region 62C, and the high-concentration region 61 form a pin junction in the Z-direction. Therefore, in the third reverse pin junction 60C, the high-concentration region 61, the third low-concentration region 62C, and the third contact region 63C form a pin diode (diode 206) with a second polarity direction.

[0055] The inner region 64 is a p-type region disposed at a location relative to the high-concentration region 61, biased towards the second surface 20R of the semiconductor chip 20, and grounded to the high-concentration region 61. The inner region 64 is positioned to overlap with the high-concentration region 61 when viewed from above. The inner region 64 is disposed in the Z direction covering the surface portion of the first semiconductor layer 23 and the region of the second semiconductor layer 24 biased towards the first semiconductor layer 23. The inner region 64 is configured to overlap with the first low-concentration region 62A, the second low-concentration region 62B, and the third low-concentration region 62C, respectively, when viewed from above.

[0056] The internal region 64 is configured to suppress the decrease in the p-type impurity concentration of the first semiconductor layer 23. That is, the internal region 64 is configured to maintain a predetermined p-type impurity concentration. The p-type impurity concentration of the internal region 64 can be set to 1 × 10⁻⁶. 16 cm -3Above and 1×10 19 cm -3 Below. In one example, the concentration of p-type impurities in internal region 64 is 1 × 10⁻⁶. 18 cm -3 Thus, the p-type impurity concentration in the internal region 64 can be equal to the p-type impurity concentration in the first region 31A of the high-concentration region 31 on the first terminal side of the first pin junction 30.

[0057] In the pn junction 60E, it is constructed by a p-type internal region 64 and an n-type high-concentration region 61. That is, the internal region 64 and the high-concentration region 61 form a pn junction in the Z direction. Therefore, a pn diode (diode 207) with a first polarity direction is constructed by the internal region 64 and the high-concentration region 61. The pn diode is reverse-connected to the pin diodes of the first reverse pin junction 60A, the second reverse pin junction 60B, and the third reverse pin junction 60C. Therefore, it can be said that the pn junction 60E is reverse-connected relative to the first reverse pin junction 60A, the second reverse pin junction 60B, and the third reverse pin junction 60C. Here, the breakdown voltage of the pn junction 60E can be set by utilizing the p-type impurity concentration of the internal region 64. That is, the p-type impurity concentration of the internal region 64 is adjusted according to the desired breakdown voltage of the pn junction 60E.

[0058] The separation region 65 is an n-shaped region located in the region offset from the high-concentration region 61 towards the first surface 20S. The separation region 65 is positioned to overlap with the high-concentration region 61 when viewed from above. The separation region 65 is used to separate the first low-concentration region 62A, the second low-concentration region 62B, and the third low-concentration region 62C. Therefore, when viewed from above, the separation region 65 is positioned to surround each of the first low-concentration region 62A, the second low-concentration region 62B, and the third low-concentration region 62C.

[0059] The peak value of the n-type impurity concentration in separation region 65 can be equal to the peak value of the n-type impurity concentration in high-concentration region 61. In one example, the peak value of the n-type impurity concentration in separation region 65 can be set to 1 × 10⁻⁶. 18 cm -3 Above and 1×10 21 cm -3 Below. In one example, the peak concentration of n-type impurities in separation region 65 was 5 × 10⁻⁶. 18 cm -3 Above and 1×10 20 cm -3 the following.

[0060] In the first reverse pin junction 60A, a pin diode is formed by the first contact region 63A, the first low-concentration region 62A, and the portion of the separation region 65 surrounding the first low-concentration region 62A. Thus, in the first reverse pin junction 60A, a first current path is provided where forward current flows in the order of the first contact region 63A, the first low-concentration region 62A, and the high-concentration region 61, and a second current path where forward current flows in the order of the first contact region 63A, the first low-concentration region 62A, and the separation region 65.

[0061] In the second reverse pin junction 60B, a pin diode is formed by the second contact region 63B, the second low-concentration region 62B, and the portion of the separation region 65 surrounding the second low-concentration region 62B. Thus, in the second reverse pin junction 60B, a first current path is provided where forward current flows in the order of the second contact region 63B, the second low-concentration region 62B, and the high-concentration region 61, and a second current path where forward current flows in the order of the second contact region 63B, the second low-concentration region 62B, and the separation region 65.

[0062] In the third reverse pin junction 60C, a pin diode is formed by the third contact region 63C, the third low-concentration region 62C, and the portion of the separation region 65 surrounding the third low-concentration region 62C. Thus, in the third reverse pin junction 60C, a first current path is provided where forward current flows in the order of the third contact region 63C, the third low-concentration region 62C, and the high-concentration region 61, and a second current path where forward current flows in the order of the third contact region 63C, the third low-concentration region 62C, and the separation region 65.

[0063] The cathodes of the pin diodes in the first reverse pin junction 60A, the second reverse pin junction 60B, and the third reverse pin junction 60C are electrically connected to the cathode of the pn diode in the pn junction 60E. Therefore, the first to third reverse pin junctions 60A to 60C respectively form diode pairs with the pn junction 60E.

[0064] (Structure on a semiconductor chip) The TVS diode 10 includes an insulating layer 70 covering the first surface 20S of the semiconductor chip 20. The insulating layer 70 can have a stacked structure formed by stacking multiple insulating layers, or it can have a monolayer structure composed of a single insulating layer. The insulating layer 70 may include at least one of a SiO2 (silicon oxide) layer and a SiN (silicon nitride) layer. The insulating layer 70 can have a stacked structure formed by stacking the SiO2 layer and the SiN layer in any order. The insulating layer 70 can also have a monolayer structure composed of either a SiO2 layer or a SiN layer. The thickness of the insulating layer 70 can be set to 1 μm or more and 10 μm or less. In one example, the thickness of the insulating layer 70 is 2 μm or more and 3 μm or less.

[0065] In one example, the insulating layer 70 includes a stacked structure of a first insulating layer 71 and a second insulating layer 72. The first insulating layer 71 is in contact with the first surface 20S of the semiconductor chip 20. The first insulating layer 71 is a monolayer structure composed of a single SiO2 layer. The first insulating layer 71 is also referred to as a field oxide film. The thickness of the first insulating layer 71 can be set, for example, to 14000 Å.

[0066] A second insulating layer 72 is disposed on the first insulating layer 71. The second insulating layer 72 may include at least one of a USG (Undoped Silica Glass) layer, a PSG (Phosphor Silicate Glass) layer, and a BPSG (Boron Phosphor Silicate Glass) layer. In one example, the second insulating layer 72 is constructed by a stack of a USG layer and a BPSG layer. The thickness of the second insulating layer 72 is, for example, thinner than the thickness of the first insulating layer 71. The thickness of the second insulating layer 72 can be, for example, 6700 Å.

[0067] The insulating layer 70 includes first to sixth openings 73A to 73F and wiring openings 73G that expose the first surface 20S of the semiconductor chip 20. The first to sixth openings 73A to 73F and wiring openings 73G each penetrate the insulating layer 70 in the Z direction.

[0068] The first opening 73A exposes the first terminal-side contact area 33 of the first pin junction 30. The second opening 73B exposes the second terminal-side contact area 43 of the second pin junction 40. The third opening 73C exposes the third terminal-side contact area 53 of the third pin junction 50. The fourth opening 73D exposes the first contact area 63A of the first reverse pin junction 60A. The fifth opening 73E exposes the second contact area 63B of the second reverse pin junction 60B. The sixth opening 73F exposes the third contact area 63C of the third reverse pin junction 60C.

[0069] The wiring opening 73G exposes the separation region 65 of the diode pair region 60. Therefore, the separation region 65 includes an exposed surface 65S that is exposed from the first surface 20S of the semiconductor chip 20. The TVS diode 10 includes a first connection electrode 81, a second connection electrode 82, and a third connection electrode 83 disposed on an insulating layer 70. The first to third connection electrodes 81 to 83 are each made of a material comprising at least one of, for example, Cu (copper) and Al (aluminum). In one example, the first to third connection electrodes 81 to 83 are each made of AlCu. The thickness of each of the first to third connection electrodes 81 to 83 can be, for example, set to 42,000 Å.

[0070] The first connecting electrode 81 electrically connects the first terminal-side contact area 33 of the first pin junction 30 to the first contact area 63A of the first reverse pin junction 60A. The first connecting electrode 81 is connected to the first terminal-side contact area 33 through the first opening 73A of the insulating layer 70. The first connecting electrode 81 is connected to the first contact area 63A through the fourth opening 73D of the insulating layer 70.

[0071] The second connecting electrode 82 electrically connects the second terminal-side contact region 43 of the second pin junction 40 to the second contact region 63B of the second reverse pin junction 60B. The second connecting electrode 82 is connected to the second terminal-side contact region 43 through the second opening 73B of the insulating layer 70. The second connecting electrode 82 is connected to the second contact region 63B through the fifth opening 73E of the insulating layer 70.

[0072] The third connecting electrode 83 electrically connects the third terminal-side contact region 53 of the third pin junction 50 to the third contact region 63C of the third reverse pin junction 60C. The third connecting electrode 83 is connected to the third terminal-side contact region 53 through the third opening 73C of the insulating layer 70. The third connecting electrode 83 is connected to the third contact region 63C through the sixth opening 73F of the insulating layer 70.

[0073] The TVS diode 10 includes wiring 90 connected to the exposed surface 65S of the separation region 65 of the diode pair region 60. Wiring 90 is made of a material comprising at least one of Cu and Al. In one example, wiring 90 is made of AlCu. That is, wiring 90 can be made of the same material as the first to third connecting electrodes 81 to 83. Furthermore, the detailed structure of wiring 90 will be described later.

[0074] The TVS diode 10 includes a protective layer 74 covering the insulating layer 70, the first to third connecting electrodes 81 to 83, and the wiring 90. The protective layer 74 is an insulating layer used to protect the semiconductor chip 20. The protective layer 74 can have a stacked structure formed by stacking multiple insulating layers, or it can have a single-layer structure composed of a single insulating layer.

[0075] In one example, the protective layer 74 has a laminated structure of a first protective layer 75 and a second protective layer 76. In one example, the first protective layer 75 may be a passivation layer, and the second protective layer 76 may be a resin layer.

[0076] The first protective layer 75 may have a single-layer structure including a SiO2 layer or a SiN layer, or it may have a stacked structure consisting of SiO2 layers and SiN layers stacked in any order. In one example, the first protective layer 75 is a single-layer structure composed of SiN layers.

[0077] The second protective layer 76 may comprise a photosensitive resin. The second protective layer 76 may comprise at least one of PI (polyimide), PA (polyamide), and PBO (polybenzoxazole) as an example of a photosensitive resin. In one example, the second protective layer 76 comprises PI.

[0078] The protective layer 74 includes first to third terminal openings 77A to 77C. The first to third terminal openings 77A to 77C penetrate the protective layer 74 in the Z direction. The first terminal opening 77A partially exposes the first connecting electrode 81. The first terminal opening 77A is positioned to overlap with the first opening 73A of the insulating layer 70 when viewed from above. The second terminal opening 77B partially exposes the second connecting electrode 82. The second terminal opening 77B is positioned to overlap with the second opening 73B of the insulating layer 70 when viewed from above. The third terminal opening 77C partially exposes the third connecting electrode 83. The third terminal opening 77C is positioned to overlap with the third opening 73C of the insulating layer 70 when viewed from above.

[0079] (Top view of a TVS diode) Reference Figure 1 and Figures 4-7 The top view of the TVS diode 10 is described. Figure 4 The diagram schematically shows the top view of the first surface 20S of the semiconductor chip 20. Figure 5 Schematic illustration of the use Figure 3 The cross-sectional structure obtained by cutting the semiconductor chip 20 with the F5-F5 line. Figure 6 schematically showing that Figure 5 The high-concentration region 61 and the internal region 64 are magnified cross-sectional structures. Additionally, in... Figure 5 and Figure 6In the accompanying diagram, the shading lines have been omitted for ease of understanding. Figure 7 The diagram schematically shows the top view of the first to third connecting electrodes 81 to 83 and wiring 90 of the TVS diode 10.

[0080] (Semiconductor chip) like Figure 4 As shown, the TVS diode 10 includes a peripheral region 110 disposed on the outer periphery of the first surface 20S of the semiconductor chip 20. The peripheral region 110 is a region containing p-type impurities. When viewed from above, the peripheral region 110 is arranged to surround the first pin junction 30, the second pin junction 40, the third pin junction 50, and the diode pair region 60.

[0081] The peripheral region 110 and the high-concentration region 31 on the first terminal side of the first pin junction 30 (refer to) Figure 2 ) and the first defined region 34, the second terminal side high concentration region 41 of the second pin junction 40 (refer to Figure 3 ) and the second defined region 44, and the high-concentration region 51 on the third terminal side of the third pin junction 50 (refer to Figure 2 The outer peripheral region 110 is integrated with the third delineated region 54. The concentration gradient of the p-type impurity concentration in the outer peripheral region 110 is the same as, for example, the high concentration region 31 on the first terminal side and the first delineated region 34.

[0082] The peripheral region 110 includes a first region 111 extending along a first side 20A when viewed from above, a second region 112 extending along a second side 20B, a third region 113 extending along a third side 20C, and a fourth region 114 extending along a fourth side 20D.

[0083] The first pin junction 30, the second pin junction 40, and the third pin junction 50 are configured separately from each other. More specifically, the first pin junction 30 and the third pin junction 50 are located at the same position in the Y direction and are configured separately from each other in the X direction. The first pin junction 30 and the third pin junction 50 are disposed at the end of the first surface 20S of the semiconductor chip 20 in the Y direction, biased towards the fourth side surface 20D. The first pin junction 30 is disposed at the end of the first surface 20S in the X direction, biased towards the first side surface 20A. The third pin junction 50 is disposed at the end of the first surface 20S in the X direction, biased towards the second side surface 20B.

[0084] The second pin junction 40 is positioned at different locations in the X and Y directions relative to the first pin junction 30 and the third pin junction 50. The second pin junction 40 is located at the end of the first surface 20S of the semiconductor chip 20 in the Y direction, biased towards the third surface 20C. The second pin junction 40 is located at the center of the first surface 20S in the X direction. Therefore, it can be said that the second pin junction 40, when viewed from the Y direction, is positioned between the first pin junction 30 and the third pin junction 50 in the X direction.

[0085] The first defined region 34 of the first pin junction 30 is connected to the first region 111 and the fourth region 114 of the outer peripheral region 110. Therefore, the low-concentration region 32 on the first terminal side of the first pin junction 30 is defined by the first region 111, the fourth region 114, and the first defined region 34 when viewed from above. The first defined region 34 includes a first portion connected to the first region 111 and extending along the X direction, a second portion connected to the fourth region 114 and extending along the Y direction, and a connecting portion connecting the first portion and the second portion. The connecting portion is curved when viewed from above.

[0086] The low-concentration region 32 on the first terminal side is square in shape when viewed from above. The four corners of the square-shaped low-concentration region 32 are curved. The contact region 33 on the first terminal side is also square in shape when viewed from above. The four corners of the square-shaped contact region 33 are curved. The contact region 33 on the first terminal side is smaller than the low-concentration region 32 when viewed from above.

[0087] The second defined region 44 of the second pin junction 40 is connected to the third region 113 of the outer peripheral region 110. The second defined region 44, when viewed from above, is U-shaped, opening towards the third region 113. The second terminal-side low-concentration region 42 of the second pin junction 40, when viewed from above, is defined by the third region 113 and the second defined region 44. The second defined region 44 includes a first portion and a second portion connected to the third region 113 and extending along the Y direction, and a third portion separated from the third region 113 by a fourth side 20D and extending along the X direction. The first portion and the second portion are separated from each other in the X direction. The second defined region 44 includes a first connecting portion connecting the first portion and the third portion, and a second connecting portion connecting the second portion and the third portion. Each connecting portion is curved when viewed from above.

[0088] The second terminal-side low-concentration region 42 is square-shaped when viewed from above. The four corners of the square-shaped second terminal-side low-concentration region 42 are curved. The second terminal-side low-concentration region 42 may, for example, be the same size and shape as the first terminal-side low-concentration region 32. The second terminal-side contact region 43 is also square-shaped when viewed from above. The four corners of the square-shaped second terminal-side contact region 43 are curved. The second terminal-side contact region 43 is smaller than the second terminal-side low-concentration region 42 when viewed from above. The second terminal-side contact region 43 may, for example, be the same size and shape as the first terminal-side contact region 33.

[0089] The third defined region 54 of the third pin junction 50 is connected to the second region 112 and the fourth region 114 of the outer peripheral region 110. Therefore, the low-concentration region 52 on the third terminal side of the third pin junction 50 is defined by the second region 112, the fourth region 114, and the third defined region 54 when viewed from above. The third defined region 54 includes a first portion connected to the second region 112 and extending along the X direction, a second portion connected to the fourth region 114 and extending along the Y direction, and a connecting portion connecting the first portion and the second portion. The connecting portion appears curved when viewed from above.

[0090] The third terminal-side low-concentration region 52 is square-shaped when viewed from above. The four corners of the square-shaped third terminal-side low-concentration region 52 are curved. The third terminal-side low-concentration region 52 may, for example, be the same size and shape as the first terminal-side low-concentration region 32. The third terminal-side contact region 53 is also square-shaped when viewed from above. The four corners of the square-shaped third terminal-side contact region 53 are curved. The third terminal-side contact region 53 is smaller than the third terminal-side low-concentration region 52 when viewed from above. The third terminal-side contact region 53 may, for example, be the same size and shape as the first terminal-side contact region 33.

[0091] In one example, the shortest distance DA between the first defined region 34 and the second defined region 44 is equal to the shortest distance DB between the second defined region 44 and the third defined region 54. The shortest distance DC between the first defined region 34 and the third defined region 54 is less than or equal to the shortest distances DA and DB.

[0092] The diode pair region 60 is located in the area surrounded by the outer peripheral region 110, the first defined region 34, the second defined region 44, and the third defined region 54 when viewed from above. Therefore, diode pair regions 60 are respectively provided between the first pin junction 30 and the second pin junction 40, between the second pin junction 40 and the third pin junction 50, and between the first pin junction 30 and the third pin junction 50.

[0093] The diode pair region 60 includes a first region 66A, a second region 66B, and a third region 66C. The first region 66A is a region parallel to the first pin junction 30 in the Y direction. The first region 66A is positioned offset from the first pin junction 30 by a third side 20C. A first reverse pin junction 60A is provided in the first region 66A. Therefore, it can be said that the first pin junction 30 and the first reverse pin junction 60A are arranged along the Y direction when viewed from above. The first region 66A includes a region parallel to the second pin junction 40 in the X direction. The first region 66A is positioned offset from the second pin junction 40 by a first side 20A in the X direction. When viewed from the X direction, the first reverse pin junction 60A includes a portion overlapping with the second pin junction 40.

[0094] The first region 66A is roughly rectangular in shape when viewed from above. In one example, the first region 66A is formed as a roughly rectangular shape with the Y direction as its length direction and the X direction as its width direction. The first region 66A includes the first to fourth sides 66AA to 66AD. The first side 66AA is the side of the first region 66A that is adjacent to the first side 20A and extends along the Y direction when viewed from above. The second side 66AB is the side of the first region 66A that is adjacent to the second side 20B and extends along the Y direction when viewed from above. The length of the second side 66AB in the Y direction is shorter than the length of the first side 66AA in the Y direction. The third side 66AC is the side of the first region 66A that is adjacent to the third side 20C and extends along the X direction when viewed from above. The fourth side 66AD is the side of the first region 66A that is adjacent to the fourth side 20D and extends along the X direction when viewed from above. The length of the fourth side 66AD in the X direction is shorter than the length of the third side 66AC in the X direction.

[0095] The first region 66A includes the corner between the first side 66AA and the third side 66AC, the corner between the first side 66AA and the fourth side 66AD, and the corner between the second side 66AB and the third side 66AC. Each corner appears curved when viewed from above.

[0096] The second region 66B is a region parallel to the second pin junction 40 in the Y direction. The second region 66B is positioned offset from the second pin junction 40 by a fourth side 20D. A second reverse pin junction 60B is provided in the second region 66B. Therefore, it can be said that the second pin junction 40 and the second reverse pin junction 60B are arranged along the Y direction when viewed from above. The second region 66B includes a region positioned between the first pin junction 30 and the third pin junction 50 in the X direction. Therefore, the second region 66B includes a region offset from the first region 66A in the Y direction. The second region 66B is positioned offset from the first region 66A by a second side 20B in the X direction. When viewed from the X direction, the second reverse pin junction 60B includes portions overlapping with both the first pin junction 30 and the third pin junction 50.

[0097] The second region 66B is roughly rectangular in shape when viewed from above. In one example, the second region 66B is formed as a roughly rectangular shape with the Y direction as its length direction and the X direction as its width direction. The second region 66B includes the first to fourth sides 66BA to 66BD. The first side 66BA is the side of the second region 66B that is adjacent to the first side 20A and extends along the Y direction when viewed from above. The length of the first side 66BA in the Y direction is, for example, equal to the length of the second side 66AB of the first region 66A in the Y direction. The second side 66BB is the side of the second region 66B that is adjacent to the second side 20B and extends along the Y direction when viewed from above. The length of the second side 66BB in the Y direction is equal to the length of the first side 66BA in the Y direction. The third side 66BC is the side of the second region 66B that is adjacent to the third side 20C and extends along the X direction when viewed from above. The fourth side 66BD is the side of the second region 66B that is adjacent to the fourth side 20D and extends along the X direction when viewed from above. The first side 66BA, the second side 66BB, and the fourth side 66BD are respectively positioned 20D away from the fourth side of the first region 66A in the Y direction. The length of the fourth side 66BD in the X direction is longer than the length of the third side 66BC in the X direction. The length of the third side 66BC in the X direction is shorter than the length of the third side 66AC of the first region 66A in the X direction.

[0098] The second region 66B includes the corner between the first side 66BA and the fourth side 66BD, as well as the corner between the second side 66BB and the fourth side 66BD. Each corner appears curved when viewed from above.

[0099] The third region 66C is a region parallel to the third pin junction 50 in the Y direction. The third region 66C is positioned offset from the third pin junction 50 by a third side 20C. The third region 66C is located at the same position as the first region 66A in the Y direction. The third region 66C is separated from the first region 66A in the X direction. A third reverse pin junction 60C is provided in the third region 66C. Therefore, it can be said that the third pin junction 50 and the third reverse pin junction 60C are arranged along the Y direction when viewed from above. The third region 66C includes a region parallel to the second pin junction 40 in the X direction. The third region 66C is positioned offset from the second pin junction 40 by a second side 20B in the X direction. Therefore, it can be said that the second pin junction 40 is positioned between the first region 66A and the third region 66C in the X direction. When viewed from the X direction, the third reverse pin junction 60C includes a portion overlapping with the second pin junction 40.

[0100] The third region 66C is roughly rectangular in shape when viewed from above. In one example, the third region 66C is formed into a roughly rectangular shape with the Y direction as its length direction and the X direction as its width direction. The third region 66C includes the first to fourth sides 66CA to 66CD. The first side 66CA is the side of the third region 66C that is closer to the first side 20A, and extends along the Y direction when viewed from above. The length of the first side 66CA in the Y direction is, for example, equal to the length of the second side 66AB of the first region 66A in the Y direction. The second side 66CB is the side of the third region 66C that is closer to the second side 20B, and extends along the Y direction when viewed from above. The length of the second side 66CB in the Y direction is longer than the length of the first side 66CA in the Y direction. The length of the second side 66CB in the Y direction is, for example, equal to the length of the first side 66AA of the first region 66A in the Y direction. The third side 66CC is the side of the third region 66C that is closer to the third side 20C, and extends along the X direction when viewed from above. The fourth side 66CD is the side of the third region 66C that is biased towards the fourth side 20D, and extends along the X direction when viewed from above. The length of the third side 66CC in the X direction is longer than the length of the fourth side 66CD in the X direction. The length of the third side 66CC in the X direction is, for example, equal to the length of the third side 66AC in the X direction of the first region 66A. The length of the fourth side 66CD in the X direction is, for example, equal to the length of the fourth side 66AD in the X direction of the first region 66A.

[0101] The third region 66C includes the corner between the first side 66CA and the third side 66CC, the corner between the second side 66CB and the fourth side 66CD, and the corner between the second side 66CB and the third side 66CC. Each corner appears curved when viewed from above.

[0102] exist Figure 4In the example shown, the width dimension (dimension in the X direction) WB of the second region 66B is larger than the width dimension (dimension in the X direction) WA of the first region 66A and the width dimension (dimension in the X direction) WC of the third region 66C. Furthermore, the width dimension WA of the first region 66A, the width dimension WB of the second region 66B, and the width dimension WC of the third region 66C can be arbitrarily changed. In one example, the width dimension WA of the first region 66A can be different from the width dimension WC of the third region 66C. In one example, the width dimension WB of the second region 66B can be equal to the width dimension WA of the first region 66A. In one example, the width dimension WB of the second region 66B can be equal to the width dimension WC of the third region 66C.

[0103] The diode pair region 60 includes a first connection region 67A connecting a first region 66A and a second region 66B, and a second connection region 67B connecting a second region 66B and a third region 66C. The first connection region 67A is disposed between the first region 66A and the second region 66B in the X direction, and the second connection region 67B is disposed between the second region 66B and the third region 66C in the X direction. In a top-view configuration, the first connection region 67A is positioned between a first pin junction 30 and a second pin junction 40 in a direction intersecting both the X and Y directions. In a top-view configuration, the second connection region 67B is positioned between a second pin junction 40 and a third pin junction 50 in a direction intersecting both the X and Y directions.

[0104] The first connecting region 67A connects the second side 66AB of the first region 66A to the third side 66BC of the second region 66B, and connects the fourth side 66AD of the first region 66A to the first side 66BA of the second region 66B. The two ends of the first connecting region 67A in the Y direction are curved when viewed from above. The radius of curvature of the two ends of the first connecting region 67A in the Y direction is larger than the radius of curvature of the corners of the first region 66A.

[0105] The second connecting region 67B connects the second side 66BB of the second region 66B to the fourth side 66CD of the third region 66C, and connects the third side 66BC of the second region 66B to the first side 66CA of the third region 66C. The two ends of the second connecting region 67B in the Y direction appear curved when viewed from above. The radius of curvature of the two ends of the second connecting region 67B in the Y direction is larger than the radius of curvature of the corners of the third region 66C.

[0106] The first low-concentration region 62A of the first reverse pin junction 60A, when viewed from above, is formed as an elongated circle with the Y direction as its length direction and the X direction as its width direction. In one example, the dimension (width dimension) of the first low-concentration region 62A in the X direction is smaller than the dimension in the X direction of the first terminal-side low-concentration region 32 of the first pin junction 30. In one example, the width dimension of the first low-concentration region 62A is smaller than the dimension in the X direction of the first terminal-side contact region 33 of the first pin junction 30. In one example, the dimension (length dimension) of the first low-concentration region 62A in the Y direction is larger than the dimension in the Y direction of the first terminal-side low-concentration region 32.

[0107] The first contact region 63A of the first reverse pin junction 60A, when viewed from above, is an elongated circle with the Y direction as its length and the X direction as its width. The first contact region 63A is smaller than the first low-concentration region 62A when viewed from above. The dimension (width) of the first contact region 63A in the X direction is smaller than the dimension (width) of the first terminal-side contact region 33 in the X direction. The dimension (length) of the first contact region 63A in the Y direction is larger than the dimension (length) of the first terminal-side low-concentration region 32 in the Y direction.

[0108] The second reverse pin junction 60B is disposed offset from the fourth side 20D relative to the first reverse pin junction 60A. Furthermore, the second reverse pin junction 60B includes a region that overlaps with the first reverse pin junction 60A when viewed from the X direction. More specifically, the second low-concentration region 62B and the second contact region 63B of the second reverse pin junction 60B both include regions that overlap with the first low-concentration region 62A and the first contact region 63A of the first reverse pin junction 60A.

[0109] The second low-concentration region 62B, when viewed from above, is an elongated circle with the Y-direction as its length and the X-direction as its width. In one example, the dimension (width) of the second low-concentration region 62B in the X-direction is smaller than the dimension (width) of the second terminal-side low-concentration region 42 of the second pin junction 40 in the X-direction. In one example, the width of the second low-concentration region 62B is smaller than the dimension (width) of the second terminal-side contact region 43 of the second pin junction 40 in the X-direction. In one example, the dimension (length) of the second low-concentration region 62B in the Y-direction is larger than the dimension (width) of the second terminal-side low-concentration region 42 in the Y-direction. In one example, the width and length dimensions of the second low-concentration region 62B are equal to the width and length dimensions of the first low-concentration region 62A.

[0110] The second contact area 63B, when viewed from above, is an elongated circle with the Y direction as its length and the X direction as its width. The second contact area 63B is smaller than the second low-concentration area 62B when viewed from above. The width dimension of the second contact area 63B in the X direction is smaller than the X-direction dimension of the second terminal-side contact area 43. The length dimension of the second contact area 63B in the Y direction is larger than the Y-direction dimension of the second terminal-side low-concentration area 42. In one example, the width and length dimensions of the second contact area 63B are equal to the width and length dimensions of the first contact area 63A.

[0111] The third reverse pin junction 60C is disposed offset from the third side 20C relative to the second reverse pin junction 60B. Furthermore, the third reverse pin junction 60C includes a region that overlaps with the second reverse pin junction 60B when viewed from the X direction. More specifically, the third low-concentration region 62C and the third contact region 63C of the third reverse pin junction 60C both include regions that overlap with the second low-concentration region 62B and the second contact region 63B. Additionally, the third reverse pin junction 60C is disposed at the same position as the first reverse pin junction 60A in the Y direction.

[0112] The third low-concentration region 62C, when viewed from above, is an elongated circle with the Y-direction as its length and the X-direction as its width. In one example, the dimension (width) of the third low-concentration region 62C in the X-direction is smaller than the dimension (width) of the third terminal-side low-concentration region 52 of the third pin junction 50 in the X-direction. In one example, the width of the third low-concentration region 62C is smaller than the dimension (width) of the third terminal-side contact region 53 of the third pin junction 50 in the X-direction. In one example, the dimension (length) of the third low-concentration region 62C in the Y-direction is larger than the dimension (width) of the third terminal-side low-concentration region 52 in the Y-direction. In one example, the width and length dimensions of the third low-concentration region 62C are equal to the width and length dimensions of the first low-concentration region 62A.

[0113] The third contact region 63C, when viewed from above, is an elongated circle with the Y direction as its length and the X direction as its width. The third contact region 63C is smaller than the third low-concentration region 62C when viewed from above. The dimension (width) of the third contact region 63C in the X direction is smaller than the dimension in the X direction of the third terminal-side contact region 53. The dimension (length) of the third contact region 63C in the Y direction is larger than the dimension in the Y direction of the third terminal-side low-concentration region 52. In one example, the width and length dimensions of the third contact region 63C are equal to the width and length dimensions of the first contact region 63A.

[0114] The high-concentration region 61 has the same area as the diode pair region 60 when viewed from above. The shape and size of the high-concentration region 61 when viewed from above are the same as those of the diode pair region 60 when viewed from above.

[0115] The separation region 65 is the region obtained by removing the first low-concentration region 62A, the second low-concentration region 62B, the third low-concentration region 62C, the first contact region 63A, the second contact region 63B, and the third contact region 63C from the high-concentration region 61 under top-view observation. Therefore, under top-view observation, the separation region 65 is provided on both the first connection region 67A and the second connection region 67B. The separation region 65 is provided around the entire outer edge of the diode pair region 60 (high-concentration region 61). The separation region 65 is provided in the first region 66A to surround the entire circumference of the first low-concentration region 62A. The separation region 65 is provided in the second region 66B to surround the entire circumference of the second low-concentration region 62B. The separation region 65 is provided in the third region 66C to surround the entire circumference of the third low-concentration region 62C.

[0116] The area of ​​the separated region 65 under top-view observation is larger than the combined area of ​​the first low-concentration region 62A, the second low-concentration region 62B, and the third low-concentration region 62C under top-view observation.

[0117] like Figure 5 As shown, the internal region 64, when viewed from above, overlaps completely with the first region 66A, the second region 66B, and the third region 66C. The internal region 64, when viewed from above, overlaps with both the first connecting region 67A and the second connecting region 67B. In one example, the internal region 64 is smaller than the high-concentration region 61 when viewed from above.

[0118] The internal region 64, like the diode pair region 60, includes a first region 68A, a second region 68B, a third region 68C, a first connection region 69A, and a second connection region 69B. The first region 68A is positioned at the location overlapping with the first region 66A when viewed from above. The first region 68A is smaller than the first region 66A when viewed from above. The first region 68A includes the first to fourth sides 68AA to 68AD. The first to fourth sides 68AA to 68AD are the sides corresponding to the first to fourth sides 66AA to 66AD of the first region 66A. The first to fourth sides 68AA to 68AD are positioned inside the first region 66A when viewed from above. That is, it can be said that the first region 68A is positioned within the first region 66A when viewed from above. Furthermore, the first region 68A extends throughout the first low-concentration region 62A (see reference 66A). Figure 4 The overall overlapping settings.

[0119] The second region 68B is positioned where it overlaps with the second region 66B when viewed from above. The second region 68B is smaller than the second region 66B when viewed from above. The second region 68B includes the first to fourth sides 68BA to 68BD. The first to fourth sides 68BA to 68BD correspond to the first to fourth sides 66BA to 66BD of the second region 66B. The first to fourth sides 68BA to 68BD are positioned inside the second region 66B when viewed from above. That is, it can be said that the second region 68B is positioned within the second region 66B when viewed from above. Furthermore, the second region 68B extends throughout the second low-concentration region 62B (see reference 66B). Figure 4 The overall overlapping settings.

[0120] The third region 68C is positioned where it overlaps with the third region 66C when viewed from above. The third region 68C is smaller than the third region 66C when viewed from above. The third region 68C includes the first to fourth sides 68CA to 68CD. The first to fourth sides 68CA to 68CD are the sides corresponding to the first to fourth sides 66CA to 66CD of the third region 66C. When viewed from above, the first to fourth sides 68CA to 68CD are positioned inside the third region 66C relative to the first to fourth sides 66CA to 66CD of the third region 66C. That is, it can be said that the third region 68C is positioned within the third region 66C when viewed from above. Furthermore, the third region 68C extends throughout the third low-concentration region 62C (see reference 62C). Figure 4 The overall overlapping settings.

[0121] The first connecting region 69A is positioned to overlap with the first connecting region 67A when viewed from above. The first connecting region 69A is smaller than the first connecting region 67A when viewed from above. The first connecting region 69A is located within the first connecting region 67A when viewed from above. The first connecting region 69A connects the second side 68AB of the first region 68A to the third side 68BC of the second region 68B, and connects the fourth side 68AD of the first region 68A to the first side 68BA of the second region 68B. The two ends of the first connecting region 69A in the Y direction are curved when viewed from above. The radius of curvature of the two ends of the first connecting region 69A in the Y direction is larger than the radius of curvature of the corners of the first region 68A.

[0122] The second connecting region 69B is positioned to overlap with the second connecting region 67B when viewed from above. The second connecting region 69B is smaller than the second connecting region 67B when viewed from above. The second connecting region 69B is located within the second connecting region 67B when viewed from above. The second connecting region 69B connects the second side 68BB of the second region 68B to the fourth side 68CD of the third region 68C, and connects the third side 68BC of the second region 68B to the first side 68CA of the third region 68C. The two ends of the second connecting region 69B in the Y direction are curved when viewed from above. The radius of curvature of the two ends of the second connecting region 69B in the Y direction is larger than the radius of curvature of the corners of the third region 68C.

[0123] Thus, when viewed from above, the internal region 64 is arranged to overlap with the entirety of the first low-concentration region 62A, the entirety of the second low-concentration region 62B, and the entirety of the third low-concentration region 62C. Furthermore, when viewed from above, the internal region 64 is formed with a shape similar to that of the high-concentration region 61 (diode pair region 60).

[0124] like Figure 6 As shown, the distance DD between the outer periphery of the inner region 64 and the outer periphery of the high-concentration region 61 remains constant throughout the outer periphery of the inner region 64. The distance DD can be set to approximately 5 μm. Furthermore, the center of curvature C1 of the corner of the inner region 64 can be located at the same position as the center of curvature C2 of the corner in the high-concentration region 61 corresponding to the aforementioned corner of the inner region 64. Therefore, the radius of curvature of the corner of the inner region 64 is smaller than the radius of curvature of the corner of the high-concentration region 61.

[0125] (Electrode connection and wiring) like Figure 7 As shown, the first connecting electrode 81, the second connecting electrode 82, and the third connecting electrode 83 are respectively arranged in the outer peripheral region 110 (see reference) when viewed from above. Figure 4Inside the first connecting electrode 81, the second connecting electrode 82, and the third connecting electrode 83 are arranged separately from each other.

[0126] The first connection electrode 81 is positioned offset from the center of the semiconductor chip 20 in the X direction, closer to the first side surface 20A, when viewed from above. The first connection electrode 81 extends along the Y direction. The first connection electrode 81 includes a pin connection portion 81A and a wiring portion 81B extending from the pin connection portion 81A toward the third side surface 20C along the Y direction. In one example, the pin connection portion 81A and the wiring portion 81B are integrated.

[0127] The pin connector 81A is positioned, when viewed from above, with the first pin junction 30 (see reference). Figure 4 The overlapping positions. The pin connection portion 81A is square when viewed from above. The pin connection portion 81A is located in the low concentration region 32 on the first terminal side of the first pin junction 30 when viewed from above (refer to...). Figure 4 Inside, the pin connection portion 81A is larger than the first terminal side contact area 33 of the first pin junction 30 when viewed from above.

[0128] The wiring section 81B, viewed from above, is formed as a strip with width in the X direction. The width dimension of the wiring section 81B is smaller than the X-direction dimension of the pin connection section 81A. The wiring section 81B is offset from the pin connection section 81A in the X direction. More specifically, the imaginary line CL1 extending in the Y direction from the center of the width of the wiring section 81B is located off-center from the center of the X-direction of the pin connection section 81A, towards the second side 20B.

[0129] The wiring portion 81B, when viewed from above, is arranged to cover the first contact area 63A of the first reverse pin junction 60A. In one example, the wiring portion 81B covers the entire first contact area 63A when viewed from above. Therefore, the width of the wiring portion 81B is larger than the width of the first contact area 63A. On the other hand, the width of the wiring portion 81B is smaller than the width of the first low-density area 62A. The tip of the wiring portion 81B is curved when viewed from above.

[0130] A reverse pin connection portion 81C is provided in the wiring portion 81B at a position overlapping with the first contact area 63A. The reverse pin connection portion 81C is connected to the first contact area 63A.

[0131] The second connection electrode 82 extends along the Y direction. The second connection electrode 82 is separated from the first connection electrode 81 in the X direction, offset from the second side 20B. The second connection electrode 82 includes a portion that overlaps with the first connection electrode 81 when viewed from the X direction. In one example, the second connection electrode 82 is positioned at the center of the semiconductor chip 20 in the X direction when viewed from above.

[0132] The second connection electrode 82 includes a pin connection portion 82A and a wiring portion 82B extending from the pin connection portion 82A toward the fourth side surface 20D along the Y direction. In one example, the pin connection portion 82A and the wiring portion 82B are integrated.

[0133] The pin connector 82A is positioned at the junction with the second pin 40 (see reference) when viewed from above. Figure 4 The overlapping positions. The pin connection portion 82A is square when viewed from above. The pin connection portion 82A is located in the low-concentration region 42 on the second terminal side of the second pin junction 40 (see reference). Figure 4 Inside. The pin connection portion 82A, when viewed from above, is larger than the second terminal side contact area 43 of the second pin junction 40. In one example, the size and shape of the pin connection portion 82A are the same as those of the pin connection portion 81A.

[0134] The wiring portion 82B, when viewed from above, is formed as a strip with width in the X direction. The width dimension of the wiring portion 82B is smaller than the X-direction dimension of the pin connection portion 82A. The wiring portion 82B, when viewed from above, is arranged to cover the second contact area 63B of the second reverse pin junction 60B. In one example, the wiring portion 82B, when viewed from above, covers the entire second contact area 63B. Therefore, the width dimension of the wiring portion 82B is larger than the width dimension of the second contact area 63B. On the other hand, the width dimension of the wiring portion 82B is smaller than the width dimension of the second low-concentration area 62B. The top end of the wiring portion 82B is curved when viewed from above. In one example, the size and shape of the wiring portion 82B are the same as those of the wiring portion 81B. The wiring portion 82B is connected to the center of the pin connection portion 82A in the X direction.

[0135] A reverse pin connection portion 82C is provided in the wiring portion 82B at a position overlapping with the second contact area 63B. The reverse pin connection portion 82C is connected to the second contact area 63B.

[0136] The third connecting electrode 83 extends along the Y direction. The third connecting electrode 83 is configured separately from the second connecting electrode 82 in the X direction, offset from the second side 20B. The third connecting electrode 83 includes a portion that overlaps with the second connecting electrode 82 when viewed from the X direction. In one example, the third connecting electrode 83 is positioned at the same location as the first connecting electrode 81 in the Y direction.

[0137] The third connection electrode 83 includes a pin connection portion 83A and a wiring portion 83B extending from the pin connection portion 83A toward the third side surface 20C along the Y direction. In one example, the pin connection portion 83A and the wiring portion 83B are integrated.

[0138] The pin connector 83A is positioned at the junction with the third pin 50 (see reference) when viewed from above. Figure 4 The overlapping position. The pin connection portion 83A is square when viewed from above. The pin connection portion 83A is located in the low-concentration region 52 on the third terminal side of the third pin junction 50 (see reference). Figure 4 Inside. The pin connection portion 83A, when viewed from above, is larger than the third terminal side contact area 53 of the third pin junction 50. In one example, the size and shape of the pin connection portion 83A are the same as those of the pin connection portion 81A.

[0139] The wiring section 83B, viewed from above, is formed as a strip with width in the X direction. The width dimension of the wiring section 83B is smaller than the X-direction dimension of the pin connection section 83A. The wiring section 83B is offset from the pin connection section 83A in the X direction. More specifically, the imaginary line CL3 extending in the Y direction from the center of the width of the wiring section 83B is located offset from the imaginary line CL4 extending in the Y direction from the center of the X direction of the pin connection section 83A, towards the first side surface 20A.

[0140] The wiring portion 83B, when viewed from above, is arranged to cover the third contact area 63C of the third reverse pin junction 60C. In one example, the wiring portion 83B covers the entire third contact area 63C when viewed from above. Therefore, the width of the wiring portion 83B is larger than the width of the third contact area 63C. On the other hand, the width of the wiring portion 83B is smaller than the width of the third low-density region 62C. The top end of the wiring portion 83B is curved when viewed from above. In one example, the size and shape of the wiring portion 83B are the same as those of the wiring portion 81B.

[0141] A reverse pin connection portion 83C is provided in the wiring portion 83B at a position overlapping with the third contact area 63C. The reverse pin connection portion 83C is connected to the third contact area 63C. When viewed from above, the reverse pin connection portion 83C is formed into an elongated circle with the Y direction as the long side and the X direction as the short side.

[0142] Wiring 90 is positioned within the outer perimeter area 110 when viewed from above. Wiring 90, when viewed from above, is aligned with... Figure 4 The diode pair region 60 (high concentration region 61) is shown to overlap with it. The outer periphery of the wiring 90 includes a portion that overlaps with the outer periphery of the diode pair region 60 (high concentration region 61) when viewed from above. In one example, the wiring 90 is arranged such that its entire area overlaps with the separation region 65 when viewed from above. Therefore, the wiring 90 is arranged to avoid the first pin junction 30, the second pin junction 40, and the third pin junction 50 when viewed from above. The wiring 90 is arranged to partially surround the first connecting electrode 81, the second connecting electrode 82, and the third connecting electrode 83 when viewed from above.

[0143] The cabling 90 includes a first area 91, a second area 92, a third area 93, a first connection area 94, and a second connection area 95. The first region 91, viewed from above, corresponds to the first region 66A of the diode in region 60 (see reference). Figure 4 The overlapping method is used. The outer perimeter of the first region 91 overlaps with the first to third sides 66AA to 66AC of the first region 66A (all refer to...). Figure 4 The corresponding part is set in a way that overlaps with the first to third sides 66AA to 66AC when viewed from above.

[0144] The first region 91 includes a first recess 96A that, when viewed from above, avoids the first connecting electrode 81. The first recess 96A opens toward the first pin junction 30. A wiring portion 81B of the first connecting electrode 81 is disposed within the first recess 96A. Thus, the first region 91, when viewed from above, partially surrounds the first connecting electrode 81. Furthermore, the first recess 96A, when viewed from above, avoids a first low-concentration region 62A (see reference 66A). Figure 4 Therefore, the first region 91 is set in a manner that surrounds the first low-concentration region 62A when viewed from above.

[0145] By providing the first recess 96A, it can be said that the first region 91 and the separated region 65 in the first region 66A (see reference) Figure 4 Local connections. More specifically, such as... Figure 4As shown, the separation region 65 in the first region 66A includes a wiring connection region 65P connected to the wiring 90, and a region connected to the first connection electrode 81 (see reference 1) when viewed from above. Figure 7 The first separation region 65A overlaps with the first region 66A. The first separation region 65A is located at the end of the first pin junction 30, which is offset from the end of the first region 66A in the Y direction. The first separation region 65A is the region located between the first low-concentration region 62A and the fourth side 66AD in the first region 66A when viewed from above. The wiring connection region 65P is provided in a manner that partially surrounds the first low-concentration region 62A when viewed from above. That is, the wiring connection region 65P is provided in a manner that partially surrounds the first reverse pin junction 60A when viewed from above. Therefore, the first region 91 (refer to the first low-concentration region 91) connected to the wiring connection region 65P is... Figure 7 (When viewed from above, it is arranged to partially surround the first reverse pin junction 60A.)

[0146] Second area 92 (refer to) Figure 7 The second region 92 is arranged in a manner that overlaps with the second region 66B of the diode pair region 60 when viewed from above. The portions of the outer periphery of the second region 92 corresponding to the first side 66BA, the second side 66BB, and the fourth side 66BD of the second region 66B are also arranged in a manner that overlaps with the first side 66BA, the second side 66BB, and the fourth side 66BD when viewed from above. Therefore, the second region 92 includes a region offset from the first region 91 in the Y direction.

[0147] like Figure 7 As shown, the second region 92 includes a second recess 96B positioned in a top view to avoid the second connection electrode 82. The second recess 96B faces the second pin junction 40 (see reference). Figure 4 The second region 92 is provided with an opening. A wiring portion 82B for the second connecting electrode 82 is disposed within the second recess 96B. Thus, the second region 92, when viewed from above, is positioned to partially surround the second connecting electrode 82. Furthermore, the second recess 96B, when viewed from above, avoids the second low-concentration region 62B (see reference 66B). Figure 4 Therefore, the second region 92 is positioned in a manner that surrounds the second low-concentration region 62B when viewed from above.

[0148] By providing the second recess 96B, it can be said that the second region 92 is partially connected to the separated region 65 in the second region 66B. More specifically, as... Figure 4As shown, the separation region 65 in the second region 66B includes a wiring connection region 65P connected to the wiring 90, and a second separation region 65B that overlaps with the second connection electrode 82 when viewed from above. The second separation region 65B is located at the end of the second pin junction 40 of the two ends of the second region 66B in the Y direction. The second separation region 65B is the region located between the second low-concentration region 62B and the third side 66BC in the second region 66B when viewed from above. The wiring connection region 65P is arranged in a manner that partially surrounds the second low-concentration region 62B when viewed from above. That is, the wiring connection region 65P is arranged in a manner that partially surrounds the second reverse pin junction 60B when viewed from above. Therefore, the second region 92 (refer to) connected to the wiring connection region 65P Figure 7 (When viewed from above, it is arranged to partially surround the second reverse pin junction 60B.)

[0149] Third Region 93 (Reference) Figure 7 When viewed from above, it is arranged to overlap with the third region 66C of the diode pair region 60. The portion of the outer periphery of the third region 93 that corresponds to the first to third sides 66CA to 66CC of the third region 66C is arranged to overlap with the first to third sides 66CA to 66CC when viewed from above.

[0150] like Figure 7 As shown, the third region 93 includes a third recess 96C that, when viewed from above, avoids the third connecting electrode 83. The third recess 96C opens toward the third pin junction 50. A wiring portion 83B of the third connecting electrode 83 is disposed within the third recess 96C. Thus, the third region 93, when viewed from above, partially surrounds the third connecting electrode 83. Furthermore, the third recess 96C, when viewed from above, avoids the third low-concentration region 62C (both refer to...) Figure 4 Therefore, the third region 93 is set up in a manner that surrounds the third low-concentration region 62C when viewed from above.

[0151] By providing the third recess 96C, it can be said that the third region 93 is locally connected to the separated region 65 in the third region 66C. More specifically, as... Figure 4As shown, the separation region 65 in the third region 66C includes a wiring connection region 65P connected to the wiring 90, and a third separation region 65C that overlaps with the third connection electrode 83 when viewed from above. The third separation region 65C is located at the end of the third pin junction 50 of the two ends of the third region 66C in the Y direction. The third separation region 65C is the region located between the third low-concentration region 62C and the fourth side 66CD in the third region 66C when viewed from above. The wiring connection region 65P is provided in a manner that partially surrounds the third low-concentration region 62C when viewed from above. That is, the wiring connection region 65P is provided in a manner that partially surrounds the third reverse pin junction 60C when viewed from above. Therefore, the third region 93 (refer to) connected to the wiring connection region 65P Figure 7 (When viewed from above, it is set up in a way that partially surrounds the third reverse pin junction 60C.)

[0152] like Figure 7 As shown, the first connection region 94, viewed from above, is adjacent to the first connection region 67A of the diode pair region 60 (both referenced). Figure 4 The first connection area 94 is arranged in an overlapping manner. The shape and size of the first connection area 94 are the same as those of the first connection area 67A. The first connection area 94 connects the entire area of ​​the first connection area 67A. In other words, the first connection area 67A is composed of the wiring connection area 65P.

[0153] The second connection region 95, viewed from above, is adjacent to the second connection region 67B of the diode pair region 60 (both referenced). Figure 4 The second connection area 95 is arranged in an overlapping manner. The shape and size of the second connection area 95 are the same as those of the second connection area 67B. The second connection area 95 connects the entire area of ​​the second connection area 67B. In other words, the second connection area 67B is composed of the wiring connection area 65P.

[0154] The area of ​​the wiring 90, viewed from above, is larger than the area of ​​the first connecting electrode 81, viewed from above. The area of ​​the wiring 90, viewed from above, is larger than the area of ​​the second connecting electrode 82, viewed from above. The area of ​​the wiring 90, viewed from above, is larger than the area of ​​the high-concentration region 61, viewed from above. In one example, the wiring 90 is positioned so as not to extend beyond the outer edge of the high-concentration region 61, viewed from above.

[0155] The area of ​​the wiring 90 as viewed from above is greater than the separation area 65 as viewed from above (refer to...). Figure 4The area of ​​the wiring 90 is small. In one example, the area of ​​the wiring 90 viewed from above can be set to be more than 75% and less than 97% of the area of ​​the separation region 65 viewed from above. In one example, the area of ​​the wiring 90 viewed from above can be set to be more than 80% and less than 95% of the area of ​​the separation region 65 viewed from above. In one example, the area of ​​the wiring 90 viewed from above can be set to be more than 85% and less than 95% of the area of ​​the separation region 65 viewed from above. In one example, the area of ​​the wiring 90 viewed from above can be set to be more than 90% and less than 95% of the area of ​​the separation region 65 viewed from above. In one example, the area of ​​the wiring 90 viewed from above can be set to be more than 85% and less than 90% of the area of ​​the separation region 65 viewed from above.

[0156] (Terminal opening) like Figure 1 As shown, the first terminal opening 77A, the second terminal opening 77B, and the third terminal opening 77C are spaced apart from each other. More specifically, the first terminal opening 77A and the third terminal opening 77C are located at the same position in the Y direction and spaced apart from each other in the X direction. The first terminal opening 77A and the third terminal opening 77C are positioned closer to the fourth side surface 20D in the Y direction than the center of the first surface 20S of the semiconductor chip 20. The first terminal opening 77A is positioned closer to the first side surface 20A in the X direction than the center of the first surface 20S. The third terminal opening 77C is positioned closer to the second side surface 20B in the X direction than the center of the first surface 20S.

[0157] The second terminal opening 77B is disposed at different positions in the X and Y directions relative to the first terminal opening 77A and the third terminal opening 77C. The second terminal opening 77B is disposed at a position closer to the third side surface 20C in the Y direction than the center of the first surface 20S of the semiconductor chip 20. The second terminal opening 77B is disposed at the center of the first surface 20S in the X direction. Therefore, it can be said that the second terminal opening 77B, when viewed from the Y direction, is disposed between the first terminal opening 77A and the third terminal opening 77C in the X direction.

[0158] like Figure 1 and Figure 4 As shown, the first terminal opening 77A is positioned to overlap with the first pin junction 30 when viewed from above. The second terminal opening 77B is positioned to overlap with the second pin junction 40 when viewed from above. The third terminal opening 77C is positioned to overlap with the third pin junction 50 when viewed from above.

[0159] When viewed from above, the first terminal opening 77A exposes the pin connection portion 81A of the first connecting electrode 81. When viewed from above, the second terminal opening 77B exposes the pin connection portion 82A of the second connecting electrode 82. When viewed from above, the third terminal 103 exposes the pin connection portion 83A of the third connecting electrode 83.

[0160] (Circuit structure of TVS diode) Next, refer to Figure 8 The TVS circuit 200 for TVS diode 10 will be explained. Figure 8 The circuit structure of TVS diode 10 is shown schematically.

[0161] like Figure 8 As shown, the TVS circuit 200 includes first to sixth diodes 201 to 206, a Zener diode 207, and first to third terminals TM1 to TM3. Here, the first terminal TM1 can, for example, be formed by the portion of the first connecting electrode 81 exposed from the first terminal opening 77A. The second terminal TM2 can, for example, be formed by the portion of the second connecting electrode 82 exposed from the second terminal opening 77B. The third terminal TM3 can, for example, be formed by the portion of the third connecting electrode 83 exposed from the third terminal opening 77C.

[0162] Diode 201 forms a pin diode with a first pin junction 30. Diode 202 forms a pin diode with a second pin junction 40. Diode 203 forms a pin diode with a third pin junction 50. Diode 204 forms a pin diode with a first reverse pin junction 60A. Diode 205 forms a pin diode with a second reverse pin junction 60B. Diode 206 forms a pin diode with a third reverse pin junction 60C.

[0163] The cathode of the first diode 201 is electrically connected to the anode of the fourth diode 204. The first terminal TM1 is electrically connected to node N1 between the cathode of the first diode 201 and the anode of the fourth diode 204. The cathode of the second diode 202 is electrically connected to the anode of the fifth diode 205. The second terminal TM2 is electrically connected to node N2 between the cathode of the second diode 202 and the anode of the fifth diode 205.

[0164] The cathode of the third diode 203 is electrically connected to the anode of the sixth diode 206. The third terminal TM3 is electrically connected to node N3 between the cathode of the third diode 203 and the anode of the sixth diode 206.

[0165] Zener diode 207 is connected in parallel with the series groups of first diode 201 and fourth diode 204, second diode 202 and fifth diode 205, and third diode 203 and sixth diode 206. The anode of Zener diode 207 is electrically connected to the anodes of first diode 201, second diode 202, and third diode 203. The cathode of Zener diode 207 is electrically connected to the cathodes of fourth diode 204, fifth diode 205, and sixth diode 206. Thus, Zener diode 207 constitutes a diode with a common reverse connection relative to fourth diode 204, fifth diode 205, and sixth diode 206.

[0166] In one example, the first terminal TM1 and the third terminal TM3 constitute an input terminal, and the second terminal TM2 constitutes a ground terminal. Therefore, when a voltage is applied to the first terminal TM1, current flows from the first terminal TM1 through the fourth diode 204, the Zener diode 207, and the second diode 202 to the second terminal TM2. Similarly, when a voltage is applied to the third terminal TM3, current flows from the third terminal TM3 through the sixth diode 206, the Zener diode 207, and the second diode 202 to the second terminal TM2. Alternatively, the first terminal TM1 and the second terminal TM2 may constitute an input terminal, and the third terminal TM3 may constitute a ground terminal. Furthermore, the second terminal TM2 and the third terminal TM3 may constitute an input terminal, and the first terminal TM1 may constitute a ground terminal.

[0167] (Manufacturing method of TVS diode) Reference Figures 9 to 25 An example of the manufacturing method of TVS diode 10 will be described. Figures 9 to 25 The diagram shows a cross-sectional view of the TVS diode 10 during its manufacturing process.

[0168] like Figure 9 As shown, the manufacturing method of the TVS diode 10 includes steps for preparing a semiconductor wafer 800. The semiconductor wafer 800 is, for example, a Si wafer. The semiconductor wafer 800 contains p-type impurities. As a p-type impurity, boron (B) can be used, for example.

[0169] like Figure 10 As shown, the manufacturing method of the TVS diode 10 includes a step for forming a first epitaxial layer 810. In this step, Si crystal is grown from the upper surface of a semiconductor wafer 800 by epitaxial growth. P-type impurity concentration diffuses into the Si along the crystal growth path of the semiconductor wafer 800. Thus, a p-type first epitaxial layer 810, which becomes a first semiconductor layer 23, is formed on the semiconductor wafer 800.

[0170] like Figure 11As shown, the manufacturing method of the TVS diode 10 includes a step of selectively introducing p-type impurities (e.g., B) into the surface portion of the first epitaxial layer 810. This step involves selectively introducing p-type impurities into the surface portion of the first epitaxial layer 810 in a region where a first terminal-side high-concentration region 31 is to be formed, and a second terminal-side high-concentration region 41 (see reference 1)... Figure 3 The process involves introducing the region of the first epitaxial layer 810 and the region where the third terminal-side high-concentration region 51 should be formed. In this process, p-type impurities can be selectively implanted into the surface portion of the first epitaxial layer 810 using, for example, an ion implantation method using an ion implantation mask (not shown). As a result, a portion of the first terminal-side high-concentration region 31 (first region 31A), a portion of the second terminal-side high-concentration region 41, and a portion of the third terminal-side high-concentration region 51 are formed.

[0171] Next, as Figure 12 As shown, p-type impurities are introduced into the region where the internal region 64 is to be formed in the surface portion of the first epitaxial layer 810. In this process, p-type impurities can be selectively implanted into the surface portion of the first epitaxial layer 810 using the ion implantation method described above. This forms a portion of the internal region 64.

[0172] In addition, including Figure 11 and Figure 12 The accompanying drawings, including those concerning the manufacturing method of the TVS diode 10 according to the first embodiment, show a portion of the high-concentration region 31 on the first terminal side (first region 31A), a portion of the high-concentration region 51 on the third terminal side, and a portion of the internal region 64, but do not show a portion of the high-concentration region 41 on the second terminal side. Alternatively, it is also possible to... Figure 11 Performed before the process shown Figure 12 The process shown.

[0173] like Figure 13 As shown, the manufacturing method of the TVS diode 10 includes a step for forming a second epitaxial layer 820. In this step, Si crystal is grown from the first epitaxial layer 810 by an epitaxial growth method. Thus, an n-type second epitaxial layer 820, which becomes the second semiconductor layer 24, is formed on the first epitaxial layer 810. Alternatively, the second epitaxial layer 820 may also be p-type.

[0174] Next, the manufacturing method of the TVS diode 10 includes a step of selectively introducing p-type impurities into the second epitaxial layer 820. In this step, the p-type impurities are selectively implanted into regions of the second epitaxial layer 820 to form the first terminal-side high-concentration region 31, the second terminal-side high-concentration region 41, the third terminal-side high-concentration region 51, and the internal region 64, for example, using an ion implantation mask (not shown). In this step, it is also possible to... Figure 11The process shown is similarly divided into a process of selectively injecting p-type impurities into the regions to which the first terminal-side high-concentration region 31, the second terminal-side high-concentration region 41, and the third terminal-side high-concentration region 51 should be formed, and a process of selectively injecting p-type impurities into the regions to which the internal region 64 should be formed.

[0175] Next, the method for manufacturing the TVS diode 10 includes a step of introducing an n-type impurity into the region 60 to be formed in the surface portion of the second epitaxial layer 820. As the n-type impurity, at least one of As (arsenic) and P (phosphorus) can be used. The n-type impurity can be implanted into the surface portion of the second epitaxial layer 820 using an ion implantation method employing an ion implantation mask (not shown). This forms a portion of a high-concentration region 61 in the surface portion of the second epitaxial layer 820. The high-concentration region 61 is formed in a manner that covers the entire area of ​​the inner region 64 when viewed from above. The high-concentration region 61 is formed in a manner that connects to the inner region 64. That is, a pn junction 60E is formed.

[0176] Next, the manufacturing method of the TVS diode 10 includes a step of diffusing p-type impurities introduced into the surface portion of the first epitaxial layer 810 and p-type and n-type impurities introduced into the second epitaxial layer 820. In this step, for example, the p-type and n-type impurities are diffused by a push-diffusion process. As a result, the p-type impurities introduced into the surface portion of the first epitaxial layer 810 diffuse into the second epitaxial layer 820.

[0177] like Figure 14 As shown, the manufacturing method of the TVS diode 10 includes a step for forming a third epitaxial layer 830. In this step, Si crystal is grown from the second epitaxial layer 820 by an epitaxial growth method accompanied by the introduction of n-type impurities. In this step, p-type impurities and n-type impurities diffuse from the second epitaxial layer 820 into the Si along the crystal growth path. As a result, the third epitaxial layer 830 is formed on the second epitaxial layer 820. In addition, a portion of a first terminal-side high-concentration region 31, a portion of a second terminal-side high-concentration region 41, a portion of a third terminal-side high-concentration region 51, and a high-concentration region 61 are formed at the boundary between the second epitaxial layer 820 and the third epitaxial layer 830.

[0178] Through the above processes, a semiconductor wafer structure 840 is formed, comprising a semiconductor wafer 800, a first epitaxial layer 810, a second epitaxial layer 820, and a third epitaxial layer 830. The semiconductor wafer structure 840 includes a first wafer surface 841 and a second wafer surface 842 located on the side opposite to the first wafer surface 841. The first wafer surface 841 corresponds to the first surface 20S of the semiconductor chip 20, and the second wafer surface 842 corresponds to the second surface 20R of the semiconductor chip 20. The first wafer surface 841 is formed by the third epitaxial layer 830. The second wafer surface 842 is formed by the semiconductor wafer 800.

[0179] like Figure 15 As shown, the manufacturing method of the TVS diode 10 includes a step for forming a defined region and a peripheral region 110. In this step, p-type impurities are selectively implanted into the surface portion of the third epitaxial layer 830 by ion implantation, for example, using an ion implantation mask 910. The ion implantation mask 910 is formed with a first defined region 34 and a second defined region 44 (see reference 1) to be formed in the third epitaxial layer 830. Figure 3 The opening 911 exposes the third defined region 54 and the outer peripheral region 110. P-type impurities are injected into the surface portion of the third epitaxial layer 830 through the opening 911. This forms the first defined region 34, the second defined region 44, the third defined region 54, and the outer peripheral region 110. By forming the first defined region 34 and the outer peripheral region 110, a first terminal-side low-concentration region 32, surrounded by the first defined region 34 in top view, is formed. By forming the second defined region 44 and the outer peripheral region 110, a second terminal-side low-concentration region 42, surrounded by the second defined region 44 in top view, is formed. By forming the third defined region 54 and the outer peripheral region 110, a third terminal-side low-concentration region 52, surrounded by the third defined region 54 in top view, is formed. Furthermore, Figure 15 The first delineated area 34, the third delineated area 54, and the outer perimeter area 110 are shown, but the second delineated area 44 is not shown.

[0180] like Figure 16As shown, the manufacturing method of the TVS diode 10 includes a step for forming a separation region 65. In this step, n-type impurities are selectively implanted into the surface portion of the third epitaxial layer 830 by ion implantation, for example, using an ion implantation mask 920. An opening 921 is formed on the ion implantation mask 920 to expose the region in the surface portion of the third epitaxial layer 830 where the separation region 65 is to be formed. The n-type impurities are implanted into the surface portion of the third epitaxial layer 830 through the opening 921. Thus, the n-type separation region 65 is formed. By forming the separation region 65, a first low-concentration region 62A, a second low-concentration region 62B, and a third low-concentration region 62C, which are surrounded by the separation region 65 when viewed from above, are formed.

[0181] like Figure 17 As shown, the manufacturing method of the TVS diode 10 includes a step for forming terminal-side contact regions. In this step, n-type impurities are selectively implanted into the surface portion of the third epitaxial layer 830 by, for example, ion implantation using an ion implantation mask 930. An opening 931 is formed on the ion implantation mask 930 to expose the regions in the surface portion of the third epitaxial layer 830 where the first terminal-side contact region 33, the second terminal-side contact region 43, and the third terminal-side contact region 53 are to be formed. The opening 931 exposes the first terminal-side low-concentration region 32 and the second terminal-side low-concentration region 42 (see reference 530) in the surface portion of the third epitaxial layer 830. Figure 3 The surface portions of the first terminal-side low-concentration region 32, the second terminal-side low-concentration region 42, and the third terminal-side low-concentration region 52 are partially exposed. An n-type impurity is injected through the opening 931 into the surface portions of the first terminal-side low-concentration region 32, the second terminal-side low-concentration region 42, and the third terminal-side low-concentration region 52. As a result, an n-type first terminal-side contact region 33 is formed on the surface portion of the first terminal-side low-concentration region 32. An n-type second terminal-side contact region 43 is formed on the surface portion of the second terminal-side low-concentration region 42 (see reference 52). Figure 3 An n-shaped third terminal-side contact region 53 is formed on the surface layer of the low-concentration region 52 on the third terminal side. Through the above processes, a first pin junction 30, a second pin junction 40, and a third pin junction 50 are formed. Furthermore, Figure 17 The first terminal side contact area 33 and the third terminal side contact area 53 are shown, but the second terminal side contact area 43 is not shown.

[0182] like Figure 18As shown, the manufacturing method of the TVS diode 10 includes a step for forming contact regions. In this step, p-type impurities are selectively implanted into the surface portion of the third epitaxial layer 830 by ion implantation, for example, using an ion implantation mask 940. An opening 941 is formed on the ion implantation mask 940 to expose the regions in the surface portion of the third epitaxial layer 830 where the first contact region 63A, the second contact region 63B, and the third contact region 63C are to be formed. The opening 941 partially exposes the surface portions of the first low-concentration region 62A, the second low-concentration region 62B, and the third low-concentration region 62C in the surface portion of the third epitaxial layer 830. P-type impurities are implanted into the surface portions of the first low-concentration region 62A, the second low-concentration region 62B, and the third low-concentration region 62C through the opening 941. Thus, a p-type first contact region 63A is formed in the surface portion of the first low-concentration region 62A. A p-type second contact region 63B is formed on the surface of the second low-concentration region 62B. A p-type third contact region 63C is formed on the surface of the third low-concentration region 62C. Through the above processes, a first reverse pin junction 60A, a second reverse pin junction 60B, and a third reverse pin junction 60C are formed.

[0183] like Figures 19-21 As shown, the manufacturing method of TVS diode 10 includes a step for forming an insulating layer 850. like Figure 19 As shown, the process for forming the insulating layer 850 includes the process of forming a first insulating layer 851. The first insulating layer 851 is formed on the first wafer surface 841 of the semiconductor wafer structure 840. The first insulating layer 851 is the insulating layer constituting the first insulating layer 71 of the insulating layer 70. The first insulating layer 851 can be formed by CVD (Chemical Vapor Deposition) or oxidation processing (e.g., thermal oxidation processing).

[0184] Next, as Figure 20 As shown, the process for forming the insulating layer 850 includes the process of forming a second insulating layer 852. The second insulating layer 852 is formed on the first insulating layer 851. The second insulating layer 852 is the insulating layer constituting the second insulating layer 72 of the insulating layer 70. The second insulating layer 852 can be formed by at least one of CVD and oxidation processes.

[0185] Next, as Figure 21As shown, the process for forming the insulating layer 850 includes forming first to sixth openings 73A to 73F and wiring openings 73G that partially expose the first wafer surface 841. In this process, a resist mask 950 with a predetermined pattern is first formed on the second insulating layer 852. The resist mask 950 exposes the areas in the insulating layer 850 where the first to sixth openings 73A to 73F and wiring openings 73G of the insulating layer 70 are to be formed, and covers the remaining areas. Then, the portions exposed from the resist mask 950 are removed by etching using the resist mask 950. Thus, the first to sixth openings 73A to 73F and wiring openings 73G are formed.

[0186] like Figure 22 As shown, the manufacturing method of the TVS diode 10 includes a step for forming a connection electrode and a step for forming a wiring 90. In one example, the step for forming the connection electrode and the step for forming the wiring 90 are performed as a common step.

[0187] First, a metal layer is formed on the insulating layer 850. The metal layer covers the insulating layer 850 and fills the first to sixth openings 73A to 73F. Therefore, the metal layer is in contact with the first terminal-side contact region 33, the second terminal-side contact region 43, the third terminal-side contact region 53, the first to third contact regions 63A to 63C, and the separation region 65. The metal layer constitutes the first to third connecting electrodes 81 to 83 and the wiring 90.

[0188] Next, unwanted portions of the metal layer are removed using an etching method employing a resist mask (illustrated but not shown) with a prescribed pattern. The resist mask covers the areas of the metal layer where the first to third connection electrodes 81 to 83 and wiring 90 are to be formed, exposing the remaining areas. Then, the portions of the metal layer exposed from the resist mask are removed. Thus, the first to third connection electrodes 81 to 83 and wiring 90 are formed. Furthermore, in Figure 22 The first connecting electrode 81, the third connecting electrode 83, and the wiring 90 are shown, but the second connecting electrode 82 is not shown.

[0189] like Figures 23-25 As shown, the manufacturing method of TVS diode 10 includes a step for forming a protective layer 860. like Figure 23 As shown, the process for forming the protective layer 860 includes the process of forming a first protective layer 861. The first protective layer 861 is an insulating layer constituting the first protective layer 75 of the protective layer 74. The first protective layer 861 can be formed by CVD.

[0190] like Figure 24As shown, the process for forming the protective layer 860 includes the process of forming a second protective layer 862. The second protective layer 862 is a resin layer constituting the second protective layer 76 of the protective layer 74. In one example, the second protective layer 862 is formed by applying a photosensitive resin (in one example, PI) onto the first protective layer 861.

[0191] like Figure 25 As shown, the process for forming the protective layer 860 includes forming the first to third terminal openings 77A to 77C. The first to third terminal openings 77A to 77C are formed by exposing and developing the first protective layer 861 and the second protective layer 862. More specifically, a photoresist is formed on the second protective layer 862. Next, openings are formed on the photoresist by, for example, exposure, to expose the areas in the second protective layer 862 where the first to third terminal openings 77A to 77C are to be formed. Then, the second protective layer 862 and the first protective layer 861 exposed from the openings in the photoresist are removed by development. Thus, the first to third terminal openings 77A to 77C are formed. Furthermore, Figure 25 The first terminal opening 77A and the third terminal opening 77C are shown, but the second terminal opening 77B is not shown (see reference). Figure 3 ).

[0192] Although not illustrated, the manufacturing method of the TVS diode 10 includes a dicing process. In this process, for example, a dicing blade is used to cut the semiconductor wafer structure 840, the insulating layer 850, and the protective layer 860. This forms the semiconductor chip 20, the insulating layer 70, and the protective layer 74 (see figure). Figure 2 After the above processes, TVS diode 10 is manufactured.

[0193] (effect) Reference Figure 26 and Figure 27 The function of the TVS diode 10 in the first embodiment will be explained. Figure 26 The diagram schematically shows an enlarged cross-sectional view of the diode pair region 60 of the TVS diode 10 and its surrounding area. Figure 27 The cross-sectional structure of the second pin junction 40, the second reverse pin junction 60B, the third reverse pin junction 60C, and the third pin junction 50 is schematically shown.

[0194] like Figure 26As shown, diode region 60 includes first to third reverse pin junctions 60A to 60C. High-concentration region 61 constitutes a common P-layer among the first to third reverse pin junctions 60A to 60C. Furthermore, internal region 64, when viewed from above, overlaps with the first low-concentration region 62A, the second low-concentration region 62B, and the third low-concentration region 62C. That is, the pn junction 60E formed by high-concentration region 61 and internal region 64 is configured as a common pn junction for the pn junction reverse-connected to the first reverse pin junction 60A, the second reverse pin junction 60B, and the third reverse pin junction 60C. Therefore, compared to a structure where pn junctions reverse-connected to the first reverse pin junction 60A, the second reverse pin junction 60B, and the third reverse pin junction 60C are independently configured, the junction area between high-concentration region 61 and internal region 64 can be increased if the chip size is the same. Furthermore, miniaturization of the TVS diode 10 can be achieved while maintaining the junction area of ​​the high-concentration region 61 and the inner region 64.

[0195] In addition, such as Figure 26 As indicated by the thick arrow, in the first reverse pin junction 60A, current flows in the order of the first contact region 63A, the first low-concentration region 62A, and the separation region 65. Current flowing to the separation region 65 flows to the wiring 90 connected to the separation region 65. The wiring 90, viewed from above, is arranged to surround the first to third reverse pin junctions 60A to 60C and cover the outer edge of the high-concentration region 61. Therefore, current flowing to the wiring 90 easily flows through the separation region 65 to the entire area of ​​the inner region 64. Similarly, current flows to the second reverse pin junction 60B and the third reverse pin junction 60C. Therefore, when current flows in the second reverse pin junction 60B and when current flows in the third reverse pin junction 60C, current also easily flows to the entire area of ​​the inner region 64.

[0196] like Figure 27As shown, by configuring a portion of the diode pair region 60 between the second pin junction 40 and the third pin junction 50, the amplification factor of the parasitic NPN transistor disposed between the second pin junction 40 and the third pin junction 50 can be reduced. This suppresses the direct current flow from the second pin junction 40 to the third pin junction 50 due to the conduction of the parasitic NPN transistor. Therefore, for example, when electrostatic discharge (ESD) is applied to the second terminal 102, the current flowing to the second terminal 102 will flow into the first semiconductor layer 23 through the second connection electrode 82, the second reverse pin junction 60B, and the pn junction 60E. Furthermore, the current will flow from the first semiconductor layer 23 through the third pin junction 50 and the third connection electrode 83 to the third terminal 103. Thus, when the diode pair region 60 is configured between the second pin junction 40 and the third pin junction 50, the current will flow through the diode pair region 60 and the first semiconductor layer 23.

[0197] (Effect) The TVS diode 10 according to the first embodiment can achieve the following effects. (1-1) The TVS diode 10 includes a semiconductor chip 20 having a first surface 20S and a second surface 20R located on the side opposite to the first surface 20S. The semiconductor chip 20 includes: a first pin junction 30 with a first polarity direction disposed biased against the first surface 20S of the semiconductor chip 20; a second pin junction 40 with a first polarity direction disposed in a region of the semiconductor chip 20 biased against the first surface 20S, separated from the first pin junction 30 when viewed from above in the thickness direction of the semiconductor chip 20; and a diode pair region 60, separated from both the first pin junction 30 and the second pin junction 40 when viewed from above. The diode pair region 60 includes: an n-type high-concentration region 61, separated from the first surface 20S of the semiconductor chip 20 by being biased towards the second surface 20R; n-type first low-concentration regions 62A and 62B, located in the region biased towards the first surface 20S from the high-concentration region 61, overlapping with the high-concentration region 61 in a top-view view, and separated from each other, with a lower impurity concentration than the high-concentration region 61; and a separation region 65, located in the region biased towards the first surface 20S from the high-concentration region 61. In the region, at a position overlapping with the high-concentration region 61 when viewed from above, a first low-concentration region 62A and a second low-concentration region 62B are separated; a p-type first contact region 63A is disposed on the surface of the first low-concentration region 62A; a p-type second contact region 63B is disposed on the surface of the second low-concentration region 62B; and a p-type internal region 64 is disposed at a position overlapping with the high-concentration region 61 when viewed from above, and is connected to the high-concentration region 61 at a position relative to the second surface 20R of the high-concentration region 61. A first reverse pin junction 60A with a second polarity direction is formed by the high-concentration region 61, the first low-concentration region 62A, and the first contact region 63A. A second reverse pin junction 60B with a second polarity direction is formed by the high-concentration region 61, the second low-concentration region 62B, and the second contact region 63B. A pn ​​junction 60E with a first polarity direction reversed relative to the first reverse pin junction 60A and the second reverse pin junction 60B is formed by the high-concentration region 61 and the internal region 64. When viewed from above, the internal region 64 is arranged to overlap with both the first low-concentration region 62A and the second low-concentration region 62B.

[0198] According to this structure, the high-concentration region 61 constitutes a common P-layer for both the first reverse pin junction 60A and the second reverse pin junction 60B. The pn junction 60E, formed by the high-concentration region 61 and the inner region 64, serves as both a pn junction reverse-connected to the first reverse pin junction 60A and a pn junction reverse-connected to the second reverse pin junction 60B. Therefore, compared to a structure that independently provides pn junctions reverse-connected to the first reverse pin junction 60A and the second reverse pin junction 60B, the junction area of ​​the high-concentration region 61 and the inner region 64 can be increased if the chip size is the same. This improves the surge absorption capability due to the increased junction area. Consequently, the electrical characteristics of the TVS diode 10 can be improved.

[0199] (1-2) The separation region 65 includes an exposed surface 65S that is exposed from the first surface 20S of the semiconductor chip 20. The TVS diode 10 includes wiring 90 connected to the exposed surface 65S. According to this structure, the current flowing to the first pin junction 30 and the second pin junction 40 flows to the wiring 90 via the separation region 65. The current flowing to the wiring 90 flows to the entire area of ​​the inner region 64 via the separation region 65. Thus, compared to a structure where the current flows to the entire area of ​​the inner region 64 through the high-concentration region 61 instead of the wiring 90, the current flows with low resistance throughout the entire area of ​​the inner region 64. As a result, surge absorption capability is improved and clamping voltage is reduced.

[0200] (1-3) The separation region 65 includes a first separation region 65A that overlaps with the first connecting electrode 81 when viewed from above, a second separation region 65B that overlaps with the second connecting electrode 82 when viewed from above, and a wiring connection region 65P that connects to the wiring 90. The wiring connection region 65P is configured in a way that independently and partially surrounds the first reverse pin junction 60A and the second reverse pin junction 60B when viewed from above.

[0201] According to this structure, current can easily flow from the first reverse pin junction 60A and the second reverse pin junction 60B through the wiring connection region 65P to the wiring 90. Thus, the current flows with low resistance throughout the entire internal region 64, thereby improving surge absorption capability and reducing clamping voltage.

[0202] (1-4) The wiring 90 is arranged in a way that independently and partially surrounds the first connecting electrode 81 and the second connecting electrode 82 when viewed from above. According to this structure, the wiring 90 can be insulated from the first connecting electrode 81 and the second connecting electrode 82 and can increase the area in contact with the separation region 65. Therefore, current flows from the high concentration region 61 to the inner region 64 through the entire area of ​​the wiring 90, thereby making it easy for current to flow with low resistance throughout the entire area of ​​the inner region 64.

[0203] (1-5) The area of ​​wiring 90 viewed from above is larger than the area of ​​the first connecting electrode 81 viewed from above. According to this structure, the area of ​​the wiring 90 connected to the separation region 65 can be increased. Therefore, current flows from the high concentration region 61 to the inner region 64 through the entire area of ​​the wiring 90, thereby making it easy for current to flow with low resistance throughout the entire area of ​​the inner region 64.

[0204] (1-6) The area of ​​wiring 90 under top view is smaller than the area of ​​separation region 65 under top view. According to this structure, the area of ​​wiring 90 extending beyond separation region 65 when viewed from above can be reduced or reduced to zero. Consequently, the current path flowing from wiring 90 to separation region 65 is shortened, thus enabling current to flow with low resistance throughout the entire area of ​​inner region 64.

[0205] (1-7) The area of ​​the wiring 90 under top view is more than 75% and less than 97% of the area of ​​the separation area 65 under top view. According to this structure, the area of ​​the wiring 90 connected to the separation region 65 can be increased. Therefore, compared to the case where the area of ​​the wiring 90 in top view is less than 75% of the area of ​​the separation region 65 in top view, the current flowing to the first pin junction 30 and the second pin junction 40 can more easily flow from the separation region 65 to the entire area of ​​the wiring 90. Consequently, the current flows from the high-concentration region 61 to the inner region 64 through the entire area of ​​the wiring 90, thereby allowing the current to flow easily with low resistance throughout the entire area of ​​the inner region 64.

[0206] (1-8) The outer edge of the inner region 64 is located further inward than the outer edge of the high concentration region 61 when viewed from above. According to this structure, compared to a structure where the outer edge of the inner region 64 is located at the same position as the outer edge of the high-concentration region 61 when viewed from above, the electric field concentration at the outer edge of the inner region 64 can be suppressed. Therefore, the ESD tolerance can be improved.

[0207] (1-9) When viewed from above, the outer edge of the inner region 64 includes multiple corners. Each of the multiple corners appears curved when viewed from above. This structure can suppress electric field concentration at the corners of the internal region 64, thereby improving ESD tolerance.

[0208] (1-10) The TVS diode 10 includes a semiconductor chip 20 having a first surface 20S and a second surface 20R located on the side opposite to the first surface 20S. The semiconductor chip 20 includes: a first pin junction 30 and a second pin junction 40 in a first polarity direction disposed in a region of the semiconductor chip 20 biased towards the first surface 20S; and a diode pair region 60 including a first reverse pin junction 60A and a second reverse pin junction 60B in a second polarity direction disposed in a region of the semiconductor chip 20 biased towards the first surface 20S, and a pn junction 60E in a first polarity direction disposed at a position overlapping the first reverse pin junction 60A and the second reverse pin junction 60B when viewed from the thickness direction of the semiconductor chip 20 and forming a diode pair with the first reverse pin junction 60A and the second reverse pin junction 60B. The diode pair region 60 is separated from the first pin junction 30 and the second pin junction 40 when viewed from the top. A diode pair region 60 is configured between the first pin junction 30 and the second pin junction 40 when viewed from above.

[0209] According to this structure, by configuring a diode pair region 60 between the first pin junction 30 and the second pin junction 40, the amplification factor of the parasitic NPN transistor located between the first pin junction 30 and the second pin junction 40 can be reduced. This suppresses the phenomenon of current flowing directly from the first pin junction 30 to the second pin junction 40 and vice versa due to the conduction of the parasitic NPN transistor. Therefore, an improvement in ESD tolerance can be achieved.

[0210] (1-11) The diode pair region 60 includes a first region 66A with a first reverse pin junction 60A and a second region 66B with a second reverse pin junction 60B. The second region 66B includes a region offset from the first region 66A in the Y direction. The first region 66A is adjacent to the second pin junction 40 in the X direction when viewed from above. The second region 66B is adjacent to the first pin junction 30 in the X direction when viewed from above.

[0211] According to this structure, the distance between the first pin junction 30 and the second pin junction 40 can be increased, and the area of ​​the diode pair region 60 can be increased. Therefore, it is possible to improve the surge absorption capability and the ESD tolerance.

[0212] (1-12) The first connecting electrode 81 and the second connecting electrode 82 are arranged separately from each other in the X direction when viewed from above. The first connecting electrode 81 and the second connecting electrode 82 extend along the Y direction when viewed from above.

[0213] According to this structure, the shapes of the first connecting electrode 81 and the second connecting electrode 82 can be simplified when viewed from above. Furthermore, the area of ​​the regions where the first connecting electrode 81 and the second connecting electrode 82 overlap with the separation region 65 when viewed from above can be reduced. Therefore, the area of ​​the wiring 90 connected to the separation region 65 can be maximized.

[0214] (1-13) The semiconductor chip 20 includes: a third pin junction 50 with a first polarity orientation, disposed biased against a first surface 20S of the semiconductor chip 20; and a third reverse pin junction 60C with a second polarity orientation, disposed biased against the first surface 20S of the semiconductor chip 20 and forming a diode pair with the pn junction 60E. In top view, the third pin junction 50 and the third reverse pin junction 60C are arranged along the Y direction and electrically connected to each other. In top view, the third pin junction 50 and the third reverse pin junction 60C are configured to be adjacent to the second pin junction 40 and the second reverse pin junction 60B on the side opposite to the first pin junction 30 and the first reverse pin junction 60A in the X direction relative to the second pin junction 40 and the second reverse pin junction 60B. In top view, the third pin junction 50 and the second reverse pin junction 60B are adjacent in the X direction. In top view, the third reverse pin junction 60C and the second pin junction 40 are adjacent in the X direction. The diode pair region 60 includes the area between the second pin junction 40 and the third pin junction 50, which are arranged in a direction intersecting the X and Y directions when viewed from above.

[0215] According to this structure, by configuring a diode pair region 60 between the second pin junction 40 and the third pin junction 50, the amplification factor of the parasitic NPN transistor located between the second pin junction 40 and the third pin junction 50 can be reduced. This suppresses the phenomenon of current flowing directly from the second pin junction 40 to the third pin junction 50 and vice versa due to the conduction of the parasitic NPN transistor. Therefore, an improvement in ESD tolerance can be achieved.

[0216] (1-14) The high-concentration region 61 includes a first region 66A with a first reverse pin junction 60A, a second region 66B with a second reverse pin junction 60B, and a third region 66C with a third reverse pin junction 60C. The second region 66B includes a region offset in the Y direction from the first region 66A and the third region 66C. The second region 66B includes a portion disposed between the first pin junction 30 and the third pin junction 50 in the X direction. The first region 66A and the third region 66C include portions adjacent to the second pin junction 40 in the X direction.

[0217] According to this structure, both the distance between the first pin junction 30 and the second pin junction 40 and the distance between the second pin junction 40 and the third pin junction 50 can be maximized, and the area of ​​the diode pair region 60 can be maximized. Therefore, it is possible to improve the surge absorption capability and the ESD tolerance.

[0218] (1-15) The first connecting electrode 81, the second connecting electrode 82, and the third connecting electrode 83 are arranged separately from each other in the X direction when viewed from above. The first connecting electrode 81, the second connecting electrode 82, and the third connecting electrode 83 extend along the Y direction when viewed from above.

[0219] According to this structure, the shapes of the first connecting electrode 81, the second connecting electrode 82, and the third connecting electrode 83 can be simplified when viewed from above. Furthermore, the area of ​​the regions where the first connecting electrode 81, the second connecting electrode 82, and the third connecting electrode 83 overlap with the separation region 65 when viewed from above can be reduced. Therefore, the area of ​​the wiring 90 connected to the separation region 65 can be maximized.

[0220] (Second Implementation) Reference Figures 28-33 The TVS diode 10 according to the second embodiment will be described. The main difference between the TVS diode 10 of the second embodiment and the TVS diode 10 of the first embodiment lies in the structure of the first pin junction 30, the second pin junction 40, and the third pin junction 50. Hereinafter, the same reference numerals will be used to denote the components common to the first embodiment, and their descriptions will be omitted.

[0221] Figure 28 and Figure 29 The cross-sectional structure of the TVS diode 10 of the second embodiment is schematically shown. Figure 28 The main features shown are the first pin junction 30, the third pin junction 50, and the diode pair region 60. Figure 29 The main features shown are the first pin junction 30, the second pin junction 40, and the diode pair region 60. Figure 30 schematically shown Figure 28 The first pin junction 30 and its surrounding enlarged structure. Figure 31 It is a graph showing the relationship between the position of the first pin junction 30 in the Z direction and the impurity concentration. Figure 32 and Figure 33 A cross-sectional view of an example of the manufacturing process of the TVS diode 10 according to the second embodiment is shown schematically.

[0222] like Figure 28As shown, the first pin junction 30 includes a p-shaped first buffer region 35. The first buffer region 35 is disposed between a first terminal-side high-concentration region 31 and a first terminal-side low-concentration region 32 in the Z direction. The first buffer region 35 is connected to the first terminal-side high-concentration region 31. The first buffer region 35 is connected to the first terminal-side low-concentration region 32. The first defined region 34 is provided to surround the first buffer region 35 when viewed from above. In the second embodiment, the first pin junction 30 is constructed by a first terminal-side contact region 33, a first terminal-side low-concentration region 32, and a first buffer region 35. That is, the first terminal-side contact region 33 constitutes an N-layer, the first terminal-side low-concentration region 32 constitutes an I-layer, and the first buffer region 35 constitutes a P-layer.

[0223] like Figure 29 As shown, the second pin junction 40 includes a p-shaped second buffer region 45. The second buffer region 45 is disposed between the second terminal-side high-concentration region 41 and the second terminal-side low-concentration region 42 in the Z direction. The second buffer region 45 is in contact with the second terminal-side high-concentration region 41. The second buffer region 45 is in contact with the second terminal-side low-concentration region 42. The second defined region 44 is provided to surround the second buffer region 45 when viewed from above. In the second embodiment, the second pin junction 40 is constructed by the second terminal-side contact region 43, the second terminal-side low-concentration region 42, and the second buffer region 45. That is, the second terminal-side contact region 43 constitutes an N-layer, the second terminal-side low-concentration region 42 constitutes an I-layer, and the second buffer region 45 constitutes a P-layer.

[0224] like Figure 28 As shown, the third pin junction 50 includes a p-type third buffer region 55. The third buffer region 55 is disposed between the third terminal-side high-concentration region 51 and the third terminal-side low-concentration region 52 in the Z direction. The third buffer region 55 is connected to the third terminal-side high-concentration region 51. The third buffer region 55 is connected to the third terminal-side low-concentration region 52. The third delineated region 54 is provided to surround the third buffer region 55 when viewed from above. In the second embodiment, the third pin junction 50 is constructed by the third terminal-side contact region 53, the third terminal-side low-concentration region 52, and the third buffer region 55. That is, the third terminal-side contact region 53 constitutes an N-layer, the third terminal-side low-concentration region 52 constitutes an I-layer, and the third buffer region 55 constitutes a P-layer.

[0225] Furthermore, the first pin 30, the second pin 40, and the third pin 50 have the same structure. Therefore, the first pin 30 will be described in detail below, while the detailed descriptions of the second pin 40 and the third pin 50 will be omitted.

[0226] like Figure 30As shown, the first buffer region 35 is disposed at the boundary between the second semiconductor layer 24 and the third semiconductor layer 25. That is, the boundary between the first buffer region 35 and the first terminal-side high-concentration region 31 is located in the second semiconductor layer 24 in the Z direction. Therefore, the thickness of the first terminal-side high-concentration region 31 is greater than the thickness of the first terminal-side high-concentration region 31 in the first embodiment (see reference). Figure 2 )Thin.

[0227] The boundary between the first buffer region 35 and the first terminal-side low-concentration region 32 is located closer to the first surface 20S of the semiconductor chip 20 than the boundary between the high-concentration region 61 and the first low-concentration region 62A in the diode pair region 60. Therefore, the thickness of the first terminal-side low-concentration region 32 is greater than the thickness of the first terminal-side low-concentration region 32 in the first embodiment (refer to...). Figure 2 Thin. In one example, the thickness of the first terminal-side low-concentration region 32 is thinner than the thickness of the first low-concentration region 62A. The thickness of the first terminal-side low-concentration region 32 is thinner than the thickness of the first buffer region 35.

[0228] like Figure 31 As shown, the concentration of p-type impurities in the first buffer region 35 can be set to 1×10⁻⁶. 14 cm -3 Above and 5×10 17 cm -3 The p-type impurity concentration in the first buffer region 35 has a concentration gradient in the Z direction that decreases from the high-concentration region 31 on the first terminal side towards the low-concentration region 32 on the first terminal side. Therefore, the p-type impurity concentration in the first buffer region 35 reaches its maximum at the boundary between the first buffer region 35 and the high-concentration region 31 on the first terminal side, and its minimum at the boundary between the first buffer region 35 and the low-concentration region 32 on the first terminal side. Thus, the first buffer region 35 has a lower p-type impurity concentration than the p-type impurity concentration in the high-concentration region 31 on the first terminal side. Furthermore, the p-type impurity concentration in the first buffer region 35 can be equal to the n-type impurity concentration in the low-concentration region 32 on the first terminal side at the boundary between the first buffer region 35 and the low-concentration region 32 on the first terminal side. In one example, the p-type impurity concentration at the boundary between the first buffer region 35 and the low-concentration region 32 on the first terminal side can be set to 1 × 10⁻⁶. 14 cm -3 .like Figure 31 As shown, the concentration of p-type impurities in the first buffer region 35 is higher than the concentration of n-type impurities in the low-concentration region 32 on the first terminal side.

[0229] Furthermore, the p-type impurity concentrations of the second buffer region 45 and the third buffer region 55 have the same concentration gradient as the p-type impurity concentration of the first buffer region 35. Therefore, the second buffer region 45 has a lower p-type impurity concentration than the p-type impurity concentration of the high-concentration region 41 on the second terminal side. The p-type impurity concentration of the second buffer region 45 has a concentration gradient in the Z direction that decreases from the high-concentration region 41 on the second terminal side towards the low-concentration region 42 on the second terminal side. The p-type impurity concentration of the second buffer region 45 is greater than or equal to the n-type impurity concentration of the low-concentration region 42 on the second terminal side. The third buffer region 55 has a lower p-type impurity concentration than the p-type impurity concentration of the high-concentration region 51 on the third terminal side. The p-type impurity concentration of the third buffer region 55 has a concentration gradient in the Z direction that decreases from the high-concentration region 51 on the third terminal side towards the low-concentration region 52 on the third terminal side. The p-type impurity concentration of the third buffer region 55 is greater than or equal to the n-type impurity concentration of the low-concentration region 52 on the third terminal side.

[0230] (Manufacturing method of TVS diode) An example of the manufacturing method of the TVS diode 10 according to the second embodiment will be described. In the second embodiment, the difference from the first embodiment is the addition of a step for forming the first buffer region 35, the second buffer region 45, and the third buffer region 55. This step will be described below.

[0231] The processes for forming the first buffer region 35, the second buffer region 45, and the third buffer region 55 are performed after the separation region 65, the first terminal-side contact region 33, the second terminal-side contact region 43, and the third terminal-side contact region 53 have been formed. The process for forming the first buffer region 35 will be described below.

[0232] Figure 32 and Figure 33 The diagram shows a cross-sectional view of the process following the formation of the first terminal-side contact region 33, the second terminal-side contact region 43, and the third terminal-side contact region 53. Additionally, in... Figure 32 and Figure 33 The second pin junction 40 is not illustrated. Please refer to [link / reference needed] for details on the second pin junction 40. Figure 29 .

[0233] like Figure 32 As shown, due to the n-type impurities forming the separation region 65, the first terminal-side contact region 33, the second terminal-side contact region 43, and the third terminal-side contact region 53, a self-doped layer 36 is formed at the end of the low-concentration region 32 on the first terminal side, biased towards the high-concentration region 31 on the first terminal side. Figure 31As shown, the n-type impurity concentration of the self-doped layer 36 becomes higher than that of the low-concentration region 32 on the first terminal side. In one example, the peak value of the n-type impurity concentration of the self-doped layer 36 is 1 × 10⁻⁶. 16 cm -3 about.

[0234] like Figure 33 As shown, in the process of forming the first buffer region 35, p-type impurities are implanted into the high-concentration region 31 on the first terminal side using ion implantation, for example, an ion implantation mask 970. Here, the p-type impurities are implanted into the self-doped layer 36 by adjusting the implantation energy (the accelerating voltage of the ions). Thus, the first buffer region 35 is formed in the self-doped layer 36. Furthermore, the processes for forming the second buffer region 45 and the third buffer region 55 are the same as those for forming the first buffer region 35, and therefore their description is omitted.

[0235] (effect) Reference Figure 31 and Figure 32 The operation of the TVS diode 10 in the second embodiment will be explained. Hereinafter, although the explanation focuses on the first pin junction 30, the same applies to the second pin junction 40 and the third pin junction 50.

[0236] like Figure 31 and Figure 32 As shown, the self-doped layer 36 formed during the manufacturing process of the TVS diode 10 has a higher n-type impurity concentration than the n-type impurity concentration of the low-concentration region 32 on the first terminal side. Therefore, the junction capacitance of the self-doped layer 36 and the high-concentration region 31 on the first terminal side in the first pin junction 30 is larger than the junction capacitance of the low-concentration region 32 and the high-concentration region 31 on the first terminal side.

[0237] Therefore, in the TVS diode 10 of the second embodiment, the p-type first buffer region 35 is disposed between the high-concentration region 31 and the low-concentration region 32 on the first terminal side. As a result, the n-type impurities in the self-doped layer 36 are canceled out by the p-type impurities in the first buffer region 35. Therefore, in the first pin junction 30, instead of the junction between the self-doped layer 36 and the high-concentration region 31 on the first terminal side, it becomes the junction between the first buffer region 35 and the low-concentration region 32 on the first terminal side. Thus, there is no longer a region with a high concentration of n-type impurities in the low-concentration region 32 on the first terminal side, thereby suppressing the increase in the junction capacitance of the first pin junction 30.

[0238] (Effect) The TVS diode 10 according to the second embodiment can achieve the following effects. (2-1) The TVS diode 10 includes a semiconductor chip 20 having a first surface 20S and a second surface 20R located on the side opposite to the first surface 20S. The semiconductor chip 20 includes: a first pin junction 30 in a first polarity direction disposed in a region of the semiconductor chip 20 biased toward the first surface 20S; a diode pair region 60 including a first reverse pin junction 60A in a second polarity direction disposed separated from the first pin junction 30 when viewed from above in the thickness direction of the semiconductor chip 20, and a pn junction 60E in a first polarity direction forming a diode pair with the first reverse pin junction 60A; and a p-type first terminal side high-concentration region 31, which is biased toward the second surface 20R and adjacent to the first surface 20S of the semiconductor chip 20. A first terminal-side low-concentration region 32 of type n is disposed in a region offset from the first terminal-side high-concentration region 31 on the first surface 20S, overlapping the first terminal-side high-concentration region 31 when viewed from above; a first terminal-side contact region 33 of type n is disposed on the surface of the first terminal-side low-concentration region 32; and a first buffer region 35 of type p is disposed between the first terminal-side high-concentration region 31 and the first terminal-side low-concentration region 32 in the thickness direction of the semiconductor chip 20 and is in contact with the first terminal-side high-concentration region 31. A pin diode is constructed using the first terminal-side contact region 33, the first terminal-side low-concentration region 32, and the first buffer region 35.

[0239] According to this structure, even if a region with a high concentration of n-type impurities is formed in the low-concentration region 32 on the first terminal side, near the high-concentration region 31 on the first terminal side, during the manufacturing process of the TVS diode 10, the region with a high concentration of n-type impurities can be eliminated by the first buffer region 35. Therefore, the increase in the junction capacitance in the first pin junction 30 can be suppressed.

[0240] (2-2) The first buffer region 35 has a lower p-type impurity concentration than the high-concentration region 31 on the first terminal side. According to this structure, the junction capacitance between the first buffer region 35 and the low-concentration region 32 on the first terminal side can be reduced, thus enabling a reduction in the junction capacitance of the first pin junction 30.

[0241] (2-3) The p-type impurity concentration in the first buffer region 35 decreases in the thickness direction of the semiconductor chip 20 as it moves from the high concentration region 31 on the first terminal side toward the low concentration region 32 on the first terminal side.

[0242] According to this structure, the p-type impurity concentration in the first buffer region 35 is minimized at the boundary between the first buffer region 35 and the low-concentration region 32 on the first terminal side. Therefore, the junction capacitance between the first buffer region 35 and the low-concentration region 32 on the first terminal side can be reduced, thereby achieving a reduction in the junction capacitance of the first pin junction 30.

[0243] (2-4) The semiconductor chip 20 includes: a second pin junction 40 in a first polarity direction, disposed in a region of the semiconductor chip 20 that is biased toward the first surface 20S and separated from the first pin junction 30 when viewed from above; a p-type second terminal side high-concentration region 41, disposed in a position that is biased toward the second surface 20R and separated from the first surface 20S of the semiconductor chip 20, and separated from the first terminal side high-concentration region 31 when viewed from above; an n-type second terminal side low-concentration region 42, disposed in a region that is biased toward the first surface 20S than the second terminal side high-concentration region 41 and overlapped with the second terminal side high-concentration region 41 when viewed from above; an n-type second terminal side contact region 43, disposed on the surface portion of the second terminal side low-concentration region 42; and a p-type second buffer region 45, disposed between the second terminal side high-concentration region 41 and the second terminal side low-concentration region 42 in the thickness direction of the semiconductor chip 20 and connected to the second terminal side high-concentration region 41. The second pin junction 40 is formed by the second buffer region 45, the second terminal side low concentration region 42, and the second terminal side contact region 43.

[0244] According to this structure, even if a region with a high concentration of n-type impurities is formed in the low-concentration region 42 on the second terminal side, near the high-concentration region 41 on the second terminal side, during the manufacturing process of the TVS diode 10, the region with a high concentration of n-type impurities can be eliminated by the second buffer region 45. Therefore, the increase in the junction capacitance in the second pin junction 40 can be suppressed.

[0245] (2-5) The second buffer region 45 has a lower p-type impurity concentration than the high-concentration region 41 on the second terminal side. According to this structure, the junction capacitance between the second buffer region 45 and the low-concentration region 42 on the second terminal side can be reduced, thus enabling a reduction in the junction capacitance of the second pin junction 40.

[0246] (2-6) The p-type impurity concentration in the second buffer region 45 decreases in the thickness direction of the semiconductor chip 20 as it moves from the high concentration region 41 on the second terminal side toward the low concentration region 42 on the second terminal side.

[0247] According to this structure, the p-type impurity concentration in the second buffer region 45 is minimized at the boundary between the second buffer region 45 and the low-concentration region 42 on the second terminal side. Therefore, the junction capacitance between the second buffer region 45 and the low-concentration region 42 on the second terminal side can be reduced, thereby achieving a reduction in the junction capacitance of the second pin junction 40.

[0248] (2-7) The semiconductor chip 20 includes: a third pin junction 50 in a first polarity direction, disposed in a region of the semiconductor chip 20 biased towards the first surface 20S, and separated from the first pin junction 30 and the second pin junction 40 when viewed from above; and a p-type third terminal side high-concentration region 51, disposed in a position separated from the first surface 20S of the semiconductor chip 20 biased towards the second surface 20R, and separated from the first terminal side high-concentration region 31 and the second terminal side high-concentration region 41 when viewed from above. The semiconductor chip 20 comprises: an n-type third terminal-side low-concentration region 52, disposed in a region offset from the third terminal-side high-concentration region 51 to the first surface 20S, overlapping the third terminal-side high-concentration region 51 when viewed from above; an n-type third terminal-side contact region 53, disposed on the surface portion of the third terminal-side low-concentration region 52; and a p-type third buffer region 55, disposed between the third terminal-side high-concentration region 51 and the third terminal-side low-concentration region 52 in the thickness direction of the semiconductor chip 20 and in contact with the third terminal-side high-concentration region 51. The third pin junction 50 is formed by the third buffer region 55, the third terminal-side low-concentration region 52, and the third terminal-side contact region 53.

[0249] According to this structure, even if a region with a high concentration of n-type impurities is formed in the low-concentration region 52 on the third terminal side, near the high-concentration region 51 on the third terminal side, during the manufacturing process of the TVS diode 10, the region with a high concentration of n-type impurities can be eliminated by the third buffer region 55. Therefore, the increase in the junction capacitance in the third pin junction 50 can be suppressed.

[0250] (2-8) The third buffer region 55 has a lower p-type impurity concentration than the high-concentration region 51 on the third terminal side. According to this structure, the junction capacitance between the third buffer region 55 and the low-concentration region 52 on the third terminal side can be reduced, thus enabling a reduction in the junction capacitance of the third pin junction 50.

[0251] (2-9) The concentration of p-type impurities in the third buffer region 55 decreases in the thickness direction of the semiconductor chip 20 as it moves from the high concentration region 51 on the third terminal side toward the low concentration region 52 on the third terminal side.

[0252] According to this structure, the p-type impurity concentration of the third buffer region 55 is minimized at the boundary between the third buffer region 55 and the low-concentration region 52 on the third terminal side. Therefore, the junction capacitance between the third buffer region 55 and the low-concentration region 52 on the third terminal side can be reduced, thereby achieving a reduction in the junction capacitance of the third pin junction 50.

[0253] (Third implementation method) Reference Figures 34-39The TVS diode 10 according to the third embodiment will be described. The main difference between the TVS diode 10 of the third embodiment and the TVS diode 10 of the first embodiment lies in the structure of the first pin junction 30, the second pin junction 40, and the third pin junction 50. Hereinafter, the same reference numerals will be used to denote the components common to the first embodiment, and their descriptions will be omitted.

[0254] Figure 34 The top view of the semiconductor chip 20 in the TVS diode 10 of the third embodiment is shown schematically. Figure 35 Schematic illustration of the use Figure 34 The cross-sectional structure obtained by cutting the TVS diode 10 along the F35-F35 line. Figure 36 Schematic illustration of the use Figure 34 The cross-sectional structure obtained by cutting the TVS diode 10 along the F36-F36 line. Figures 37-39 A cross-sectional view of an example of the manufacturing process of the TVS diode 10 according to the third embodiment is shown schematically.

[0255] like Figure 34 and Figure 35 As shown, the first pin junction 30 includes a first separation trench configuration 120A to replace the first defined region 34 (see reference). Figure 2 The first separation trench configuration 120A is configured, for example, in such a way that the first pin junction 30 is separated from the diode pair region 60.

[0256] The first separation trench structure 120A includes a first separation trench 121A, a first separation insulating layer 122A, and a first separation electrode 123A. The first separation trench 121A, when viewed from above, is formed as an annular shape surrounding the high-concentration region 31 on the first terminal side. In one example, the first separation trench 121A is formed as a square annular shape when viewed from above. The first separation trench 121A is constructed by excavating from the first surface 20S of the semiconductor chip 20 toward the second surface 20R. The first separation trench 121A penetrates the third semiconductor layer 25 and the second semiconductor layer 24 and reaches the first semiconductor layer 23. In one example, the bottom wall of the first separation trench 121A is located in the Z direction closer to the second surface 20R of the semiconductor chip 20 than the boundary between the high-concentration region 31 on the first terminal side and the first semiconductor layer 23. Therefore, the bottom wall of the first separation trench 121A exposes the first semiconductor layer 23.

[0257] The first separation trench 121A includes an inner peripheral wall and an outer peripheral wall. The inner peripheral wall of the first separation trench 121A exposes the low-concentration region 32 and the high-concentration region 31 on the first terminal side. The outer peripheral wall of the first separation trench 121A exposes the first to third semiconductor layers 23 to 25. Thus, the first separation trench 121A separates the low-concentration region 32 and the high-concentration region 31 on the first terminal side from the second semiconductor layer 24 and the third semiconductor layer 25.

[0258] The inner and outer peripheral walls of the first separation trench 121A can be arranged perpendicularly to the first surface 20S of the semiconductor chip 20. In addition, the inner and outer peripheral walls of the first separation trench 121A can be formed into a tapered shape that gradually tapers from the first surface 20S toward the bottom wall.

[0259] The width of the first separation groove 121A can be set to be 0.1 μm or more and 3 μm or less. In one example, the width of the first separation groove 121A is 1.5 μm or more and 2.5 μm or less. Here, the width of the first separation groove 121A can be defined by the distance between the inner and outer peripheral walls in a direction orthogonal to the direction in which the first separation groove 121A extends, as viewed from above.

[0260] The depth of the first separation trench 121A can be set to be 1 μm or more and 50 μm or less. In one example, the depth of the first separation trench 121A is 15 μm or more and 35 μm or less. Here, the depth of the first separation trench 121A can be defined by the distance between the first surface 20S of the semiconductor chip 20 in the Z direction and the bottom surface of the first separation trench 121A.

[0261] A first separation insulating layer 122A is disposed within a first separation trench 121A. More specifically, the first separation insulating layer 122A is formed as a film along the inner wall of the first separation trench 121A. Thus, the first separation insulating layer 122A defines a recessed space within the first separation trench 121A.

[0262] The first separating insulating layer 122A may comprise at least one of a SiO2 layer and a SiN layer. The first separating insulating layer 122A may have a laminated structure formed by stacking the SiO2 layer and the SiN layer in any order. The first separating insulating layer 122A may have a single-layer structure composed of either a SiO2 layer or a SiN layer. The first separating insulating layer 122A may be made of the same insulating material as the first insulating layer 71. In one example, the first separating insulating layer 122A has a single-layer structure composed of a SiO2 layer.

[0263] The first separation electrode 123A is embedded in the first separation trench 121A through the first separation insulating layer 122A. When viewed from above, the first separation electrode 123A is formed as a ring surrounding the high-concentration region 31 on the first terminal side. In one example, the first separation electrode 123A is formed as a square ring when viewed from above. The first separation electrode 123A is, for example, made of polysilicon. The first separation electrode 123A is in an electrically floating state.

[0264] like Figure 34 and Figure 36 As shown, the second pin junction 40 includes a second separation trench configuration 120B to replace the second defined region 44 (see reference). Figure 3 The second separation trench structure 120B is configured, for example, to demarcate the second pin junction 40 from the diode pair region 60. The second separation trench structure 120B includes a second separation trench 121B, a second separation insulating layer 122B, and a second separation electrode 123B. The second separation trench 121B is disposed on the first surface 20S of the semiconductor chip 20 such that the second pin junction 40 is demarcated from the diode pair region 60. The second separation insulating layer 122B is disposed within the second separation trench 121B. The second separation electrode 123B is embedded in the second separation trench 121B through the second separation insulating layer 122B. The second separation electrode 123B is in an electrically floating state. Furthermore, since the structures of the second separation trench 121B, the second separation insulating layer 122B, and the second separation electrode 123B are the same as those of the first separation trench 121A, the first separation insulating layer 122A, and the first separation electrode 123A, detailed descriptions of these structures are omitted.

[0265] like Figure 34 and Figure 35 As shown, the third pin junction 50 includes a third separation trench structure 120C to replace the third defined region 54 (see reference). Figure 2 The third separation trench structure 120C is configured, for example, to demarcate the third pin junction 50 from the diode pair region 60. The third separation trench structure 120C includes a third separation trench 121C, a third separation insulating layer 122C, and a third separation electrode 123C. The third separation trench 121C is disposed on the first surface 20S of the semiconductor chip 20 such that the third pin junction 50 is demarcated from the diode pair region 60. The third separation insulating layer 122C is disposed within the third separation trench 121C. The third separation electrode 123C is embedded in the third separation trench 121C through the third separation insulating layer 122C. The third separation electrode 123C is in an electrically floating state. Since the structures of the third separation trench 121C, the third separation insulating layer 122C, and the third separation electrode 123C are the same as those of the first separation trench 121A, the first separation insulating layer 122A, and the first separation electrode 123A, their description is omitted.

[0266] (Manufacturing method of TVS diode) An example of a manufacturing method for the TVS diode 10 according to the third embodiment will be described. The main difference between the manufacturing method of the TVS diode 10 in the third embodiment and the first embodiment is that the process for forming the first defined region 34, the second defined region 44, and the third defined region 54 is replaced by a process for forming the first separation trench structure 120A, the second separation trench structure 120B, and the third separation trench structure 120C. This process will be described below.

[0267] Figures 37-39 The process for forming the first separation trench structure 120A and the third separation trench structure 120C is shown. Additionally, although not shown, the second separation trench structure 120B is formed in the same manner as the first separation trench structure 120A and the third separation trench structure 120C.

[0268] like Figure 37 As shown, this process includes forming a first separation trench 121A and a third separation trench 121C. More specifically, firstly, a hard mask (not shown) with a predetermined pattern is formed on the first surface 20S of the semiconductor chip 20. The hard mask exposes the areas in the first surface 20S where the separation trenches 121A, 121B, and 121C are to be formed and covers the remaining areas. The hard mask can be formed by CVD or oxidation. The patterning of the hard mask can be performed by an etching method using an etching mask. Next, the areas exposed from the hard mask in the first surface 20S of the semiconductor chip 20 are removed by an etching method using the hard mask. The etching method can be a dry etching method. An example of a dry etching method can be RIE (Reactive Ion Etching). Thus, the first separation trench 121A, the second separation trench 121B, and the third separation trench 121C are formed. Afterward, the hard mask is removed.

[0269] like Figure 38 As shown, the process for forming the first separation trench structure 120A and the third separation trench structure 120C includes forming an insulating layer 870. The insulating layer 870 is formed as a film along the first surface 20S of the semiconductor chip 20 and the inner walls of each separation trench 121A, 121B, 121C. The insulating layer 870 constitutes the first separation insulating layer 122A and the third separation insulating layer 122C. Additionally, although not shown, the insulating layer 870 constitutes the second separation insulating layer 122B. The insulating layer 870 can be formed by CVD or an oxidation process (e.g., thermal oxidation). In one example, the insulating layer 870 is formed by thermal oxidation.

[0270] like Figure 39As shown, the process for forming the first separation trench structure 120A and the third separation trench structure 120C includes forming a first separation electrode 123A and a third separation electrode 123C. In this process, an electrode layer 880 is first formed on an insulating layer 870. The electrode layer 880 is the layer constituting the first separation electrode 123A and the third separation electrode 123C. Additionally, although not shown, a single electrode layer 880 is the layer constituting the second separation electrode 123B. The electrode layer 880 is, for example, made of polysilicon. The electrode layer 880 is embedded in each of the separation trenches 121A, 121B, and 121C, separated by the insulating layer 870. The electrode layer 880 can be formed, for example, by a CVD method.

[0271] Next, although not shown, unwanted portions of the electrode layer 880 are removed by etching. The portion of the electrode layer 880 other than those embedded in the separation trenches 121A and 121C is removed. The electrode layer 880 is removed until the insulating layer 870 is exposed. This forms the first separation electrode 123A and the third separation electrode 123C. Through the above processes, the first separation trench structure 120A and the third separation trench structure 120C are formed. Furthermore, by removing the portion of the electrode layer 880 other than those embedded in the second separation trench 121B, the second separation electrode 123B is formed. This forms the second separation trench structure 120B.

[0272] Subsequently, although not illustrated, a process for forming the insulating layer 850 is performed. The first insulating layer 851 of the insulating layer 850 covers the first separation trench structure 120A, the second separation trench structure 120B, and the third separation trench structure 120C. Therefore, each separation electrode 123A, 123B, and 123C is covered by the insulating layer 870 and the first insulating layer 851, respectively.

[0273] (Effect) The TVS diode 10 according to the third embodiment can achieve the following effects. (3-1) The semiconductor chip 20 includes: a first separation trench 121A disposed on a first surface 20S such that a first pin junction 30 is demarcated from the diode pair region 60; and a second separation trench 121B disposed on the first surface 20S such that a second pin junction 40 is demarcated from the diode pair region 60. The TVS diode 10 includes a first separation insulating layer 122A disposed in the first separation trench 121A and a second separation insulating layer 122B disposed in the second separation trench 121B.

[0274] According to this structure, the insulation between the first pin junction 30 and the diode pair region 60, and the insulation between the second pin junction 40 and the diode pair region 60, can be improved respectively. This allows for a reduction in the distance between the first pin junction 30 and the second pin junction 40 and the diode pair region 60. Therefore, if the chip size is the same, the area of ​​the diode pair region 60 viewed from above can be increased, thus improving surge absorption performance. On the other hand, if the area of ​​the diode pair region 60 viewed from above is the same, miniaturization of the TVS diode 10 can be achieved corresponding to the reduction in the distance between the first pin junction 30 and the second pin junction 40 and the diode pair region 60.

[0275] (Fourth Implementation) Reference Figures 40-43 The TVS diode 10 according to the fourth embodiment will be described. The main difference between the TVS diode 10 of the fourth embodiment and the TVS diode 10 of the first embodiment lies in the top view structure of the TVS diode 10. Hereinafter, the same reference numerals will be used to label the components common to the first embodiment, and their descriptions will be omitted.

[0276] Figure 40 The top view of the semiconductor chip 20 in the TVS diode 10 of the fourth embodiment is shown schematically. Figure 41 The diagram schematically shows the top view of the first to third connecting electrodes 81 to 83 and wiring 90 of the TVS diode 10. Figure 42 Schematic illustration of the use Figure 40 The cross-sectional structure obtained by cutting the TVS diode 10 along the F42-F42 line. Figure 43 The top view of the TVS diode 10 is shown schematically.

[0277] like Figure 40 As shown, in the TVS diode 10 of the fourth embodiment, the first pin junction 30, the second pin junction 40, and the third pin junction 50 are arranged along the Y direction with the diode pair region 60. The first pin junction 30, the second pin junction 40, and the third pin junction 50 are positioned relative to the fourth side 20D of the diode pair region 60 when viewed from above. In other words, the diode pair region 60 is positioned relative to the third side 20C of the first pin junction 30, the second pin junction 40, and the third pin junction 50 when viewed from above.

[0278] The first pin 30, the second pin 40, and the third pin 50 are arranged along the X direction. More specifically, the first pin 30, the second pin 40, and the third pin 50 are located at the same position in the Y direction and are spaced apart from each other in the X direction. Figure 42As shown, the cross-sectional structures of the first pin junction 30, the second pin junction 40, and the third pin junction 50 are the same as in the first embodiment. Furthermore, the defined region between the first terminal-side low-concentration region 32 and the second terminal-side low-concentration region 42 constitutes the first defined region 34 and the second defined region 44. The defined region between the second terminal-side low-concentration region 42 and the third terminal-side low-concentration region 52 constitutes the second defined region 44 and the third defined region 54.

[0279] like Figure 40 As shown, the diode pair region 60 is rectangular in shape when viewed from above. In one example, the diode pair region 60 is formed as a rectangle with the X direction (the arrangement direction of the first pin junction 30, the second pin junction 40, and the third pin junction 50) as its length and the Y direction as its width. A first reverse pin junction 60A, a second reverse pin junction 60B, and a third reverse pin junction 60C are provided in the diode pair region 60. Each of the reverse pin junctions 60A, 60B, and 60C is positioned to overlap with the high-concentration region 61 when viewed from above.

[0280] The first reverse pin 60A, the second reverse pin 60B, and the third reverse pin 60C are arranged separately from each other in the X direction. The first reverse pin 60A is positioned to overlap with the first pin 30 when viewed from the Y direction. The second reverse pin 60B is positioned to overlap with the second pin 40 when viewed from the Y direction. The third pin 50 is positioned to overlap with the third pin 50 when viewed from the Y direction. Figure 42 As shown, the cross-sectional structure of each reverse pin junction 60A, 60B, and 60C is the same as that of the first embodiment.

[0281] like Figure 40 As shown, the separation region 65 is configured to surround the first low-concentration region 62A, the second low-concentration region 62B, and the third low-concentration region 62C. Similar to the first embodiment, the separation region 65 includes the first to third separation regions 65A to 65C and the wiring connection region 65P. The first separation region 65A is located within the separation region 65 between the first contact region 63A and the first terminal-side contact region 33 in the Y direction. The second separation region 65B is located within the separation region 65 between the second contact region 63B and the second terminal-side contact region 43 in the Y direction. The third separation region 65C is located within the separation region 65 between the third contact region 63C and the third terminal-side contact region 53 in the Y direction. In top view, the wiring connection region 65P is configured to independently and partially surround each of the reverse pin junctions 60A, 60B, and 60C.

[0282] like Figure 40As shown by the dashed lines, the outer edge of the inner region 64 is located further inward than the outer edge of the high-concentration region 61 when viewed from above. In one example, the inner region 64 is formed into a rectangular shape that is slightly smaller than the high-concentration region 61 (diode pair region 60) when viewed from above. Therefore, the inner region 64 is arranged to overlap with each of the reverse pin junctions 60A, 60B, and 60C when viewed from above. More specifically, the inner region 64 is arranged to overlap with the first low-concentration region 62A, the second low-concentration region 62B, and the third low-concentration region 62C when viewed from above. Figure 42 As shown, the cross-sectional structure of the pn junction 60E is the same as that of the first embodiment.

[0283] like Figure 41 As shown, the first connecting electrode 81, like in the first embodiment, includes a pin connection portion 81A, a wiring portion 81B, and a reverse pin connection portion 81C. In one example, the pin connection portion 81A, when viewed from above, is formed in a rectangular shape covering the entire area of ​​the first terminal-side contact region 33. The wiring portion 81B, when viewed from above, extends along the Y direction from the pin connection portion 81A toward the third side surface 20C. The wiring portion 81B is connected to the pin connection portion 81A in the X direction at a location relative to the center of the pin connection portion 81A, biased towards the second side surface 20B. In one example, the reverse pin connection portion 81C, when viewed from above, covers the entire area of ​​the first contact region 63A.

[0284] The second connecting electrode 82, like in the first embodiment, includes a pin connection portion 82A, a wiring portion 82B, and a reverse pin connection portion 82C. The wiring portion 82B extends from the pin connection portion 82A toward the third side surface 20C along the Y direction. In one example, the center of the wiring portion 82B in the X direction is at the same position as the center of the pin connection portion 82A. In one example, the reverse pin connection portion 82C covers the entire area of ​​the second contact region 63B when viewed from above.

[0285] The third connecting electrode 83, like in the first embodiment, includes a pin connection portion 83A, a wiring portion 83B, and a reverse pin connection portion 83C. The wiring portion 83B extends from the pin connection portion 83A toward the third side surface 20C along the Y direction. In one example, the wiring portion 83B is connected to the pin connection portion 83A in the X direction at a position relative to the center of the pin connection portion 83A, closer to the first side surface 20A. In one example, the reverse pin connection portion 83C covers the entire area of ​​the third contact region 63C when viewed from above.

[0286] The wiring 90, when viewed from above, has a comb-like shape. Like the first embodiment, the wiring 90 includes a first recess 96A, a second recess 96B, and a third recess 96C. Each recess 96A to 96C opens towards the fourth side surface 20D in the Y direction. Furthermore, the wiring 90 includes first to fourth teeth 97A to 97D and a connecting portion 97E. The first to fourth teeth 97A to 97D are arranged separately from each other in the X direction when viewed from above. The connecting portion 97E is positioned closer to the third side surface 20C than the first to fourth teeth 97A to 97D. The connecting portion 97E connects the first to fourth teeth 97A to 97D. The first to fourth teeth 97A to 97D are arranged sequentially from the first side surface 20A towards the second side surface 20B. The first to fourth teeth 97A to 97D extend along the Y direction from the connecting portion 97E towards the fourth side surface 20D. The first recess 96A is composed of a first tooth 97A, a second tooth 97B, and a connecting portion 97E. The second recess 96B is composed of a second tooth 97B, a third tooth 97C, and a connecting portion 97E. The third recess 96C is composed of a third tooth 97C, a fourth tooth 97D, and a connecting portion 97E.

[0287] A wiring portion 81B for a first connecting electrode 81 is disposed within a first recess 96A. A wiring portion 82B for a second connecting electrode 82 is disposed within a second recess 96B. A wiring portion 83B for a third connecting electrode 83 is disposed within a third recess 96C. Thus, the wiring 90, when viewed from above, is arranged in a manner that independently and partially surrounds the first connecting electrode 81, the second connecting electrode 82, and the third connecting electrode 83.

[0288] like Figure 43 As shown, in the fourth embodiment, the first to third terminal openings 77A to 77C of the TVS diode 10 are located at the same position in the Y direction and are spaced apart from each other in the X direction. When viewed from above, the first to third terminal openings 77A to 77C are positioned closer to the fourth side 20D than the third side 20C. The first terminal opening 77A is located in the contact area 33 with the first terminal side when viewed from above (see reference 1). Figure 40 The second terminal opening 77B is positioned at the overlapping location. When viewed from above, it is located in the contact area 43 with the second terminal side (see reference). Figure 40 The third terminal opening 77C is positioned to overlap with the third terminal side contact area 53 when viewed from above. Furthermore, the TVS diode 10 according to the fourth embodiment achieves the same effect as the first embodiment.

[0289] (Fifth Implementation) Reference Figures 44-46The TVS diode 10 according to the fifth embodiment will be described. The main difference between the TVS diode 10 of the fifth embodiment and the TVS diode 10 of the first embodiment lies in the top view structure of the TVS diode 10. Hereinafter, the same reference numerals will be used to label the components common to the first embodiment, and their descriptions will be omitted.

[0290] Figure 44 The top view of the semiconductor chip 20 in the TVS diode 10 of the fifth embodiment is shown schematically. Figure 45 The diagram schematically shows the top view of the first to third connecting electrodes 81 to 83 and wiring 90 of the TVS diode 10. Figure 46 The top view of the TVS diode 10 is shown schematically.

[0291] like Figure 44 As shown, the TVS diode 10 of the fifth embodiment includes a first pin junction 30, a second pin junction 40, a first reverse pin junction 60A, a second reverse pin junction 60B, and a pn junction 60E. In other words, the TVS diode 10 of the fifth embodiment omits the third pin junction 50 and the third reverse pin junction 60C (both referred to in the first embodiment). Figure 2 The resulting structure. In addition, although not shown, the cross-sectional structure of the first pin junction 30 and the second pin junction 40 is the same as that of the first embodiment.

[0292] The diode pair region 60 (high-concentration region 61) includes a first region 66A, a second region 66B, and a first connection region 67A. In other words, the diode pair region 60 (high-concentration region 61) of the fifth embodiment is a structure obtained by omitting the third region 66C and the second connection region 67B from the first embodiment. Figure 44 As shown by the dashed lines, the outer edge of the inner region 64 is located further inward than the outer edge of the high-concentration region 61 when viewed from above. In one example, the inner region 64 is smaller than the high-concentration region 61 (diode pair region 60) when viewed from above. Therefore, the inner region 64 is arranged to overlap with each of the reverse pin junctions 60A and 60B when viewed from above. More specifically, the inner region 64 is arranged to overlap with the first low-concentration region 62A and the second low-concentration region 62B when viewed from above. The cross-sectional structure of each of the reverse pin junctions 60A and 60B is the same as in the first embodiment.

[0293] like Figure 45As shown, the TVS diode 10 includes a first connecting electrode 81, a second connecting electrode 82, and wiring 90. In other words, the TVS diode 10 of the fifth embodiment is a structure obtained by omitting the third connecting electrode 83 from the first embodiment. Furthermore, the top view of the wiring 90 differs from that of the first embodiment. The structures of the first connecting electrode 81 and the second connecting electrode 82 are the same as those of the first embodiment.

[0294] The wiring 90 includes a first region 91, a second region 92, and a first connecting region 94. Additionally, the wiring 90 includes a first recess 96A and a second recess 96B. In other words, the wiring 90 of the fifth embodiment is a structure obtained by omitting the third region 93, the second connecting region 95, and the third recess 96C from the first embodiment.

[0295] like Figure 46 As shown, the TVS diode 10 of the fifth embodiment includes a first terminal opening 77A that exposes a portion of the first connecting electrode 81 and a second terminal opening 77B that exposes a portion of the second connecting electrode 82. The first terminal opening 77A, when viewed from above, is disposed at a corner of the semiconductor chip 20 adjacent to the first side 20A and the fourth side 20D. The second terminal opening 77B, when viewed from above, is disposed at a corner of the semiconductor chip 20 adjacent to the second side 20B and the fourth side 20D. The first terminal opening 77A is disposed in the contact area 33 with the first terminal side when viewed from above (see reference 33). Figure 44 The second terminal opening 77B is positioned at the overlapping location. When viewed from above, it is located in the contact area 43 with the second terminal side (see reference). Figure 44 The overlapping positions. Furthermore, the TVS diode 10 according to the fifth embodiment can achieve the same effect as the first embodiment.

[0296] (Sixth Implementation Method) Reference Figures 47-49 The TVS diode 10 according to the sixth embodiment will be described. The main difference between the TVS diode 10 of the sixth embodiment and the TVS diode 10 of the first embodiment lies in the top view structure of the TVS diode 10. Hereinafter, the same reference numerals will be used to denote the components common to the first embodiment, and their descriptions will be omitted.

[0297] Figure 47 The top view of the semiconductor chip 20 in the TVS diode 10 of the sixth embodiment is shown schematically. Figure 48 The diagram schematically shows the top view of the first to third connecting electrodes 81 to 83 and wiring 90 of the TVS diode 10. Figure 49 The top view of the TVS diode 10 is shown schematically.

[0298] like Figure 47 As shown, the TVS diode 10 of the sixth embodiment includes a first pin junction 30, a second pin junction 40, a first reverse pin junction 60A, a second reverse pin junction 60B, and a pn junction 60E. In other words, the TVS diode 10 of the third embodiment omits the third pin junction 50 and the third reverse pin junction 60C from the first embodiment (see reference). Figure 2 The resulting structure.

[0299] The first pin junction 30 and the second pin junction 40 are configured to be separated from each other in the Y direction. The diode pair region 60 is configured to be separated from the first pin junction 30 and the second pin junction 40 in the Y direction.

[0300] The first pin junction 30 and the second pin junction 40 are formed into a rectangular shape with the X direction as the length direction and the Y direction (the arrangement direction of the first pin junction 30 and the second pin junction 40) as the width direction. Therefore, the first terminal-side low-concentration region 32 and the second terminal-side low-concentration region 42, when viewed from above, are both formed into a roughly rectangular shape with the X direction as the length direction and the Y direction as the width direction. The first terminal-side contact region 33 and the second terminal-side contact region 43, when viewed from above, are both formed into a roughly rectangular shape with the X direction as the length direction and the Y direction as the width direction. The four corners of each terminal-side low-concentration region 32, 42 and each terminal-side contact region 33, 43 are respectively curved. The cross-sectional structure of the first pin junction 30 and the second pin junction 40 is the same as that in the first embodiment.

[0301] The diode pair region 60 (high-concentration region 61) is rectangular in shape when viewed from above. In one example, the diode pair region 60 (high-concentration region 61) is formed into a rectangle with the X direction as its length direction and the Y direction as its width direction when viewed from above. A first reverse pin junction 60A and a second reverse pin junction 60B are provided in the diode pair region 60. In one example, the first reverse pin junction 60A and the second reverse pin junction 60B are located at the same position in the Y direction and are separated from each other in the X direction. A first low-concentration region 62A and a second low-concentration region 62B are located at the same position in the Y direction and are separated from each other in the X direction. A first contact region 63A and a second contact region 63B are located at the same position in the Y direction and are separated from each other in the X direction. Each low-concentration region 62A, 62B is formed into an approximately elongated oval shape with the X direction (the arrangement direction of the first low-concentration region 62A and the second low-concentration region 62B) as its width direction and the Y direction as its length direction. Each contact area 63A and 63B is formed into an approximate elongated oval shape, with the X direction (the arrangement direction of the first contact area 63A and the second contact area 63B) being the width direction and the Y direction being the length direction.

[0302] like Figure 47 As shown by the dashed lines, the outer edge of the inner region 64 is located further inward than the outer edge of the high-concentration region 61 when viewed from above. In one example, the inner region 64 is formed into a rectangular shape that is slightly smaller than the high-concentration region 61 (diode pair region 60) when viewed from above. Therefore, the inner region 64 is arranged to overlap with each of the reverse pin junctions 60A and 60B when viewed from above. More specifically, the inner region 64 is arranged to overlap with the first low-concentration region 62A and the second low-concentration region 62B when viewed from above. The cross-sectional structure of the pn junction 60E is the same as in the first embodiment.

[0303] like Figure 48 As shown, the TVS diode 10 includes a first connecting electrode 81, a second connecting electrode 82, and wiring 90. In other words, the TVS diode 10 of the third embodiment is a structure obtained by omitting the third connecting electrode 83 from the first embodiment. Furthermore, the top view of the wiring 90 differs from that of the first embodiment.

[0304] The first connecting electrode 81 includes a pin connection portion 81A, a wiring portion 81B, and a reverse pin connection portion 81C. The wiring portion 81B and the reverse pin connection portion 81C are the same as those in the first connecting electrode 81 of the first embodiment. The pin connection portion 81A, when viewed from above, is formed in a generally rectangular shape with the X direction being the length direction and the Y direction being the width direction. When viewed from above, the pin connection portion 81A covers the entire area of ​​the first terminal side contact region 33.

[0305] The second connection electrode 82 includes a pin connection portion 82A, a wiring portion 82B, and a reverse pin connection portion 82C. The wiring portion 82B and the reverse pin connection portion 82C are the same as those in the second connection electrode 82 of the first embodiment. The pin connection portion 82A, when viewed from above, is formed in a generally rectangular shape with the X direction being the length direction and the Y direction being the width direction. When viewed from above, the pin connection portion 82A covers the entire area of ​​the second terminal side contact area 43.

[0306] The wiring 90, when viewed from above, is arranged to independently and partially surround both the first connecting electrode 81 and the second connecting electrode 82. The wiring 90 includes a first recess 96A and a second recess 96B. The first recess 96A, when viewed from above, is arranged to surround the first connecting electrode 81. The second recess 96B, when viewed from above, is arranged to surround the second connecting electrode 82.

[0307] like Figure 49 As shown, in the sixth embodiment, the first terminal opening 77A and the second terminal opening 77B of the TVS diode 10 are located at the same position in the X direction and are separated from each other in the Y direction. The first terminal opening 77A, viewed from above, is located at the end of the semiconductor chip 20 closest to the fourth side 20D in the Y direction. The second terminal opening 77B, viewed from above, is located at the end of the semiconductor chip 20 closest to the third side 20C in the Y direction. The first terminal opening 77A and the second terminal opening 77B, viewed from above, are each formed into a generally elongated oval shape, with the X direction being the length direction and the Y direction being the width direction. The first terminal opening 77A is located in the contact region 33 with the first terminal side (see reference 33). Figure 47 The second terminal opening 77B is located at the overlapping position with the second terminal side contact area 43 (refer to...). Figure 47 The overlapping positions. Furthermore, the TVS diode 10 according to the sixth embodiment can achieve the same effect as the first embodiment.

[0308] (Seventh Implementation) Reference Figures 50-53 The TVS diode 10 according to the seventh embodiment will be described. The main difference between the TVS diode 10 of the seventh embodiment and the TVS diode 10 of the first embodiment lies in the top view structure of the TVS diode 10. Hereinafter, the same reference numerals will be used to label the components common to the first embodiment, and their descriptions will be omitted.

[0309] Figure 50 The top view of the semiconductor chip 20 in the TVS diode 10 of the seventh embodiment is shown schematically. Figure 51 Schematic illustration of the use Figure 50The cross-sectional structure obtained by cutting the TVS diode 10 along the F51-F51 line. Figure 52 The diagram schematically shows the top view of the first to third connecting electrodes 81 to 83 and wiring 90 of the TVS diode 10. Figure 53 The top view of the TVS diode 10 is shown schematically.

[0310] like Figure 50 As shown, the TVS diode 10 of the seventh embodiment is a structure obtained by adding a fourth pin junction 130 and a fourth reverse pin junction 60D to the TVS diode 10 of the first embodiment.

[0311] In a top-view configuration, the fourth pin junction 130 is positioned relative to the third pin junction 50, offset from the second side 20B and the third side 20C. The fourth pin junction 130 is located at the same position as the second pin junction 40 in the Y direction. In a top-view configuration, the third region 66C of the diode pair region 60 is disposed between the second pin junction 40 and the fourth pin junction 130. Therefore, it can be said that the second pin junction 40 and the fourth pin junction 130 are configured opposite each other in a manner that sandwiches the diode pair region 60 in a top-view configuration.

[0312] like Figure 51 As shown, the fourth pin junction 130 includes a high-concentration region 131 on the fourth terminal side, a low-concentration region 132 on the fourth terminal side, a contact region 133 on the fourth terminal side, and a fourth defined region 134. The fourth pin junction 130 is formed by the high-concentration region 131, the low-concentration region 132, and the contact region 133 on the fourth terminal side. Figure 50 and Figure 51As shown, the structure of the fourth pin junction 130 is the same as that of the third pin junction 50. Furthermore, in the seventh embodiment, the structures of the first pin junction 30, the second pin junction 40, and the third pin junction 50 are the same as in the first embodiment. Therefore, the first pin junction 30, the second pin junction 40, the third pin junction 50, and the fourth pin junction 130 have identical structures. Therefore, detailed descriptions of the fourth terminal-side high-concentration region 131, the fourth terminal-side low-concentration region 132, the fourth terminal-side contact region 133, and the fourth defined region 134 are omitted. In the fourth pin junction 130, the p-type fourth terminal-side high-concentration region 131 constitutes the P-layer of the pin diode, the n-type fourth terminal-side low-concentration region 132 constitutes the I-layer of the pin diode, and the n-type fourth terminal-side contact region 133 constitutes the N-layer of the pin diode. That is, the fourth terminal-side high-concentration region 131, the fourth terminal-side low-concentration region 132, and the fourth terminal-side contact region 133 form a pin junction in the Z-direction. Therefore, in the fourth pin junction 130, a pin diode (diode 208) with the first polarity direction is formed by the high concentration region 131 on the fourth terminal side, the low concentration region 132 on the fourth terminal side, and the contact region 133 on the fourth terminal side.

[0313] exist Figure 51 In the example shown, the shortest distance DE between the fourth defined region 134 of the fourth pin 130 and the third defined region 54 of the third pin 50 is equal to the shortest distance DB between the second defined region 44 and the third defined region 54 of the second pin 40. Additionally, the shortest distance DE is equal to the shortest distance DA between the first defined region 34 and the second defined region 44 of the first pin 30. The shortest distance DF between the fourth defined region 134 and the second defined region 44 is equal to the shortest distance DC between the first defined region 34 and the third defined region 54. Furthermore, the shortest distances DE and DF can be arbitrarily changed. In one example, the shortest distance DE may also differ from at least one of the shortest distances DA and DB. The shortest distance DF may also differ from the shortest distance DC.

[0314] like Figure 50 As shown, diode pair region 60 (high concentration region 61) includes a fourth region 66D and a third connection region 67C. The fourth region 66D is offset from the third region 66C in the Y direction. More specifically, the fourth region 66D is offset from the third region 66C towards the second side 20B and is disposed on the fourth side 20D. The fourth region 66D is located at the same position as the second region 66B in the Y direction.

[0315] The fourth region 66D includes the first to fourth sides 66DA to 66DD. The first side 66DA is the side of the fourth region 66D that is biased towards the first side 20A, extending along the Y direction when viewed from above. The second side 66DB is the side of the fourth region 66D that is biased towards the second side 20B, extending along the Y direction when viewed from above. The third side 66DC is the side of the fourth region 66D that is biased towards the third side 20C, extending along the X direction when viewed from above. The fourth side 66DD is the side of the fourth region 66D that is biased towards the fourth side 20D, extending along the X direction when viewed from above. The first side 66BA and the fourth side 66BD are positioned in the Y direction that are biased towards the fourth side 20D compared to the third region 66C.

[0316] The fourth region 66D includes the corner between the first side 66DA and the fourth side 66DD, the corner between the second side 66DB and the fourth side 66DD, and the corner between the second side 66DB and the third side 66DC. Each corner appears curved when viewed from above.

[0317] The third connecting region 67C is located between the third region 66C and the fourth region 66D. The third connecting region 67C is the region connecting the third region 66C and the fourth region 66D. When viewed from above, the third region 66C and the third connecting region 67C are positioned between the third pin junction 50 and the fourth pin junction 130 in the directions intersecting the X and Y directions.

[0318] Because of the presence of a fourth region 66D and a third connecting region 67C, the shape of the third region 66C as viewed from above differs from that of the first embodiment. Specifically, the corner between the second side 66CB and the fourth side 66CD is omitted from the third region 66C.

[0319] exist Figure 50 In the example shown, the width dimension (dimension in the X direction) WD of the fourth region 66D is equal to the width dimension WA of the first region 66A. The width dimension WB of the second region 66B is larger than the width dimension WD of the fourth region 66D. The width dimension WC of the third region 66C is larger than the width dimension WD of the fourth region 66D. The width dimension WB of the second region 66B is equal to the width dimension WC of the third region 66C.

[0320] Furthermore, the width dimensions WA of the first region 66A, WB of the second region 66B, WC of the third region 66C, and WD of the fourth region 66D can be arbitrarily changed. In one example, the width dimension WA of the first region 66A can be equal to the width dimension WC of the third region 66C. In another example, the width dimension WD of the fourth region 66D can be equal to the width dimension WB of the second region 66B. The width dimension WD of the fourth region 66D can also be different from the width dimension WA of the first region 66A.

[0321] A fourth reverse pin junction 60D is provided in the fourth region 66D. The fourth reverse pin junction 60D is aligned with the fourth pin junction 130 along the Y direction. The fourth reverse pin junction 60D is offset from the third reverse pin junction 60C in the Y direction. The fourth reverse pin junction 60D includes a portion that overlaps with the third reverse pin junction 60C when viewed from the X direction.

[0322] like Figure 51 As shown, the fourth reverse pin junction 60D includes a fourth low-concentration region 62D and a fourth contact region 63D. The structures of the fourth low-concentration region 62D and the fourth contact region 63D are, for example, the same as those of the third low-concentration region 62C and the third contact region 63C. In the fourth reverse pin junction 60D, the p-type fourth contact region 63D constitutes the P-layer of the pin diode, the n-type fourth low-concentration region 62D constitutes the I-layer of the pin diode, and the n-type high-concentration region 61 constitutes the N-layer of the pin diode. That is, the fourth contact region 63D, the fourth low-concentration region 62D, and the high-concentration region 61 form a pin junction in the Z-direction. Therefore, in the fourth reverse pin junction 60D, a pin diode (diode 209) with a second polarity direction is formed by the high-concentration region 61, the fourth low-concentration region 62D, and the fourth contact region 63D.

[0323] like Figure 50 As shown by the dashed lines, the outer edge of the inner region 64 is located further inward than the outer edge of the high-concentration region 61 when viewed from above. In one example, the inner region 64 is formed into a rectangular shape that is slightly smaller than the high-concentration region 61 (diode pair region 60) when viewed from above. Therefore, the inner region 64 is arranged to overlap with each of the reverse pin junctions 60A, 60B, 60C, and 60D when viewed from above. More specifically, the inner region 64 is arranged to overlap with the first low-concentration region 62A, the second low-concentration region 62B, the third low-concentration region 62C, and the fourth low-concentration region 62D when viewed from above. The cross-sectional structure of the pn junction 60E is the same as in the first embodiment.

[0324] like Figure 52As shown, the TVS diode 10 of the seventh embodiment is a structure obtained by adding a fourth connecting electrode 84 to the TVS diode 10 of the first embodiment. The fourth connection electrode 84 is positioned, when viewed from above, slightly offset from the center of the semiconductor chip 20 in the X direction, towards the second side surface 20B. The first connection electrode 81 extends along the Y direction. The fourth connection electrode 84 includes a pin connection portion 84A and a wiring portion 84B extending from the pin connection portion 84A toward the fourth side surface 20D along the Y direction. In one example, the pin connection portion 84A and the wiring portion 84B are integrated.

[0325] The pin connector 84A is positioned at the fourth pin junction 130 (see top view) Figure 50 The overlapping position. The pin connection portion 84A is square when viewed from above. The pin connection portion 84A is located in the low concentration region 132 on the fourth terminal side of the fourth pin junction 130 when viewed from above. The pin connection portion 84A is larger than the fourth terminal side contact region 133 of the fourth pin junction 130 when viewed from above.

[0326] The wiring portion 84B, viewed from above, is formed as a strip with width in the X direction. The width dimension of the wiring portion 84B is smaller than the X-direction dimension of the pin connection portion 84A. The wiring portion 84B is offset from the pin connection portion 84A in the X direction. More specifically, the imaginary line CL5 extending in the Y direction from the center of the width of the wiring portion 84B is located offset from the imaginary line CL6 extending in the Y direction from the center of the X direction of the pin connection portion 84A, towards the first side surface 20A.

[0327] The wiring portion 84B, when viewed from above, is arranged to cover the fourth contact area 63D of the fourth reverse pin junction 60D. In one example, the wiring portion 84B covers the entire fourth contact area 63D when viewed from above. Therefore, the width of the wiring portion 84B is larger than the width of the fourth contact area 63D. On the other hand, the width of the wiring portion 84B is smaller than the width of the fourth low-density region 62D. The top end of the wiring portion 84B is curved when viewed from above.

[0328] A reverse pin connection portion 84C is provided in the wiring portion 84B at a position overlapping with the fourth contact area 63D. The reverse pin connection portion 84C is connected to the fourth contact area 63D. In one example, the structure of the fourth connection electrode 84 is the same as that of the first connection electrode 81.

[0329] like Figure 51As shown, the fourth connecting electrode 84 electrically connects the fourth terminal-side contact region 133 of the fourth pin junction 130 to the fourth contact region 63D of the fourth reverse pin junction 60D. The fourth connecting electrode 84 is connected to the fourth terminal-side contact region 133 through the seventh opening 73H of the insulating layer 70. The fourth connecting electrode 84 is connected to the fourth contact region 63D through the eighth opening 73J of the insulating layer 70.

[0330] like Figure 52 As shown, along with the provision of the fourth connecting electrode 84, the shape of the third connecting electrode 83 differs from that in the first embodiment. In the seventh embodiment, the structure of the third connecting electrode 83 is the same as that of the second connecting electrode 82. That is, the center of the wiring portion 83B of the third connecting electrode 83 in the X direction is located at the same position as the center of the pin connection portion 83A in the X direction.

[0331] The wiring 90 includes a fourth region 98, a third connection region 99, and a fourth recess 96D. The fourth region 98, viewed from above, corresponds to the fourth region 66D of the diode pairing region 60 (see reference). Figure 50 The outer perimeter of the fourth region 98 is set in an overlapping manner with the first side 66DA, the second side 66DB, and the fourth side 66DD of the fourth region 66D (all refer to...). Figure 50 The corresponding part is set in a way that overlaps with the first side 66DA, the second side 66DB and the fourth side 66DD when viewed from above.

[0332] The fourth recess 96D, when viewed from above, is positioned to avoid the fourth connecting electrode 84. The fourth recess 96D opens toward the third side surface 20C. Thus, the fourth region 98, when viewed from above, is positioned to partially surround the fourth connecting electrode 84. Furthermore, the fourth recess 96D, when viewed from above, avoids the fourth low-concentration region 62D of the fourth region 66D (high-concentration region 61) of the diode pair region 60 (both refer to...). Figure 50 Therefore, the fourth region 98 is set up in a manner that surrounds the fourth low-concentration region 62D when viewed from above.

[0333] By providing the fourth recess 96D, it can be said that the fourth region 98 is locally connected to the separated region 65 in the fourth region 66D. More specifically, as... Figure 50As shown, the separation region 65 in the fourth region 66D includes a wiring connection region 65P connected to the wiring 90 and a fourth separation region 65D overlapping the fourth connection electrode 84 in a top view. The fourth separation region 65D is located at the end of the fourth pin junction 130 at one of the two ends in the Y direction of the fourth region 66D. The fourth separation region 65D is the region located between the fourth low-concentration region 62D and the third side 66DC in the fourth region 66D in a top view. The wiring connection region 65P is arranged in a way that partially surrounds the fourth low-concentration region 62D in a top view. That is, the wiring connection region 65P is arranged in a way that partially surrounds the fourth reverse pin junction 60D in a top view. Therefore, the fourth region 98 (refer to) connected to the wiring connection region 65P Figure 51 (When viewed from above, it is arranged in a way that partially surrounds the fourth reverse pin junction 60D.)

[0334] like Figure 52 As shown, the third connection region 99, viewed from above, is connected to the third connection region 67C of the diode pair region 60 (see reference). Figure 51 The third connection area 99 is arranged in an overlapping manner. The shape and size of the third connection area 99 are the same as those of the first connection area 67A. The third connection area 99 connects the entire area of ​​the third connection area 67C. In other words, the third connection area 67C is composed of the wiring connection area 65P.

[0335] like Figure 53 As shown, the TVS diode 10 of the seventh embodiment is a structure obtained by adding a fourth terminal opening 77D to the TVS diode 10 of the first embodiment. The arrangement and structure of the first to third terminal openings 77A to 77C are the same as those of the first embodiment.

[0336] The fourth terminal opening 77D is offset from the third terminal 103 in both the X and Y directions when viewed from above. Specifically, the fourth terminal opening 77D is positioned further away from the second side 20B than the third terminal opening 77C when viewed from above. In one example, the fourth terminal opening 77D is positioned at the same location as the second terminal opening 77B in the Y direction.

[0337] like Figure 51 As shown, the fourth terminal opening 77D, like the first to third terminal openings 77A to 77C, exposes the pin connection portion 84A of the fourth connecting electrode 84. The fourth terminal opening 77D is positioned to overlap with the fourth terminal-side contact area 133 when viewed from above. Furthermore, the TVS diode 10 according to the seventh embodiment achieves the same effect as the first embodiment.

[0338] (Eighth Implementation) Reference Figures 54-56 The TVS diode 10 of the eighth embodiment will be described. The main difference between the TVS diode 10 of the eighth embodiment and the TVS diode 10 of the seventh embodiment lies in the top view structure of the TVS diode 10. Hereinafter, the same reference numerals will be used to label the components common to the seventh embodiment, and their descriptions will be omitted.

[0339] like Figure 54 As shown, in the TVS diode 10 of the eighth embodiment, the first pin junction 30, the second pin junction 40, the third pin junction 50, and the fourth pin junction 130 are disposed at the four corners of the first surface 20S of the semiconductor chip 20 when viewed from above. The first pin junction 30 is disposed at the corner of the first surface 20S of the semiconductor chip 20, biased towards the first side surface 20A and the fourth side surface 20D. The second pin junction 40 is disposed at the corner of the first surface 20S of the semiconductor chip 20, biased towards the first side surface 20A and the third side surface 20C. The third pin junction 50 is disposed at the corner of the first surface 20S of the semiconductor chip 20, biased towards the second side surface 20B and the fourth side surface 20D. The fourth pin junction 130 is disposed at the corner of the first surface 20S of the semiconductor chip 20, biased towards the second side surface 20B and the third side surface 20C. The cross-sectional structure of each of the first pin junction 30, the second pin junction 40, the third pin junction 50, and the fourth pin junction 130 is the same as that of the seventh embodiment.

[0340] The diode pair region 60 (high-concentration region 61) appears cross-shaped when viewed from above. The diode pair region 60, like in the seventh embodiment, includes first to fourth regions 66A to 66D and first to fourth reverse pin junctions 60A to 60D.

[0341] The first region 66A is the region where the first reverse pin junction 60A is disposed. The first region 66A includes a portion located in the Y direction between the first pin junction 30 and the second pin junction 40. In other words, the first pin junction 30 and the second pin junction 40 are arranged opposite each other in a manner that sandwiches the first region 66A. In addition, the first reverse pin junction 60A includes a portion located in the Y direction between the first pin junction 30 and the second pin junction 40.

[0342] The first low-concentration region 62A and the first contact region 63A of the first reverse pin junction 60A, when viewed from above, are roughly rectangular in shape with the X direction as the length direction and the Y direction as the width direction. In one example, when viewed from the Y direction, the first low-concentration region 62A and the first contact region 63A include areas extending beyond the first pin junction 30 and the second pin junction 40.

[0343] The second region 66B is the region where the second reverse pin junction 60B is disposed. The second region 66B includes a portion located in the X direction between the second pin junction 40 and the fourth pin junction 130. In other words, the second pin junction 40 and the fourth pin junction 130 are arranged opposite each other, sandwiching the second region 66B. Furthermore, the second reverse pin junction 60B includes a portion located in the X direction between the second pin junction 40 and the fourth pin junction 130.

[0344] The second low-concentration region 62B and the second contact region 63B of the second reverse pin junction 60B, when viewed from above, are roughly rectangular in shape with the X direction as the width direction and the Y direction as the length direction. In one example, when viewed from the X direction, the second low-concentration region 62B and the second contact region 63B include areas extending beyond the second pin junction 40 and the fourth pin junction 130.

[0345] The third region 66C is the region where the third reverse pin junction 60C is disposed. The third region 66C includes the portion located in the X direction between the first pin junction 30 and the third pin junction 50. In other words, the first pin junction 30 and the third pin junction 50 are arranged opposite each other in a manner that sandwiches the third region 66C. In addition, the third reverse pin junction 60C includes the portion located in the X direction between the first pin junction 30 and the third pin junction 50.

[0346] The third low-concentration region 62C and the third contact region 63C of the third reverse pin junction 60C, when viewed from above, are roughly rectangular in shape with the X direction as the width direction and the Y direction as the length direction. In one example, when viewed from the X direction, the third low-concentration region 62C and the third contact region 63C include areas extending beyond the first pin junction 30 and the third pin junction 50.

[0347] The fourth region 66D is the region where the fourth reverse pin junction 60D is provided. The fourth region 66D includes the portion located in the Y direction between the third pin junction 50 and the fourth pin junction 130. In other words, the third pin junction 50 and the fourth pin junction 130 are arranged opposite each other, sandwiching the fourth region 66D. Additionally, the fourth reverse pin junction 60D includes the portion located in the Y direction between the third pin junction 50 and the fourth pin junction 130.

[0348] The fourth low-concentration region 62D and the fourth contact region 63D of the fourth reverse pin junction 60D, when viewed from above, form a roughly rectangular shape with the X direction as the length direction and the Y direction as the width direction. In one example, when viewed from the Y direction, the fourth low-concentration region 62D and the fourth contact region 63D include areas extending beyond the third pin junction 50 and the fourth pin junction 130.

[0349] In region 60 (high-concentration region 61), the regions connecting the first region 66A and the second region 66B, the first region 66A and the third region 66C, the second region 66B and the fourth region 66D, and the third region 66C and the fourth region 66D, respectively, appear curved when viewed from above. Furthermore, the corners of each of the first to fourth regions 66A to 66D also appear curved when viewed from above. The radii of curvature of the regions connecting the first region 66A and the second region 66B, the first region 66A and the third region 66C, the second region 66B and the fourth region 66D, and the third region 66C and the fourth region 66D are all larger than the radii of curvature of the corners of the first to fourth regions 66A to 66D.

[0350] like Figure 54 As shown by the dashed lines, the outer edge of the inner region 64 is located further inward than the outer edge of the high-concentration region 61 when viewed from above. In one example, the inner region 64 is formed into a rectangular shape that is slightly smaller than the high-concentration region 61 (diode pair region 60) when viewed from above. Therefore, the inner region 64 is arranged to overlap with each of the reverse pin junctions 60A, 60B, 60C, and 60D when viewed from above. More specifically, the inner region 64 is arranged to overlap with the first low-concentration region 62A, the second low-concentration region 62B, the third low-concentration region 62C, and the fourth low-concentration region 62D when viewed from above. pn junction 60E (refer to...) Figure 2 The cross-sectional structure of the first embodiment is the same.

[0351] like Figure 55 As shown, the shapes of the first to fourth connecting electrodes 81 to 84 in the eighth embodiment, when viewed from above, are different from those of the first to fourth connecting electrodes 81 to 84 in the seventh embodiment. The first connecting electrode 81 includes a pin connection portion 81A, a wiring portion 81B, and a reverse pin connection portion 81C. The pin connection portion 81A, when viewed from above, covers the entire area of ​​the first terminal-side contact region 33 of the first pin junction 30. The pin connection portion 81A is in contact with the first terminal-side contact region 33. The pin connection portion 81A has a rectangular shape when viewed from above. The wiring portion 81B extends from the pin connection portion 81A toward the third side surface 20C along the Y direction. The reverse pin connection portion 81C, when viewed from above, covers the entire area of ​​the first contact region 63A of the first reverse pin junction 60A. The reverse pin connection portion 81C is in contact with the first contact region 63A. The reverse pin connection portion 81C is formed into a generally rectangular shape with the X direction as the length direction and the Y direction as the width direction when viewed from above. Here, in the eighth embodiment, the first to fourth connecting electrodes 81 to 84 are formed to have the same shape when viewed from above. Therefore, detailed descriptions of the second to fourth connecting electrodes 82 to 84 are omitted.

[0352] The shape of the wiring 90 in the eighth embodiment, viewed from above, differs from that in the seventh embodiment. The wiring 90 is configured to partially and independently surround the first to fourth connecting electrodes 81 to 84. More specifically, the wiring 90, like in the seventh embodiment, includes first to fourth recesses 96A to 96D. The first recess 96A of the wiring 90, viewed from above, is configured to avoid the reverse pin connection portion 81C of the first connecting electrode 81. The first recess 96A opens toward the pin connection portion 81A to allow the wiring portion 81B to pass through. Thus, the wiring 90 is configured to partially surround the reverse pin connection portion 81C and the wiring portion 81B of the first connecting electrode 81. The second recess 96B, viewed from above, is configured to avoid the reverse pin connection portion 82C of the second connecting electrode 82. The second recess 96B opens toward the pin connection portion 82A to allow the wiring portion 82B to pass through. Thus, the wiring 90 is configured to partially surround the reverse pin connection portion 82C and the wiring portion 82B of the second connecting electrode 82. The third recess 96C, when viewed from above, is positioned to avoid the reverse pin connection portion 83C of the third connecting electrode 83. The third recess 96C opens toward the pin connection portion 83A to allow the wiring portion 83B to pass through. Thus, the wiring 90 is positioned to partially surround the reverse pin connection portion 83C and the wiring portion 83B in the third connecting electrode 83. The fourth recess 96D, when viewed from above, is positioned to avoid the reverse pin connection portion 84C of the fourth connecting electrode 84. The fourth recess 96D opens toward the pin connection portion 84A to allow the wiring portion 84B to pass through. Thus, the wiring 90 is positioned to partially surround the reverse pin connection portion 84C and the wiring portion 84B in the fourth connecting electrode 84.

[0353] Furthermore, when viewed from above, the first recess 96A surrounds the first low-concentration region 62A of the diode-pair region 60 (high-concentration region 61) (see reference). Figure 54 The second recess 96B, when viewed from above, surrounds the second low-concentration region 62B (see reference). Figure 54 The third recess 96C, when viewed from above, surrounds the third low-concentration region 62C (see reference). Figure 54 The fourth recess 96D, when viewed from above, surrounds the fourth low-concentration region 62D (see reference). Figure 54 Set it in the way of ).

[0354] Wiring 90 is locally connected to the separation region 65 of diode pair region 60 (high concentration region 61). More specifically, as... Figure 54 As shown, the separation region 65 includes first to fourth separation regions 65A to 65D that are not connected to the wiring 90, and a wiring connection region 65P that is connected to the wiring 90. The first separation region 65A is the region in the separation region 65 that corresponds to the first region 66A, and is connected to the wiring section 81B (see reference). Figure 55 The portion covered by the wiring section 82B. The second separation region 65B is the area within the separation region 65 corresponding to the second region 66B. (Refer to...) Figure 55 The third separation region 65C is the area within separation region 65 corresponding to the third region 66C, covered by wiring section 83B (see reference). Figure 55 The portion covered by the wiring section 84B (see reference 66D) is the fourth separation region 65, corresponding to the fourth region 66D. Figure 55 The portion covered by the wiring connection area 65P is thus arranged such that, when viewed from above, the first to fourth low-concentration areas 62A to 62D are independently and partially surrounded. Therefore, the wiring 90 connected to the wiring connection area 65P is arranged such that, when viewed from above, the first to fourth low-concentration areas 62A to 62D are independently and partially surrounded.

[0355] like Figure 56As shown, the first to fourth terminal openings 77A to 77D of the TVS diode 10 in the eighth embodiment are disposed at the four corners of the first surface 20S of the semiconductor chip 20 when viewed from above. The first terminal opening 77A is disposed at a corner of the first surface 20S of the semiconductor chip 20, adjacent to the first side surface 20A and the fourth side surface 20D. The second terminal opening 77B is disposed at a corner of the first surface 20S of the semiconductor chip 20, adjacent to the first side surface 20A and the third side surface 20C. The third terminal opening 77C is disposed at a corner of the first surface 20S of the semiconductor chip 20, adjacent to the second side surface 20B and the fourth side surface 20D. The fourth terminal opening 77D is disposed at a corner of the first surface 20S of the semiconductor chip 20, adjacent to the second side surface 20B and the third side surface 20C.

[0356] The first terminal opening 77A is disposed in the contact area 33 with the first terminal side when viewed from above (see reference). Figure 54 The second terminal opening 77B is positioned at the overlapping location. When viewed from above, it is located in the contact area 43 with the second terminal side (see reference). Figure 54 The third terminal opening 77C is positioned at the overlapping location. When viewed from above, it is located in the contact area 53 with the third terminal side (see reference). Figure 54 The fourth terminal opening 77D is positioned at the overlapping location with the fourth terminal side contact area 133 when viewed from above (see reference). Figure 54 The overlapping positions. Furthermore, the TVS diode 10 according to the eighth embodiment achieves the same effect as the first embodiment.

[0357] (Example of amendment) The above-described embodiments can be implemented with modifications as follows. Furthermore, the above-described embodiments and the following modifications can be combined and implemented within a technically compatible framework.

[0358] The second and third embodiments can be combined with each other. That is, the first pin junction 30 may include a first buffer region 35 and a first separation trench structure 120A. The second pin junction 40 may include a second buffer region 45 and a second separation trench structure 120B. The third pin junction 50 may include a third buffer region 55 and a third separation trench structure 120C. In this case, the first defined region 34 can be omitted from the first pin junction 30. The second defined region 44 can be omitted from the second pin junction 40. The third defined region 54 can be omitted from the third pin junction 50.

[0359] In the fourth to eighth embodiments, the structure of at least one of the second and third embodiments can be applied. In the third embodiment, at least one of the first separation electrode 123A, the second separation electrode 123B, and the third separation electrode 123C may be omitted.

[0360] In the third embodiment, at least one of the first separating insulating layer 122A, the second separating insulating layer 122B, and the third separating insulating layer 122C may be omitted. In the third embodiment, the size of the high-concentration region 61 can be arbitrarily changed. Figure 57 The cross-sectional structure of the TVS diode 10 after changing the size of the high-concentration region 61 is shown. (See diagram below.) Figure 57 As shown, the high-concentration region 61 can expand to a position adjacent to the first separation trench 121A and the second separation trench 121B. Furthermore, although not shown, the high-concentration region 61 can also expand to a position adjacent to the third separation trench 121C. Along with this expansion of the high-concentration region 61, the internal region 64 can also expand. Figure 57 The modified TVS diode 10 shown can improve its surge absorption performance by increasing the junction area between the high-concentration region 61 and the internal region 64.

[0361] In addition, Figure 57 In one variation, the high-concentration region 61 may be expanded to a position adjacent to, for example, the first separation trench 121A, while in another variation, the high-concentration region 61 may be positioned separately from the second separation trench 121B. Alternatively, in another example, the high-concentration region 61 may be expanded to a position adjacent to the second separation trench 121B, while in another variation, the high-concentration region 61 may be positioned separately from the first separation trench 121A.

[0362] In the second embodiment, the TVS diode 10 may have a structure including a first pin junction 30 and a diode pair region 60 including a first reverse pin junction 60A and a pn junction 60E. That is, the second pin junction 40, the third pin junction 50, the second reverse pin junction 60B, and the third reverse pin junction 60C can be omitted from the TVS diode 10. Figure 58 The cross-sectional structure of a TVS diode 10, which schematically shows a variation of a first pin junction 30 and a diode pair region 60 including a first reverse pin junction 60A and a pn junction 60E, is shown.

[0363] like Figure 58 As shown, the outer edge of the inner region 64 in diode pair region 60 is located further inward than the outer edge of the high-concentration region 61 when viewed from above. The outer edge of the inner region 64 is positioned to overlap with the separation region 65 when viewed from above.

[0364] Although not illustrated, the high-concentration region 61 is rectangular in shape when viewed from above. The high-concentration region 61 includes four corners. Each corner of the high-concentration region 61 appears curved when viewed from above. In one example, the inner region 64 is rectangular in shape when viewed from above. The inner region 64 is smaller than the high-concentration region 61 when viewed from above. Therefore, the inner edge of the inner region 64 is located further inward than the outer edge of the high-concentration region 61 when viewed from above. The inner region 64 is positioned to overlap with the first low-concentration region 62A when viewed from above. The outer edge of the inner region 64 includes four corners. Each of the four corners appears curved when viewed from above.

[0365] In the first and third embodiments, the TVS diode 10 may have a structure including a first pin junction 30 and a diode pair region 60 including a first reverse pin junction 60A and a pn junction 60E. That is, the second pin junction 40, the third pin junction 50, the second reverse pin junction 60B, and the third reverse pin junction 60C can be omitted from the TVS diode 10.

[0366] In the second embodiment, the p-type impurity concentration of the first buffer region 35 can be arbitrarily changed. In one example, the p-type impurity concentration of the first buffer region 35 can be higher than the p-type impurity concentration of the high-concentration region 31 on the first terminal side. In another example, the minimum p-type impurity concentration of the first buffer region 35 can be less than the n-type impurity concentration of the low-concentration region 32 on the first terminal side. Furthermore, the p-type impurity concentrations of the second buffer region 45 and the third buffer region 55 can also be changed in the same way.

[0367] In the second embodiment, the concentration gradient of p-type impurities in the first buffer region 35 can be arbitrarily changed. In one example, the p-type impurity concentration in the first buffer region 35 can be approximately constant in the Z direction. Similarly, the p-type impurity concentrations in the second buffer region 45 and the third buffer region 55 can also be changed.

[0368] In the first to third and seventh embodiments, the shape of the diode when viewed from above in region 60 (high concentration region 61) can be arbitrarily changed. In one example, the shape of the diode when viewed from above in region 60 (high concentration region 61) can be rectangular.

[0369] In the second embodiment, the diode pair region 60 (high-concentration region 61) can be constructed by a first diode pair region, a second diode pair region, and a third diode pair region arranged separately from each other. A first reverse pin junction 60A is provided in the first diode pair region. A second reverse pin junction 60B is provided in the second diode pair region. A third reverse pin junction 60C is provided in the third diode pair region. In this case, the internal region 64 can be constructed by a first internal region, a second internal region, and a third internal region arranged separately from each other. The first internal region is connected to the high-concentration region of the first diode pair region. The second internal region is connected to the high-concentration region of the second diode pair region. The third internal region is connected to the high-concentration region of the third diode pair region.

[0370] In various embodiments, the internal region 64 may be configured such that, when viewed from above, it overlaps only with any one of the first low-concentration region 62A, the second low-concentration region 62B, and the third low-concentration region 62C. Alternatively, in one example, the internal region 64 may be configured such that, when viewed from above, it overlaps with both the first low-concentration region 62A and the third low-concentration region 62C, but not with the second low-concentration region 62B. Furthermore, in another example, the internal region 64 may be configured such that, when viewed from above, it overlaps with both the second low-concentration region 62B and the third low-concentration region 62C, but not with the first low-concentration region 62A.

[0371] In the first to third, fifth, and seventh embodiments, the configuration of the first pin junction 30, the second pin junction 40, the third pin junction 50, and the first to third reverse pin junctions 60A to 60C can be arbitrarily changed. In one example, the first pin junction 30 and the first reverse pin junction 60A may not be arranged along the Y direction when viewed from above. In one example, the first pin junction 30 and the first reverse pin junction 60A may be staggered along the X direction when viewed from above. In one example, the second pin junction 40 and the second reverse pin junction 60B may not be arranged along the Y direction when viewed from above. In one example, the second pin junction 40 and the second reverse pin junction 60B may be staggered along the X direction when viewed from above. In one example, the third pin junction 50 and the third reverse pin junction 60C may not be arranged along the Y direction when viewed from above. In one example, the third pin junction 50 and the third reverse pin junction 60C may be staggered along the X direction when viewed from above.

[0372] In one example, the first pin 30 and the second reverse pin 60B may not be adjacent in the X direction when viewed from above. In another example, when viewed from the X direction, the first pin 30 may be staggered along the Y direction without overlapping with the second reverse pin 60B. In another example, the third pin 50 and the second reverse pin 60B may not be adjacent in the X direction when viewed from above. In another example, when viewed from the X direction, the third pin 50 may be staggered along the Y direction without overlapping with the second reverse pin 60B. In another example, the first reverse pin 60A and the second pin 40 may not be adjacent in the X direction when viewed from above. In another example, when viewed from the X direction, the second pin 40 may be staggered along the Y direction without overlapping with the first reverse pin 60A. In another example, the third reverse pin 60C and the second pin 40 may not be adjacent in the X direction when viewed from above. In one example, when viewed from the X direction, the second pin junction 40 can be staggered along the Y direction in a manner that does not overlap with the third reverse pin junction 60C.

[0373] In the seventh embodiment, the fourth pin junction 130 and the fourth reverse pin junction 60D may not be arranged along the Y direction when viewed from above. In one example, the fourth pin junction 130 and the fourth reverse pin junction 60D may be staggered along the X direction when viewed from above.

[0374] In one example, the fourth pin 130 and the third reverse pin 60C may not be adjacent in the X direction when viewed from above. In another example, when viewed from the X direction, the fourth pin 130 may be staggered along the Y direction without overlapping with the third reverse pin 60C. In yet another example, the fourth reverse pin 60D and the fourth pin 130 may not be adjacent in the X direction when viewed from above. In another example, when viewed from the X direction, the third pin 50 may be staggered along the Y direction without overlapping with the fourth reverse pin 60D.

[0375] In various embodiments, the position of the outer edge of the inner region 64 under top-view can be arbitrarily changed. In one example, the outer edge of the inner region 64 may be positioned to overlap with the outer edge of the high-concentration region 61 under top-view. In another example, the outer edge of the inner region 64 may include a portion extending beyond the high-concentration region 61 under top-view. In yet another example, at least a portion of the outer edge of the inner region 64 may be configured at a different position from the separation region 65 under top-view.

[0376] In various embodiments, at least one of the multiple corners of the outer edge of the inner region 64 may be formed as a right angle rather than a curved shape when viewed from above. In various embodiments, the size and shape of the separation region 65 as viewed from above can be arbitrarily changed. The separation region 65 only needs to be provided covering the entire circumference of the outer periphery of the high-concentration region 61. That is, the separation region 65 may not include the portion surrounding the first reverse pin junction 60A as viewed from above. The separation region 65 may not include the portion surrounding the second reverse pin junction 60B as viewed from above. The separation region 65 may not include the portion surrounding the third reverse pin junction 60C as viewed from above. The separation region 65 may not include the portion surrounding the fourth reverse pin junction 60D as viewed from above.

[0377] In various embodiments, the size of the wiring 90 can be arbitrarily changed. In one example, the area of ​​the wiring 90 in top view can be less than 75% of the area of ​​the separation region 65 in top view. In one example, the area of ​​the wiring 90 in top view can be larger than 97% of the area of ​​the separation region 65 in top view. In one example, the area of ​​the wiring 90 in top view can be greater than or equal to the area of ​​the separation region 65 in top view. In one example, the area of ​​the wiring 90 in top view can be less than or equal to the area of ​​the first connecting electrode 81 in top view. The area of ​​the wiring 90 in top view can be less than or equal to the area of ​​the second connecting electrode 82 in top view.

[0378] In the first to third embodiments, the shape of the wiring 90 as viewed from above can be arbitrarily changed. In one example, the wiring 90 may not partially surround at least one of the first connecting electrode 81 and the second connecting electrode 82 as viewed from above.

[0379] In the fourth embodiment, the shape of the wiring 90 as viewed from above can be arbitrarily changed. In one example, the wiring 90 may be located in the area overlapping the outer periphery of the separation region 65 as viewed from above, and may not be located between at least one of the first reverse pin junction 60A and the second reverse pin junction 60B, or between the second reverse pin junction 60B and the third reverse pin junction 60C. Alternatively, in one example, the wiring 90 may be located only between the first reverse pin junction 60A and the second reverse pin junction 60B, and between the second reverse pin junction 60B and the third reverse pin junction 60C.

[0380] In the fifth embodiment, the shape of the wiring 90 as viewed from above can be arbitrarily changed. In one example, the wiring 90 may be provided in the area that overlaps with the outer periphery of the separation region 65 as viewed from above, and not in the portion that overlaps with the first connection region 67A. Alternatively, in another example, the wiring 90 may be provided only in the portion that overlaps with the first connection region 67A.

[0381] In the sixth embodiment, the shape of the wiring 90 as viewed from above can be arbitrarily changed. In one example, the wiring 90 may be disposed in the area that overlaps with the outer periphery of the separation region 65 as viewed from above, and may not be disposed between the first reverse pin junction 60A and the second reverse pin junction 60B. Alternatively, in another example, the wiring 90 may be disposed only between the first reverse pin junction 60A and the second reverse pin junction 60B.

[0382] In the seventh embodiment, the shape of the wiring 90 as viewed from above can be arbitrarily changed. In one example, the wiring 90 may be provided in the region overlapping the outer periphery of the separation region 65 as viewed from above, and not in at least one of the regions overlapping the first to third connection regions 67A to 67C. In another example, the wiring 90 may be provided only in the region overlapping the first to third connection regions 67A to 67C as viewed from above. In yet another example, the wiring 90 may be provided only in the region overlapping the first connection region 67A and the second connection region 67B as viewed from above. In yet another example, the wiring 90 may be provided only in the region overlapping the second connection region 67B and the third connection region 67C as viewed from above. In yet another example, the wiring 90 may be provided only in the region overlapping the first connection region 67A and the third connection region 67C as viewed from above. Alternatively, in one example, wiring 90 may be provided only in any one of the areas that overlap with the first to third connection areas 67A to 67C when viewed from above.

[0383] In the eighth embodiment, the wiring 90 may be disposed in a region that overlaps with the outer periphery of the separation region 65 when viewed from above, and may not be disposed in the center of the separation region 65. Alternatively, in one example, the wiring 90 may be disposed only in the center of the separation region 65.

[0384] In various embodiments, wiring 90 can be omitted from TVS diode 10. Figure 59 The diagram schematically shows a top view of the TVS diode 10 of the first embodiment, omitting the wiring 90. Figure 60 Schematic illustration of the use Figure 59 The cross-sectional structure obtained by cutting the TVS diode 10 along the F60-F60 line. For example... Figure 59 As shown, a protective layer 74 is provided between the first and third connecting electrodes 81 to 83. Therefore, as Figure 60 As shown, the separation region 65 of the diode pair region 60 is covered by an insulating layer 70. The separation region 65 is in contact with the insulating layer 70.

[0385] In various embodiments, a structure obtained by inverting the conductivity types in the semiconductor chip 20 can also be used. That is, a p-type region can be set as an n-type region, and an n-type region can be set as a p-type region. In this case, p-type is an example of a "first conductivity type", and n-type is an example of a "second conductivity type".

[0386] Regarding the TVS diode 10, as long as the outer edge of the inner region 64 is located further inward than the outer edge of the high-concentration region 61 when viewed from above, it can also have the following structure, for example: having a first pin junction 30 and a diode pair region 60 including a first reverse pin junction 60A and a pn junction 60E, but not having a second pin junction 40, a third pin junction 50 and a fourth pin junction 130, as well as a second reverse pin junction 60B, a third reverse pin junction 60C and a fourth reverse pin junction 60D.

[0387] In various embodiments, the TVS diode 10 may include terminals for mounting the TVS diode 10 to, for example, a circuit board. An example of a TVS diode 10 including terminals... Figures 61-63 As shown. Figure 61 The top view of the modified TVS diode 10 is shown schematically. Figure 62 Schematic illustration of the use Figure 61 The cross-sectional structure obtained by cutting the TVS diode 10 along the F62-F62 line. Figure 63 Schematic illustration of the use Figure 61 The cross-sectional structure obtained by cutting the TVS diode 10 along the F63-F63 line.

[0388] like Figures 61-63 As shown, the TVS diode 10 includes a first terminal 101, a second terminal 102, and a third terminal 103 disposed on the protective layer 74. like Figure 61 As shown, the first terminal 101, the second terminal 102, and the third terminal 103 are spaced apart from each other. More specifically, the first terminal 101 and the third terminal 103 are located at the same position in the Y direction and spaced apart from each other in the X direction. The first terminal 101 and the third terminal 103 are positioned closer to the fourth side 20D in the Y direction than the center of the first surface 20S of the semiconductor chip 20. The first terminal 101 is positioned closer to the first side 20A in the X direction than the center of the first surface 20S. The third terminal 103 is positioned closer to the second side 20B in the X direction than the center of the first surface 20S.

[0389] The second terminal 102 is positioned differently from the first terminal 101 and the third terminal 103 in the X and Y directions. The second terminal 102 is positioned closer to the third side surface 20C in the Y direction than the center of the first surface 20S of the semiconductor chip 20. The second terminal 102 is positioned in the center of the first surface 20S in the X direction. Therefore, it can be said that the second terminal 102, when viewed from the Y direction, is positioned between the first terminal 101 and the third terminal 103 in the X direction.

[0390] like Figure 62 and Figure 63 As shown, the first terminal 101 is positioned to overlap with the first pin junction 30 when viewed from above. The second terminal 102 is positioned to overlap with the second pin junction 40 when viewed from above. The third terminal 103 is positioned to overlap with the third pin junction 50 when viewed from above.

[0391] The first terminal 101 is positioned to overlap with the pin connection portion 81A of the first connecting electrode 81 when viewed from above. The second terminal 102 is positioned to overlap with the pin connection portion 82A of the second connecting electrode 82 when viewed from above. The third terminal 103 is positioned to overlap with the pin connection portion 83A of the third connecting electrode 83 when viewed from above.

[0392] The first terminal 101 is electrically connected to the first connecting electrode 81 through the first terminal opening 77A. The first terminal 101 includes: a first contact portion 101A disposed within the first terminal opening 77A and connected to the first connecting electrode 81; and a first mounting portion 101B disposed on the protective layer 74. In one example, the first contact portion 101A and the first mounting portion 101B are integrated.

[0393] The second terminal 102 is electrically connected to the second connecting electrode 82 through the second terminal opening 77B. The second terminal 102 includes: a second contact portion 102A disposed within the second terminal opening 77B and in contact with the second connecting electrode 82; and a second mounting portion 102B disposed on the protective layer 74. In one example, the second contact portion 102A and the second mounting portion 102B are integrated.

[0394] The third terminal 103 is electrically connected to the third connecting electrode 83 through the third terminal opening 77C. The third terminal 103 includes: a third contact portion 103A, disposed within the third terminal opening 77C and connected to the third connecting electrode 83; and a third mounting portion 103B, disposed on the protective layer 74. In one example, the third contact portion 103A and the third mounting portion 103B are integrated.

[0395] The first to third terminals 101 to 103 each have a stacked structure, for example, including a Ni (nickel) layer, a Pd (palladium) layer and an Au (gold) layer stacked sequentially from the first surface 20S side of the semiconductor chip 20.

[0396] Furthermore, in the fifth and sixth embodiments, the TVS diode 10 can be coupled with... Figures 61-63 The example shown similarly includes a first terminal 101 and a second terminal 102. Additionally, in the seventh and eighth embodiments, the TVS diode 10 can be... Figures 61-63 The example shown also includes a first terminal 101, a second terminal 102, a third terminal 103, and a fourth terminal.

[0397] One or more of the various examples described in this disclosure may be combined within a technically inconsistent range. As used in this disclosure, the term "on" includes both "on" and "above". Therefore, a statement such as "the first element is disposed on the second element" means that in one embodiment the first element may be in contact with the second element and directly disposed on the second element, but in other embodiments the first element may be disposed above the second element without contacting the second element. That is, the term "on" does not preclude a configuration where other elements are formed between the first and second elements.

[0398] The Z-direction used in this disclosure does not necessarily need to be vertical, nor does it need to be completely consistent with the vertical direction. Therefore, the various configurations in this disclosure are not limited to the case where the "up" and "down" of the Z-direction described in this disclosure are the "up" and "down" of the vertical direction. For example, the X-direction can be vertical, or the Y-direction can also be vertical.

[0399] (Postscript) The following describes the technical concepts that can be grasped based on this disclosure. Furthermore, for the purpose of aiding understanding and not limitation, the constituent elements described in the appendices are labeled with the corresponding reference numerals in the above embodiments. The reference numerals are merely illustrative to aid understanding, and the constituent elements described in each appendix should not be limited to those shown by the reference numerals.

[0400] (Note A1) A TVS diode (10) includes a semiconductor chip (20) having a first surface (20S) and a second surface (20R) located on the side opposite to the first surface (20S), wherein, The semiconductor chip (20) includes: A first pin junction (30) of a first polarity direction is disposed in a region of the semiconductor chip (20) that is biased toward the first surface (20S); The second pin junction (40) in the first polarity direction is disposed in a region of the semiconductor chip (20) biased towards the first surface (20S), at a position separated from the first pin junction (30) when viewed from above in the thickness direction (Z) of the semiconductor chip (20); and The diode pair region (60), as viewed from above, is separated from both the first pin junction (30) and the second pin junction (40). The diode pair region (60) includes: The high-concentration region (61) of the first conductivity type is separated from the first surface (20S) of the semiconductor chip (20) by being biased toward the second surface (20R); The first low-concentration region (62A) and the second low-concentration region (62B) of the first conductivity type are disposed in a region that is closer to the first surface (20S) than the high-concentration region (61) and are separated from each other in the position that overlaps with the high-concentration region (61) when viewed from above. The impurity concentration of the first low-concentration region (62A) and the impurity concentration of the second low-concentration region (62B) are lower than the impurity concentration of the high-concentration region (61). The separation region (65) is located in a region that is closer to the first surface (20S) than the high concentration region (61) and overlaps with the high concentration region (61) in the top view, separating the first low concentration region (62A) from the second low concentration region (62B). The first contact area (63A) of the second conductivity type is disposed on the surface layer of the first low concentration area (62A); A second contact region (63B) of the second conductivity type is disposed on the surface portion of the second low concentration region (62B); and The internal region (64) of the second conductivity type is disposed at a position overlapping the high concentration region (61) in the top view, and is connected to the high concentration region (61) at a position relative to the high concentration region (61) and closer to the second surface (20R). The high-concentration region (61), the first low-concentration region (62A), and the first contact region (63A) form a first reverse pin junction (60A) with a second polarity direction. The high-concentration region (61), the second low-concentration region (62B), and the second contact region (63B) form a second reverse pin junction (60B) with a second polarity direction. A pn junction (60E) is formed by means of the high concentration region (61) and the inner region (64) in a first polarity direction that is reverse connected to the first reverse pin junction (60A) and the second reverse pin junction (60B). The internal region (64) is arranged in a manner that overlaps with both the first low-concentration region (62A) and the second low-concentration region (62B) under the top view.

[0401] (Note A2) According to Appendix A1, the TVS diode, wherein, The first polarity direction refers to the direction in which the forward current flows from the second surface (20R) toward the first surface (20S) along the thickness direction (Z) of the semiconductor chip (20). The second polarity direction refers to the direction in which the positive current, which is opposite to the first polarity direction, flows in the thickness direction (Z) of the semiconductor chip (20).

[0402] (Note A3) According to appendix A1 or A2, the TVS diode, wherein, The separation region (65) includes an exposed surface (65S) that is exposed from the first surface (20S). The TVS diode includes wiring (90) connected to the exposed surface (65S).

[0403] (Note A4) According to Appendix A3, the TVS diode, wherein... The semiconductor chip (20) includes: The high-concentration region (31) on the first terminal side of the second conductivity type is separated from the first surface (20S) of the semiconductor chip (20) by being biased toward the second surface (20R); The first terminal side low concentration region (32) of the first conductivity type is disposed in a region that is closer to the first surface (20S) than the first terminal side high concentration region (31) at a position that overlaps with the first terminal side high concentration region (31) when viewed from above. The first terminal side contact area (33) of the first conductivity type is provided on the surface of the low concentration area (32) of the first terminal side; The first defined area (34) is located in a region that is closer to the first surface (20S) than the high concentration area (31) on the first terminal side, and overlaps with the high concentration area (31) on the first terminal side when viewed from above, and is set in such a way as to surround the low concentration area (32) on the first terminal side. The high-concentration region (41) on the second terminal side of the second conductivity type is located at a position separated from the first surface (20S) of the semiconductor chip (20) by being biased toward the second surface (20R), and is separated from the high-concentration region (31) on the first terminal side when viewed from above. The low-concentration region (42) on the second terminal side of the first conductivity type is disposed in a region that is closer to the first surface (20S) than the high-concentration region (41) on the second terminal side, at a position that overlaps with the high-concentration region (41) on the second terminal side when viewed from above. The second terminal side contact area (43) of the first conductivity type is disposed on the surface layer of the low concentration area (42) on the second terminal side; and The second defined region (44) is located in a region that is closer to the first surface (20S) than the high concentration region (41) on the second terminal side, at a position that overlaps with the high concentration region (41) on the second terminal side when viewed from above, and is set in a manner that surrounds the low concentration region (42) on the second terminal side. The first pin junction (30) is formed by the first terminal side high concentration region (31), the first terminal side low concentration region (32), and the first terminal side contact region (33). The second pin junction (40) is formed by the high concentration region (41) on the second terminal side, the low concentration region (42) on the second terminal side, and the contact region (43) on the second terminal side.

[0404] (Note A5) According to Appendix A4, the TVS diode, wherein... include: An insulating layer (70) covers the first surface (20S); A first connecting electrode (81) is disposed on the insulating layer (70) to connect the first contact area (63A) to the first terminal-side contact area (33); and The second connecting electrode (82) is disposed on the insulating layer (70) to connect the second contact area (63B) to the second terminal side contact area (43).

[0405] (Note A6) According to the TVS diode described in Appendix A5, wherein, The separation region (65) includes: The first separation region (65A) overlaps with the first connecting electrode (81) under the top view; The second separation region (65B) overlaps with the second connecting electrode (82) under the top view; and The wiring connection area (65P) is connected to the wiring (90). The wiring connection area (65P) is configured, under the top view, to independently and partially surround both the first reverse pin junction (60A) and the second reverse pin junction (60B).

[0406] (Note A7) According to Appendix A6, the TVS diode, wherein... The wiring (90) is arranged in a manner that independently and locally surrounds both the first connecting electrode (81) and the second connecting electrode (82) in the top view.

[0407] (Note A8) According to the TVS diode described in Appendix A6 or A7, wherein, The area of ​​the wiring (90) as viewed from above is larger than the area of ​​the first connecting electrode (81) as viewed from above.

[0408] (Note A9) The TVS diode according to any one of Appendices A5 to A8, wherein, The area of ​​the wiring (90) viewed from above is smaller than the area of ​​the separation region (65) viewed from above.

[0409] (Note A10) According to Appendix A9, the TVS diode, wherein, The area of ​​the wiring (90) under the top view is more than 75% and less than 97% of the area of ​​the separation region (65) under the top view.

[0410] (Note A11) The TVS diode according to any one of Appendices A5 to A10, wherein, include: A protective layer (74) covers the first connecting electrode (81) and the second connecting electrode (82). The first terminal (101) is disposed on the protective layer (74) and electrically connected to the first pin junction (30); and The second terminal (102) is disposed on the protective layer (74) and electrically connected to the second pin junction (40). The protective layer (74) includes: The first terminal opening (77A) partially exposes the first connecting electrode (81); and The second terminal opening (77B) partially exposes the second connecting electrode (82). The first terminal (101) is electrically connected to the first connecting electrode (81) through the first terminal opening (77A). The second terminal (102) is electrically connected to the second connecting electrode (82) through the second terminal opening (77B).

[0411] (Note A12) The TVS diode according to any one of Appendices A1 to A11, wherein, The outer edge of the inner region (64) is located inside the outer edge of the high-concentration region (61) when viewed from above.

[0412] (Note A13) According to the TVS diode described in Appendix A12, wherein, From the top view, the outer edge of the inner region (64) includes multiple corners. The various corners appear curved when viewed from above.

[0413] (Note A14) According to appendix A12 or A13, the TVS diode, wherein, In the top view, the outer edge of the inner region (64) is positioned to overlap with the separated region (65).

[0414] (Note A15) The TVS diode according to any one of Appendices A1 to A3, wherein, The semiconductor chip (20) includes: The high-concentration region (31) on the first terminal side of the second conductivity type is separated from the first surface (20S) of the semiconductor chip (20) by being biased toward the second surface (20R); The first terminal side low concentration region (32) of the first conductivity type is disposed in a region that is closer to the first surface (20S) than the first terminal side high concentration region (31) at a position that overlaps with the first terminal side high concentration region (31) when viewed from above. The first terminal side contact area (33) of the first conductivity type is provided on the surface of the low concentration area (32) of the first terminal side; The first separation trench (121A) is disposed on the first surface (20S) in such a way as to surround the high concentration region (31) on the first terminal side, the low concentration region (32) on the first terminal side, and the contact region (33) on the first terminal side. The high-concentration region (41) on the second terminal side of the second conductivity type is located at a position separated from the first surface (20S) of the semiconductor chip (20) by being biased toward the second surface (20R), and is separated from the high-concentration region (31) on the first terminal side when viewed from above. The low-concentration region (42) on the second terminal side of the first conductivity type is disposed in a region that is closer to the first surface (20S) than the high-concentration region (41) on the second terminal side, at a position that overlaps with the high-concentration region (41) on the second terminal side when viewed from above. The second terminal side contact area (43) of the first conductivity type is disposed on the surface layer of the low concentration area (42) on the second terminal side; and The second separation groove (121B) is disposed on the first surface (20S) in such a way as to surround the high concentration region (41) on the second terminal side, the low concentration region (42) on the second terminal side, and the contact region (43) on the second terminal side. The first pin junction (30) is formed by the high concentration region (31) on the first terminal side, the low concentration region (32) on the first terminal side, and the contact region (33) on the first terminal side. The second pin junction (40) is formed by the high concentration region (41) on the second terminal side, the low concentration region (42) on the second terminal side, and the contact region (43) on the second terminal side.

[0415] (Note A16) According to the TVS diode described in Appendix A15, wherein, The semiconductor chip (20) includes: A first separation insulating layer (122A) is disposed within the first separation trench (121A); and The second separation insulation layer (122B) is disposed within the second separation trench (121B).

[0416] (Note A17) According to the TVS diode described in Appendix A16, wherein, include: The first separation electrode (123A) is embedded in the first separation trench (121A) through the first separation insulating layer (122A); and The second separation electrode (123B) is embedded in the second separation trench (121B) through the second separation insulating layer (122B). Both the first separation electrode (123A) and the second separation electrode (123B) are in an electrically floating state.

[0417] (Note A18) The TVS diode according to any one of Appendices A15 to A17, wherein, The high-concentration region (61) includes a region adjacent to at least one of the first separation trench (121A) and the second separation trench (121B) under the top view.

[0418] (Note A19) The TVS diode according to any one of Appendices A1 to A3, wherein, The third pin junction (50) includes a third pin junction (50) in a first polarity direction. The third pin junction (50) in the first polarity direction is disposed in a region of the semiconductor chip (20) that is biased against the first surface (20S) and is separated from the first pin junction (30) and the second pin junction (40) when viewed from above. The diode pair region (60) includes: A third low-concentration region (62C) of the first conductivity type is disposed in a region that is closer to the first surface (20S) than the high-concentration region (61), at a position overlapping the high-concentration region (61) in a top-view view, and is separated from both the first low-concentration region (62A) and the second low-concentration region (62B). The impurity concentration of the third low-concentration region (62C) is lower than the impurity concentration of the high-concentration region (61). The third contact region (63C) of the second conductivity type is disposed on the surface portion of the third low concentration region (62C). The separation region (65) separates the first low-concentration region (62A) and the second low-concentration region (62B) from the third low-concentration region (62C). The high-concentration region (61), the third low-concentration region (62C), and the third contact region (63C) form a third reverse pin junction (60C) in the second polarity direction. The pn junction (60E) is configured to be connected in reverse relative to the third reverse pin junction (60C). The internal region (64) is arranged in a manner that overlaps with the first low-concentration region (62A), the second low-concentration region (62B) and the third low-concentration region (62C) in the top view.

[0419] (Note A20) According to the TVS diode described in Appendix A19, wherein, The semiconductor chip (20) includes: The high-concentration region (31) on the first terminal side of the second conductivity type is separated from the first surface (20S) of the semiconductor chip (20) by being biased toward the second surface (20R); The first terminal side low concentration region (32) of the first conductivity type is disposed in a region that is closer to the first surface (20S) than the first terminal side high concentration region (31) at a position that overlaps with the first terminal side high concentration region (31) when viewed from above. The first terminal side contact area (33) of the first conductivity type is provided on the surface of the low concentration area (32) of the first terminal side; The first defined area (34) is located in a region that is closer to the first surface (20S) than the high concentration area (31) on the first terminal side, and overlaps with the high concentration area (31) on the first terminal side when viewed from above, and is set in such a way as to surround the low concentration area (32) on the first terminal side. The high-concentration region (41) on the second terminal side of the second conductivity type is located at a position separated from the first surface (20S) of the semiconductor chip (20) by being biased toward the second surface (20R), and is separated from the high-concentration region (31) on the first terminal side when viewed from above. The low-concentration region (42) on the second terminal side of the first conductivity type is disposed in a region that is closer to the first surface (20S) than the high-concentration region (41) on the second terminal side, at a position that overlaps with the high-concentration region (41) on the second terminal side when viewed from above. The second terminal side contact area (43) of the first conductivity type is provided on the surface of the low concentration area (42) of the second terminal side; The second defined area (44) is located in a region that is closer to the first surface (20S) than the high concentration area (41) on the second terminal side, and overlaps with the high concentration area (41) on the second terminal side when viewed from above, and is set in such a way as to surround the low concentration area (42) on the second terminal side. The high-concentration region (51) on the third terminal side of the second conductivity type is located at a position separated from the first surface (20S) of the semiconductor chip (20) by being biased toward the second surface (20R), and is separated from both the high-concentration region (31) on the first terminal side and the high-concentration region (41) on the second terminal side when viewed from above. The low-concentration region (52) on the third terminal side of the first conductivity type is disposed in a region that is closer to the first surface (20S) than the high-concentration region (51) on the third terminal side, at a position that overlaps with the high-concentration region (51) on the third terminal side when viewed from above. The third terminal-side contact region (53) of the first conductivity type is disposed on the surface portion of the low-concentration region (52) on the third terminal side; and The third defined region (54) is located in a region that is closer to the first surface (20S) than the high concentration region (51) on the third terminal side, at a position that overlaps with the high concentration region (51) on the third terminal side when viewed from above, and is configured to surround the low concentration region (52) on the third terminal side. The first pin junction (30) is formed by the high concentration region (31) on the first terminal side, the low concentration region (32) on the first terminal side, and the contact region (33) on the first terminal side. The second pin junction (40) is formed by the high concentration region (41) on the second terminal side, the low concentration region (42) on the second terminal side, and the contact region (43) on the second terminal side. The third pin junction (50) is formed by the high concentration region (51) on the third terminal side, the low concentration region (52) on the third terminal side, and the contact region (53) on the third terminal side.

[0420] (Note A21) According to Appendix A20, the TVS diode, wherein, include: An insulating layer (70) covers the first surface (20S); The first connecting electrode (81) is disposed on the insulating layer (70) to connect the first contact area (63A) with the first terminal side contact area (33); A second connecting electrode (82) is disposed on the insulating layer (70) to connect the second contact area (63B) to the second terminal-side contact area (43); and The third connecting electrode (83) is disposed on the insulating layer (70) to connect the third contact area (63C) to the third terminal side contact area (53).

[0421] (Note A22) According to the TVS diode described in Appendix A21, wherein, The separation region (65) includes an exposed surface (65S) that is exposed from the first surface (20S). The TVS diode includes wiring (90) connected to the exposed surface (65S). The separation region (65) includes: The first separation region (65A) overlaps with the first connecting electrode (81) under the top view; The second separation region (65B) overlaps with the second connecting electrode (82) under the top view; The third separation region (65C) overlaps with the third connecting electrode (83) under the top view; and The wiring connection area (65P) is connected to the wiring (90). The wiring connection area (65P) is arranged in a manner that independently and partially surrounds the first reverse pin junction (60A), the second reverse pin junction (60B) and the third reverse pin junction (60C) when viewed from above.

[0422] (Note A23) According to the TVS diode described in Appendix A22, wherein, The wiring (90) is arranged in a manner that independently and locally surrounds the first connecting electrode (81), the second connecting electrode (82) and the third connecting electrode (83) in the top view.

[0423] (Note A24) According to the TVS diode described in Appendix A19, wherein, The semiconductor chip (20) includes: The high-concentration region (31) on the first terminal side of the second conductivity type is separated from the first surface (20S) of the semiconductor chip (20) by being biased toward the second surface (20R); The first terminal side low concentration region (32) of the first conductivity type is disposed in a region that is closer to the first surface (20S) than the first terminal side high concentration region (31) at a position that overlaps with the first terminal side high concentration region (31) when viewed from above. The first terminal side contact area (33) of the first conductivity type is provided on the surface of the low concentration area (32) of the first terminal side; The first separation trench (121A) is disposed on the first surface (20S) in such a way as to surround the high concentration region (31) on the first terminal side, the low concentration region (32) on the first terminal side, and the contact region (33) on the first terminal side. The high-concentration region (41) on the second terminal side of the second conductivity type is located at a position separated from the first surface (20S) of the semiconductor chip (20) by being biased toward the second surface (20R), and is separated from the high-concentration region (31) on the first terminal side when viewed from above. The low-concentration region (42) on the second terminal side of the first conductivity type is disposed in a region that is closer to the first surface (20S) than the high-concentration region (41) on the second terminal side, at a position that overlaps with the high-concentration region (41) on the second terminal side when viewed from above. The second terminal side contact area (43) of the first conductivity type is provided on the surface of the low concentration area (42) of the second terminal side; The second separation groove (121B) is disposed on the first surface (20S) in such a way as to surround the high concentration region (41) on the second terminal side, the low concentration region (42) on the second terminal side, and the contact region (43) on the second term...

Claims

1. A TVS diode comprising a semiconductor chip, said semiconductor chip having a first side and a second side located on a side opposite to the first side, wherein, The semiconductor chip includes: A first pin junction and a second pin junction of a first polarity direction are disposed in a region of the semiconductor chip adjacent to the first surface; and The diode pair region includes a first reverse pin junction, a second reverse pin junction, and a pn junction with a first polarity direction. The first reverse pin junction and the second reverse pin junction are disposed in a region of the semiconductor chip biased towards the first surface. The pn junction with the first polarity direction is disposed at a position overlapping the first reverse pin junction and the second reverse pin junction when viewed from above in the thickness direction of the semiconductor chip, and forms a diode pair with the first reverse pin junction and the second reverse pin junction. The diode pair region is separated from the first pin junction and the second pin junction when viewed from above. The diode pair region is disposed between the first pin junction and the second pin junction as viewed from above.

2. The TVS diode according to claim 1, wherein, The first pin junction and the first reverse pin junction are arranged along the first direction when viewed from above. The second pin and the second reverse pin are arranged along the first direction when viewed from above. The first pin junction and the second reverse pin junction are adjacent in a second direction orthogonal to the first direction when viewed from above. The first reverse pin junction and the second pin junction are adjacent in the second direction when viewed from above. The diode pair region includes the area between the first pin junction and the second pin junction disposed in the direction intersecting the first direction and the second direction under the top view.

3. The TVS diode according to claim 2, wherein, The diode pair region includes: The first region is provided with the first reverse pin junction; and The second region is equipped with the second reverse pin junction. The second region includes a region that is offset from the first region in the first direction.

4. The TVS diode according to claim 3, wherein, The first region, viewed from above, is adjacent to the second pin junction in the second direction. The second region is adjacent to the first pin junction in the second direction when viewed from above.

5. The TVS diode according to claim 1, wherein, The diode pair region, viewed from above, is positioned in a first direction between the first pin junction and the second pin junction. The first pin junction is positioned side-by-side with the first reverse pin junction and the second reverse pin junction when viewed from above. The second pin junction is positioned side-by-side with the first reverse pin junction and the second reverse pin junction when viewed from above.

6. The TVS diode according to any one of claims 2 to 4, wherein, The diode pair region includes: The high-concentration region of the first conductivity type is separated from the first surface of the semiconductor chip by being positioned biased towards the second surface; The first low-concentration region and the second low-concentration region of the first conductivity type are disposed in the region of the semiconductor chip that is biased against the first surface, at a position that overlaps with the high-concentration region when viewed from above, and are separated from each other. The impurity concentration of the first low-concentration region and the impurity concentration of the second low-concentration region are lower than the impurity concentration of the high-concentration region. A separation region is set in a region that is closer to the first surface than the high concentration region, at a position that overlaps with the high concentration region when viewed from above, to electrically separate the first low concentration region from the second low concentration region; The first contact area of ​​the second conductivity type is disposed on the surface layer of the first low concentration area; A second contact region of a second conductivity type is disposed on the surface portion of the second low concentration region; and The internal region of the second conductivity type is positioned at a location overlapping the high-concentration region in the top-view view, and is connected to the high-concentration region at a position relative to the high-concentration region, closer to the second surface. The first reverse pin junction is formed by the high-concentration region, the first low-concentration region, and the first contact region. The second reverse pin junction is formed by the high-concentration region, the second low-concentration region, and the second contact region. The pn junction is formed by the high-concentration region and the internal region, which are in reverse connection with respect to the first reverse pin junction and the second reverse pin junction.

7. The TVS diode according to claim 6, in, include: An insulating layer covers the first surface; A first connecting electrode is disposed on the insulating layer, electrically connecting the first contact area to the first pin junction; and The second connecting electrode is disposed on the insulating layer, and electrically connects the second contact area to the second pin junction.

8. The TVS diode according to claim 7, wherein, The first connecting electrode and the second connecting electrode are arranged separately from each other in the second direction when viewed from above. The first connecting electrode and the second connecting electrode extend along the first direction when viewed from above.

9. The TVS diode according to claim 7 or 8, in, include: A protective layer covers the first connecting electrode and the second connecting electrode; A first terminal is disposed on the protective layer and electrically connected to the first pin junction; and The second terminal is disposed on the protective layer and electrically connected to the second pin junction. The protective layer includes: The first terminal opening partially exposes the first connecting electrode; and The second terminal opening partially exposes the second connecting electrode. The first terminal is electrically connected to the first connecting electrode through the opening of the first terminal. The second terminal is electrically connected to the second connecting electrode through the second terminal opening.

10. The TVS diode according to any one of claims 2 to 4, wherein, The semiconductor chip includes: A third pin junction with a first polarity direction is disposed in a region of the semiconductor chip biased towards the first surface; and A third reverse pin junction with a second polarity direction is disposed in a region of the semiconductor chip biased towards the first surface and forms a diode pair with the pn structure. Under the aforementioned top-down view, the third pin junction and the third reverse pin junction are arranged along the first direction and electrically connected to each other. The third pin and the third reverse pin, as viewed from above, are configured to be adjacent to the second pin and the second reverse pin on the side opposite to the first pin and the first reverse pin in the second direction, relative to the second pin and the second reverse pin. The third pin junction and the second reverse pin junction are adjacent in the second direction when viewed from above. The third reverse pin junction and the second pin junction are adjacent in the second direction when viewed from above. The diode pair region includes the area between the second pin junction and the third pin junction disposed in a direction that intersects the first direction and the second direction in the top view.

11. The TVS diode according to claim 10, wherein, The diode pair region includes: The high-concentration region of the first conductivity type is separated from the first surface of the semiconductor chip by being positioned biased towards the second surface; The first low-concentration region, the second low-concentration region, and the third low-concentration region of the first conductivity type are disposed in the region of the semiconductor chip that is biased against the first surface, at a position that overlaps with the high-concentration region when viewed from above, and are separated from each other. The impurity concentration of the first low-concentration region, the impurity concentration of the second low-concentration region, and the impurity concentration of the third low-concentration region are lower than the impurity concentration of the high-concentration region. A separation region is set in a region that is closer to the first surface than the high concentration region, at a position that overlaps with the high concentration region when viewed from above, to electrically separate the first low concentration region, the second low concentration region, and the third low concentration region; The first contact area of ​​the second conductivity type is disposed on the surface layer of the first low concentration area; The second contact region of the second conductivity type is disposed on the surface layer of the second low concentration region; A third contact region of the second conductivity type is disposed on the surface portion of the third low concentration region; and The internal region of the second conductivity type is positioned at a location overlapping the high-concentration region in the top-view view, and is connected to the high-concentration region at a position relative to the high-concentration region, closer to the second surface. The first reverse pin junction is formed by the high-concentration region, the first low-concentration region, and the first contact region. The second reverse pin junction is formed by the high-concentration region, the second low-concentration region, and the second contact region. The third reverse pin junction is formed by the high-concentration region, the third low-concentration region, and the third contact region. The pn junction is formed by the high-concentration region and the inner region, which are in reverse connection with respect to the first reverse pin junction, the second reverse pin junction and the third reverse pin junction.

12. The TVS diode according to claim 11, wherein, The high-concentration region includes: The first region is provided with the first reverse pin junction; The second region is provided with the second reverse pin junction; and The third region is equipped with the aforementioned third reverse pin junction. The second region includes regions that are offset from the first region and the third region in the first direction.

13. The TVS diode according to claim 12, wherein, The second region includes the portion between the first pin junction and the third pin junction disposed in the second direction. The first region and the third region include portions adjacent to the second pin junction in the second direction.

14. The TVS diode according to any one of claims 11 to 13, wherein, The semiconductor chip includes: The high-concentration region on the first terminal side of the second conductivity type is separated from the first surface of the semiconductor chip by being biased towards the second surface; The low-concentration region on the first terminal side of the first conductivity type is disposed in a region of the semiconductor chip that is biased against the first surface, at a position that overlaps with the high-concentration region on the first terminal side when viewed from above. The first terminal side contact area of ​​the first conductivity type is disposed on the surface layer of the low concentration region on the first terminal side. The first defined region is located in the region of the semiconductor chip that is biased towards the first surface, at a position that overlaps with the high-concentration region on the first terminal side when viewed from above, and is configured to surround the low-concentration region on the first terminal side. The high-concentration region on the second terminal side of the second conductivity type is located at a position separated from the first surface of the semiconductor chip by being biased towards the second surface, and is separated from the high-concentration region on the first terminal side when viewed from above. The low-concentration region on the second terminal side of the first conductivity type is disposed in the region of the semiconductor chip that is biased against the first surface, at a position that overlaps with the high-concentration region on the second terminal side when viewed from above. The second defined region is located in the region of the semiconductor chip that is biased towards the first surface and overlaps with the high-concentration region on the second terminal side when viewed from above, and is configured to surround the low-concentration region on the second terminal side. The second terminal side contact area of ​​the first conductivity type is provided on the surface layer of the low concentration area on the second terminal side. The high-concentration region on the third terminal side of the second conductivity type is located at a position separated from the first surface of the semiconductor chip by being biased towards the second surface, and is separated from both the high-concentration region on the first terminal side and the high-concentration region on the second terminal side when viewed from above. The low-concentration region on the third terminal side of the first conductivity type is disposed in a region of the semiconductor chip that is biased against the first surface, at a position that overlaps with the high-concentration region on the third terminal side when viewed from above. The third terminal side contact region of the first conductivity type is provided in the surface layer of the low concentration region on the third terminal side; and The third defined region is located in the region of the semiconductor chip adjacent to the first surface, at a position that overlaps with the high-concentration region on the third terminal side when viewed from above, and is configured to surround the low-concentration region on the third terminal side. The first pin junction is formed by the high-concentration region on the first terminal side, the low-concentration region on the first terminal side, and the contact region on the first terminal side. The second pin junction is formed by the high-concentration region on the second terminal side, the low-concentration region on the second terminal side, and the contact region on the second terminal side. The third pin junction is formed by the high concentration region on the third terminal side, the low concentration region on the third terminal side, and the contact region on the third terminal side.

15. The TVS diode according to claim 14, in, include: An insulating layer covers the first surface; A first connecting electrode is disposed on the insulating layer to connect the first contact area with the first terminal side contact area. A second connecting electrode is disposed on the insulating layer, connecting the second contact area to the second terminal-side contact area; and A third connecting electrode is disposed on the insulating layer, connecting the third contact area to the third terminal side contact area.

16. The TVS diode according to claim 15, wherein, The first connecting electrode, the second connecting electrode, and the third connecting electrode are arranged separately from each other in the second direction when viewed from above. The first connecting electrode, the second connecting electrode, and the third connecting electrode extend along the first direction when viewed from above.

17. The TVS diode according to claim 15 or 16, in, include: A protective layer covers the first connecting electrode, the second connecting electrode, and the third connecting electrode; The first terminal is disposed on the protective layer and electrically connected to the first pin junction; The second terminal is disposed on the protective layer and electrically connected to the second pin junction; and The third terminal is disposed on the protective layer and electrically connected to the third pin junction. The protective layer includes: The first terminal opening exposes part of the first connecting electrode; The second terminal opening partially exposes the second connecting electrode; and The third terminal opening partially exposes the third connecting electrode. The first terminal is electrically connected to the first connecting electrode through the opening of the first terminal. The second terminal is electrically connected to the second connecting electrode through the opening of the second terminal. The third terminal is electrically connected to the third connecting electrode through the opening of the third terminal.

18. The TVS diode according to any one of claims 2 to 4, wherein, The semiconductor chip includes: The third and fourth pin junctions, in a first polarity direction, are disposed in a region of the semiconductor chip biased towards the first surface; and The third and fourth reverse pin junctions, with a second polarity orientation, are disposed in a region of the semiconductor chip biased towards the first surface and form a diode pair with the pn structure. The third pin and the third reverse pin are arranged along the first direction when viewed from above. The fourth pin and the fourth reverse pin are arranged along the first direction when viewed from above. The third pin and the third reverse pin, as viewed from above, are configured to be adjacent to the second pin and the second reverse pin on the side opposite to the first pin and the first reverse pin in the second direction, relative to the second pin and the second reverse pin. The fourth pin and the fourth reverse pin, as viewed from above, are configured to be adjacent to the third pin and the third reverse pin on the side opposite to the second pin and the second reverse pin in the second direction. The third pin junction and the second reverse pin junction are adjacent in the second direction when viewed from above. The third reverse pin junction and the second pin junction are adjacent in the second direction when viewed from above. The fourth pin and the third reverse pin are adjacent in the second direction when viewed from above. The fourth reverse pin junction and the third pin junction are adjacent in the second direction when viewed from above. The diode pair region includes the area between the third pin junction and the fourth pin junction disposed in a direction that intersects the first direction and the second direction in the top view.

19. The TVS diode according to claim 1, wherein, The semiconductor chip includes: The third and fourth pin junctions, in a first polarity direction, are disposed in a region of the semiconductor chip biased towards the first surface; and The third and fourth reverse pin junctions, with a second polarity orientation, are disposed in a region of the semiconductor chip biased towards the first surface and form a diode pair with the pn structure. The first pin, the first reverse pin, and the second pin are arranged along a first direction when viewed from above, and the first reverse pin is positioned between the first pin and the second pin in the first direction. The third pin, the fourth reverse pin, and the fourth pin are arranged along the first direction when viewed from above, and the fourth reverse pin is positioned between the third pin and the fourth pin in the first direction. The first pin, the third reverse pin, and the third pin are arranged along a second direction orthogonal to the first direction when viewed from above, and the third reverse pin is positioned between the first pin and the third pin in the second direction. The second pin, the second reverse pin, and the fourth pin are arranged along the second direction when viewed from above, and the second reverse pin is positioned between the second pin and the fourth pin in the second direction.

20. The TVS diode according to any one of claims 1 to 19, wherein, The first polarity direction refers to the direction in which the forward current flows from the second surface toward the first surface along the thickness direction of the semiconductor chip. The second polarity direction refers to the direction in which the positive current, which is opposite to the first polarity direction, flows in the thickness direction of the semiconductor chip.

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