Oled color patterning based on lithography and chemical mechanical polishing

Abstract

In one or more embodiments, a sub-pixel includes adjacent overhang structures disposed over a substrate. Each overhang structure has an upper portion having a top surface and a bottom surface. The bottom surface is wider than a top surface of a lower portion. The adjacent overhang structures define an opening of the sub-pixel. An anode is disposed over the substrate between the adjacent overhang structures. An organic light emitting diode (OLED) material is disposed over the anode. A cathode is disposed over the OLED material. An encapsulation layer is disposed over the cathode. The encapsulation layer extends along sidewalls of the lower portion under at least a portion of the overhang structures and contacts the bottom surface of the upper portion of the overhang structures.

Description

Background Technology

[0001] field

[0002] The embodiments described herein generally relate to a display. More specifically, the embodiments described herein relate to subpixel circuits and methods of forming subpixel circuits, which can be used in displays such as organic light-emitting diode (OLED) displays.

[0003] Related technical descriptions

[0004] Input devices, including display devices, are used in a wide variety of electronic systems. Organic light-emitting diodes (OLEDs) are light-emitting diodes (LEDs) in which the emitting electroluminescent layer is a film of an organic compound, emitting light in response to an electric current. OLED devices are classified as bottom-emitting devices if the emitted light passes through a transparent or translucent bottom electrode and the substrate on which the panel is fabricated. Top-emitting devices are classified based on whether the light emitted from the OLED device passes through a cover added after the device is manufactured. Today, OLEDs are used to form display devices in many electronic products. Electronics manufacturers are currently pushing these display devices to shrink in size while offering higher resolutions than just a few years ago.

[0005] OLED pixel patterning is currently based on a process that limits panel size, pixel resolution, and substrate size. Instead of using fine metal masks, lithography is used to pattern pixels. Currently, OLED pixel patterning requires the removal of organic materials after the patterning process. During removal, the organic material leaves behind particles that interfere with OLED performance. Therefore, there is a need in the art for sub-pixel circuits and methods for forming these circuits to increase the number of pixels per inch and provide improved OLED performance. Summary of the Invention

[0006] The embodiments described herein generally relate to a display. More specifically, the embodiments described herein relate to subpixel circuitry that can be used in a display and methods for forming subpixel circuitry, such as in an organic light-emitting diode (OLED) display.

[0007] In one or more embodiments, a sub-pixel includes adjacent overhang structures disposed above a substrate. Each overhang structure has an upper portion having a top surface and a bottom surface. The bottom surface is wider than the top surface of the lower portion. The adjacent overhang structures define an opening for the sub-pixel. An anode is disposed above the substrate between the adjacent overhang structures. An organic light-emitting diode (OLED) material is disposed above the anode. A cathode is disposed above the OLED material. An encapsulation layer is disposed above the cathode. The encapsulation layer extends along the sidewall of the lower portion below at least a portion of the overhang structure and contacts the bottom surface of the upper portion of the overhang structure. The encapsulation layer has an uppermost surface coplanar with the top surfaces of the upper portions of the adjacent overhang structures. An intermediate encapsulation layer is deposited above the encapsulation layer. The intermediate encapsulation layer extends above the upper portions of the overhang structures. A global encapsulation layer is deposited above the intermediate encapsulation layer.

[0008] In one or more embodiments, a device includes a plurality of sub-pixels. The plurality of sub-pixels includes at least a first sub-pixel and a second sub-pixel. Each first and second sub-pixel includes an adjacent overhang structure disposed over a substrate. Each overhang structure has an upper portion having a top surface and a bottom surface. The bottom surface is wider than the top surface of the lower portion. The adjacent overhang structures define an opening in the sub-pixel. An anode is disposed over the substrate between the adjacent overhang structures. An organic light-emitting diode (OLED) material is disposed over the anode. A cathode is disposed over the OLED material. An encapsulation layer is disposed over the cathode. The encapsulation layer extends along the sidewall of the lower portion below at least a portion of the overhang structure and contacts the bottom surface of the upper portion of the overhang structure. The encapsulation layer has a uppermost surface coplanar with the top surfaces of the upper portions of the adjacent overhang structures. An intermediate encapsulation layer is deposited over the encapsulation layer. The intermediate encapsulation layer extends over the upper portions of the overhang structures. A global encapsulation layer is deposited over the intermediate encapsulation layer.

[0009] In one or more embodiments, a method of manufacturing a sub-pixel device includes depositing a plurality of anodes over a substrate and patterning a plurality of pixel-defining layer (PDL) structures over the substrate. The method further includes depositing a lower portion material over the substrate, depositing an upper portion material over the substrate, and forming a first sub-pixel opening in the lower and upper portion materials. The first sub-pixel opening defines an adjacent overhang structure. The adjacent overhang structure has an upper portion having a top surface and a bottom surface. The bottom surface is wider than the top surface of the lower portion. The method further includes performing a first deposition process. The first deposition process includes depositing a first OLED material, a first cathode, and a first encapsulation layer within the first sub-pixel opening. A portion of the first OLED material, the first cathode, and the first encapsulation layer extends above the upper surface of the upper portion material. The method further includes performing a first CMP process to remove the portion of the first OLED material, the first cathode, and the first encapsulation layer extending above the upper surface of the upper portion material. Attached Figure Description

[0010] To gain a more detailed understanding of the features described above in this disclosure, a more specific description of the disclosure, which has been briefly outlined above, can be obtained with reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate exemplary embodiments only and are therefore not intended to limit the scope of the embodiments, and other equally effective embodiments are appreciated.

[0011] Figure 1A This is a schematic cross-sectional view of a sub-pixel circuit according to one or more embodiments.

[0012] Figure 1B This is a schematic top view of a subpixel circuit with a dot-type architecture according to one or more embodiments.

[0013] Figure 1C This is a schematic top view of a sub-pixel circuit with a linear architecture according to one or more embodiments.

[0014] Figure 2 This is a flowchart of an on-demand CMP method for forming sub-pixel circuits according to one or more embodiments.

[0015] Figures 3A to 3N This is a schematic cross-sectional view of a substrate during a method for forming a sub-pixel circuit according to an embodiment.

[0016] Figures 4A to 4F This is a close-up schematic cross-sectional view of the upper portion of the overhang structure of the sub-pixel circuit according to an embodiment.

[0017] Figures 5A to 5F This is a close-up schematic cross-sectional view of the upper portion of the overhang structure of the sub-pixel circuit according to an embodiment.

[0018] To facilitate understanding, the same element symbols have been used where possible to denote common elements across the figures. It is contemplated that elements and features of one embodiment can be advantageously incorporated into other embodiments without further description. Detailed Implementation

[0019] The embodiments described herein generally relate to displays. More specifically, the embodiments described herein relate to subpixel circuits and methods of forming subpixel circuits, which can be used in displays such as organic light-emitting diode (OLED) displays. In one embodiment that can be combined with other embodiments described herein, the display is a bottom-emitting (BE) or top-emitting (TE) OLED display. In another embodiment that can be combined with other embodiments described herein, the display is a passive-matrix (PM) or active-matrix (AM) OLED display.

[0020] A first exemplary embodiment of the embodiments described herein includes a subpixel circuit with a dot-matrix architecture. A second exemplary embodiment of the embodiments described herein includes a subpixel circuit with a linear architecture. Each of the subpixel circuits in the embodiments described herein (including the exemplary embodiments) includes a plurality of subpixels, wherein each of the subpixels is defined by adjacent overhang structures, and these adjacent overhang structures are permanent to the subpixel circuit. Although the figures depict two subpixels, each defined by adjacent inorganic overhang structures, the subpixel circuits of the embodiments described herein include a plurality of subpixels, such as two or more subpixels, such as three or more subpixels. Each subpixel has an OLED material configured to emit white, red, green, blue, or other colored light when powered on. For example, the OLED material of the first subpixel emits green light when powered on, the OLED material of the second subpixel emits red light when powered on, and the OLED material of the third subpixel emits blue light when powered on.

[0021] The inorganic overhang structure is permanent to the sub-pixel circuit and includes at least an upper portion disposed on a lower portion. A first configuration of the inorganic overhang structure includes an upper portion of non-conductive inorganic material and a lower portion of conductive inorganic material. A second configuration of the inorganic overhang structure includes an upper portion of conductive inorganic material and a lower portion of conductive inorganic material. A third configuration of the inorganic overhang structure includes an upper portion of non-conductive inorganic material, a lower portion of non-conductive inorganic material, and an auxiliary cathode disposed below the lower portion. A fourth configuration of the inorganic overhang structure includes an upper portion of conductive inorganic material, a lower portion of non-conductive inorganic material, and an auxiliary cathode disposed below the lower portion. Each of the exemplary embodiments includes an inorganic overhang structure in at least one of the first, second, third, or fourth configurations.

[0022] Adjacent inorganic overhang structures for each subpixel of a display's subpixel circuitry are provided for forming the subpixel circuitry using vapor deposition, and for maintaining the inorganic overhang structures in place after the subpixel circuitry is formed. Vapor deposition can be used to deposit OLED material (including a hole injection layer (HIL), a hole transport layer (HTL), an emitter layer (EML), and an electron transport layer (ETL)) and a cathode. One or more of an encapsulation layer and an overall passivation layer can be disposed via vapor deposition. In embodiments including one or more capping layers, the capping layer is disposed between the cathode and the encapsulation layer. The inorganic overhang structures define the deposition angle of each of the OLED material and the cathode, i.e., providing a shielding effect during vapor deposition such that the OLED material does not contact the lower portion (and, according to embodiments with a third and fourth configuration, does not contact the auxiliary cathode) and the cathode contacts the lower portion according to a first and second configuration, or at least contacts the auxiliary cathode according to a third and fourth configuration. In one or more embodiments, both the OLED material and the cathode contact the lower portion. The encapsulation layer of the corresponding sub-pixel is disposed above the cathode, wherein the encapsulation layer extends below at least a portion of each of the adjacent inorganic overhang structures and extends along the sidewall of each of the adjacent inorganic overhang structures.

[0023] Figure 1A This is a schematic cross-sectional view of a sub-pixel circuit 100 according to one or more embodiments. The sub-pixel circuit 100 may have, for example... Figure 1B The point-type architecture 101A shown or as follows Figure 1C The linear architecture 101B is shown. Figure 1A The cross-sectional view is along Figure 1B and Figure 1C The section line 1''-1'' was used to cut the section.

[0024] Subpixel circuitry 100 includes a substrate 102. A metal layer 104 may be patterned on or above the substrate 102 and is defined by adjacent pixel defining layer (PDL) structures 126 disposed on or above the substrate 102. In one embodiment, which may be combined with other embodiments described herein, the metal layer 104 is pre-patterned on or above the substrate 102. For example, the substrate 102 is a pre-patterned indium tin oxide (ITO) glass substrate. The metal layer 104 is configured to operate the anode of a respective subpixel. The metal layer 104 includes, but is not limited to, chromium, titanium, gold, silver, copper, aluminum, ITO, combinations thereof, or other suitable conductive materials. In one or more embodiments, each of the metal layers 104 is a layer stack of a first transparent conductive oxide (TCO) layer, a second metal-containing layer disposed on the first TCO layer, and a third TCO layer disposed on the second metal-containing layer.

[0025] PDL structure 126 is disposed on or above substrate 102. PDL structure 126 comprises one of organic materials, organic materials with an inorganic coating disposed thereon, or inorganic materials. The organic materials of PDL structure 126 include, but are not limited to, polyimide. The inorganic materials of PDL structure 126 include, but are not limited to, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (Si2N2O), magnesium fluoride (MgF2), or combinations thereof. Adjacent PDL structures 126 define corresponding sub-pixels and expose the anode (i.e., metal layer 104) of the corresponding sub-pixel of sub-pixel circuit 100.

[0026] The subpixel circuit 100 has a plurality of subpixels 108, including at least a first subpixel 108a and a second subpixel 108B. Although the first subpixel 108a and the second subpixel 108B are depicted in the accompanying drawings, the subpixel circuit 100 of the embodiments described herein may include two or more subpixels 108, such as a third subpixel and a fourth subpixel. Each subpixel 108 has an OLED material 112 configured to emit white, red, green, blue, or other colored light when powered on. For example, the OLED material 112 of the first subpixel 108a emits green light when powered on, the OLED material of the second subpixel 108B emits red light when powered on, the OLED material of the third subpixel emits blue light when powered on, and the OLED material of the fourth subpixel emits another color of light when powered on.

[0027] Inorganic overhang structure 110 is disposed on or above the upper surface of each of the PDL structures 126. Inorganic overhang structure 110 is permanent to the sub-pixel circuit. Inorganic overhang structure 110 further defines each sub-pixel 108 of the sub-pixel circuit 100. Inorganic overhang structure 110 includes at least an upper portion 110B disposed on or above the lower portion 110A. A first configuration of inorganic overhang structure 110 includes an upper portion 110B of non-conductive inorganic material and a lower portion 110A of conductive inorganic material. A second configuration of inorganic overhang structure 110 includes an upper portion 110B of conductive inorganic material and a lower portion 110A of conductive inorganic material. A third configuration of inorganic overhang structure 110 includes an upper portion 110B of non-conductive inorganic material, a lower portion 110A of non-conductive inorganic material, and an auxiliary cathode disposed below the lower portion 110A. The fourth configuration of the inorganic overhang structure 110 includes an upper portion 110B of conductive inorganic material, a lower portion 110A of non-conductive inorganic material, and an auxiliary cathode disposed below the lower portion 110A. It is contemplated that, in one or more embodiments, the first and second configurations further include the auxiliary cathode disposed below the lower portion 110A. The first, second, third, and fourth exemplary embodiments of the sub-pixel circuit 100 include an inorganic overhang structure 110 in at least one of the first, second, third, or fourth configurations. The inorganic overhang structure 110 can be held in place, i.e., permanently. Therefore, no organic material that interferes with OLED performance is left from being peeled off the overhang structure. Eliminating the need for a peeling process also increases throughput.

[0028] Non-conductive inorganic materials include, but are not limited to, silicon-containing inorganic materials. For example, silicon-containing materials include silicon oxides or nitrides, or combinations thereof. Conductive inorganic materials include, but are not limited to, metallic materials. For example, metallic materials include copper, titanium, aluminum, molybdenum, silver, indium tin oxide, indium zinc oxide, chromium, or combinations thereof.

[0029] At least the bottom surface 107 of the upper portion 110B is wider than the top surface 105 of the lower portion 110A to form an overhang 109. The bottom surface 107 being larger than the top surface 105 to form the overhang 109 allows the upper portion 110B to shield the lower portion 110A. The shielding provided by the overhang 109 provides for the vapor deposition of each of the OLED material 112 and the cathode 114.

[0030] OLED material 112 may include one or more of HIL, HTL, EML, and ETL. OLED material 112 is disposed on metal layer 104. In some embodiments that may be combined with other embodiments described herein, OLED material 112 is disposed on metal layer 104 and over a portion of PDL structure 126. Cathode 114 is disposed on or over OLED material 112 of PDL structure 126 in each sub-pixel 108. Cathode 114 includes a conductive material, such as a metal. For example, cathode 114 includes, but is not limited to, silver, chromium, titanium, aluminum, ITO, or combinations thereof. Auxiliary cathodes include, but are not limited to, metal-containing materials. For example, metal-containing materials include copper, titanium, aluminum, molybdenum, silver, indium tin oxide, indium zinc oxide, chromium, or combinations thereof.

[0031] Each sub-pixel 108 includes an encapsulation layer 116. The encapsulation layer 116 may be or may correspond to a local passivation layer. The encapsulation layer 116 of the respective sub-pixel is disposed over the cathode 114 (and OLED material 112), wherein the encapsulation layer 116 extends below at least a portion of each of the inorganic overhang structures 110 and extends along the sidewall of each of the inorganic overhang structures 110. The encapsulation layer 116 is disposed over the cathode 114 and over at least the sidewall 111 of the lower portion 110A. In some embodiments that may be combined with other embodiments described herein, the encapsulation layer 116 is disposed over the upper sidewall 113 of the upper portion 110B. The encapsulation layer 116 comprises a non-conductive inorganic material, such as a silicon-containing material. The silicon-containing material may include a Si3N4-containing material.

[0032] In embodiments including one or more capping layers, the capping layer is disposed between the cathode 114 and the encapsulation layer 116. Although Figure 1A The subpixel circuit 100 is depicted without any capping layer, but each of the embodiments described herein may include one or more capping layers disposed between the cathode 114 and the encapsulation layer 116.

[0033] The sub-pixel circuit 100 further includes at least a global encapsulation layer 120 disposed above the inorganic overhang structure 110 and the encapsulation layer 116. An intermediate encapsulation layer 118 may be disposed between the global encapsulation layer 120, the top surface 115 of the upper portion 110B of the inorganic overhang structure 110, and the encapsulation layer 116. The intermediate encapsulation layer 118 may comprise an acrylic material.

[0034] Figure 1B This is a schematic top view of a sub-pixel circuit 100 having a dot-type architecture 101A according to one or more embodiments. Figure 1C This is a schematic top view of a sub-pixel circuit 100 having a linear architecture 101B according to one or more embodiments.

[0035] The dot-matrix architecture 101A includes a plurality of pixel openings 124A. Each of the pixel openings 124A is surrounded by inorganic overhang structures 110, which define each of the sub-pixels 108 of the dot-matrix architecture 101A. The linear architecture 101B includes a plurality of pixel openings 124B. Each of the pixel openings 124B is adjacent to the inorganic overhang structures 110, which define each of the sub-pixels 108 of the linear architecture 101B.

[0036] Figure 2 This is a flowchart of an on-demand CMP method 200 for forming a sub-pixel circuit 100 according to one or more embodiments. The on-demand CMP method 200 corresponds to an on-demand method for manufacturing a sub-pixel circuit 100 having a dot-type architecture 101A or a line-type architecture 101B. Figures 3A to 3N This is a schematic cross-sectional view of the substrate 102 during a method 200 for forming a sub-pixel circuit 100 according to an embodiment.

[0037] At operation 201, such as Figure 3A As shown, multiple metal layers 104 are patterned on or above a substrate 102. In one or more embodiments, the metal layers 104 are formed of multiple layers. Figure 3A1 This is a close-up schematic cross-sectional view of a portion of metal layer 104. Metal layer 104 includes a first layer 304A. The first layer 304A is formed of a first material comprising indium tin oxide (ITO). A second layer 304B is formed over the first layer 304A. The second layer 304B is formed of a second material comprising silver (Ag). A third layer 304C is formed over the second layer 304B. The third layer 304C is formed of a third material comprising ITO. In one or more embodiments, the first material and the third material are the same. Metal layer 104 has a thickness T1. The thickness T1 is from about 100 nm to about 200 nm.

[0038] At operation 202, such as Figure 3B As shown, a PDL material 326 is deposited over the substrate 102 and the metal layer 104. In one or more embodiments, the PDL material comprises silicon nitride (SiN). x The PDL material has a PDL material thickness T2 when it is deposited. The PDL material thickness T2 is approximately 100 nm to approximately 1000 nm.

[0039] At operation 203, such as Figure 3C As shown, a chemical mechanical planarization (CMP) process is used to planarize the PDL material 326. The PDL material thickness T2 is changed to the planarized PDL material thickness T2'. The planarized PDL material thickness T2' is approximately 100 nm to approximately 800 nm. It is contemplated that, in one or more embodiments, operation 203 is optional when performing method 200.

[0040] At operation 204, such as Figure 3D As shown, a patterning process is performed on PDL material 326 to form PDL structure 126. During the patterning process, photoresist is deposited over PDL material 326. Then, a photolithography process is used to pattern the desired pattern onto the photoresist. After the photolithography process, the desired portion of the photoresist is removed, thereby exposing the PDL material 326 beneath the photoresist. A dry etching process is performed on the exposed areas of the PDL material. The exposed areas of the PDL material 326 are etched away to expose a portion of each of the metal layers 104. After the dry etching process is complete, the remaining photoresist is stripped away, thereby forming the PDL structure.

[0041] At operation 205, such as Figure 3E As shown, a lower portion material 310A is deposited above the metal layer 104 and the PDL structure 126. The lower portion material 310A may comprise a conductive inorganic material or a non-conductive inorganic material. The lower portion material 310A comprises the same material as the lower portion 110A of the overhang structure. At operation 206, as... Figure 3F As shown, a chemical mechanical planarization (CMP) process is used to planarize the lower portion of material 310A. In operation 207, as... Figure 3G As shown, an upper portion material 310B is deposited above the lower portion material 310A. The upper portion material 310B may comprise a conductive inorganic material or a non-conductive inorganic material. The upper portion material 310B comprises the same material as the upper portion 110B of the cantilever structure. Non-conductive inorganic materials include, but are not limited to, silicon-containing inorganic materials. For example, silicon-containing materials include oxides or nitrides of silicon or combinations thereof. Conductive inorganic materials include, but are not limited to, metallic materials. For example, metallic materials include copper, titanium, aluminum, molybdenum, silver, indium tin oxide, indium zinc oxide, chromium, or combinations thereof.

[0042] At operation 208, such as Figure 3H As shown, a second sub-pixel opening 308B is formed in an upper portion material 310B and a lower portion material 310A. The second sub-pixel opening 308B is patterned using a photolithography process. During the photolithography process, photoresist 370 is deposited on or above the upper portion material 310B. After the photolithography process, the desired portion of the photoresist 370 is removed, thereby exposing the upper portion material 310B. The exposed portion of the upper portion material 310B and the lower portion material 310A are etched away to form the second sub-pixel opening 308B. An adjacent overhang structure 110 is formed during the etching process and at least partially defines the second sub-pixel opening 308B. A portion of the metal layer 104 and a portion of the adjacent PDL structure 126 are exposed through the second sub-pixel opening 308B. The lower sidewall 111 and the upper sidewall 113 of the adjacent overhang structure 110 are exposed through the second sub-pixel opening 308B.

[0043] At operation 209, such as Figure 3I As shown, a first deposition process is performed. During the deposition process, OLED material 112 for the second sub-pixel 108B is deposited within the second sub-pixel opening 308B. OLED material 112 is deposited over the exposed portion of the metal layer 104 and extends over the exposed portion of the adjacent PDL structure 126. OLED material 112 extends below at least a portion of the overhang 109 of the overhang structure 110. In one or more embodiments, OLED material 112 contacts the lower sidewall 111 of the adjacent overhang structure 110. OLED material 112 is further deposited on or above the upper portion material 310B. In one or more embodiments, OLED material 112 is further deposited over the upper sidewall 113 of the adjacent overhang structure 110. Cathode 114 is deposited on or above OLED material 112. Encapsulation layer 116 is deposited on or above cathode 114 to complete the second sub-pixel 108B. In one or more embodiments, the encapsulation layer 116 fills the second subpixel opening 308B and contacts the bottom surface 107 of the upper portion 110B of the adjacent overhang structure 110. The encapsulation layer 116 includes an upper subpixel surface 316. The upper subpixel surface 316 extends over at least a portion of the second subpixel opening 308B. Figure 3I An upper subpixel surface 316 is shown above the upper surface 305 of the upper portion 110B of the adjacent overhang structure 110. The upper subpixel surface 316 may be located below the upper surface 305 of the upper portion 110B of the adjacent overhang structure 110, such as below the bottom surface 107 of the upper portion 110B of the adjacent overhang structure 110.

[0044] At operation 210, such as Figure 3J As shown, a CMP process is performed. During the CMP process, the encapsulation layer 116, cathode 114, and OLED material 112 deposited on or above the upper surface 305 of the upper portion material 310B are removed by the CMP process. The portion of the encapsulation layer 116 deposited above the second sub-pixel opening 308B is planarized by the CMP process. In one or more embodiments, when the upper sub-pixel surface 316 of the encapsulation layer 116 is above the upper surface 305 of the upper portion material 310B, as... Figure 3JAs shown, the upper sub-pixel surface 316 of the encapsulation layer 116 is planarized. After performing the CMP process, the upper surface 305 of the upper portion material 310B is coplanar with the upper sub-pixel surface 316 of the encapsulation layer 116. In one or more embodiments, the upper sub-pixel surface 316 of the encapsulation layer 116 is below the upper surface 305 of the upper portion material 310B. The CMP process is performed on the encapsulation layer 116, and a portion of the upper surface of the encapsulation layer 116 is planarized to be coplanar with the upper surface 305 of the upper portion material 310B. The upper sub-pixel surface 316 of the encapsulation layer 116 is not planarized by the CMP process. Figures 5A to 5F An embodiment in which the upper sub-pixel surface 316 of the encapsulation layer 116 is located below the upper surface 305 of the upper portion material 310B is described in more detail. It is envisioned that, after the CMP process, wet etching and / or dry etching processes can be performed to remove excess OLED material 112 and cathode 114 deposited on or above the upper portion 110B of the overhang structure 110.

[0045] At operation 211, such as Figure 3K As shown, a first sub-pixel opening 308A is formed in the upper portion material 310B and the lower portion material 310A adjacent to the second sub-pixel opening 308B. The first sub-pixel opening 308A is patterned using a photolithography process. During the photolithography process, photoresist 370 is deposited on or above the upper portion material 310B. After the photolithography process, the desired portion of the photoresist 370 is removed, thereby exposing the upper portion material 310B. The exposed portion of the upper portion material 310B and the lower portion material 310A are etched away to form the first sub-pixel opening 308A. An adjacent overhang structure 110 is formed during the etching process and at least partially defines the first sub-pixel opening 308A. A portion of the metal layer 104 and a portion of the adjacent PDL structure 126 are exposed through the second sub-pixel opening 308B. The lower sidewall 111 and the upper sidewall 113 of the adjacent overhang structure 110 are exposed through the second sub-pixel opening 308B.

[0046] At operation 212, such as Figure 3LAs shown, a second deposition process is performed. During the deposition process, OLED material 112 of the first sub-pixel 108a is deposited within the first sub-pixel opening 308A. OLED material 112 is deposited over the exposed portion of the metal layer 104 and extends over the exposed portion of the adjacent PDL structure 126. OLED material 112 extends below at least a portion of the overhang 109 of the overhang structure 110. In one or more embodiments, OLED material 112 contacts the lower sidewall 111 of the adjacent overhang structure 110. OLED material 112 is further deposited over the upper surface 305 of the upper portion 110B of the overhang structure 110 and the upper sub-pixel surface 316 of the encapsulation layer 116 in the second sub-pixel opening 308B. In one or more embodiments, OLED material 112 is further deposited over the upper sidewall 113 of the adjacent overhang structure 110. Cathode 114 is deposited over OLED material 112. Encapsulation layer 116 is deposited on cathode 114 to complete the first sub-pixel 108a. In one or more embodiments, the encapsulation layer 116 fills the first subpixel opening 308A and contacts the bottom surface 107 of the upper portion 110B of the adjacent overhang structure 110. The encapsulation layer 116 includes an upper subpixel surface 316. The upper subpixel surface 316 extends over at least a portion of the first subpixel opening 308A. Figure 3I An upper subpixel surface 316 is shown above the upper surface 305 of the upper portion 110B of the adjacent overhang structure 110. The upper subpixel surface 316 may also be located below the upper surface 305 of the upper portion 110B of the adjacent overhang structure 110, such as below the bottom surface 107 that contacts the upper portion 110B of the adjacent overhang structure 110.

[0047] At operation 213, such as Figure 3M As shown, a CMP process is performed. During the CMP process, the encapsulation layer 116, cathode 114, and OLED material 112 deposited on or above the upper surface 305 of the upper portion material 310B are removed by the CMP process. The portion of the encapsulation layer 116 deposited on the second sub-pixel opening 308B is planarized by the CMP process. In one or more embodiments, when the upper sub-pixel surface 316 of the encapsulation layer 116 is above the upper surface 305 of the upper portion material 310B, as... Figure 3MAs shown, the upper sub-pixel surface 316 of the encapsulation layer 116 is planarized. After performing the CMP process, the upper surface 305 of the upper portion material 310B is coplanar with the upper sub-pixel surface 316 of the encapsulation layer 116. In one or more embodiments, the upper sub-pixel surface 316 of the encapsulation layer 116 is below the upper surface 305 of the upper portion material 310B. The CMP process is performed on the encapsulation layer 116, and a portion of the upper surface of the encapsulation layer 116 is planarized to be coplanar with the upper surface 305 of the upper portion material 310B. The upper sub-pixel surface 316 of the encapsulation layer 116 is not planarized by the CMP process. Figures 5A to 5F An embodiment in which the upper sub-pixel surface 316 of the encapsulation layer 116 lies beneath the upper surface 305 of the upper portion material 310B is described in more detail. It is envisioned that a wet etching process can be performed after the CMP process to remove excess OLED material 112 and cathode 114 deposited on or above the upper portion 110B of the overhang structure 110.

[0048] At operation 214, such as Figure 3N As shown, an intermediate encapsulation layer 118 and a global encapsulation layer 120 are deposited over the encapsulation layer 116 in the first sub-pixel 108a and the second sub-pixel 108B, as well as over the upper surface 305 of the upper portion 110B of the adjacent overhang structure 110, thereby completing the sub-pixel circuit 100.

[0049] Figures 4A to 4F This is a close-up schematic cross-sectional view of the upper portion 110B of the overhang structure 110 of the sub-pixel circuit according to an embodiment. Figure 4A and 4B The upper portion 110B with an upper sloping sidewall 450 is shown. Figure 4A In this process, OLED material 112, cathode 114, and encapsulation layer 116 are deposited over the upper surface 405 and upper ramp sidewall 450 of the upper portion 110B of the overhang structure 110, as described in operation 209 of method 200. The encapsulation layer has an upper sub-pixel surface 316 above the upper surface 405 of the upper portion 110B.

[0050] Figure 4B This illustrates the CMP process following operation 210 of method 200. Figure 4AThe upper portion 110B has an upper slope sidewall 450. During the CMP process, portions of the OLED material 112, cathode 114, and encapsulation layer 116 disposed above the upper surface 405 of the upper portion 110B are removed. The upper sub-pixel surface 316 is planarized such that the upper sub-pixel surface 316 is coplanar with the upper surface 405 of the upper portion 110B. After the CMP process, a wet etching process and / or a dry etching process are performed to remove portions of the OLED material 112 and cathode 114 deposited above the upper slope sidewall 450. After the etching process, a gap 460 is formed between the upper slope sidewall 450 and the sloped lower surface 451 of the encapsulation layer 116. The upper slope sidewall 450 and the sloped lower surface 451 contact at a lower edge 470. The lower edge 470 is defined by the point where the upper slope sidewall 450 meets the bottom surface 107. In one or more embodiments, when an intermediate encapsulation layer 118 is deposited over the upper portion 110B and the encapsulation layer 116 as described in operation 214 of method 200, the intermediate encapsulation layer fills the gap 460.

[0051] Figure 4C and Figure 4D An upper portion 110B with a sloping lower sidewall 452 is shown according to an embodiment. Figure 4C In this process, OLED material 112, cathode 114, and encapsulation layer 116 are deposited over the upper portion 110B of the overhang structure 110, as described in operation 209 of method 200. The encapsulation layer has an upper sub-pixel surface 316 above the upper surface 405 of the upper portion 110B.

[0052] Figure 4D This illustrates the CMP process following operation 210 of method 200. Figure 4C The upper portion 110B has sloping lower sidewalls 450, 452. During the CMP process, portions of the OLED material 112, cathode 114, and encapsulation layer 116 disposed above the upper surface 405 of the upper portion 110B are removed. The upper sub-pixel surface 316 is planarized such that the upper sub-pixel surface 316 is coplanar with the upper surface 405 of the upper portion 110B.

[0053] Figure 4E and Figure 4F Figure 1 shows an upper portion 110B with an upper sidewall 113. The bottom surface 107 of the upper portion 110B has a first width. The upper surface 405 of the upper portion 110B has a second width. The first width and the second width are equal. Figure 4EIn this process, OLED material 112, cathode 114, and encapsulation layer 116 are deposited on the upper surface 405 of the upper portion 110B of the cantilever structure 110 and on the upper sidewall 113 of the upper portion 110B of the cantilever structure 110, as described in operation 209 of method 200. The encapsulation layer has an upper sub-pixel surface 316 above the upper surface 405 of the upper portion 110B.

[0054] Figure 4F This illustrates the CMP process following operation 210 of method 200. Figure 4E The upper portion 110B has an upper sidewall 113. During the CMP process, portions of the OLED material 112, cathode 114, and encapsulation layer 116 disposed on the upper surface 405 of the upper portion 110B are removed. The upper sub-pixel surface 316 is planarized such that the upper sub-pixel surface 316 is coplanar with the upper surface 405 of the upper portion 110B. After performing the CMP process, a wet etching process and / or a dry etching process are performed to remove portions of the OLED material 112 and cathode 114 deposited above the sidewalls. After performing the etching process, a gap 460 is formed between the upper sidewall 113 and the encapsulation sidewall 453 of the encapsulation layer 116. The encapsulation sidewall 453 is parallel to the upper sidewall 113. The encapsulation layer 116 further includes a lower encapsulation surface 454 between the upper sidewall 113 and the encapsulation sidewall 453. The lower encapsulation surface 454 is coplanar with the bottom surface 107 of the upper portion 110B. In one or more embodiments, when an intermediate encapsulation layer 118 is deposited over the upper portion 110B and the encapsulation layer 116 as described in operation 214 of method 200, the intermediate encapsulation layer fills the gap 460. Figures 4A to 4F In the middle, the upper sub-pixel surface 316 is the uppermost surface of the encapsulation layer.

[0055] Figures 5A to 5F This is a close-up schematic cross-sectional view of the upper portion 110B of the overhang structure 110 of the sub-pixel circuit according to an embodiment. Figures 5A to 5F Includes an encapsulation layer 116, which has an upper sub-pixel surface 316 disposed below the upper surface 405 of the upper portion 110B. Figures 5A to 5F In the upper portion 110B, the upper subpixel surface 316 is disposed below the bottom surface 107 of the upper portion 110B. However, it should be understood that the upper pixel surface can be disposed anywhere below the upper surface 405 of the upper portion 110B. Figure 5A and Figure 5B An upper portion 110B with an upper sloping sidewall 450 is shown according to an embodiment. Figure 5AIn this process, OLED material 112, cathode 114, and encapsulation layer 116 are deposited over the upper surface 405 and upper ramp sidewall 450 of the upper portion 110B of the overhang structure 110, as described in operation 209 of method 200. The encapsulation layer 116 has an upper sub-pixel surface 316 below the upper surface 405 of the upper portion 110B.

[0056] Figure 5B This illustrates the CMP process following operation 210 of method 200. Figure 5A The upper portion 110B has an upper slope sidewall 450. During the CMP process, portions of the OLED material 112, cathode 114, and encapsulation layer 116 disposed above the upper surface 405 of the upper portion 110B are removed. The encapsulation layer 116 is planarized to form an upper planarized surface 516. The upper planarized surface 516 is coplanar with the upper surface 405. After performing the CMP process, a wet etching process and / or a dry etching process are performed to remove portions of the OLED material 112 and cathode 114 deposited above the upper slope sidewall 450. After performing the etching process, a gap 460 is formed between the upper slope sidewall 450 and the sloped lower surface 451 of the encapsulation layer 116. The upper slope sidewall 450 and the sloped lower surface 451 contact at a lower edge 470. The lower edge 470 is defined by the point where the upper slope sidewall 450 meets the bottom surface 107. In one or more embodiments, when an intermediate encapsulation layer 118 is deposited over the upper portion 110B and the encapsulation layer 116 as described in operation 214 of method 200, the intermediate encapsulation layer fills the gap 460.

[0057] Figure 5C and Figure 5D An upper portion 110B with a sloping lower sidewall 452 is shown according to an embodiment. Figure 5C In this process, OLED material 112, cathode 114, and encapsulation layer 116 are deposited over the upper portion 110B of the overhang structure 110, as described in operation 209 of method 200. The encapsulation layer 116 has an upper sub-pixel surface 316 below the upper surface 405 of the upper portion 110B.

[0058] Figure 5D This illustrates the CMP process following operation 210 of method 200. Figure 4C The upper portion 110B has sloping lower sidewalls 450, 452. During the CMP process, portions of the OLED material 112, cathode 114, and encapsulation layer 116 disposed above the upper surface 405 of the upper portion 110B are removed. The encapsulation layer 116 is planarized to form an upper planarized surface 516. The upper planarized surface 516 is coplanar with the upper surface 405.

[0059] Figure 5E and Figure 5FFigure 1 shows an upper portion 110B with an upper sidewall 113. The bottom surface 107 of the upper portion 110B has a first width. The upper surface 405 of the upper portion 110B has a second width. The first width and the second width are equal. Figure 5E In this process, OLED material 112, cathode 114, and encapsulation layer 116 are deposited on the upper surface 405 of the upper portion 110B of the overhang structure 110 and above the upper sidewall 113 of the upper portion 110B of the overhang structure 110, as described in operation 209 of method 200. The encapsulation layer 116 has an upper sub-pixel surface 316 below the upper surface 405 of the upper portion 110B.

[0060] Figure 5F This illustrates the CMP process following operation 210 of method 200. Figure 5E The upper portion 110B has an upper sidewall 113. During the CMP process, portions of the OLED material 112, cathode 114, and encapsulation layer 116 disposed above the upper surface 405 of the upper portion 110B are removed. The encapsulation layer 116 is planarized to form an upper planarized surface 516. The upper planarized surface 516 is coplanar with the upper surface 405. After performing the CMP process, a wet etching process and / or a dry etching process are performed to remove portions of the OLED material 112 and cathode 114 deposited on the sidewalls. After performing the etching process, a gap 460 is formed between the upper sidewall 113 and the encapsulation sidewall 453 of the encapsulation layer 116. The encapsulation sidewall 453 is parallel to the upper sidewall 113. The encapsulation layer 116 further includes a lower encapsulation surface 454 between the upper sidewall 113 and the encapsulation sidewall 453. The lower encapsulation surface 454 is coplanar with the bottom surface 107 of the upper portion 110B. In one or more embodiments, when an intermediate encapsulation layer 118 is deposited over the upper portion 110B and the encapsulation layer 116 as described in operation 214 of method 200, the intermediate encapsulation layer fills the gap 460. Figures 5A to 5F In the middle, the planarized surface 516 is the uppermost surface of the encapsulation layer.

[0061] The benefits of this disclosure include a method for forming subpixel circuitry 100 by removing encapsulation layer 116 using a CMP process. Removing encapsulation layer 116 using a CMP process requires fewer photolithography steps when forming subpixel circuitry 100. Fewer photolithography steps result in a reduced chance of damaging the subpixel and less residue from the etching process. The CMP process also allows subpixel circuitry to be formed with a reduced amount of operation, which in turn allows for shorter manufacturing time, lower costs, and less maintenance when fabricating subpixel circuitry 100.

[0062] It is envisioned that one or more aspects disclosed herein may be combined. For example, one or more aspects, features, components, operations, and / or properties of sub-pixel circuitry 100, substrate 102, metal layer 104, PDL structure 126, first sub-pixel 108a, second sub-pixel 108B, overhang structure 110, OLED material 112, cathode 114, overhang 109, encapsulation layer 116, intermediate encapsulation layer 118, global encapsulation layer 120, method 200, first layer 304A, second layer 304B, third layer 304C, PDL material 326, lower portion material 310A, upper portion material 310B, first sub-pixel opening 308A, and / or second sub-pixel opening 308B may be combined. Furthermore, it is envisioned that one or more aspects disclosed herein may include some or all of the foregoing benefits.

[0063] While the foregoing describes embodiments of this disclosure, other and further embodiments of this disclosure may be conceived without departing from the basic scope of this disclosure, and the scope of this disclosure is defined by the appended claims.

Claims

1. A sub-pixel, comprising: Adjacent overhang structures are disposed above a substrate, each overhang structure having an upper portion having a top surface and a bottom surface, the bottom surface being wider than the top surface of the lower portion, and the adjacent overhang structures defining the opening of the sub-pixel; An anode, wherein the anode is disposed above the substrate between the adjacent overhanging structures; Organic light-emitting diode (OLED) material, wherein the OLED material is disposed above the anode; Cathode, which is disposed above the OLED material; as well as An encapsulation layer disposed above the cathode, wherein the encapsulation layer extends along the sidewall of the lower portion below at least a portion of the overhang structure and contacts the bottom surface of the upper portion of the overhang structure, the encapsulation layer having an uppermost surface coplanar with the top surface of the upper portion of the adjacent overhang structure; An intermediate encapsulation layer is deposited above the encapsulation layer and extends above the upper portion of the overhang structure; as well as A global encapsulation layer is deposited on top of the intermediate encapsulation layer.

2. The sub-pixel of claim 1, further comprising a gap between the sidewall of the upper portion and the encapsulation layer adjacent to the upper portion.

3. The sub-pixel of claim 1, wherein the top surface of the upper portion is wider than the bottom surface of the upper portion.

4. The sub-pixel of claim 1, wherein the bottom surface of the upper portion is wider than the top surface of the upper portion.

5. The sub-pixel of claim 4, wherein the upper portion further comprises: An upper sloping sidewall extends between the top surface and the bottom surface of the upper portion, and the upper sloping sidewall meets the bottom surface of the upper portion at an edge; and The encapsulation layer includes a lower slope surface that contacts the upper slope sidewall of the upper portion at the edge, wherein a gap is defined between the lower slope surface of the encapsulation layer and the upper slope sidewall of the upper portion.

6. The sub-pixel of claim 5, wherein the intermediate encapsulation layer is at least partially deposited within the gap.

7. The sub-pixel of claim 1, wherein the bottom surface of the upper portion has a first width equal to the second width of the top surface of the upper portion.

8. The sub-pixel of claim 7, wherein the upper portion further comprises: Upper sidewall, the upper sidewall extending between the top surface of the upper portion and the bottom surface of the upper portion; and The encapsulation layer includes: Encapsulating sidewall, the encapsulating sidewall being parallel to the upper sidewall of the upper portion, wherein the upper sidewall of the upper portion and the encapsulating sidewall define a gap; as well as A lower encapsulation surface extends between the encapsulation sidewall and the upper sidewall of the upper portion, wherein the lower encapsulation surface and the lower surface of the upper portion are coplanar.

9. The sub-pixel of claim 8, wherein the intermediate encapsulation layer is at least partially deposited within the gap.

10. A device comprising: Multiple sub-pixels, the multiple sub-pixels including at least a first sub-pixel and a second sub-pixel, each of the first sub-pixel and the second sub-pixel comprising: Adjacent overhang structures are disposed above a substrate, each overhang structure having an upper portion having a top surface and a bottom surface, the bottom surface being wider than the top surface of the lower portion, and the adjacent overhang structures defining the opening of the sub-pixel; An anode, wherein the anode is disposed above the substrate between the adjacent overhanging structures; Organic light-emitting diode (OLED) material, wherein the OLED material is disposed above the anode; Cathode, the cathode being disposed above the OLED material; and An encapsulation layer disposed above the cathode, wherein the encapsulation layer extends along the sidewall of the lower portion below at least a portion of the overhang structure and contacts the bottom surface of the upper portion of the overhang structure, the encapsulation layer having an uppermost surface coplanar with the top surface of the upper portion of the adjacent overhang structure; An intermediate encapsulation layer, the intermediate encapsulation layer being deposited above the encapsulation layer, the intermediate encapsulation layer extending above the upper portion of the overhang structure; and A global encapsulation layer is deposited on top of the intermediate encapsulation layer.

11. The device of claim 10, further comprising a gap between the sidewall of the upper portion and the encapsulation layer adjacent to the upper portion.

12. The device of claim 10, wherein the top surface of the upper portion is wider than the bottom surface of the upper portion.

13. The device of claim 10, wherein the bottom surface of the upper portion is wider than the top surface of the upper portion.

14. The device of claim 13, wherein the upper portion further comprises: An upper sloping sidewall extends between the top surface and the bottom surface of the upper portion, and the upper sloping sidewall meets the bottom surface of the upper portion at an edge; and The encapsulation layer includes a lower slope surface that contacts the upper slope sidewall of the upper portion at the edge, wherein a gap is defined between the lower slope surface of the encapsulation layer and the upper slope sidewall of the upper portion.

15. The device of claim 14, wherein the intermediate encapsulation layer is at least partially deposited within the gap.

16. The device of claim 10, wherein the bottom surface of the upper portion has a first width equal to the second width of the top surface of the upper portion.

17. The device of claim 16, wherein the upper portion further comprises: Upper sidewall, the upper sidewall extending between the top surface of the upper portion and the bottom surface of the upper portion; and The encapsulation layer includes: Encapsulating sidewall, the encapsulating sidewall being parallel to the upper sidewall of the upper portion, wherein the upper sidewall of the upper portion and the encapsulating sidewall define a gap; as well as A lower encapsulation surface extends between the encapsulation sidewall and the upper sidewall of the upper portion, wherein the lower encapsulation surface is coplanar with the bottom surface of the upper portion.

18. The device of claim 17, wherein the intermediate encapsulation layer is at least partially deposited within the gap.

19. A method for manufacturing a sub-pixel device, comprising: Multiple anodes are deposited on the substrate; Multiple pixel-defined layer (PDL) structures are patterned over the substrate; A portion of the material is deposited above the substrate; A portion of the material is deposited over the substrate; A first sub-pixel opening is formed in the lower part of the material and the upper part of the material; The first sub-pixel opening defines an adjacent overhang structure, the adjacent overhang structure having an upper portion having a top surface and a bottom surface, the bottom surface being wider than the top surface of the lower portion; Perform a first deposition process, the first deposition process including depositing a first OLED material, a first cathode and a first encapsulation layer within the first sub-pixel opening, wherein a portion of the first OLED material, the first cathode and the first encapsulation layer extends above the upper surface of the upper portion material; as well as A first CMP process is performed to remove the portion of the first OLED material, the first cathode, and the first encapsulation layer that extends above the upper surface of the upper portion material.

20. The method of claim 19, further comprising: A second sub-pixel opening is formed in the lower part of the material and the upper part of the material; The second sub-pixel opening defines an adjacent overhang structure, the adjacent overhang structure having an upper portion having a top surface and a bottom surface, the bottom surface being wider than the top surface of the lower portion; Perform a second deposition process, the second deposition process including depositing a second OLED material, a second cathode and a second encapsulation layer within the second sub-pixel opening, wherein a portion of the second OLED material, the second cathode and the second encapsulation layer extends above the upper surface of the upper portion material; as well as A second CMP process is performed to remove the portions of the second OLED material, the second cathode, and the second encapsulation layer that extend above the upper surface of the upper portion material.

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