Integrated circuits (ICs) and related three-dimensional (3D) ICs (3DICs) and manufacturing methods with separate signal interconnect structures and power distribution network (PDN) interconnect structures to reduce power signal routing congestion and path length

Abstract

Integrated circuits (ICs) and related three-dimensional (3D) ICs (3DICs) and methods of manufacture having separate signal interconnect structures and power distribution network (PDN) interconnect structures to reduce power signal routing congestion and path length. The ICs include separate signal interconnect structures that provide input / output (I / O) signal routing, and PDN interconnect structures for providing power distribution signal routing. The signal interconnect structures are disposed on a first side of a semiconductor layer in the IC, and the PDN interconnect structures are disposed on a second side of the semiconductor layer opposite the first side. In this way, performance of semiconductor devices in the semiconductor layer can be improved because power distribution signals do not have to be routed in shared interconnect structures that are also used to route I / O signals, which can otherwise cause congestion in the IC and increase power distribution signal routing path length.

Description

Priority application

[0001] This application claims priority to U.S. Patent Application Serial No. 18 / 609,314, filed March 19, 2024, entitled “INTEGRATED CIRCUITS (ICs) HAVING SEPARATE SIGNAL AND POWER DISTRIBUTION NETWORK (PDN) INTERCONNECTSTRUCTURES FOR REDUCED POWER SIGNAL ROUTING CONGESTION AND PATH LENGTHS, AND RELATED THREE-DIMENSIONAL (3D) ICs (3DICs) AND FABRICATION METHODS”, which is incorporated herein by reference in its entirety. background I. Technical Field The field of this disclosure relates to integrated circuit (IC) / semiconductor dies including interconnect structures with metallization layers for providing power and signal wiring to devices formed in semiconductor layers of the IC; and also to three-dimensional ICs (3DICs) comprising multiple stacked dies.

[0002] II. Background Technology Integrated circuits (ICs) are the cornerstone of electronic devices. ICs are packaged in IC packages, also known as “semiconductor packages” or “chip packages.” An IC package includes one or more semiconductor dies that serve as the IC, mounted on and electrically coupled to a substrate such as a wiring substrate (e.g., a package substrate) to provide physical support and electrical interfaces for the dies. The dies are electrically bonded to exposed metal interconnects (e.g., metal traces) in an upper layer of the substrate that are part of a signal wiring path. The substrate also includes one or more metallization layers comprising metal interconnects (e.g., metal traces, metal lines), wherein vertical interconnect channels (vias) couple the metal interconnects between adjacent metallization layers together to provide electrical interfaces between the dies. If the substrate is a package substrate, the substrate also includes a lower outer metallization layer comprising metal interconnects coupled to external metal interconnects (e.g., ball grid array (BGA) interconnects) to provide external interfaces between the dies in the IC package. External metal interconnects can also be coupled (e.g., soldered) to traces in a printed circuit board (PCB) to attach the package to the PCB and electrically interconnect its die with the PCB's circuitry.

[0003] Some IC packages are referred to as multi-die (multi-die) IC packages, which include multiple dies contained within the IC package for different purposes or applications. For example, a multi-die IC package may include a first application die (e.g., a processor or system-on-a-chip (SoC)) and a separate second die providing support circuitry for the application die. Separating the main application / function into a separate die is an alternative to placing the circuitry for all such applications / functions into a single die. Manufacturing costs and complexity increase disproportionately with die size. For example, the second die may include a die with power management circuitry for a modem, processor, or memory (as an example). These multi-die IC packages can be provided in the form of three-dimensional (3D) IC (3DIC) packages. For example, a 3DIC package may include a first bottom die coupled to a first bottom package substrate, and a second top die stacked directly on the bottom die in a vertical direction. Through-silicon vias (TSVs) are provided through the bottom die to provide signal routing paths from the package substrate and / or the bottom die to the top die. These TSVs can provide signal routing paths not only to the second die but also to power signal routing paths to distribute power to the power distribution network (PDN) in the upper die via the bottom die. However, this means that the power signal routing distance on the upper die is greater than that on the lower die, which increases loop inductance and DC losses in the PDN of the upper die. Summary of the Invention

[0004] The aspects disclosed herein include integrated circuits (ICs) having separate signal interconnect structures and power distribution network (PDN) interconnect structures to reduce power signal wiring congestion and path length. Related three-dimensional (3D) ICs (3DICs) and manufacturing methods are also disclosed. The IC includes a semiconductor die (“die”) comprising a semiconductor layer in which semiconductor devices are formed. The die also includes an interconnect structure comprising one or more metallization layers, each having a metal layer in which metal interconnects are formed to provide signal wiring paths within the die and leading to the semiconductor devices. In an exemplary aspect, the IC includes separate signal interconnect structures (e.g., as part of the die) and separate PDN interconnect structures. The signal interconnect structure includes a metallization layer having a first metal interconnect for providing input / output (I / O) signal wiring paths to the semiconductor devices. The PDN interconnect structure includes a second metallization layer with second metal interconnects for providing power distribution signal routing paths to semiconductor devices as part of the PDN (i.e., power signal paths and ground signal paths), thereby powering the operation of the semiconductor devices. In an exemplary aspect, a signal interconnect structure is disposed on a first side of the semiconductor layer, and a PDN interconnect structure is disposed on a second side of the semiconductor layer, which is vertically opposite to the first side of the semiconductor layer. Through-silicon vias (TSVs) are disposed in the semiconductor layer and coupled to the signal interconnect structure and the PDN interconnect structure to transmit power signals from the PDN interconnect structure to the signal interconnect structure and to transmit I / O signals from the signal interconnect structure to the PDN interconnect structure.

[0005] In this way, the performance of semiconductor devices in an IC can be improved. This is because power distribution signals do not need to be routed in a shared interconnect structure that is also used for routing I / O signals, which could otherwise cause congestion in the IC and increase the length of power distribution signal routing paths. This can help shorten the length of power distribution signal paths that are set in the PDN interconnect structure and routed to the semiconductor device. Therefore, by shortening the length of power distribution signal routing paths, loop inductance and DC power loss are reduced. Setting up a separate PDN interconnect structure in the IC can also help minimize the capacitive routing path length between the decoupling capacitor and the PDN in the PDN interconnect structure coupled to the semiconductor device, thereby also reducing loop inductance to improve power noise filtering. Furthermore, for example, by setting up a separate PDN interconnect structure, decoupling capacitors can be more easily integrated into the PDN interconnect structure (e.g., as silicon capacitors (DTCs) in the silicon layer of the PDN interconnect structure or dielectric capacitors in the dielectric layer (e.g., silicon oxide layer) due to reduced routing congestion in the PDN interconnect structure). Integrating capacitors into the PDN interconnect structure further shortens the capacitor wiring path length between the decoupling capacitor and the PDN coupled to the semiconductor device, thereby further improving power noise filtering.

[0006] Furthermore, by incorporating separate signal interconnect structures and PDN interconnect structures within the IC, each interconnect structure can be fabricated as a separate wafer as part of the wafer fabrication process and subsequently coupled together, such as via wafer-to-wafer (WoW) bonding. This not only enables the separate fabrication of signal interconnect structures and PDN interconnect structures but also allows for the use of different fabrication processes. For example, lower-cost, less expensive fabrication techniques can be used to fabricate the PDN interconnect structure, such as where the spacing of the metal interconnects in the PDN interconnect structure can be relaxed. Then, if desired, more advanced fabrication techniques can be used to fabricate the signal interconnect structure, such as where a reduction in the spacing of the metal interconnects is required or desired, to provide more efficient I / O signal routing for the die in a smaller area. This can reduce the overall cost of manufacturing the IC. As an example, the semiconductor layer of the die can be fabricated together with the signal interconnect structure as a back-to-work (BEOL) structure in a first wafer as part of the first wafer fabrication process. The PDN interconnect structure can then be fabricated separately in a second wafer as part of a second wafer fabrication process. Then, a first wafer and a second wafer, each having a corresponding separate signal interconnect structure and a PDN interconnect structure, can be coupled together (e.g., by WoW bonding) to provide a single IC, which includes signal interconnect structures and PDN interconnect structures located on opposite sides of a semiconductor layer in the first wafer. The combined first and second wafers can then be diced to form individual ICs, each having a semiconductor layer in which semiconductor devices are formed, the semiconductor layer being surrounded on both sides by separate signal interconnect structures and PDN interconnect structures.

[0007] In another exemplary aspect, a three-dimensional (3D) IC (3DIC) can be provided as part of a 3DIC package. The 3DIC includes a first bottom die comprising a semiconductor layer and interconnect structures coupled to a package substrate to provide signal routing paths between the package substrate and the first bottom die. The 3DIC also includes a second top IC stacked vertically on the first bottom die. The second top IC includes separate signal interconnect structures and PDN interconnect structures as described above. A TSV is disposed in the semiconductor layer of the first bottom die and coupled to the second top IC to provide signal routing paths between the interconnect structures of the first bottom die and the second top IC. Power distribution signals and I / O signals can be routed to the second top IC via the TSV in the first bottom die. Power distribution signals can be routed to the PDN interconnect structure of the second top IC via coupling of the TSV in the first bottom die with the PDN interconnect structure adjacent to the first bottom die. I / O signals can be routed through the PDN interconnect structure and through second TSVs in the second semiconductor layer of the second upper die in the second upper IC. These second TSVs are vertically coupled to signal interconnect structures on the side of the second semiconductor layer opposite to the PDN interconnect structure. In this way, the first bottom die facilitates the provision of signal routing paths for power distribution signals and I / O signals between the package substrate and the second upper IC. By utilizing a separate PDN interconnect structure disposed in the second upper IC and adjacent to the first bottom die, the power distribution signal path length is shortened to reduce loop inductance and DC power loss, as discussed above.

[0008] Furthermore, as discussed above, placing a separate PDN interconnect structure within the second upper IC of the 3DIC can help minimize the capacitive wiring path length between the decoupling capacitor and the PDN in the PDN interconnect structure coupled to the semiconductor device, thereby also reducing loop inductance to improve power noise filtering. The decoupling capacitor integrated into the PDN interconnect structure of the second upper IC allows for efficient shortening of the capacitive wiring path length from the decoupling capacitor to the PDN in the second upper IC and to the PDN in the lower bottom die adjacent to the PDN interconnect structure of the second upper IC (e.g., via signal wiring through the TSV in the lower bottom die). Again, power noise filtering is further improved by shortening the capacitive wiring path length between the decoupling capacitor and the PDN in the first bottom IC and the second upper IC. Routing the decoupling capacitor through the interconnect between the second upper IC and the lower bottom die also avoids the need for pad-side capacitors (LSCs) and / or die-side capacitors (DSCs) that would involve large capacitive wiring path distances. By routing the decoupling capacitors through the interconnects between the second upper IC and the lower bottom die, the need for the second upper IC to be laterally offset from the first bottom die in the first horizontal direction can be eliminated, providing space for the decoupling capacitors to couple to the PDN interconnect structure of the second upper IC, thereby avoiding an increase in the distance of the capacitor wiring path from the LSC and / or DSC.

[0009] In this regard, in one exemplary aspect, an IC is provided. The IC includes a semiconductor layer and a plurality of semiconductor devices, the semiconductor layer including a first side and a second side opposite to the first side. The IC also includes a signal interconnect structure adjacent to the first side of the semiconductor layer. The signal interconnect structure includes a plurality of first metal interconnects, each of the plurality of first metal interconnects being configured to transmit input / output (I / O) signals to coupled first semiconductor devices in the plurality of semiconductor devices. The IC also includes a PDN interconnect structure adjacent to the second side of the semiconductor layer. The PDN interconnect structure includes a plurality of second metal interconnects, each of the plurality of second metal interconnects being configured to transmit power signals. The IC also includes a plurality of first vias, each of the plurality of first vias extending through the semiconductor layer and each coupled to one of the plurality of second metal interconnects and the signal interconnect structure.

[0010] In another exemplary aspect, a method of manufacturing an IC is provided. The method includes forming a semiconductor layer including a first side and a second side opposite to the first side. The method further includes forming a plurality of semiconductor devices in the semiconductor layer. The method further includes forming a plurality of first vias, each of the plurality of first vias extending through the semiconductor layer. The method further includes forming a signal interconnect structure adjacent to the first side of the semiconductor layer, wherein forming the signal interconnect structure further includes forming a plurality of first metal interconnects, each of the plurality of first metal interconnects being configured to transmit an input / output (I / O) signal to a coupled first semiconductor device among the plurality of semiconductor devices. The method further includes forming a PDN interconnect structure, wherein forming the PDN interconnect structure further includes forming a plurality of second metal interconnects, each of the plurality of second metal interconnects being configured to transmit a power signal. The method further includes coupling the PDN interconnect structure adjacent to the second side of the semiconductor layer by coupling each of the plurality of second metal interconnects to a first via of the plurality of first vias.

[0011] In another exemplary aspect, a three-dimensional (3D) integrated circuit (IC) (3DIC) is provided. The 3DIC includes a first IC. The first IC includes a first semiconductor layer and a plurality of first semiconductor devices, the first semiconductor layer including a first side and a second side opposite to the first side. The first IC also includes a signal interconnect structure adjacent to the first side of the first semiconductor layer. The signal interconnect structure includes a plurality of first metal interconnects, each configured to transmit I / O signals to coupled first semiconductor devices among the plurality of first semiconductor devices. The first IC also includes a PDN interconnect structure adjacent to the second side of the first semiconductor layer. The PDN interconnect structure includes a plurality of second metal interconnects, each configured to transmit a power signal. The first IC also includes a plurality of first vias, each extending through the first semiconductor layer and each coupled to one of the second metal interconnects and the signal interconnect structure. The 3DIC also includes a second IC. The second IC includes a second semiconductor layer. The second IC also includes a third interconnect structure adjacent to the second semiconductor layer. The third interconnect structure includes a plurality of third metal interconnects, each of the plurality of third metal interconnects including a power signal node. The second IC also includes a plurality of second vias, each extending through the second semiconductor layer and each coupled to one of a plurality of third metal interconnects. The first IC is coupled to the second IC by coupling each of the plurality of second metal interconnects in the second IC to one of the plurality of second vias in the first IC, thereby coupling each of the plurality of second metal interconnects to one of the plurality of third metal interconnects in the second IC. Attached Figure Description

[0012] Figure 1A and Figure 1B The images are a side view and a close-up side view of an exemplary three-dimensional (3D) integrated circuit (IC) (3DIC), which includes a first bottom die and a second top IC. The first bottom die includes a semiconductor layer and an interconnect structure that can be coupled to a package substrate. The second top IC is stacked on the first bottom die in a second vertical direction. The second top IC includes separate signal interconnect structures and power distribution network (PDN) interconnect structures to reduce signal wiring congestion and power signal wiring path length, thereby improving IC performance. Decoupling capacitors are integrated into the PDN interconnect structure of the second top IC to provide decoupling capacitance to the PDN in the second top IC and the first bottom die. Figure 2 This is a side view of a 3D die structure for a 3DIC, which includes a first bottom die and a second top die stacked vertically on the first bottom die, wherein the first bottom die includes through-silicon vias (TSVs) to provide signal routing paths through the first bottom die to the second top die; Figure 3 This is a side view of a 3DIC package, which includes a second upper die stacked above and laterally offset from the first bottom die to provide space for a decoupling capacitor to be directly coupled to the second upper die. Figure 4A and Figure 4B These are a side view and a close-up side view of another exemplary IC with a single die, which is similar to... Figure 1A and Figure 1B The second upper die in the 3DIC, wherein the wafer-to-wafer (WoW) bonding of the signal interconnect structure and semiconductor layer to the PDN interconnect structure is achieved by metal bumps, and wherein the decoupling capacitor is integrated as a silicon capacitor in the silicon layer of the PDN interconnect structure; Figure 5A and Figure 5B These are a side view and a close-up side view of another exemplary IC with a single die, which is similar to... Figure 1A and Figure 1B The second upper die in the 3DIC, wherein the signal interconnect structure and semiconductor layer are WoW bonded to the PDN interconnect structure by metal bumps, and wherein the decoupling capacitor is integrated as a dielectric capacitor in the dielectric layer of the PDN interconnect structure of the second upper IC; Figure 5C It is similar to Figure 5BA close-up side view of another IC package in the IC package, but with direct WoW bonding of the signal interconnect structure and the semiconductor layer to PDN interconnect structure; Figure 6 This is a flowchart illustrating an exemplary process for manufacturing an IC, which includes separate signal interconnect structures and PDN interconnect structures to reduce signal routing congestion and power signal routing path length, thereby improving IC and die performance, and wherein decoupling capacitors may be integrated into the PDN interconnect structure of the IC to provide decoupling capacitance to the PDN in the IC, including but not limited to... Figures 1A to 1B and Figures 4A to 5C IC in the middle; Figures 7A to 7C This is a flowchart illustrating an exemplary process for separately fabricating a second wafer, which includes a PDN interconnect structure that can be coupled to a first wafer having a semiconductor layer and a signal interconnect structure to form a combined wafer, which can be diced to form Figure 4A and Figure 4B IC in the middle; Figures 8A to 8E It is based on Figures 7A to 7C Exemplary manufacturing process in Figures 4A to 4B Exemplary manufacturing stages during the PDN interconnect structure of the IC; Figures 9A to 9C This is a flowchart illustrating an exemplary process for separately manufacturing a first wafer, the first wafer including a semiconductor layer and a signal interconnect structure that can be coupled to... Figure 8E The second wafer is used to form a composite wafer, which can be diced to form... Figure 4A and Figure 4B IC in the middle; Figures 10A to 10E It is based on Figures 9A to 9C Exemplary manufacturing process in Figures 4A to 5C Exemplary manufacturing stages during the semiconductor layer and signal interconnect structure of the IC; Figure 11 This is an example of Figure 8E A separately fabricated second wafer with a PDN interconnect structure is coupled to Figure 10E A flowchart illustrating an exemplary process for forming a composite wafer from a first wafer having a second semiconductor layer and signal interconnect structures, the composite wafer being diced into individual ICs, such as... Figure 4A and Figure 4B IC in the middle.

[0013] Figure 12A and Figure 12B It is based on Figure 11 An exemplary manufacturing stage of an exemplary process; Figures 13A to 13C This is an example of separately manufactured for Figure 5A and Figure 5B A flowchart illustrating an exemplary process of the PDN interconnect structure of the IC in the process; Figures 14A to 14E It is based on Figures 13A to 13C Exemplary manufacturing process in Figure 5A and Figure 5B An exemplary manufacturing phase during the PDN interconnect structure; Figure 15 This is an example of Figure 10E Individually fabricated semiconductor layers and signal interconnect structures are coupled to Figure 14E Individually fabricated PDN interconnect structures to form Figure 5A and Figure 5B A flowchart illustrating an exemplary process of the IC in the process; Figure 16A and Figure 16B It is based on Figure 15 The exemplary process in Figure 10E Individually fabricated semiconductor layers and signal interconnect structures are coupled to Figure 14E Individually fabricated PDN interconnect structures to form Figure 5A and Figure 5B An exemplary manufacturing phase during the IC process; Figure 17 This is a block diagram of an exemplary wireless communication device including one or more IC packages, each IC including an IC with separate signal interconnect structures and PDN interconnect structures to reduce signal wiring congestion and power signal wiring path length, thereby improving IC and die performance, and wherein decoupling capacitors may be integrated into the PDN interconnect structure of the IC to provide decoupling capacitance to the PDN in the IC, the IC including but not limited to Figures 1A to 1B , Figures 4A to 5C , Figure 12B and Figure 16B The IC in question can be manufactured according to a manufacturing process, which includes, but is not limited to, the following processes: Figure 6 , Figures 7A to 7C , Figures 9A to 9C , Figure 11 , Figures 13A to 13C and Figure 15 The exemplary manufacturing process in; and Figure 18 This is a block diagram of an exemplary electronic device in the form of a processor-based system. The electronic device includes one or more IC packages, each including an IC. The IC includes separate signal interconnect structures and PDN interconnect structures to reduce signal routing congestion and power signal routing path length, thereby improving IC and die performance. Decoupling capacitors may be integrated into the PDN interconnect structure of the IC to provide decoupling capacitance to the PDN within the IC. The IC includes, but is not limited to, […]. Figures 1A to 1B , Figures 4A to 5C , Figure 12B and Figure 16B The IC in question can be manufactured according to a manufacturing process, which includes, but is not limited to, the following processes: Figure 6 , Figures 7A to 7C , Figures 9A to 9C , Figure 11 , Figures 13A to 13C and Figure 15 An exemplary manufacturing process is shown in the figure. Detailed Implementation

[0014] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0015] The aspects disclosed herein include integrated circuits (ICs) having separate signal interconnect structures and power distribution network (PDN) interconnect structures to reduce power signal wiring congestion and path length. Related three-dimensional (3D) ICs (3DICs) and manufacturing methods are also disclosed. The IC includes a semiconductor die (“die”) comprising a semiconductor layer in which semiconductor devices are formed. The die also includes an interconnect structure comprising one or more metallization layers, each having a metal layer in which metal interconnects are formed to provide signal wiring paths within the die and leading to the semiconductor devices. In an exemplary aspect, the IC includes separate signal interconnect structures (e.g., as part of the die) and separate PDN interconnect structures. The signal interconnect structure includes a metallization layer having a first metal interconnect for providing input / output (I / O) signal wiring paths to the semiconductor devices. The PDN interconnect structure includes a second metallization layer with second metal interconnects for providing power distribution signal routing paths to semiconductor devices as part of the PDN (i.e., power signal paths and ground signal paths), thereby powering the operation of the semiconductor devices. In an exemplary aspect, a signal interconnect structure is disposed on a first side of the semiconductor layer, and a PDN interconnect structure is disposed on a second side of the semiconductor layer, which is vertically opposite to the first side of the semiconductor layer. Through-silicon vias (TSVs) are disposed in the semiconductor layer and coupled to the signal interconnect structure and the PDN interconnect structure to transmit power signals from the PDN interconnect structure to the signal interconnect structure and to transmit I / O signals from the signal interconnect structure to the PDN interconnect structure.

[0016] In this way, the performance of semiconductor devices in an IC can be improved. This is because power distribution signals do not need to be routed in a shared interconnect structure that is also used for routing I / O signals, which could otherwise cause congestion in the IC and increase the length of power distribution signal routing paths. This can help shorten the length of power distribution signal paths that are set in the PDN interconnect structure and routed to the semiconductor device. Therefore, by shortening the length of power distribution signal routing paths, loop inductance and DC power loss are reduced. Setting up a separate PDN interconnect structure in the IC can also help minimize the capacitive routing path length between the decoupling capacitor and the PDN in the PDN interconnect structure coupled to the semiconductor device, thereby also reducing loop inductance to improve power noise filtering. Furthermore, for example, by setting up a separate PDN interconnect structure, decoupling capacitors can be more easily integrated into the PDN interconnect structure (e.g., as silicon capacitors (DTCs) in the silicon layer of the PDN interconnect structure or dielectric capacitors in the dielectric layer (e.g., silicon oxide layer) due to reduced routing congestion in the PDN interconnect structure). Integrating capacitors into the PDN interconnect structure further shortens the capacitor wiring path length between the decoupling capacitor and the PDN coupled to the semiconductor device, thereby further improving power noise filtering.

[0017] In this regard, Figure 1A and Figure 1B These are a side view and a close-up side view of an exemplary 3DIC package 100 including 3DIC 102. The 3DIC includes a first bottom IC 104(1) and a second top IC 104(2). The first bottom IC includes a first bottom die 106(1), and the second top IC includes a second top die 106(2). The die includes a semiconductor layer in which semiconductor devices are formed. Figure 1A As shown, the area occupied by the first bottom IC 104(1) and the second top IC 104(2) extends in the first horizontal direction (X-axis and Y-axis directions). 3DIC 102 is a three-dimensional IC because the second top IC 104(2) is vertically adjacent to the first top IC 104(1) in a second vertical direction (Z-axis direction) orthogonal to the first horizontal direction (X-axis and Y-axis directions). In other words, 3DIC 102 is constructed by vertically stacking the different ICs 104(1), 104(2) together into a single IC package as 3DIC package 100, thereby saving the area of ​​3DIC package 100. This allows each IC 104(1), 104(2) to be designed to provide specific functionality and to be manufactured and tested individually, but combined in a single vertical structure in an area-saving manner to provide 3DIC 102.

[0018] Each die 106(1), 106(2) of the corresponding IC 104(1), 104(2) includes a corresponding semiconductor layer 108(1), 108(2) in which semiconductor devices 110(1), 110(2) are formed. Each IC 104(1), 104(2) also has a corresponding metal interconnect structure 112(1), 112(2) (e.g., metal line, metal trace), each of which has a metallization layer 114(1), 114(2), each of which has a metal interconnect 116(1), 116(2) to provide signal routing paths in the die 106(1), 106(2) to its semiconductor device 110(1), 110(2), another corresponding die 106(2), 106(1) for die-to-die (D2D) connections, and / or to external interconnects 118 (e.g., solder balls, ball grid array (BGA) interconnects) that can be coupled to the substrate 120 (e.g., the package substrate 120 (e.g., embedded trace substrate (ETS), modified semi-additive process (mSAP) substrate) for external signal routing with the 3DIC package 100. Signal interconnection is provided between IC 104(1) and IC 104(2) via first through-silicon vias (TSVs) 122(1). These first through-silicon vias (TSVs) are disposed through a first semiconductor layer 108(1) of a first bottom die 106(1) extending in a second vertical direction (Z-axis direction) to provide a signal pass-through path through the first bottom die 106(1) to the second upper die 106(2). Figure 1A As shown, the first TSV 122(1) in the first bottom IC 104(1) is coupled to the second top IC 104(2) via a metal interconnect 111 (e.g., solder bump, ball grid array (BGA) interconnect) to electrically and physically couple the second top IC 104(2) to the first bottom IC 104(1).

[0019] like Figure 1BA close-up partial side view of the 3DIC package 100 is shown, and as discussed in more detail below, in this example, the second upper IC 104(2) in the 3DIC 102 includes a metal interconnect structure 112(2) comprising a separate signal interconnect structure 124 and a PDN interconnect structure 126. This reduces signal routing congestion and power signal routing path length in the second upper IC 104(2) to improve the performance of the second upper IC 104(2) and its second upper die 106(2). For example, as discussed in more detail below, the signal interconnect structure 124 may be fabricated as part of a back-to-office (BEOL) process, adjacent to or on the first side 128(1) of the second semiconductor layer 108(2) which is part of the first wafer in the second vertical direction (Z-axis direction). In this example, the second upper die 106(2) becomes a semiconductor die by including the semiconductor layer 108(2) and the signal interconnect structure 124. In this example, the PDN interconnect structure 126 does not include a semiconductor layer in which semiconductor devices are formed. However, the PDN interconnect structure 126 may be fabricated separately as part of a second separate wafer and coupled in a second vertical direction (Z-axis direction) to or adjacent to a second side 128(2) of the semiconductor layer 108(2) opposite to the first side 128(1). It should be noted that, alternatively, the PDN interconnect structure 126 may be included as part of a die that also includes a semiconductor layer in which semiconductor devices are formed, and the signal interconnect structure 124 may be fabricated without a semiconductor layer.

[0020] like Figure 1BAs shown, the combined second semiconductor layer 108(2) and signal interconnect structure 124 can be coupled to a separate PDN interconnect structure 126 via a metal bump layer 129 (e.g., formed by a wafer-to-wafer (WoW) bonding process during manufacturing). This metal bump layer includes a plurality of metal bumps 131 interconnecting exposed second TSVs 122(2) with exposed second metal interconnects 130(2) in the PDN interconnect structure 126. These second TSVs extend through the second semiconductor layer 108(2) in a second vertical direction (Z-axis direction) and are adjacent to the PDN interconnect structure 126. It should be noted that, alternatively, the combined second semiconductor layer 108(2) and signal interconnect structure 124 can be coupled to the separate PDN interconnect structure 126 by directly coupling or bonding the exposed second TSVs 122(2) from the second semiconductor layer 108(2) to the exposed second metal interconnects 130(2) in the PDN interconnect structure 126. The signal interconnect structure 124 of the second upper die 106(2) is designed with a first metallization layer 127(1) having metal interconnects 130(1) interconnected vias 132(1) extending in the second vertical direction (Z-axis direction). These interconnected first metal interconnects 130(1) and first vias 132(1) provide input / output (I / O) signal wiring paths for transmitting I / O signals 135S to I / O terminals 134 of the second semiconductor device 110(2) formed in the second semiconductor layer 108(2) of the second upper die 106(2). In this example, the I / O signal 135S is not a power signal for providing power for the operation of the second semiconductor device 110(2). The I / O signal 135S is an input signal for controlling the operation of the coupled second semiconductor device 110(2) as part of a circuit, and / or an output signal carrying a response signal generated by the coupled second semiconductor device 110(2) based on its operation as part of a circuit. The I / O signal 135S may be, for example, a control signal, a communication signal, a sensor signal, etc., associated with a circuit formed by the coupled second semiconductor device 110(2). For example, the I / O terminal 134 may be a source contact, a drain contact, and / or a gate contact coupled to the corresponding source, drain, and gate of the second semiconductor device 110(2).

[0021] PDN interconnect structure 126 includes second metallization layers 137(1) to 137(5), wherein second metal interconnects 130(2) are interconnected vias 132(2) extending in a second vertical direction (Z-axis direction). The interconnected second metal interconnects 130(2) and second vias 132(2) provide power signal routing paths (i.e., power signal paths and ground signal paths) for routing a power signal 135P, which is part of a second PDN 133(2) in a second upper IC 104(2), to a second semiconductor device 110(2), thereby powering the operation of the second semiconductor device. The power signal 135P is a voltage signal for a power node or a ground node, which can provide energy / power to operate the coupled second semiconductor device 110(2). The second TSV 122(2) is disposed in the second semiconductor layer 108(2) in the second vertical direction (Z-axis direction) and coupled to the signal interconnect structure 124 and the PDN interconnect structure 126 to transmit power signals from the PDN interconnect structure 126 to the die 106(2) and to transmit I / O signals from the signal interconnect structure 124 to the PDN interconnect structure 126.

[0022] In this way, I / O signal 135S and power signal 135P can be transmitted via first TSV 122(1) in the first bottom IC 104(1), which are transmitted via metal interconnect 111 (see Figure 1A A second metal interconnect 130(2) coupled to the PDN interconnect structure 126 reaches the second upper IC 104(2). The first bottom IC 104(1) facilitates the supply of power signals (voltage signals, i.e., power signals and ground signals) to the second upper IC 104(2) for distribution within its PDN interconnect structure 126, thereby wiring and distribution to the second semiconductor device 110(2). Power signals 135P can be transmitted from the second TSV 122(2) coupled to the second metal interconnect 130(2) as power signal nodes 130P(2) (i.e., power terminals and ground terminals or planes) in the PDN interconnect structure 126 for distribution to the second semiconductor device 110(2) via the interconnect between the second metal interconnect 130(2) and the second semiconductor device 110(2) interconnected by the second via 132(2). For example, the 3DIC package 100 can be coupled to a power source, such as a power management IC (PMIC), via an external interconnect 118. This power source is configured to supply power via a power signal that is wired through the substrate 120 (e.g., as the package substrate). The power signal transmitted on the external interconnect 118 is coupled to a first metal interconnect 116(1) as part of a first PDN 133(1) in the metal interconnect structure 112(1) of the first bottom die 106(1), such as... Figure 1AAs shown, it can then be wired to the second semiconductor device 110(2) by the second metal interconnect 130(2) of the PDN interconnect structure 126 of the second upper IC 104(2) through the coupled first TSV 122(1) and the metal interconnect 111.

[0023] Continue to refer to Figure 1B The first bottom IC 104(1) also facilitates the provision of I / O signals to the second top IC 104(2), which can then be routed through the second TSV 122(2) to the signal interconnect structure 124 for routing and distributing the I / O signals to the second semiconductor device 110(2). I / O signals can be transmitted from the second TSV 122(2) to coupled first metal interconnects 130(1) in the signal interconnect structure 124. These second TSVs are coupled to second metal interconnects 130S(2) interconnected by second vias 122S(2), each dedicated to I / O signal transmission in the PDN interconnect structure 126. These I / O signal-dedicated second metal interconnects 130S(2) and second vias 122S(2) are not coupled to other metal interconnects 130(2) forming power signal nodes 130P(2), which in this example are configured to transmit power signals. These I / O signals can then be routed from the first metal interconnect 130(1) in the signal interconnect structure 124 and transmitted to the second semiconductor device 110(2). In this way, the performance of the second semiconductor device 110(2) in the second upper die 106(2) can be improved. This is because the power distribution signals do not need to be routed in the shared interconnect structure that is also used to route I / O signals, which could otherwise cause congestion and increase the length of the power distribution signal routing path in the second upper IC 104(2). This can help shorten the length of the power distribution signal path that is located in the PDN interconnect structure 126 and routed to the second semiconductor device 110(2). Therefore, by shortening the length of the power distribution signal routing path, the loop inductance and DC power loss in the power signal are reduced.

[0024] For example Figure 1BAs shown and discussed in more detail below, the separate PDN interconnect structure 126 in the second upper IC 104(2) also helps to minimize the capacitive wiring path length between the decoupling capacitors 138 disposed in the PDN interconnect structure 126, thereby also reducing the loop inductance to improve power noise filtering. In this example, the decoupling capacitor 138 is disposed in the PDN interconnect structure 126 and coupled to the second PDN 133(2) disposed in the second upper IC 104(2) via the second metal interconnect 130(2), which is interconnected via the second via 132(2) and coupled to the second semiconductor device 110(2) to power the operation of the second semiconductor device. In this example, the decoupling capacitor 138 is integrated into the separate PDN interconnect structure 126. Providing a separate PDN interconnect structure 126 in the second upper IC 104(2) facilitates the integration of the decoupling capacitor 138 into the PDN interconnect structure 126, and thus into the second upper IC 104(2), because the I / O signal routing in the PDN interconnect structure 126 is reduced due to the separate signal interconnect structure 124 in the second upper IC 104(2). This, in turn, provides a shorter capacitor signal routing path between the capacitor 138 and the second PDN 133(2) in the second upper IC 104(2). In another example, by coupling a capacitor 138 in the PDN interconnect structure 126 of the second upper IC 104(2) to a second metal interconnect 130(2) serving as a power signal node 130P(2) in the first lower IC 104(1) to receive a power signal 135P, the capacitor 138 can also conveniently provide decoupling capacitance to the first PDN 133(1) in the first lower IC 104(1). This avoids or reduces the need for die-side capacitors (DSC) or pad-side capacitors (LSC), which would have longer capacitive signal routing paths to the first lower IC 104(1) and the second upper IC 104(2) due to wiring through the substrate 120.

[0025] In this example, cavity 140 is formed in second metallization layers 137(1) to 137(2), wherein capacitor 138 may be configured to be integrated within PDN interconnect structure 126. For example, capacitor 138 may be a silicon capacitor (e.g., a deep trench capacitor (DTC)) formed as a separate device in silicon layer 142, which may then be inserted into cavity 140 and interconnected to second metal interconnect 130(2) in PDN interconnect structure 126 to couple to second PDN 133(2). As discussed in more detail below, capacitor 138 may also be formed in a separate dielectric layer (e.g., a silicon oxide layer) in PDN interconnect structure 126, wherein the dielectric layer is Figure 1A and Figure 1B The capacitor 138 is not shown in 3DIC 102. The capacitor 138 can also be directly coupled to a terminal of the second semiconductor device 110 (2), which is coupled to a power signal node 130P (2) in the second metal interconnect 130 (2) to couple the capacitor 138 to the second PDN 133 (2).

[0026] Figure 1A and Figure 1B 3DIC 102 and Figure 2 In contrast to 3DIC 202 in 3DIC package 200, the 3DIC package has an upper second die 206(2) that does not include separate signal interconnect structures and PDN interconnect structures, such as the separate signal interconnect structure 124 and PDN interconnect structure 126 in 3DIC 102. Figure 2 As shown in the side view of 3DIC202, the same first bottom die 106(1) is provided with... Figure 1A and Figure 1B Common elements with common element numbers. The second upper die 206(2) is vertically adjacent to the first lower die 106(1) in the second vertical direction (Z-axis direction) and is coupled to the first lower die 106(1) via a metal interconnect 111. The second upper die 206(2) has a second semiconductor layer 108(2) which is included in... Figure 1A and Figure 1BIn the second upper die 106(2) of the 3DIC 102. However, the second upper die 206(2) has only one interconnect structure 212(2) with metal interconnects 214(2) for routing all I / O signals and power signals to the second semiconductor device 110(2) and the first lower die 106(1). This may increase signal routing congestion in the single interconnect structure 212(2), making it potentially more difficult to provide sufficient signal routing density in the second upper die 206(2) without otherwise increasing the footprint of the first lower die 106(1) and the second upper die 206(2). Furthermore, setting a single interconnect structure 212(2) in the second upper die 206(2) may make it more difficult to set decoupling capacitors in the second interconnect structure 212(2) to facilitate providing decoupling capacitance in the 3DIC 202.

[0027] like Figure 3 As shown in another exemplary 3DIC package 300, a second upper die 206(2) may be laterally offset from a first bottom die 106(1) in a first horizontal direction (X-axis and / or Y-axis direction) to provide space for a decoupling capacitor 302 to be directly coupled to a non-overlapping second side 304(2) of the second upper die 206(2), which is opposite to the first side 304(1) of the second upper die 206(2) in a second vertical direction (Z-axis direction). In this way, the decoupling capacitor 302 is positioned closer to the second upper die 206(2) to shorten the capacitance signal wiring path from the decoupling capacitor 302 to the second upper die 206(2) and / or the first bottom die 106(1), rather than providing decoupling capacitance via DSC or LSC. However, as Figure 3 As shown, this increases the lateral distance D1 and thus the lateral area of ​​the 3DIC 302, thereby increasing the overall size of the 3DIC package 300, which may be undesirable or impractical for the intended application of the 3DIC package 300.

[0028] Figure 4A and Figure 4B The figures shown are a side view and a close-up side view of another exemplary IC package 400 including IC 404. This IC includes a die 406, which also includes a separate signal interconnect structure 124. IC 404 also includes a separate PDN interconnect structure 426 to reduce signal routing congestion and power signal routing path length in IC 404, thereby improving the performance of die 406. As a non-limiting example, die 406 may be included as... Figure 1A and Figure 1B The second upper bare die 106(2) in 3DIC 102. Figure 4A and Figure 4BNude film 406 and Figure 1A and Figure 1B The common elements between the second upper die 106(2) are shown by common element numbering. As discussed below, in this exemplary IC 404, the PDN interconnect structure 426 is similar to Figure 1A and Figure 1B The second upper IC 104(2) in the 3DIC 102 has a PDN interconnect structure 126, but the PDN interconnect structure 426 includes a separate silicon layer 442 having a capacitor 438 disposed therein to provide the capacitor 438 as a silicon capacitor.

[0029] In this example, die 406 is a semiconductor die by including semiconductor layer 108(2) and signal interconnect structure 124. In this example, PDN interconnect structure 426 does not include a semiconductor layer in which semiconductor devices are formed. However, it should be noted that alternatively, PDN interconnect structure 426 may be included as part of a die that also includes a semiconductor layer in which semiconductor devices are formed, and signal interconnect structure 124 may be manufactured without a semiconductor layer.

[0030] refer to Figure 4A The occupied area of ​​IC 404 and its die 406 extends in a first horizontal direction (X-axis and Y-axis directions). Die 406 includes a second semiconductor layer 108(2), wherein the second semiconductor device 110(2) is as described above. Figure 1A and Figure 1B The die 406 is formed as described in 3DIC 102. The die 406 also has corresponding metal interconnect structures 412 (e.g., metal lines, metal traces) having metallization layers 414, each having metal interconnects 116(2) to provide signal wiring paths in the die 406 to its second semiconductor device 110(2). Figure 4A and Figure 4BA close-up partial side view of IC 404 is shown. IC 404 includes a separate signal interconnect structure 124 and a PDN interconnect structure 426 on a die 406 to reduce signal routing congestion and power signal routing path length in IC 404, thereby improving the performance of the second semiconductor device 110(2). I / O signals 135S and power signals 135P can be transmitted from the second metal interconnect 130(2) in the PDN interconnect structure 426 to the second semiconductor device 110(2). Power signals 135P can be transmitted from the second semiconductor device 110(2) from third TSVs 122(3), which are coupled to the second metal interconnect 130(2) and its interconnect vias 132(2), serving as power signal nodes 130P(2) (i.e., power terminals and ground terminals or planes) in the PDN interconnect structure 426. Power signal 135P is transmitted from the third TSV 122(3) in the PDN interconnect structure 426 to the second TSV 122(2) coupled to the second semiconductor device 110(2) in the semiconductor layer 108(2). For example, IC package 400 can be coupled to a power source, such as a power management IC (PMIC), via external interconnect 118, which is configured to supply power via a power signal that is wired through substrate 120 (e.g., as a package substrate).

[0031] For example Figure 4A As shown, providing a separate PDN interconnect structure 426 in IC 404 can also help minimize the capacitive wiring path length between the decoupling capacitors 438 disposed in the PDN interconnect structure 426, thereby also reducing the loop inductance to improve power noise filtering. In this example, the decoupling capacitors 438 are disposed in the PDN interconnect structure 426 and are coupled to the second PDN 133(2) disposed in IC 404 via the second metal interconnect 130(2), which is interconnected via third TSVs 122(3), which are coupled to the second TSVs 122(2) in semiconductor layer 108(2), which are coupled to the second semiconductor device 110(2) to power the operation of the second semiconductor device. Setting up a separate PDN interconnect structure 426 within IC 404 makes it easier to integrate the decoupling capacitor 438 into the PDN interconnect structure 426, and thus into IC 404, because the I / O signal routing in the PDN interconnect structure 426 is reduced due to the separate PDN interconnect structure 426 within IC 404. This, in turn, provides a shorter capacitor signal routing path between capacitor 438 and the second PDN 133(2) in IC 404. This avoids or reduces the need for a DSC or LSC, which would have a longer capacitor signal routing path to IC 404 due to routing through substrate 120.

[0032] In this example, decoupling capacitor 438 is integrated as a silicon capacitor (e.g., DTC) into a separate silicon layer 442 within a separate PDN interconnect structure 426. The decoupling capacitor 438, interconnected to a second metal interconnect 130(2) in the PDN interconnect structure 426, is coupled to a second PDN 133(2). Capacitor 438 can also be directly coupled to a terminal of a second semiconductor device 110(2), which is coupled to a power signal node 130P(2) in the second metal interconnect 130(2), to couple capacitor 438 to the second PDN 133(2).

[0033] In addition, such as Figure 4B As shown, the signal interconnect structure 124 and the PDN interconnect structure 426 can be fabricated separately as part of a second separate wafer and coupled in the second vertical direction (Z-axis direction) to or adjacent to a second side 128(2) of the second semiconductor layer 108(2) opposite to the first side 128(1). The combined second semiconductor layer 108(2) and signal interconnect structure 124 can be coupled to the separate PDN interconnect structure 426 via a metal bump layer 129 (e.g., via a wafer-to-wafer (WoW) bonding process during fabrication), which includes a plurality of metal bumps 131 interconnecting between exposed second TSVs 122(2) and exposed third TSVs 122(3) of second metal interconnects 130(2) interconnected to the PDN interconnect structure 426, the second TSVs extending through the second semiconductor layer 108(2) in the second vertical direction (Z-axis direction) and adjacent to the PDN interconnect structure 426. It should be noted that, alternatively, the combined second semiconductor layer 108(2) and signal interconnect structure 124 can be coupled to a separate PDN interconnect structure 426 by directly coupling or bonding an exposed second TSV 122(2) from the second semiconductor layer 108(2) to an exposed third TSV 122(3) of a second metal interconnect 130(2) interconnected to the PDN interconnect structure 426.

[0034] Figure 5A and 5B The figures shown are a side view and a close-up side view of another exemplary IC package 500 including IC 504. This IC includes a die 506, which also includes a separate signal interconnect structure 124. IC 504 includes a die 506 with signal interconnect structure 124 and a separate PDN interconnect structure 526 to reduce signal routing congestion and power signal routing path length in IC 504, thereby improving the performance of die 506. As a non-limiting example, die 506 may be included as... Figure 1A and Figure 1B The second upper bare die 106(2) in 3DIC 102. Figure 5A and Figure 5B Nude film 506 and Figure 1A and Figure 1B The common elements between the second upper die 106(2) are shown by common element numbering. As discussed below, in this example IC504, the PDN interconnect structure 526 is similar to Figure 1A and Figure 1B 3DIC 102 and Figure 4A and Figure 4B The PDN interconnect structures 126, 426 in IC 404 and the second upper IC 104 (2). However, the PDN interconnect structure 526 in IC 504 includes a separate dielectric layer 542 (e.g., a silicon oxide layer) having a capacitor 538 disposed therein to provide the capacitor 538 as a dielectric capacitor.

[0035] In this example, die 506 is a semiconductor die by including semiconductor layer 108(2) and signal interconnect structure 124. In this example, PDN interconnect structure 526 does not include a semiconductor layer in which semiconductor devices are formed. However, it should be noted that alternatively, PDN interconnect structure 526 may be included as part of a die that also includes a semiconductor layer in which semiconductor devices are formed, and signal interconnect structure 124 may be manufactured without a semiconductor layer.

[0036] refer to Figure 5A The occupied area of ​​IC 504 and its die 506 extends in a first horizontal direction (X-axis and Y-axis directions). Die 506 includes a second semiconductor layer 108(2), wherein the second semiconductor device 110(2) is as described above. Figure 1A and Figure 1B The die 506 is formed as described in 3DIC 102. The die 506 also has corresponding metal interconnect structures 512 (e.g., metal lines, metal traces) having metallization layers 514, each having metal interconnects 116(1) to provide signal wiring paths in the die 506 to its second semiconductor device 110(2). Figure 5A and Figure 5BA close-up partial side view of IC 504 is shown. IC 504 includes separate signal interconnect structure 124 and PDN interconnect structure 526 to reduce signal routing congestion and power signal routing path length in IC 504, thereby improving the performance of the second semiconductor device 110(2). I / O signal 135S and power signal 135P can be transmitted from the second metal interconnect 130(2) in PDN interconnect structure 526 to the second semiconductor device 110(2). Power signal 135P can be transmitted from the third TSV 122(3) coupled to the second metal interconnect 130(2), as power signal node 130P(2) in PDN interconnect structure 526 (i.e., power terminal and ground terminal or plane), to be distributed to the second semiconductor device 110(2) through the interconnect between the second metal interconnect 130(2) interconnected by the second via 132(2). For example, IC package 500 can be coupled to a power source, such as a PMIC, via external interconnect 118, which is configured to supply power via a power signal that is wired through substrate 120 (e.g., as a package substrate).

[0037] like Figure 5A As shown, providing a separate PDN interconnect structure 526 in IC 504 can also help minimize the capacitive wiring path length between the decoupling capacitors 538 disposed in the PDN interconnect structure 526, thereby also reducing loop inductance to improve power noise filtering. In this example, the decoupling capacitors 538 are disposed in the PDN interconnect structure 526 and coupled to the second PDN 133(2) disposed in IC 504 via the second metal interconnect 130(2), which is interconnected via the second via 132(2) and coupled to the second semiconductor device 110(2) to power the operation of the second semiconductor device. Providing a separate PDN interconnect structure 526 in IC 504 makes it easier to integrate the decoupling capacitors 538 into the PDN interconnect structure 526, and thus into IC 504, because the I / O signal wiring in the PDN interconnect structure 526 is reduced due to the separate PDN interconnect structure 526 in IC 504. This, in turn, provides a shorter capacitor signal routing path between capacitor 538 and the second PDN 133(2) in IC 504. This avoids or reduces the need for a DSC or LSC, which would have a longer capacitor signal routing path to IC 504 due to the routing through substrate 120.

[0038] In this example, the decoupling capacitor 538 is integrated as a silicon capacitor (e.g., an integrated stacked capacitor (ISC)) into a separate dielectric layer 542 within a separate PDN interconnect structure 526. The decoupling capacitor 538 is interconnected to a second metal interconnect 130(2) within the PDN interconnect structure 526 to couple to a second PDN 133(2). The capacitor 538 can also be directly coupled to a terminal of a second semiconductor device 110(2), which is coupled to a power signal node 130P(2) within the second metal interconnect 130(2), to couple the capacitor 538 to the second PDN 133(2).

[0039] In addition, such as Figure 5B As shown, the signal interconnect structure 124 and the PDN interconnect structure 526 can be fabricated separately as part of a second separate wafer and coupled in the second vertical direction (Z-axis direction) to or adjacent to a second side 128(2) of the second semiconductor layer 108(2) opposite to the first side 128(1). The combined second semiconductor layer 108(2) and signal interconnect structure 124 can be coupled to the separate PDN interconnect structure 526 via a metal bump layer 129 comprising a plurality of metal bumps 131 (e.g., formed by a wafer-to-wafer (WoW) bonding process during fabrication). The metal bumps 131 interconnect between exposed second TSVs 122(2) and exposed third TSVs 122(3) extending through the second semiconductor layer 108(2) in the second vertical direction (Z-axis direction) and adjacent to the PDN interconnect structure 526, and the third TSVs interconnect to second metal interconnects 130(2) in the PDN interconnect structure 526. Note that alternative locations, such as Figure 5C As shown, the combined second semiconductor layer 108(2) and signal interconnect structure 124 can be coupled to the individual PDN interconnect structure 526 by directly coupling or bonding the exposed second TSV 122(2) from the second semiconductor layer 108(2) to the exposed third TSV 122(3) of the second metal interconnect 130(2) interconnected to the PDN interconnect structure 526.

[0040] An IC can be manufactured according to a specific manufacturing process, comprising separate signal interconnect structures and PDN interconnect structures to reduce signal routing congestion and power signal routing path length, thereby improving IC and die performance. Decoupling capacitors can be integrated into the IC's PDN interconnect structure to provide decoupling capacitance to the PDN within the IC. In this regard, Figure 6 This is a flowchart illustrating an exemplary manufacturing process 600 for manufacturing an IC, including but not limited to... Figures 1A to 1B , Figures 4A to 4B and Figures 5A to 5CICs 102, 404, and 504 include separate signal interconnect structures and PDN interconnect structures to reduce signal routing congestion and power signal routing path length, thereby improving IC and die performance, and wherein decoupling capacitors can be integrated into the PDN interconnect structure of the IC to provide decoupling capacitance to the PDN in the IC. Figure 6 The manufacturing process 600 in the document is a reference. Figures 4A to 4B This discussion is based on IC404, but the manufacturing process 600 is not limited to this.

[0041] In this regard, such as Figure 6 As shown, the manufacturing process 600 for manufacturing IC 404 may include forming a semiconductor layer 108(2), the semiconductor layer including a first side 128(1) and a second side 128(2) opposite to the first side 128(1). Figure 6 (See box 602 in the middle). The manufacturing process 600 may also include forming a plurality of semiconductor devices 110(2), each of the plurality of semiconductor devices including I / O terminals 134 located in the semiconductor layer 108(2). Figure 6 (See frame 604 in the text). The manufacturing process 600 may further include forming a plurality of first vias 122(2), each of the plurality of first vias extending through the semiconductor layer 108(2). Figure 6 (Box 606 in the middle). The manufacturing process 600 may also include forming a signal interconnect structure 124 adjacent to the first side 128(1) of the semiconductor layer 108(2). Figure 6 (See box 608 in the image). The signal interconnect structure 124 also includes forming a plurality of first metal interconnects 130(1), each of the plurality of first metal interconnects being coupled to an I / O terminal 134 of a first semiconductor device 110(2) among the plurality of semiconductor devices 110(2). Figure 6 (Box 610 in the middle). Manufacturing process 600 may also include forming PDN interconnect structure 426 ( Figure 6 (See box 612 in the middle). Forming the PDN interconnect structure 426 also includes forming a plurality of second metal interconnects 130(2), each of which is coupled to a power signal node 130P(2). Figure 6 (Box 614 in the middle). The manufacturing process 600 may also include coupling the PDN interconnect structure 426 adjacent to the second side 128(2) of the semiconductor layer 108(2) by coupling each of the plurality of second metal interconnects 130(2) to a first via 122(2) of the plurality of vias 122(2). Figure 6 (Box 616 in the middle).

[0042] An IC can be manufactured according to a specific manufacturing process, comprising separate signal interconnect structures and PDN interconnect structures to reduce signal routing congestion and power signal routing path length, thereby improving IC and die performance. Decoupling capacitors can be integrated into the IC's PDN interconnect structure to provide decoupling capacitance to the PDN within the IC. In this regard, Figure 6 This is a flowchart illustrating an exemplary manufacturing process 600 for manufacturing an IC, including but not limited to... Figures 1A to 1B , Figures 4A to 5C ICs 102, 404, and 504 can be manufactured in other manufacturing processes.

[0043] For example, Figures 7A to 7C This is a flowchart illustrating a manufacturing process 700 for manufacturing a second wafer 802(2), the second wafer comprising as... Figure 4A and Figure 4B The PDN interconnect structure 426 is a part of IC 404. As discussed below, a second wafer 802(2) having the PDN interconnect structure 426 can be coupled to a first wafer including a second semiconductor layer 108(2) and a signal interconnect structure 124 to form a die 406 as part of a WoW bonding process. As discussed above, fabricating the PDN interconnect structure 426 and the second semiconductor layer 108(2) and signal interconnect structure 124 as separate wafers has the advantage of using a die fabrication process to form IC 404 having its two separate PDN interconnect structures 426 and signal interconnect structures 124. Figures 8A to 8E It is based on Figures 7A to 7C Exemplary manufacturing stages 800A to 800E are described below during the exemplary manufacturing process 700, which manufactures the PDN interconnect structure 426. Figure 4A and Figure 4B Discussion of exemplary IC 404 Figures 7A to 7C The manufacturing process is 700, but this is not limiting.

[0044] In this regard, such as Figure 8A As shown in exemplary manufacturing stage 800A, the first step in manufacturing process 700 for manufacturing a second wafer 802(2) including a PDN interconnect structure 426 is to provide a carrier wafer 803 and form a silicon layer 804 on the carrier wafer 803. Figure 7A (Box 702 in the middle). This is to prepare silicon layer 804 for processing, thereby forming capacitor 438 in silicon layer 804, which will become silicon layer 442 in PDN interconnect structure 426, wherein capacitor 438 will be coupled to second metal interconnect 130(2) as part of second PDN 133(2) to provide decoupling capacitance in IC 404. Then, as Figure 8BAs shown in exemplary manufacturing stage 800B, the next step in manufacturing process 700, which manufactures a second wafer 802(2) including a PDN interconnect structure 426, is to form a capacitor 438 in silicon layer 804 and a third TSV 122(3) in silicon layer 804. Figure 7A (Box 704 in the diagram). This is to provide signal routing paths between the PDN interconnect structure 426 and the capacitor 438, and between the final second semiconductor layer 108(2) coupled to the PDN interconnect structure 426 and the signal interconnect structure 124.

[0045] Then, as Figure 8C As shown in exemplary manufacturing stage 800C, the next step in manufacturing process 700, which manufactures a second wafer 802(2) including a PDN interconnect structure 426, is to form a metallization layer 137 on a silicon layer 804, wherein certain metal interconnects 130(2) in the metallization layer 137 are coupled to a capacitor 438. Figure 7B (See box 706 in the image). The metallization layer 137 can be formed using the BEOL process, which is typically used to form metallization layers in a die. Then, as... Figure 8D As shown in the exemplary manufacturing stage 800D, the next step in the manufacturing process 700 of manufacturing a second wafer 802(2) including a PDN interconnect structure 426 is to provide a solder mask layer 806 on the metallization layer 137 to create openings in the outer metallization layer 137(3) to form an outer interconnect 118. Figure 7B (Box 708 in the text). Then, as... Figure 8E As shown in the exemplary manufacturing stage 800E, the next step in the manufacturing process 700 for manufacturing a second wafer 802(2) including the PDN interconnect structure 426 is to remove the carrier wafer 803, then grind and thin the solder resist layer 806 to form the PDN interconnect structure 426, and prepare the metallization layer 137 for bump formation to form an external interconnect 118 to be formed to contact the second metal interconnect 130(2) in the external metallization layer 137(3). Figure 7C (See box 710 in the middle). A second metal bump layer 129(2) with second metal bumps 131(2) is also formed on the silicon layer 446 to prepare for bonding the PDN interconnect structure 426 to another wafer, which will have a second semiconductor layer 108(2) and signal interconnect structure 124 formed as part of a separate wafer, as part of the WoW bonding process.

[0046] Figures 9A to 9CThis is a flowchart illustrating an exemplary manufacturing process 900 in which a second semiconductor layer 108(2) and a signal interconnect structure 124 are separately manufactured as part of a separate first wafer 802(1), which is coupled to the second wafer 802(2) via a PDN interconnect structure 426 to form a combined wafer, which can then be diced to form a shape similar to Figure 4A and Figure 4B IC 404 in the middle. Figures 10A to 10E This refers to exemplary manufacturing stages 1000A to 1000E during the fabrication of a first wafer 802(1), which will include a second semiconductor layer 108(2) and a signal interconnect structure 124 that can be coupled to... Figure 8E The second wafer 802(2) is used to form a combined wafer, which can be configured according to... Figures 9A to 9C The exemplary manufacturing process 900 in the example is cut into similar shapes. Figure 4A and Figure 4B The IC 404 is mentioned below. See reference below. Figure 4A and Figure 4B Let's discuss the exemplary die 406 in IC 404. Figures 9A to 9C The manufacturing process is 900, but this is not limiting.

[0047] In this regard, such as Figure 10A As shown in the exemplary manufacturing stage 1000A, the first step in the manufacturing process 900 for manufacturing a first wafer 802(1) including a second semiconductor layer 108(2) and a signal interconnect structure 124 is to provide a carrier wafer 1003 and form the second semiconductor layer 108(2), which undergoes diffusion to prepare for the formation of a second semiconductor device 110(2) therein. Figure 9A (Box 902 in the middle). Then, as... Figure 10B As shown in the exemplary manufacturing stage 1000B, the next step in the manufacturing process 900 for manufacturing the first wafer 802 (1) includes forming a second semiconductor device 110 (2) in a second semiconductor layer 108 (2) and drilling a borehole 1006 in the second semiconductor layer 108 (2) to form a second TSV 122 (2). Figure 9A (in box 904). Part of forming the second semiconductor device 110(2) is forming a metal contact layer 1004 including a gate and metal contacts for the second semiconductor device 110(2), either of which may be an I / O terminal 134.

[0048] Then, as Figure 10CAs shown in the exemplary manufacturing stage 1000C, the next step in the manufacturing process 900 of manufacturing a first wafer 802(1) including a second semiconductor layer 108(2) and a signal interconnect structure 124 is to form a second TSV 122(2) in the second semiconductor layer 108(2) by depositing metal into a drill hole 1006. Figure 9B (in box 906). The second TSV 122(2) will be coupled to the second semiconductor device 110(2). Figure 9B (in box 906). The second TSV 122(2) will eventually be coupled to Figure 8E The PDN interconnect structure 426 in the second wafer 802(2) provides signal routing paths between the PDN interconnect structure 426 and the second semiconductor layer 108(2) and between the second semiconductor device 110(2) and the signal interconnect structure 124. Then, as Figure 10D As shown in the exemplary manufacturing stage 1000D, the next step in the manufacturing process 900 of manufacturing the first wafer 802 (1) is to form first metallization layers 127 (1) to 127 (3) and their first metal interconnects 130 (1) and first vias 132 (1), thereby forming a signal interconnect structure 124 on the metal contact layer 1004 and the second semiconductor layer 108 (2). Some of the first metal interconnects 130 (1) are coupled to the second TSV 122 (2) and the second semiconductor device 110 (2) to provide I / O signals 135S (which are routed to the second semiconductor device 110 (2) and ultimately to the PDN interconnect structure 426 when the second wafer 802 (2) is coupled to the first wafer 802 (1). Figure 9B (in box 908). The first metallization layers 127(1) to 127(3) can be formed as part of the BEOL manufacturing process.

[0049] Then, as Figure 10E As shown in the exemplary manufacturing stage 1000E, the next step in the manufacturing process 900 of manufacturing a first wafer 802(1) including a second semiconductor layer 108(2) and a signal interconnect structure 124 is to remove the carrier wafer 1003 and form an insulating layer 1008 on the outer metallization layer 127(3) of the signal interconnect structure 124 to protect the signal interconnect structure 124. Figure 9C (in box 910). A first metal bump layer 129(1) having a first metal bump 131(1) is also formed on the second semiconductor layer 108(2), wherein the first metal bump 131(1) is coupled to the second TSV 122(2) in preparation for bonding the first wafer 802(1) to the second semiconductor layer 108(2) as part of the WoW bonding process. Figure 8E The second wafer 802(2) in the process.

[0050] Figure 11 This is an example of Figure 8E A separately fabricated second wafer 802(2) with a PDN interconnect structure 426 is coupled to Figure 10E A flowchart of an exemplary manufacturing process 1100 for forming a composite wafer 1202 from a first wafer 802(1) having a second semiconductor layer 108(2) and a signal interconnect structure 124, which can be diced into individual ICs, such as... Figure 4A and Figure 4B IC 404 in the middle. Figure 12A and Figure 12B Is it to Figure 8E A separately fabricated second wafer 802(2) with a PDN interconnect structure 426 is coupled to Figure 10E The exemplary manufacturing stages 1200A to 1200B during the formation of a combined wafer 1202 from a first wafer 802(1) having a second semiconductor layer 108(2) and a signal interconnect structure 124, which can be manufactured according to... Figure 11 The exemplary process in the example is cut into individual ICs, such as Figure 4A and Figure 4B IC 404 in the middle.

[0051] In this regard, such as Figure 12A As shown in the exemplary manufacturing stage 1200A, manufacturing Figure 4A and Figure 4B The first step in the manufacturing process 1100 of IC 404 is to provide a first wafer 802(1) and a second wafer 802(2), and to align the first wafer 802(1) and the second wafer 802(2) such that their respective metal bump layers 129(1), 129(2) are adjacent to each other and aligned for coupling. Figure 11 (Box 1102 in the middle). Then, as... Figure 12B As shown in the exemplary manufacturing stage 1200B, manufacturing Figure 4A and Figure 4B The next step in the manufacturing process 1100 of IC 404 is to couple the first metal bump 131(1) and the second metal bump 131(2) of the corresponding first wafer 802(1) and second wafer 802(2) to couple the first wafer 802(1) to the second wafer 802(1), thereby providing a combined wafer 1202 ( Figure 11 (Box 1104 in the diagram). This provides electrical coupling between the PDN interconnect structure 426 and the signal wiring path between the second semiconductor layer 108(2) and the signal interconnect structure 124. The combined wafer 1202 can then be diced to form multiple ICs, such as... Figure 4A and Figure 4B IC 404 in the middle.

[0052] Figures 13A to 13CThis is a flowchart illustrating a manufacturing process 1300 for manufacturing a second wafer 1402(2), the second wafer comprising as... Figure 5A and Figure 5B A portion of IC 504 contains a PDN interconnect structure 526. As discussed below, a second wafer 1402(2) having the PDN interconnect structure 526 can be coupled to... Figure 10E The first wafer 802(1) in the process includes Figures 5A to 5B and Figure 10E The second semiconductor layer 108(2) and signal interconnect structure 124 are formed as part of the WoW bonding process to create a die 506. As discussed above, fabricating the PDN interconnect structure 526 and the second semiconductor layer 108(2) and signal interconnect structure 124 as separate wafers has the advantage of using a die fabrication process to form an IC 504 having its two separate PDN interconnect structures 526 and signal interconnect structures 124. Figures 14A to 14E It is based on Figures 13A to 13C Exemplary manufacturing stages 1400A to 1400E are described in exemplary manufacturing process 1300 during the manufacture of PDN interconnect structure 526. References below... Figure 5A and Figure 5B Discussion of Exemplary IC 504 Figures 13A to 13C The manufacturing process is 1300, but this is not limiting.

[0053] In this regard, such as Figure 14A As shown in exemplary manufacturing stage 1400A, the first step in manufacturing process 1300 for manufacturing a second wafer 1402(2) including a PDN interconnect structure 526 is to provide a carrier wafer 1403 and form a dielectric layer 1404 on the carrier wafer 1403. Figure 13A (Box 1302 in the diagram). This is to prepare the dielectric layer 1404 for processing, thereby forming the third TSV 122(3) in the PDN interconnect structure 526. Then, as... Figure 14B As shown in exemplary manufacturing stage 1400B, the next step in manufacturing process 1300, which manufactures a second wafer 1404(2) including a PDN interconnect structure 526, is to form a third TSV 122(3) in the dielectric layer 1404. Figure 13A (Box 1304 in the diagram). This is to provide a signal routing path between the PDN interconnect structure 526 and the capacitor 538 and the metal interconnects 130 (2), which will be formed in the added metallization layers 137 (1) to 137 (3) and the final second semiconductor layer 108 (2) coupled to the PDN interconnect structure 526 and the signal interconnect structure 124.

[0054] Then, as Figure 14CAs shown in the exemplary manufacturing stage 1400C, the next step in the manufacturing process 1300 for manufacturing a second wafer 1402(2) including a PDN interconnect structure 526 is to form metallization layers 137(1) to 137(3) on a dielectric layer 1404, wherein certain metal interconnects 130(2) are present in the metallization layers 137(1) to 137(3), and to form a dielectric layer 542, wherein a dielectric capacitor 538 formed therein is coupled to the metal interconnects 130(2) to provide decoupling capacitance. Figure 13B (See box 1306 in the image). Metallization layers 137(1) to 137(3) can be formed using the BEOL process commonly used to form metallization layers in a die. Then, as... Figure 14D As shown in exemplary manufacturing stage 1400D, the next step in manufacturing process 1300 for manufacturing a second wafer 1402(2) including PDN interconnect structure 526 is to form a solder resist layer 1406 on dielectric layer 542 to create openings in external metallization layer 137(3) to form external interconnect 118. Figure 13B (Box 1308 in the middle).

[0055] Then, as Figure 14E As shown in the exemplary manufacturing stage 1400E, the next step in the manufacturing process 1300 for manufacturing a second wafer 1402(2) including the PDN interconnect structure 526 is to remove the carrier wafer 1403, then grind and thin the solder resist layer 1406 to form the PDN interconnect structure 526, and prepare the external metallization layer 137(3) for bump formation to form the external interconnect 118 to be formed to contact the second metal interconnect 130(2) in the external metallization layer 137(3). Figure 13C (Box 1310 in the middle). A second metal bump layer 129(2) with second metal bumps 131(2) is also formed on the dielectric layer 546 to prepare for bonding the PDN interconnect structure 526 to. Figure 10E Another first wafer 802(1) will have a second semiconductor layer 108(2) and a signal interconnect structure 124 formed as part of a separate wafer, as part of the WoW bonding process.

[0056] Figure 15 This is an example of Figure 14E A separately fabricated second wafer 1402(2) with a PDN interconnect structure 526 is coupled to Figure 10E A flowchart of an exemplary process 1500 for forming a composite wafer 1602 from a first wafer 802 (1) having a second semiconductor layer 108 (2) and a signal interconnect structure 124, which can be diced into individual ICs, such as... Figure 5A and Figure 5B IC 504 in the middle. Figure 16A and Figure 16B Is it to Figure 14E A separately fabricated second wafer 1402(2) with a PDN interconnect structure 526 is coupled to Figure 10E The exemplary manufacturing stages 1600A to 1600B during the formation of a combined wafer 1602, which has a second semiconductor layer 108(2) and a signal interconnect structure 124, can be customized according to the following specifications: Figure 11 The exemplary process in the example is cut into individual ICs, such as Figure 5A and Figure 5B IC 504 in the middle.

[0057] In this regard, such as Figure 16A As shown in the exemplary manufacturing stage 1600A, manufacturing Figure 5A and Figure 5B The first step in the manufacturing process of IC 504 in 1500 is to provide Figure 10E The first wafer 802(1) and Figure 14E The second wafer 1402(2) is aligned with the first wafer 802(1) and the second wafer 1402(2) such that their respective metal bump layers 129(1), 129(2) are adjacent to each other and aligned for coupling. Figure 15 (Box 1502 in the middle). Then, as... Figure 16B As shown in the exemplary manufacturing stage 1600B, manufacturing Figure 5A and Figure 5B The next step in the manufacturing process 1500 of IC 504 is to couple the first metal bump 131(1) and the second metal bump 132(2) of the corresponding first wafer 802(1) and second wafer 1402(2) to couple the first wafer 802(1) to the second wafer 1402(1), thereby providing a combined wafer 1602 ( Figure 15 (Box 1504 in the diagram). This provides electrical coupling between the PDN interconnect structure 526 and the signal wiring path between the second semiconductor layer 108(2) and the signal interconnect structure 124. The combined wafer 1602 can then be diced to form multiple ICs, such as... Figure 5A and Figure 5B IC 504 in the middle.

[0058] It should be understood that the terms “first,” “second,” “third,” etc., used herein are relative terms and do not imply limitation or a strict orientation. It should also be understood that the terms “top,” “above,” “over,” and “bottom,” “below,” “below,” “below,” “top,” “bottom,” “below,” “bottom,” “below,” “top,” “above,” “top,” “bottom,” “below,” “bottom,” “below,” “top,” “above,” “top,” “bottom,” “below,” “bottom,” “below,” “top,” “top,” “top,” “bottom,” “below,” “bottom,” “bottom,” “bottom,” “bottom,” “top,” “top,” “top,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “top,” “top,” “above,” “top,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “top,” “above,” “top,” “above,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “top,” “above,” “top,” “above,” “top,” “above,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “top,” “above,” “top,” “above,” “top,” “above,” “top,” “top,” “bottom ...top,” “top,” “above,” “top,” “above,” “top,” “top,” “bottom,” “bottom

[0059] Additionally, as discussed in this paper, object "proximity" refers to an object being next to or adjacent to another stated object. Adjacent objects may not be directly physically coupled to each other. Objects can be directly adjacent to another object, meaning that such objects are directly next to or adjacent to another object, without any other object or layer situated between the directly adjacent objects. Objects can be indirectly or indirectly adjacent to another object, meaning that such objects are not directly next to or directly close to each other, but rather with an intermediate object or layer situated between the indirectly adjacent objects.

[0060] The IC can be located in or integrated into any processor-based device. The IC includes separate signal interconnect structures and PDN interconnect structures to reduce signal routing congestion and power signal routing path length, thereby improving IC and die performance. Decoupling capacitors can be integrated into the IC's PDN interconnect structure to provide decoupling capacitance to the PDN within the IC, including but not limited to... Figures 1A to 1B , Figures 4A to 5C , Figure 12B and Figure 16B ICs 102, 404, and 504, and can be manufactured according to manufacturing processes, including but not limited to... Figure 6 , Figures 7A to 7C , Figures 9A to 9C , Figure 11 , Figures 13A to 13C and Figure 15The exemplary manufacturing processes 600, 700, 900, 1100, 1300, and 1500 described herein, and manufacturing in accordance with any aspect disclosed herein, are examples. Examples not intended to be limiting include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet devices, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotor aircraft.

[0061] In this regard, Figure 17 An exemplary wireless communication device 1700 is illustrated, which includes one or more IC packages 1702(1), 1702(2), the one or more IC packages including one or more ICs 1703, 1703(1), 1703(2), including but not limited to Figures 1A to 1B , Figures 4A to 5C , Figure 12B and Figure 16B ICs 102, 404, and 504, one or more of which include separate signal interconnect structures and PDN interconnect structures to reduce signal routing congestion and power signal routing path length, thereby improving IC and die performance, and wherein decoupling capacitors may be integrated into the PDN interconnect structure of the IC to provide decoupling capacitance to the PDN in the IC, and may be manufactured according to a manufacturing process, including but not limited to Figure 6 , Figures 7A to 7C , Figures 9A to 9C , Figure 11 , Figures 13A to 13C and Figure 15 The exemplary manufacturing processes 600, 700, 900, 1100, 1300, and 1500 are described herein and are manufactured according to any aspect disclosed herein.

[0062] As an example, wireless communication device 1700 may include any of the devices mentioned above or be provided in any of the devices mentioned above. Figure 17As shown, the wireless communication device 1700 includes a transceiver 1704 and a data processor 1706. The data processor 1706 may include memory for storing data and program code. The transceiver 1704 includes a transmitter 1708 and a receiver 1710 supporting bidirectional communication. Generally, the wireless communication device 1700 may include any number of transmitters 1708 and / or receivers 1710 for any number of communication systems and frequency bands. All or part of the transceiver 1704 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0063] The transmitter 1708 or receiver 1710 can be implemented using either a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes multi-stage frequency conversion between RF and baseband; for example, for receiver 1710, it is converted from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal is converted between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 17 In the wireless communication device 1700, the transmitter 1708 and receiver 1710 are implemented using a direct frequency conversion architecture.

[0064] In the transmission path, data processor 1706 processes the data to be transmitted and provides I and Q analog output signals to transmitter 1708. In the exemplary wireless communication device 1700, data processor 1706 includes digital-to-analog converters (DACs) 1712(1) and 1712(2) to convert the digital signals generated by data processor 1706 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0065] Within transmitter 1708, low-pass filters 1714(1) and 1714(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1716(1) and 1716(2) amplify the signals from low-pass filters 1714(1) and 1714(2), respectively, and provide I and Q baseband signals. Upconverter 1718 upconverts the I and Q baseband signals using the I and Q TX LO signals from transmit (TX) local oscillator (LO) signal generator 1722 via mixers 1720(1) and 1720(2) to provide upconverted signal 1724. Filter 1726 filters upconverted signal 1724 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 1728 amplifies the up-converted signal 1724 from filter 1726 to obtain the desired output power level and provide a transmit RF signal. The transmit RF signal is directed through duplexer or switch 1730 and transmitted via antenna 1732.

[0066] In the receiving path, antenna 1732 receives signals transmitted by the base station and provides the received RF signal, which is guided through duplexer or switch 1730 and provided to low-noise amplifier (LNA) 1734. Duplexer or switch 1730 is designed to operate using a specific receive (RX) to TX duplexer frequency separation, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1734 and filtered by filter 1736 to obtain the desired RF input signal. Downconversion mixers 1738(1) and 1738(2) mix the output of filter 1736 with the I and Q RXLO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1740 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1742(1) and 1742(2) and further filtered by low-pass filters 1744(1) and 1744(2) to obtain I and Q analog input signals, which are provided to data processor 1706. In this example, data processor 1706 includes analog-to-digital converters (ADCs) 1746(1) and 1746(2) to convert the analog input signals into digital signals to be further processed by data processor 1706.

[0067] exist Figure 17In the wireless communication device 1700, a TX LO signal generator 1722 generates I and Q TXLO signals for up-conversion, while an RX LO signal generator 1740 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. A TX phase-locked loop (PLL) circuit 1748 receives timing information from a data processor 1706 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 1722. Similarly, an RX PLL circuit 1750 receives timing information from a data processor 1706 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 1740.

[0068] Figure 18 An example of a processor-based system 1800 is illustrated, which includes one or more IC packages 1802, 1802(1) to 1802(8), the one or more IC packages including one or more ICs, including but not limited to Figures 1A to 1B , Figures 4A to 5C , Figure 12B and Figure 16B ICs 102, 404, and 504, one or more of which include separate signal interconnect structures and PDN interconnect structures to reduce signal routing congestion and power signal routing path length, thereby improving IC and die performance, and wherein decoupling capacitors may be integrated into the PDN interconnect structure of the IC to provide decoupling capacitance to the PDN in the IC, and may be manufactured according to a manufacturing process, including but not limited to Figure 6 , Figures 7A to 7C , Figures 9A to 9C , Figure 11 , Figures 13A to 13C and Figure 15 The exemplary manufacturing processes 600, 700, 900, 1100, 1300, and 1500 are described herein and are manufactured according to any aspect disclosed herein.

[0069] In this example, the processor-based system 1800 may include a capacitor package 1804, which is included in an IC package 1802, such as a system-on-a-chip (SoC) 1806. The processor-based system 1800 includes a CPU 1808, which includes one or more processors 1810, which may also be referred to as a CPU core or processor core. The CPU 1808 may be disposed in an IC package 1802(1), which includes a package substrate having an embedded capacitor package 1804(1). The CPU 1808 may have a cache memory 1812 coupled to the CPU 1808 for fast access to temporarily stored data. The CPU 1808 is coupled to a system bus 1814 and may be coupled to master and slave devices included in the processor-based system 1800. As is well known, the CPU 1808 communicates with these other devices by exchanging address, control, and data information via the system bus 1814. For example, CPU 1808 can communicate bus transaction requests to memory controller 1816, which is an example of a slave device. Although in Figure 18 Not illustrated, but multiple system buses 1814 may be provided, each of which constitutes a different architecture.

[0070] Other master and slave devices can be connected to system bus 1814. For example... Figure 18As illustrated, by way of example, these devices may include a memory system 1820, one or more input devices 1822, one or more output devices 1824, one or more network interface devices 1826, and one or more display controllers 1828, the memory system including a memory controller 1816 and a memory array 1818. The memory system 1820 may be disposed in an IC package 1802(2) including a package substrate having an embedded capacitor package 1804(2). The network interface device 1826 may be disposed in an IC package 1802(3) including a package substrate having an embedded capacitor package 1804(3). Each of the memory system 1820, one or more input devices 1822, one or more output devices 1824, one or more network interface devices 1826, and one or more display controllers 1828 may be disposed in the same or different circuit packages. Input device 1822 and / or output device 1824 may be disposed in corresponding IC packages 1802(4), 1802(5), which include a package substrate having corresponding embedded capacitor packages 1804(4), 1804(5). Input device 1822 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output device 1824 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface device 1826 may be any device configured to allow the exchange of data to and from network 1830. Network 1830 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth. ™ Networks and the Internet. The network interface device 1826 can be configured to support any type of communication protocol desired.

[0071] The CPU 1808 can also be configured to access the display controller 1828 via the system bus 1814 to control information transmitted to one or more displays 1832. The displays 1832 may be housed in an IC package 1802(6) including a package substrate with embedded capacitor packages 1804(6). The display controller 1828 transmits information to be displayed to the displays 1832 via one or more video processors 1834, which process the information to be displayed into a format suitable for the displays 1832. As an example, the display controller 1828 and the video processors 1834 may be housed in corresponding IC packages 1802(7), 1802(8) including package substrates with corresponding embedded capacitor packages 1804(7), 1804(8), or may be housed in the same IC package 1802, or may be housed in the same IC package 1802(1) containing the CPU 1808. The display 1832 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0072] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the functionality of the various exemplary components, blocks, modules, circuits, and steps has been generally described above. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0073] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0074] The aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0075] It should also be noted that the operational steps described in any of the exemplary aspects of this document are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. In addition, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different techniques and arts can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0076] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0077] Specific implementation examples are described in the following numbered clauses: 1. An integrated circuit (IC), said integrated circuit (IC) comprising: Semiconductor layer, the semiconductor layer comprising: The first side and the second side opposite to the first side; and Multiple semiconductor devices; A signal interconnect structure, wherein the signal interconnect structure is adjacent to the first side of the semiconductor layer, the signal interconnect structure comprising: A plurality of first metal interconnects, each of the plurality of first metal interconnects being configured to transmit input / output (I / O) signals to a coupled first semiconductor device in the plurality of semiconductor devices; A power distribution network (PDN) interconnect structure, wherein the PDN interconnect structure is adjacent to the second side of the semiconductor layer, the PDN interconnect structure comprising: A plurality of second metal interconnects, each configured to transmit a power signal; and A plurality of first vias, each of the plurality of first vias extending through the semiconductor layer and each coupled to one of the plurality of second metal interconnects and the signal interconnect structure.

[0078] 2. The IC as described in Clause 1, wherein: The signal interconnect structure includes a plurality of first metallization layers, the plurality of first metallization layers including: The plurality of first metal interconnects; and A plurality of second vias, wherein the plurality of second vias interconnect the plurality of second metal interconnects; and The PDN interconnect structure includes a plurality of second metallization layers, the plurality of second metallization layers including: The plurality of second metal interconnects; and Multiple third vias interconnect the multiple second metal interconnects.

[0079] 3. The IC according to Clause 1 or 2, wherein the PDN interconnect structure further includes a plurality of third metal interconnects; and The PDN interconnect structure also includes: A plurality of second vias, each of the plurality of second vias extending through the semiconductor layer and each coupled to one of the plurality of third metal interconnects and one of the plurality of first metal interconnects.

[0080] 4. The IC according to Clause 3, wherein each of the plurality of third metal interconnects is not coupled to a power signal node.

[0081] 5. The IC according to Clause 3 or 4, wherein the PDN interconnect structure further includes a plurality of third vias, each of the plurality of third vias being coupled to one of the plurality of second metal interconnects and one of the plurality of second vias.

[0082] 6. The IC according to any one of Clauses 1 to 5, the IC further comprising one or more capacitors located in the PDN interconnect structure and each of the plurality of second metal interconnects coupled to one of the second metal interconnects.

[0083] 7. The IC as described in Clause 6, wherein: The PDN interconnect structure includes a silicon layer; and At least one of the one or more capacitors includes at least one silicon capacitor located in the silicon layer.

[0084] 8. The IC according to Clause 7, wherein the at least one silicon capacitor includes at least one deep trench capacitor (DTC).

[0085] 9. The IC as described in Clause 6, wherein: The PDN interconnect structure includes a dielectric layer; and At least one of the one or more capacitors includes at least one dielectric capacitor located in the dielectric layer.

[0086] 10. The IC according to Clause 9, wherein the dielectric layer comprises a silicon oxide layer.

[0087] 11. The IC according to any one of clauses 1 to 10, wherein the IC further comprises: A first die structure, the first die structure including the semiconductor layer and the signal interconnect structure; and The second die structure includes the PDN interconnect structure; The first die structure is bonded to the second die structure to couple each of the plurality of second metal interconnects to one of the plurality of first vias.

[0088] 12. The IC according to Clause 11, the IC further comprising a metal bump layer located between the PDN interconnect structure and the semiconductor layer, the metal bump layer comprising a plurality of metal bumps, each of the plurality of metal bumps being coupled to a second metal interconnect of the plurality of second metal interconnects and a first via of the plurality of first vias.

[0089] 13. The IC according to Clause 11, wherein each of the plurality of second metal interconnects is directly bonded to one of the plurality of first vias.

[0090] 14. The IC according to any one of clauses 1 to 13, wherein: The semiconductor layer extends in a first direction; The second side is opposite to the first side in a second direction orthogonal to the first direction; Each of the plurality of first vias extends through the semiconductor layer in the second direction; and Multiple second vias each extend through the semiconductor layer in the second direction.

[0091] 15. The IC according to any one of Clauses 1 to 14, wherein the plurality of first vias includes a plurality of first through-silicon vias (TSVs).

[0092] 16. The IC according to any one of Clauses 3 to 5, wherein the plurality of second vias includes a plurality of second through-silicon vias (TSVs).

[0093] 17. The IC according to any one of Clauses 1 to 16, wherein the IC is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft.

[0094] 18. A method for manufacturing an integrated circuit (IC), the method comprising: A semiconductor layer is formed, the semiconductor layer including a first side and a second side opposite to the first side; Multiple semiconductor devices are formed in the semiconductor layer; A plurality of first vias are formed, each of the plurality of first vias extending through the semiconductor layer; Forming a signal interconnect structure adjacent to the first side of the semiconductor layer, wherein forming the signal interconnect structure further includes: A plurality of first metal interconnects are formed, each of the plurality of first metal interconnects being configured to transmit input / output (I / O) signals to a coupled first semiconductor device in the plurality of semiconductor devices; Forming a power distribution network (PDN) interconnection structure, wherein forming the PDN interconnection structure further includes: A plurality of second metal interconnects are formed, each of the plurality of second metal interconnects being configured to transmit a power signal; The PDN interconnect structure is coupled adjacent to the second side of the semiconductor layer by coupling each of the plurality of second metal interconnects to a first via of the plurality of first vias.

[0095] 19. The method according to Clause 18, the method further comprising forming a plurality of second vias, each of the plurality of second vias extending through the semiconductor layer; in: The signal interconnect structure formed adjacent to the first side of the semiconductor layer further includes coupling the signal interconnect structure to each of the plurality of second vias; Forming the PDN interconnect structure further includes forming a plurality of third metal interconnects in the PDN interconnect structure; and The PDN interconnect structure coupled adjacent to the second side of the semiconductor layer further includes coupling each of the plurality of third metal interconnects to one of the plurality of second vias.

[0096] 20. The method according to Clause 19, further comprising not coupling the plurality of third metal interconnects to the power signal node.

[0097] 21. The method according to any one of clauses 18 to 20, wherein the method further comprises: One or more capacitors are disposed in the PDN interconnect structure; and Each of the one or more capacitors is coupled to one of the plurality of second metal interconnects.

[0098] 22. The method according to Clause 21, wherein: Forming the PDN interconnect structure further includes forming a silicon layer in the PDN interconnect structure; and The provision of one or more capacitors in the PDN interconnect structure further includes the provision of at least one silicon capacitor in the silicon layer.

[0099] 23. The method according to Clause 21, wherein: Forming the PDN interconnect structure further includes forming a dielectric layer in the PDN interconnect structure; and The provision of one or more capacitors in the PDN interconnect structure further includes the provision of at least one dielectric capacitor in the dielectric layer of the one or more capacitors.

[0100] 24. The method according to any one of clauses 18 to 23, wherein the method further comprises: Forming the first wafer includes: The semiconductor layer is formed, the semiconductor layer including a first side and a second side opposite to the first side; The plurality of semiconductor devices are formed in the semiconductor layer, and each of the plurality of semiconductor devices includes an I / O terminal; Forming the plurality of first vias, each of the plurality of first vias extending through the semiconductor layer; and A signal interconnect structure is formed adjacent to the first side of the semiconductor layer, the signal interconnect structure comprising: The plurality of first metal interconnects, each of the plurality of first metal interconnects being coupled to an I / O terminal of a first semiconductor device in the plurality of semiconductor devices; and Forming a second wafer includes: The PDN interconnect structure is formed, the PDN interconnect structure includes the plurality of second metal interconnects, each of the plurality of second metal interconnects being coupled to a power signal node; in: Coupled to the second side of the semiconductor layer, the PDN interconnect structure includes coupling the second wafer structure to the first wafer structure to form a combined wafer structure by coupling each of the plurality of second metal interconnects to a first via of the plurality of first vias.

[0101] 25. The method according to Clause 24, wherein: Forming the second wafer structure further includes forming a metal bump layer, the metal bump layer including a plurality of metal bumps, each of the plurality of metal bumps being coupled to one of the plurality of second metal interconnects; and Couple the second wafer structure to the first wafer structure includes coupling each of the plurality of metal bumps to a first via of the plurality of first vias.

[0102] 26. The method according to Clause 24, wherein coupling the second wafer structure to the first wafer structure includes directly bonding each of the plurality of second metal interconnects to one of the plurality of first vias.

[0103] 27. The method according to any one of clauses 24 to 26, the method further comprising dicing the wafer structure of the combination to form the IC.

[0104] 28. A three-dimensional (3D) integrated circuit (IC) (3DIC), said three-dimensional (3D) integrated circuit (IC) (3DIC) comprising: A first IC, the first IC comprising: A first semiconductor layer, the first semiconductor layer comprising: The first side and the second side opposite to the first side; and Multiple first semiconductor devices; A signal interconnect structure, wherein the signal interconnect structure is adjacent to the first side of the first semiconductor layer, the signal interconnect structure comprising: A plurality of first metal interconnects, each of the plurality of first metal interconnects being configured to transmit input / output (I / O) signals to a coupled first semiconductor device in the plurality of first semiconductor devices; A power distribution network (PDN) interconnect structure, wherein the PDN interconnect structure is adjacent to the second side of the first semiconductor layer, the PDN interconnect structure comprising: A plurality of second metal interconnects, each configured to transmit a power signal; and A plurality of first vias, each extending through the first semiconductor layer and each coupled to one of the plurality of second metal interconnects and the signal interconnect structure; and The second IC includes: Second semiconductor layer; A third interconnect structure, adjacent to the second semiconductor layer, comprises: A plurality of third metal interconnects, each of the plurality of third metal interconnects including a power signal node; and A plurality of second vias, each of the plurality of second vias extending through the second semiconductor layer and each coupled to one of the plurality of third metal interconnects; in: The first IC is coupled to the second IC by coupling each of the plurality of second metal interconnects in the second IC to a second via in the first IC to a third metal interconnect in the plurality of third metal interconnects.

[0105] 29. The 3DIC according to Clause 28, the 3DIC further comprising one or more capacitors located in the PDN interconnect structure of the first IC and each coupled to one of the plurality of second metal interconnects in the first IC.

[0106] 30. The 3DIC according to Clause 29, wherein at least one of the one or more capacitors in the PDN interconnect structure of the first IC is each further coupled to a second via in one of the plurality of second vias in the second IC to couple the at least one capacitor to at least one of the plurality of third metal interconnects.

Claims

1. An integrated circuit (IC), said integrated circuit (IC) comprising: Semiconductor layer, the semiconductor layer comprising: The first side and the second side opposite to the first side; and Multiple semiconductor devices; A signal interconnect structure, wherein the signal interconnect structure is adjacent to the first side of the semiconductor layer, the signal interconnect structure comprising: A plurality of first metal interconnects, each of the plurality of first metal interconnects being configured to transmit input / output (I / O) signals to a coupled first semiconductor device in the plurality of semiconductor devices; A power distribution network (PDN) interconnect structure, wherein the PDN interconnect structure is adjacent to the second side of the semiconductor layer, the PDN interconnect structure comprising: A plurality of second metal interconnects, each configured to transmit a power signal; and A plurality of first vias, each of the plurality of first vias extending through the semiconductor layer and each coupled to one of the plurality of second metal interconnects and the signal interconnect structure.

2. The IC according to claim 1, wherein: The signal interconnect structure includes a plurality of first metallization layers, the plurality of first metallization layers including: The plurality of first metal interconnects; and A plurality of second vias, wherein the plurality of second vias interconnect the plurality of second metal interconnects; and The PDN interconnect structure includes a plurality of second metallization layers, the plurality of second metallization layers including: The plurality of second metal interconnects; and Multiple third vias interconnect the multiple second metal interconnects.

3. The IC according to claim 1, wherein the PDN interconnect structure further comprises a plurality of third metal interconnects; and The PDN interconnect structure also includes: A plurality of second vias, each of the plurality of second vias extending through the semiconductor layer and each coupled to one of the plurality of third metal interconnects and one of the plurality of first metal interconnects.

4. The IC of claim 3, wherein each of the plurality of third metal interconnects is not coupled to a power signal node.

5. The IC of claim 3, wherein the PDN interconnect structure further comprises a plurality of third vias, each of the plurality of third vias being coupled to one of the plurality of second metal interconnects and one of the plurality of second vias.

6. The IC of claim 1, further comprising one or more capacitors located in the PDN interconnect structure and each coupled to one of the plurality of second metal interconnects.

7. The IC according to claim 6, wherein: The PDN interconnect structure includes a silicon layer; and At least one of the one or more capacitors includes at least one silicon capacitor located in the silicon layer.

8. The IC of claim 7, wherein the at least one silicon capacitor comprises at least one deep trench capacitor (DTC).

9. The IC according to claim 6, wherein: The PDN interconnect structure includes a dielectric layer; and At least one of the one or more capacitors includes at least one dielectric capacitor located in the dielectric layer.

10. The IC of claim 9, wherein the dielectric layer comprises a silicon oxide layer.

11. The IC according to claim 1, further comprising: A first die structure, the first die structure including the semiconductor layer and the signal interconnect structure; and The second die structure includes the PDN interconnect structure; The first die structure is bonded to the second die structure to couple each of the plurality of second metal interconnects to one of the plurality of first vias.

12. The IC of claim 11, further comprising a metal bump layer located between the PDN interconnect structure and the semiconductor layer, the metal bump layer comprising a plurality of metal bumps, each of the plurality of metal bumps being coupled to one of the plurality of second metal interconnects and one of the plurality of first vias.

13. The IC of claim 11, wherein each of the plurality of second metal interconnects is directly bonded to one of the plurality of first vias.

14. The IC according to claim 1, wherein: The semiconductor layer extends in a first direction; The second side is opposite to the first side in a second direction orthogonal to the first direction; Each of the plurality of first vias extends through the semiconductor layer in the second direction; and Multiple second vias each extend through the semiconductor layer in the second direction.

15. The IC of claim 1, wherein the plurality of first vias comprises a plurality of first through-silicon vias (TSVs).

16. The IC of claim 3, wherein the plurality of second vias comprises a plurality of second through-silicon vias (TSVs).

17. The IC of claim 1, wherein the IC is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft.

18. A method for manufacturing an integrated circuit (IC), the method comprising: A semiconductor layer is formed, the semiconductor layer including a first side and a second side opposite to the first side; Multiple semiconductor devices are formed in the semiconductor layer; A plurality of first vias are formed, each of the plurality of first vias extending through the semiconductor layer; Forming a signal interconnect structure adjacent to the first side of the semiconductor layer, wherein forming the signal interconnect structure further includes: A plurality of first metal interconnects are formed, each of the plurality of first metal interconnects being configured to transmit input / output (I / O) signals to a coupled first semiconductor device in the plurality of semiconductor devices; Forming a power distribution network (PDN) interconnection structure, wherein forming the PDN interconnection structure further includes: A plurality of second metal interconnects are formed, each of the plurality of second metal interconnects being configured to transmit a power signal; The PDN interconnect structure is coupled adjacent to the second side of the semiconductor layer by coupling each of the plurality of second metal interconnects to a first via of the plurality of first vias.

19. The method of claim 18, further comprising forming a plurality of second vias, each of the plurality of second vias extending through the semiconductor layer; in: The signal interconnect structure formed adjacent to the first side of the semiconductor layer further includes coupling the signal interconnect structure to each of the plurality of second vias; Forming the PDN interconnect structure further includes forming a plurality of third metal interconnects in the PDN interconnect structure; and The PDN interconnect structure coupled adjacent to the second side of the semiconductor layer further includes coupling each of the plurality of third metal interconnects to one of the plurality of second vias.

20. The method of claim 19, further comprising not coupling the plurality of third metal interconnects to the power signal node.

21. The method of claim 18, further comprising: One or more capacitors are disposed in the PDN interconnect structure; as well as Each of the one or more capacitors is coupled to one of the plurality of second metal interconnects.

22. The method of claim 21, wherein: Forming the PDN interconnect structure further includes forming a silicon layer in the PDN interconnect structure; and The provision of one or more capacitors in the PDN interconnect structure further includes the provision of at least one silicon capacitor in the silicon layer.

23. The method of claim 21, wherein: Forming the PDN interconnect structure further includes forming a dielectric layer in the PDN interconnect structure; and The provision of one or more capacitors in the PDN interconnect structure further includes the provision of at least one dielectric capacitor in the dielectric layer of the one or more capacitors.

24. The method according to claim 18, further comprising: Forming the first wafer includes: The semiconductor layer is formed, the semiconductor layer including a first side and a second side opposite to the first side; The plurality of semiconductor devices are formed in the semiconductor layer, and each of the plurality of semiconductor devices includes an I / O terminal; Forming the plurality of first vias, each of the plurality of first vias extending through the semiconductor layer; and A signal interconnect structure is formed adjacent to the first side of the semiconductor layer, the signal interconnect structure comprising: The plurality of first metal interconnects, each of the plurality of first metal interconnects being coupled to an I / O terminal of a first semiconductor device in the plurality of semiconductor devices; and Forming a second wafer includes: The PDN interconnect structure is formed, the PDN interconnect structure includes the plurality of second metal interconnects, each of the plurality of second metal interconnects being coupled to a power signal node; in: Coupled to the second side of the semiconductor layer, the PDN interconnect structure includes coupling the second wafer structure to the first wafer structure to form a combined wafer structure by coupling each of the plurality of second metal interconnects to a first via of the plurality of first vias.

25. The method of claim 24, wherein: Forming the second wafer structure further includes forming a metal bump layer, the metal bump layer including a plurality of metal bumps, each of the plurality of metal bumps being coupled to one of the plurality of second metal interconnects; as well as Couple the second wafer structure to the first wafer structure includes coupling each of the plurality of metal bumps to a first via of the plurality of first vias.

26. The method of claim 24, wherein coupling the second wafer structure to the first wafer structure comprises directly bonding each of the plurality of second metal interconnects to one of the plurality of first vias.

27. The method of claim 24, further comprising dicing the combined wafer structure to form the IC.

28. A three-dimensional (3D) integrated circuit (IC) (3DIC), said three-dimensional (3D) integrated circuit (IC) (3DIC) comprising: A first IC, the first IC comprising: A first semiconductor layer, the first semiconductor layer comprising: The first side and the second side opposite to the first side; and Multiple first semiconductor devices; A signal interconnect structure, wherein the signal interconnect structure is adjacent to the first side of the first semiconductor layer, the signal interconnect structure comprising: A plurality of first metal interconnects, each of the plurality of first metal interconnects being configured to transmit input / output (I / O) signals to a coupled first semiconductor device in the plurality of first semiconductor devices; A power distribution network (PDN) interconnect structure, wherein the PDN interconnect structure is adjacent to the second side of the first semiconductor layer, the PDN interconnect structure comprising: A plurality of second metal interconnects, each configured to transmit a power signal; and A plurality of first vias, each extending through the first semiconductor layer and each coupled to one of the plurality of second metal interconnects and the signal interconnect structure; and The second IC includes: Second semiconductor layer; A third interconnect structure, adjacent to the second semiconductor layer, comprises: A plurality of third metal interconnects, each of the plurality of third metal interconnects including a power signal node; and A plurality of second vias, each of the plurality of second vias extending through the second semiconductor layer and each coupled to one of the plurality of third metal interconnects; in: The first IC is coupled to the second IC by coupling each of the plurality of second metal interconnects in the second IC to a second via in the first IC to a third metal interconnect in the plurality of third metal interconnects.

29. The 3DIC of claim 28, further comprising one or more capacitors located in the PDN interconnect structure of the first IC and each coupled to one of the plurality of second metal interconnects in the first IC.

30. The 3DIC of claim 29, wherein at least one of the one or more capacitors in the PDN interconnect structure of the first IC is further coupled to a second via of the plurality of second vias in the second IC to couple the at least one capacitor to at least one of the plurality of third metal interconnects.

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