Embedded bump structure

Abstract

In one aspect, an apparatus includes a die including a plurality of die connectors. The apparatus can include a package substrate including a first metallization structure disposed below the die, the first metallization structure including: a plurality of dielectric layers; a plurality of metal layers disposed in the plurality of dielectric layers; a plurality of vias configured to couple adjacent metal layers of the plurality of metal layers through the plurality of dielectric layers; and a plurality of under bump metallurgy structures disposed in a top dielectric layer of the plurality of dielectric layers, wherein the plurality of under bump metallurgy structures are directly coupled to the plurality of die connectors.

Description

Technical Field

[0001] This disclosure relates in its entirety to semiconductor devices including integrated circuit (IC) packages, and more specifically, but not exclusively, to devices including embedded bump structures and techniques for their fabrication. Background Technology

[0002] IC technology has made significant progress in improving computing power through the miniaturization of electronic components. An IC chip or IC die may include a set of circuitry integrated thereon. In some embodiments, an IC device can be formed by incorporating and protecting one or more IC chips or dies within an IC package, wherein various power and signal nodes of the one or more IC chips are electrically coupled to corresponding conductive terminals of the IC package via electrical paths formed in one or more packaging substrates of the IC package. Unless otherwise specified, the term "substrate" in this disclosure refers to a packaging substrate used to package one or more IC chips into an IC package, which is different from the semiconductor substrate used to form the IC chip.

[0003] Various packaging technologies are found in many electronic devices, including processors, servers, and radio frequency (RF) ICs. Advanced packaging and processing technologies enable complex devices such as multi-die devices and system-on-a-chip (SoC) devices, which may include multiple functional blocks, each designed to perform a specific function, such as microprocessor functions, graphics processing unit (GPU) functions, communication functions (e.g., Wi-Fi, Bluetooth, and other communications). As used herein, the term "functional block" should not be construed as a power line or signal line, trace, conductor, pad, etc., used only for transmitting voltage and / or current.

[0004] As designs become more complex, the demands on package substrate design are increasing. Conventional package substrate technologies, such as flip-chip ball grid array (FCBGA) substrate technology, use a semi-additive process (SAP) with surface mount device (SMD) type flip-chip (FC) pad connections. However, conventional technologies have limitations in handling fine bump pitch due to limitations in solder mask opening (SRO) and solder mask (SR) alignment process capabilities.

[0005] Therefore, there is a need for improved substrates or IC packages, and methods for manufacturing such improved substrates or IC packages, to address the problems identified above in the conventional art and to achieve other improvements as disclosed herein. Summary of the Invention

[0006] The following is a simplified summary of the invention relating to one or more aspects disclosed herein. Therefore, this summary should not be considered an exhaustive overview relating to all conceived aspects, nor should it be considered to identify key or decisive elements relating to all conceived aspects or to depict the scope associated with any particular aspect. Thus, the sole purpose of this summary is to present, in a simplified form, certain concepts relating to one or more aspects involving the mechanisms disclosed herein, prior to the detailed description presented below.

[0007] In some aspects, the apparatus includes: a die including a plurality of die connectors; and a package substrate including a first metallization structure disposed beneath the die, the first metallization structure including: a plurality of dielectric layers; a plurality of metal layers disposed in the plurality of dielectric layers; a plurality of vias configured to couple adjacent metal layers among the plurality of metal layers through the plurality of dielectric layers; and a plurality of embedded bump structures disposed in a top dielectric layer among the plurality of dielectric layers, wherein the plurality of embedded bump structures are directly coupled to the plurality of die connectors.

[0008] In some aspects, the technology described herein relates to a method of manufacturing an apparatus, the method comprising: providing a die including a plurality of die connectors; forming a package substrate, the package substrate including forming a first metallization structure, the first metallization structure including: forming a plurality of dielectric layers; forming a plurality of metal layers disposed in the plurality of dielectric layers; forming a plurality of vias coupling adjacent metal layers among the plurality of metal layers through the plurality of dielectric layers; forming a plurality of embedded bump structures disposed in a top dielectric layer among the plurality of dielectric layers; and directly coupling the plurality of embedded bump structures to the plurality of die connectors.

[0009] Based on the accompanying drawings and detailed description, other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art. Attached Figure Description

[0010] The accompanying drawings are provided to help describe various aspects of this disclosure, and are provided for illustrative purposes only and not to limit the aspects.

[0011] Figure 1A and Figure 1B A partial cross-sectional view of an apparatus including an integrated circuit (IC) package according to various aspects of the present disclosure is illustrated.

[0012] Figures 2A to 2P The structures of various stages in the manufacture of substrates for IC packages are illustrated according to various aspects of this disclosure.

[0013] Figure 3A and Figure 3B The structure of the final stage of manufacturing an IC package according to various aspects of this disclosure is illustrated.

[0014] Figure 3C A partial cross-sectional view of an apparatus according to various aspects of this disclosure is shown.

[0015] Figure 4 Methods for manufacturing substrates for IC packages according to various aspects of this disclosure are illustrated.

[0016] Figure 5 Mobile devices according to various aspects of this disclosure are illustrated.

[0017] Figure 6 Various electronic devices that can be incorporated into IC packages described herein are illustrated according to various aspects of this disclosure.

[0018] By convention, features depicted in the accompanying drawings may not be drawn to scale. Accordingly, for clarity, the dimensions of the depicted features may be arbitrarily enlarged or reduced. By convention, some figures in the drawings are simplified for clarity. Therefore, the drawings may not depict all components of a particular device or method. Furthermore, similar reference numerals are used throughout the specification and drawings to represent similar features. Detailed Implementation

[0019] Various aspects of this disclosure are provided in the following description and accompanying drawings of various examples provided for illustrative purposes. Alternative aspects may be devised without departing from the scope of this disclosure. Additionally, well-known elements of this disclosure will not be described in detail or will be omitted so as not to obscure the relevant details of this disclosure.

[0020] The terms “exemplary” and / or “example” are used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” and / or “example” is not necessarily to be construed as superior to or better than other aspects. Similarly, the term “aspects of this disclosure” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed.

[0021] In some of the described example implementations, instances are identified where various component structures and operational parts are derived from known conventional techniques and subsequently arranged according to one or more aspects. In such instances, internal details of known conventional component structures and / or operational parts may be omitted to help avoid potential confusion with the concepts illustrated in the exemplary aspects disclosed herein.

[0022] The terminology used herein is for descriptive purposes only and is not intended to be limiting. As used herein, the singular forms “a,” “some,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the term “comprising” as used herein indicates the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Additionally, terms such as approximate, approximately, substantially, etc., indicate that the examples provided are not intended to be limited to precise numerical values ​​or geometries and include normal variations due to manufacturing tolerances and variations, material variations, and other design considerations. Furthermore, relative terms such as “small,” “large,” “wide,” “thin,” “narrow,” “wide,” “thick,” “thin,” “high,” “low” should be interpreted within the context of various design standards, techniques, and / or applications. For example, a thin wire pitch may be interpreted based on the minimum distance between the wires for a given design standard, and a high voltage will depend on a given operating or standard voltage range for a given design. Those skilled in the art will readily understand any of these terms used in the context of the disclosure provided herein.

[0023] As previously noted, conventional techniques, including SR processing and the resulting SRO formation, limit the reduction of bump pitch for die attachment. The various aspects disclosed herein offer improvements to reduce the pitch / distance between pads / bumps for die attachment to the package substrate, resulting in a smaller pitch compared to conventional designs. In some aspects, metal (e.g., copper (Cu)) patterning using an Ajinomoto laminate (ABF) thinning process can be used to create fine bump pitches with structures similar to embedded trace substrate (ETS) processing, referred to herein as "buried bump structures." Conventional package substrates include bump pitches of 110 micrometers (µm). The various aspects disclosed herein allow for bump pitches that are approximately half that of conventional designs. For example, a buried bump structure can have a 64-micrometer (µm) pitch and a three-line escape pattern. In some aspects, with a 3-line escape configuration (e.g., 15µm bump + three 5µm traces and spacing), the embedded bump structure allows for a pitch reduction to the range of 40µm to 65µm. In addition to the reduced bump pitch, the disclosed aspects also protect the escape lines between the bumps and the dielectric material, preventing short-circuit faults. In contrast, in conventional designs and processes, it is difficult to form escape lines between bumps and prevent short-circuit problems. Furthermore, the disclosed aspects prevent TC bumps from being damaged during assembly. Because the bumps are embedded in the dielectric material, they are protected from mechanical damage during assembly. Further, the aspects eliminate the solder mask process, which simplifies the fabrication process and allows for a reduction in overall thickness.

[0024] Additionally, the various disclosed aspects can prevent bump-on-lead (BOL) lifting caused by fine patterns during assembly, and the BOL is buried under ABF processing. Additionally, the various disclosed aspects allow the use of conventional assembly process infrastructure. Additionally, the various disclosed aspects provide elimination of top SR processing for the package substrate (i.e., the package substrate does not have an SR layer).

[0025] Figure 1A is a cross-sectional view of an apparatus 100 in accordance with various aspects of the present disclosure. In some aspects, Figure 1A is a simplified cross-sectional view of the apparatus 100, and certain details and components of the apparatus 100 may be simplified or omitted in Figure 1A . Figure 1B is a cross-sectional view of an apparatus 100 in accordance with various aspects of the present disclosure. In some aspects, Figure 1B is an expanded cross-sectional view of a portion 101 of the apparatus 100, and certain details and components of the apparatus 100 may be simplified or omitted in Figure 1B .

[0026] In some aspects, as shown in Figure 1A and Figure 1B , the apparatus 100 is illustrated as an IC package and / or part of a larger device such as a mobile phone or the like. In some aspects, the apparatus 100 includes a die 150 and a package substrate 105, the die including a plurality of die connectors 151. In some aspects, an underfill 160 is disposed between the die 150 and the package substrate 105 to provide mechanical bonding and encapsulate the connections (e.g., the die connectors 151 and the embedded bump structures 115) of the die 150 to the package substrate 105. In some aspects, the die connectors 151 may be die bumps and solder balls, and in other aspects, the die connectors 151 may be only pins or posts directly coupled to the package substrate 105. It should be understood that one or more dies may be coupled to the first metallization structure 110, and the various disclosed and claimed aspects are not limited to the illustrated example.

[0027] In some aspects, the package substrate 105 includes a base substrate 130 having a first side and a second side. In some aspects, the base substrate 130 may include a core. A first metallization structure 110 is disposed on the first side of the base substrate 130. A second metallization structure 120 is disposed on the second side of the base substrate 130. In some aspects, the base substrate 130 may be coreless (e.g., designed as an additional laminated layer, or in some aspects, the base substrate 130 may not be present in a coreless design). Further, in some aspects, the package substrate may be considered to have only one metallization structure that includes the embedded bump structures as disclosed herein. Cored and coreless substrate designs are well known in the art, and various substrate design options will not be elaborated and illustrated in detail herein.

[0028] The first metallization structure 110 includes a plurality of dielectric layers 112, a plurality of metal layers 114 disposed in the plurality of dielectric layers 112, and a plurality of vias 113 coupling adjacent metal layers 114 among the plurality of metal layers 114 through the plurality of dielectric layers 112. The first metallization structure 110 also includes a plurality of embedded bump structures 115 disposed in a top dielectric layer 112(a) among the plurality of dielectric layers 112, wherein the plurality of embedded bump structures 115 are directly coupled to a plurality of die connectors 151. It should be understood that the embedded bump structures 115 do not have solder mask openings in any solder mask (SR) layer because no SR layer is deposited on the top dielectric layer 112(a) among the plurality of dielectric layers 112. Therefore, in the disclosed aspects, solder mask (SR) treatment is not required on the top of the package substrate 105. In some aspects, a plurality of escape lines 117 (e.g., a three-line escape pattern as illustrated) may be disposed between adjacent embedded bump structures 115. It should be understood that the various aspects disclosed and claimed are not limited to three lines, and there may be more or fewer lines (including no lines) between adjacent embedded bump structures 115.

[0029] Additionally, such as Figure 1B As illustrated, in some aspects, the pitch of the plurality of embedded bump structures 115 is approximately 64 micrometers (µm), which is significantly reduced compared to conventional designs, as discussed above. In some aspects, the width of each embedded bump structure in the embedded bump structure 115 is approximately 18 micrometers (µm). In some aspects, the width of each escape line in the escape line 117 is approximately 6 micrometers (µm). In some aspects, the spacing between each escape line in the escape line 117 is approximately 6 micrometers (µm), and the spacing between the embedded bump structure 115 and the adjacent escape line 117 is approximately 8 micrometers (µm). It should be understood that the various aspects disclosed and claimed are not limited to these specific numerical examples, and each of the embedded bump structures 115 and escape lines 117 may have different widths, pitches, and / or spacings.

[0030] Return to reference Figure 1AA second metallization structure 120 is disposed on a second side of the base substrate 130. The second metallization structure 120 includes a plurality of dielectric layers 122, a plurality of metal layers 124 disposed in the plurality of dielectric layers 122, and a plurality of vias 123 coupling adjacent metal layers 124 among the plurality of metal layers 124 through the plurality of dielectric layers 122. Connection structures 140 (e.g., solder balls, solder paste, copper pillars, etc.) are disposed on the bottom of the second metallization structure 120 opposite to the base substrate 130 and are configured to electrically couple the package substrate 105 to external components, devices, etc., through the second metallization structure 120. A solder resist layer 145 is disposed on the bottom of the second metallization structure 120, wherein the connection structures 140 are coupled to the second metallization structure 120 through solder resist openings (SROs) in the solder resist layer 145.

[0031] In some aspects, the base substrate 130 further includes a first metal layer 131 on a first side and a second metal layer 132 on a second side, the first and second metal layers being separated by a core 135. In some aspects, the core 135 may include a dielectric material in which a pre-impregnated reinforcing component is embedded. In some aspects, the core 135 may include a prepreg (also referred to as PPG) that may include a polymer resin in which a fiberglass sheet is impregnated. In some aspects, the base substrate 130 includes at least one plated through-hole (PTH) 136 disposed through the core 135, the at least one plated through-hole (PTH) being configured to couple portions of the first metal layer 131 and the second metal layer 132 located on opposite sides of the core 135.

[0032] In some aspects, the first metallization structure 110 may include a multilayer Ajinomoto laminate (ABF) or other similar epoxy resin or resin substrate. In some aspects, the second metallization structure may include resin-impregnated glass fiber (prepreg), Ajinomoto laminate (ABF), resin-coated copper (RCC) laminate, or any similar material. In some aspects, the metal layers and vias of the first metallization structure 110, the second metallization structure 120, and the base substrate 130 may be made of any highly conductive material, such as copper (Cu), aluminum (Al), silver (Ag), gold (Au), titanium (Ti), nickel (Ni), tin (Sn), lead (Pb), alloys of these, or combinations thereof.

[0033] It should be understood that the illustrated configurations and descriptions provided herein are merely illustrative of the various aspects disclosed herein. Accordingly, the foregoing illustrative examples should not be construed as limiting the various aspects disclosed and claimed herein.

[0034] To fully illustrate the various aspects of the design of this disclosure, manufacturing methods are proposed. Furthermore, many details of the manufacturing processes known to those skilled in the art may be omitted or combined in the various overview process sections to facilitate understanding of the various aspects disclosed without presenting every detail and / or all possible process variations in detail. Other manufacturing methods are also possible, and the manufacturing methods discussed are only for the purpose of aiding understanding the concepts disclosed herein.

[0035] Figures 2A to 2P An example of a manufacturing / fabrication apparatus 200 (which is similar to) according to various aspects of this disclosure is illustrated. Figure 1A The example device 100 (as a non-limiting example) has various stages of structure. Figures 2A to 2O Many of the components illustrated herein are Figure 1A The components in the text are the same or similar, so their detailed descriptions can be omitted.

[0036] like Figure 2A As shown, the fabrication process of device 200 may begin with the partial formation of a packaging substrate 205, which includes a first metallization structure 210, a second metallization structure 220, and a base substrate 230, similar to the corresponding components described above. The packaging substrate can be formed using conventional processes (layering processes) as indicated above. To simplify the illustration and eliminate unnecessary repetition, the following process stages will focus on the top layer of the first metallization structure 210.

[0037] exist Figure 2B In the process, the manufacturing process can continue with the first metallization structure 210, which includes a plurality of dielectric layers 212, a plurality of metal layers 214 disposed in the plurality of dielectric layers 212, and a plurality of vias 213 coupling adjacent metal layers 214 in the plurality of metal layers 214 through the plurality of dielectric layers 212.

[0038] exist Figure 2C During this process, the fabrication of device 200 can continue, wherein a package substrate 205 is partially formed. Package substrate 205 includes a first metallization structure 210. The first metallization structure 210 includes a plurality of dielectric layers 212, a plurality of metal layers 214, and a plurality of vias 213. At this stage of fabrication, the currently top dielectric layer among the plurality of dielectric layers 212 has an opening 271, which is formed to pattern the vias to couple the existing metal layer 214 to the metal layer to be formed in subsequent processing.

[0039] exist Figure 2DIn this process, the fabrication of device 200 can continue, wherein a packaging substrate 205 is partially formed. The packaging substrate 205 includes a first metallization structure 210. The first metallization structure 210 includes a plurality of dielectric layers 212, a plurality of metal layers 214, a plurality of vias 213, and an opening 271. At this stage, a thick metal layer 272 is deposited over an exposed top portion of the packaging substrate 205, which includes the current top layer of the plurality of dielectric layers 212 and the opening 271. In some aspects, the thickness of the thick metal layer 272 is in the range of 50% to 75% of the thickness of the buried bump structure.

[0040] exist Figure 2E In this stage, the fabrication process of device 200 can continue, wherein packaging substrate 205 is partially formed. Packaging substrate 205 includes a first metallization structure 210. The first metallization structure 210 includes a plurality of dielectric layers 212, a plurality of metal layers 214, a plurality of vias 213, openings 271, and a thick metal layer 272. In this stage, a dry film resist (DFR) layer 270 is deposited on the thick metal layer 272 on packaging substrate 205.

[0041] exist Figure 2F In this process, the fabrication of device 200 can continue, wherein packaging substrate 205 is partially formed. Packaging substrate 205 includes a first metallization structure 210. The first metallization structure 210 includes a plurality of dielectric layers 212, a plurality of metal layers 214, a plurality of vias 213, an opening 271, a thick metal layer 272, and a DFR layer 270. At this stage, a second opening 273 is formed above the opening 271 in the DFR layer 270. In addition, a plurality of fine openings 274 are formed in the DFR layer 270 and extend to the thick metal layer 272.

[0042] exist Figure 2G In this process, the fabrication of device 200 can continue, wherein packaging substrate 205 is partially formed. Packaging substrate 205 includes a first metallization structure 210, which includes multiple dielectric layers 212, multiple metal layers 214, multiple vias 213, openings 271, a thick metal layer 272, and a DFR layer 270. The DFR layer 270 includes a second opening 273 and multiple fine openings 274. At this stage, multiple escape lines 217 (e.g., three sets of three-line escape patterns as illustrated) are formed in the bottom of the multiple fine openings 274.

[0043] exist Figure 2HIn this stage, the fabrication process of device 200 can continue, wherein a packaging substrate 205 is partially formed. The packaging substrate 205 includes a first metallization structure 210. The first metallization structure 210 includes multiple dielectric layers 212, multiple metal layers 214, multiple vias 213, a thick metal layer 272, and multiple escape lines 217. At this stage, a second DFR layer 280 is deposited on the top surface of the packaging substrate 205. The second DFR layer 280 fills the various openings and causes the multiple escape lines 217 to be covered.

[0044] exist Figure 2I In this process, the fabrication of device 200 can continue, wherein packaging substrate 205 is partially formed. Packaging substrate 205 includes a first metallization structure 210. The first metallization structure 210 includes a plurality of dielectric layers 212, a plurality of metal layers 214, a plurality of vias 213, a thick metal layer 272, a plurality of escape lines 217, and a second DFR layer 280. In this stage, a plurality of bump openings 281 are formed in the second DFR layer 280. The plurality of bump openings 281 extend to the thick metal layer 272 and are disposed adjacent to the three-line groups of the plurality of escape lines 217.

[0045] exist Figure 2J In this process, the fabrication of device 200 can continue, wherein a package substrate 205 is partially formed. Package substrate 205 includes a first metallization structure 210. The first metallization structure 210 includes a plurality of dielectric layers 212, a plurality of metal layers 214, a plurality of vias 213, a thick metal layer 272, a plurality of escape lines 217, and a second DFR layer 280. At this stage, a plurality of embedded bump structures 215 are formed in a plurality of bump openings 281. It should be understood that the pitch of the plurality of bump openings 281 and the plurality of embedded bump structures 215 corresponds to the pitch of the embedded bump structures discussed above, which is substantially smaller than the bump pad pitch in conventional designs. Furthermore, it should be understood that forming the escape lines 217 and the plurality of embedded bump structures 215 may include multiple plating operations in the same layer. For example, a first thin plating may be performed for the escape lines 217, and then a second plating may be performed in the same layer to form a thicker structure, such as the plurality of embedded bump structures 215, in the same layer. Therefore, forming multiple escape lines 217 may include a first metal portion of a first metal layer among multiple metal layers. Forming multiple embedded bump structures 215 may include a second metal portion of the same metal layer, and the first metal portion plated for the escape lines 217 is thinner than the second metal portion plated for the multiple embedded bump structures 215.

[0046] exist Figure 2KIn this stage, the fabrication process of device 200 can continue, wherein a packaging substrate 205 is partially formed. The packaging substrate 205 includes a first metallization structure 210. The first metallization structure 210 includes multiple dielectric layers 212, multiple metal layers 214, multiple vias 213, a thick metal layer 272, multiple escape lines 217, and multiple buried bump structures 215. At this stage, a second DFR layer 280 is removed from the packaging substrate 205 by a stripping process or any suitable process. Upon removal of the second DFR layer 280, the thick metal layer 272, the multiple escape lines 217, and the multiple buried bump structures 215 are exposed for further processing.

[0047] exist Figure 2L In this stage, the fabrication process of device 200 can continue, wherein a package substrate 205 is partially formed. The package substrate 205 includes a first metallization structure 210. The first metallization structure 210 includes a plurality of dielectric layers 212, a plurality of metal layers 214, a plurality of vias 213, a plurality of escape lines 217, and a plurality of buried bump structures 215. At this stage, a thick metal layer 272 is removed (e.g., etched) from the package substrate 205, thereby exposing the plurality of escape lines 217 and the plurality of buried bump structures 215 on the current top surface of the package substrate 205.

[0048] exist Figure 2M In this process, the fabrication of device 200 can continue, wherein packaging substrate 205 is partially formed. Packaging substrate 205 includes a first metallization structure 210. The first metallization structure 210 includes a plurality of dielectric layers 212, a plurality of metal layers 214, a plurality of vias 213, a plurality of escape lines 217, and a plurality of buried bump structures 215. In this stage, the top dielectric layer 212(a) of the plurality of dielectric layers 212 is deposited on packaging substrate 205, thereby encapsulating the plurality of escape lines 217 and the plurality of buried bump structures 215.

[0049] exist Figure 2NIn this process, the fabrication of device 200 can continue, wherein a packaging substrate 205 is partially formed. The packaging substrate 205 includes a first metallization structure 210. The first metallization structure 210 includes multiple dielectric layers 212, multiple metal layers 214, multiple vias 213, multiple escape lines 217, multiple embedded bump structures 215, and a top dielectric layer 212(a). At this stage, the top dielectric layer 212(a) is ground away to expose the multiple embedded bump structures 215, while the multiple escape lines 217 remain encapsulated within the top dielectric layer 212(a). It should be understood that after grinding, the multiple embedded bump structures 215 are flush with the top surface of the top dielectric layer 212(a). In some aspects, the grinding is panel-level dielectric grinding, which also allows for thickness control of the packaging substrate 205 and ultimately allows for thickness control of device 200. In some respects, this part of the manufacturing process can be stopped at this stage, where multiple embedded bump structures 215 are flush with the top surface of the top dielectric layer 212(a). However, in other respects, further processing can be performed.

[0050] exist Figure 2O In this process, the fabrication of device 200 can continue, wherein a packaging substrate 205 is partially formed. The packaging substrate 205 includes a first metallization structure 210. The first metallization structure 210 includes a plurality of dielectric layers 212, a plurality of metal layers 214, a plurality of vias 213, a plurality of escape lines 217, a plurality of embedded bump structures 215, and a top dielectric layer 212(a). At this stage (which is optional in some respects and is performed), the plurality of embedded bump structures 215 are partially etched (e.g., by a soft etching process) to form recesses 216. Thus, the plurality of embedded bump structures 215 are recessed from the top surface of the top dielectric layer 212(a) among the plurality of dielectric layers 212. It should be understood that after performing this optional recessing process, the plurality of embedded bump structures 215 are no longer flush with the top surface of the top dielectric layer 212(a).

[0051] exist Figure 2P In this process, the fabrication of device 200 can continue, wherein a packaging substrate 205 is substantially formed. The packaging substrate 205 includes a first metallization structure 210, a base substrate 230, and a second metallization structure 220. At this stage, a solder resist (SR) layer 245 is deposited on the bottom of the second metallization structure 220. A plurality of solder resist openings (SROs) 285 are formed in the SR layer 245 to allow for ball attachment processes in subsequent processing stages.

[0052] Figure 3A and Figure 3Billustrates the structure at the final stage of the manufacturing / fabrication apparatus 200. Additionally, process stages have been truncated to minimize redundant description. Accordingly, detailed descriptions of elements and process stages may be omitted. For example, at this stage, a ball attachment process has been performed using conventional techniques. For instance, in some aspects, the ball attachment process may be used for the BGA of a flip chip ball grid array (FCBGA) device. Additionally, the die 250 is coupled to the package substrate 205 using conventional process techniques (e.g., a thermocompression bonding process). Furthermore, an underfill 260 may be deposited between the die 250 and the package substrate 205.

[0053] Figure 3A is a cross-sectional view of the apparatus 200 at a final processing stage in accordance with aspects of the present disclosure. Various elements will be discussed for completeness even if not explicitly discussed in the example fabrication process. In some aspects, Figure 3A is a simplified cross-sectional view of the apparatus 200, and certain details and components of the apparatus 200 may be simplified or omitted in Figure 3A . Figure 3B is a cross-sectional view of the apparatus 200 in accordance with aspects of the present disclosure. In some aspects, Figure 3B is an enlarged cross-sectional view of the portion 301 of the apparatus 200, and certain details and components of the apparatus 200 may be simplified or omitted in Figure 3B .

[0054] In some aspects, as shown in Figure 3A and Figure 3B , the apparatus 200 is illustrated as an IC package and / or part of a larger device (such as a mobile phone or the like). In some aspects, the apparatus 200 includes a die 250 comprising a plurality of die connectors 251 and a package substrate 205. In some aspects, an underfill 260 is disposed between the die 250 and the package substrate 205 to provide mechanical bonding and encapsulate the connections (e.g., the die connectors 251 and the embedded bump structures 215) of the die 250 to the package substrate 205. In some aspects, the die connectors 251 may be die bumps and solder balls, and in other aspects, the die connectors 251 may merely be pins or pillars directly coupled to the package substrate 205. It should be appreciated that one or more dies may be coupled to the first metallization structure 210, and the various disclosed and claimed aspects are not limited to the illustrated example.

[0055] In some aspects, the package substrate 205 includes a base substrate 230 having a first side and a second side. In some aspects, the base substrate 230 may include a core, and in other aspects, the base substrate 230 may be coreless, as discussed above. The first metallization structure 210 includes a plurality of dielectric layers 212, a plurality of metal layers 214 disposed in the plurality of dielectric layers 212, and a plurality of vias 213 coupling adjacent metal layers 214 among the plurality of metal layers 214 through the plurality of dielectric layers 212. The first metallization structure 210 also includes a plurality of embedded bump structures 215 disposed in the top dielectric layer 212(a) among the plurality of dielectric layers 212, wherein the plurality of embedded bump structures 215 are directly coupled to a plurality of die connectors 251. It should be understood that the embedded bump structures 215 do not have solder mask openings (SRO) in the solder mask (SR) layer because no SR layer is deposited on the top dielectric layer 212(a) among the plurality of dielectric layers 212. Therefore, solder mask (SR) treatment is not required on the top of the package substrate 205 in the disclosed aspects. In some aspects, multiple escape lines 217 (e.g., a three-line escape pattern as illustrated) may be provided between adjacent embedded bump structures 215. It should be understood that the various aspects disclosed and claimed are not limited to three lines, and more or fewer lines (including no lines) may exist between adjacent embedded bump structures 215.

[0056] Additionally, such as Figure 3B As illustrated, in some aspects, the pitch of the plurality of embedded bump structures 215 is approximately 64 micrometers (µm), which is significantly reduced compared to conventional designs, as discussed above. In some aspects, the width of each embedded bump structure in the embedded bump structure 215 is approximately 18 micrometers (µm). In some aspects, the width of each escape line in the escape line 217 is approximately 6 micrometers (µm). In some aspects, the spacing between each escape line in the escape line 217 is approximately 6 micrometers (µm), and the spacing between the embedded bump structure 215 and the adjacent escape line 217 is approximately 8 micrometers (µm). It should be understood that the various aspects disclosed and claimed are not limited to these specific numerical examples, and each of the embedded bump structure 215 and the escape line 217 may have different widths, pitches, and / or spacings. Furthermore, as illustrated, the embedded bump structure 215 is recessed from the top surface of the top dielectric layer 212(a), which corresponds to the foregoing description of... Figure 2O The concave process discussed.

[0057] Return to reference Figure 3A, the second metallization structure 220 is disposed on the second side of the base substrate 230. The second metallization structure 220 includes a plurality of dielectric layers 222, a plurality of metal layers 224 disposed in the plurality of dielectric layers 222, and a plurality of vias 223 that couple adjacent metal layers 224 of the plurality of metal layers 224 through the plurality of dielectric layers 222. The connection structure 240 (for example, solder balls, BGA, solder paste, copper pillars, etc.) is disposed on the bottom of the second metallization structure 220 opposite to the base substrate 230, and is configured to electrically couple the package substrate 205 to an external component, device, etc. through the second metallization structure 220. The solder resist layer 245 is disposed on the bottom of the second metallization structure 220, wherein the connection structure 240 is coupled to the second metallization structure 220 through a solder resist opening (SRO) in the solder resist layer 245.

[0058] In some aspects, the base substrate 230 further includes a first metal layer 231 on the first side and a second metal layer 232 on the second side, the first metal layer and the second metal layer being separated by a core 235. In some aspects, the core 235 may include a dielectric material with a pre-impregnated reinforcing component embedded therein. In some aspects, the core 235 may include a prepreg (also referred to as PPG), which may include a polymer resin impregnated with fiberglass sheets. In some aspects, the base substrate 230 includes at least one plated through hole (PTH) 236 disposed through the core 235, the at least one plated through hole (PTH) being configured to couple portions of the first metal layer 231 and the second metal layer 232 on opposite sides of the core 235.

[0059] In some aspects, the first metallization structure 210 may include multiple layers of Ajinomoto Build-up Film (ABF) or other similar epoxy or resin-based layers. In some aspects, the second metallization structure may include resin-impregnated fiberglass (prepreg), Ajinomoto Build-up Film (ABF), Resin Coated Copper (RCC) build-up film, or any similar material. In some aspects, the metal layers and vias of the first metallization structure 210, the second metallization structure 220, and the base substrate 230 may be made of any highly conductive material, such as copper (Cu), aluminum (Al), silver (Ag), gold (Au), titanium (Ti), nickel (Ni), tin (Sn), lead (Pb), their alloys or combinations.

[0060] Figure 3C illustrates a device 300 similar to devices 100 and 200, except that it is a coreless configuration. Therefore, Figure 3C is a simplified cross-sectional view of the device 300, and certain details and components of the device 300 may be simplified or omitted in Figure 3C . Additionally, Figure 3B the connection details illustrated in also apply to the coreless configuration.

[0061] In some aspects, such as Figure 3C As shown, device 300 is illustrated as part of an IC package and / or a larger device (such as a mobile phone). In some aspects, device 300 includes a die 350 and a package substrate 305, the die including a plurality of die connectors 351. In some aspects, underfill 360 is disposed between the die 350 and the package substrate 305 to provide mechanical engagement and encapsulate the connection from the die 350 to the package substrate 305 (e.g., die connectors 351 and embedded bump structures 315). In some aspects, die connectors 351 may be die bumps and solder balls; in other aspects, die connectors 351 may be simply pins or posts directly coupled to the package substrate 305. It should be understood that one or more dies may be coupled to a first metallization structure 310, and the various aspects disclosed and claimed are not limited to the illustrated examples.

[0062] In some aspects, the first metallization structure 310 includes a plurality of dielectric layers 312, a plurality of metal layers 314 disposed in the plurality of dielectric layers 312, and a plurality of vias 313 coupling adjacent metal layers 314 among the plurality of metal layers 314 through the plurality of dielectric layers 312. The first metallization structure 310 also includes a plurality of embedded bump structures 315 disposed in a top dielectric layer 312(a) among the plurality of dielectric layers 312, wherein the plurality of embedded bump structures 315 are directly coupled to a plurality of die connectors 351. It should be understood that the embedded bump structures 315 do not have solder mask openings (SRO) in the solder mask (SR) layer because no SR layer is deposited on the top dielectric layer 312(a) among the plurality of dielectric layers 312. Therefore, in the disclosed aspects, solder mask (SR) treatment is not required on the top of the package substrate 305. In some aspects, a plurality of escape lines 317 (e.g., a three-line escape pattern as illustrated) may be disposed between adjacent embedded bump structures 315. It should be understood that the various aspects disclosed and claimed are not limited to three lines, and there may be more or fewer lines (including no lines) between adjacent embedded bump structures 315.

[0063] A connection structure 340 (e.g., solder ball, BGA, solder paste, copper pillar, etc.) is disposed on the bottom of the first metallization structure 310 opposite to the die 350, and is configured to electrically couple the package substrate 305 to external components, devices, etc. through the first metallization structure 310. A solder mask layer 345 is disposed on the bottom of the first metallization structure 310, wherein the connection structure 340 is coupled to the first metallization structure 310 through solder mask openings (SROs) in the solder mask layer 345.

[0064] In some aspects, the first metallization structure 310 may include a multilayer Ajinomoto laminate (ABF) or similar other epoxy resin or resin substrate. In some aspects, the metal layers and vias of the first metallization structure 310 may be made of any highly conductive material, such as copper (Cu), aluminum (Al), silver (Ag), gold (Au), titanium (Ti), nickel (Ni), tin (Sn), lead (Pb), alloys of them, or combinations thereof.

[0065] It should be understood that the illustrated configurations and descriptions provided herein are merely illustrative of the various aspects disclosed herein. Accordingly, the foregoing illustrative examples should not be construed as limiting the various aspects disclosed and claimed herein.

[0066] It should be understood that known techniques can be used to perform additional processing to form and attach additional structures (e.g., molding compounds, caps, etc., can be used to encapsulate the die / package substrate). The additional die can be directly coupled to the package substrate or arranged in a stacked structure. Furthermore, the various aspects disclosed may include additional substrates that can be used to interface with printed circuit boards (PCBs) or other external devices. Therefore, it should be understood that the various aspects disclosed in this invention are not limited to the specific configurations illustrated in the drawings.

[0067] It should be understood that the foregoing manufacturing processes are provided only as general examples of some aspects of this disclosure and are not intended to limit this disclosure or the appended claims. Furthermore, many details of the manufacturing processes known to those skilled in the art may be omitted or combined in the various overview process sections to facilitate an understanding of the various aspects disclosed without presenting every detail and / or all possible process variations in detail.

[0068] Figure 4 A method 400 for manufacturing / fabricating an apparatus having an embedded bump structure (such as a substrate for an IC package, the substrate incorporating features of any of the example apparatuses 100, 200, and / or 300) according to various aspects of this disclosure is illustrated. In some aspects, Figures 2A to 2P The substrate can be depicted at different manufacturing stages according to method 400. It should be understood from the foregoing that various methods exist for fabricating devices including those comprising multiple embedded bump structures as disclosed herein.

[0069] At operation 410, the process includes providing a die (e.g., die 150 or 250) that includes a plurality of die connectors (e.g., die connector 151 or 251).

[0070] At operation 420, the process includes forming a packaging substrate (e.g., packaging substrate 105 or 205), and forming the packaging substrate includes forming a first metallization structure (e.g., first metallization structure 110 or 210).

[0071] At operation 430, the process for forming a first metallization structure (e.g., first metallization structure 110 or 210) includes forming a plurality of dielectric layers (e.g., dielectric layer 112 or 212).

[0072] At operation 440, the process for forming a first metallization structure (e.g., first metallization structure 110 or 210) includes forming a plurality of metal layers (e.g., metal layer 114 or 214) disposed in a plurality of dielectric layers (e.g., dielectric layer 112 or 212).

[0073] At operation 450, the process for forming a first metallization structure (e.g., first metallization structure 110 or 210) includes forming a plurality of vias (e.g., vias 113 or 213) that are coupled to adjacent metal layers (e.g., metal layers 114 or 214) through a plurality of dielectric layers (e.g., dielectric layer 112 or 212).

[0074] At operation 460, the process for forming a first metallization structure (e.g., first metallization structure 110 or 210) includes forming a plurality of embedded bump structures (e.g., embedded bump structures 115 or 215) disposed in a top dielectric layer (e.g., top dielectric layer 112(a) or 212(a)) among a plurality of dielectric layers (e.g., dielectric layer 112 or 212).

[0075] At operation 470, the process includes providing a die (e.g., die 150 or 250) and directly coupling a plurality of embedded bump structures (e.g., embedded bump structures 115 or 215) to a plurality of die connectors (e.g., die connector 151 or 251).

[0076] Figure 5 A mobile device 500 according to various aspects of this disclosure is illustrated. In some aspects, the mobile device 500 may be implemented by including one or more IC devices, which include embedded bump structures as disclosed herein.

[0077] In some aspects, mobile device 500 can be configured as a wireless communication device. As shown, mobile device 500 includes a processor 501. Processor 501 is communicatively coupled to memory 532 via a link, which can be a die-to-die or chip-to-chip link. Mobile device 500 also includes a display 528 and a display controller 526, wherein display controller 526 is coupled to processor 501 and display 528. Mobile device 500 may include an input device 530 (e.g., a physical or virtual keyboard), a power supply 544 (e.g., a battery), a speaker 536, a microphone 538, and a wireless antenna 542. In some aspects, power supply 544 may directly or indirectly provide power supply voltage for some or all of the components of mobile device 500.

[0078] In some respects, Figure 5 It may include a decoder / decoder (codec) 534 (e.g., an audio and / or voice codec) coupled to the processor 501; a speaker 536 and a microphone 538 coupled to the codec 534; and a wireless circuit 540 (which may include a modem, RF circuitry, filters, etc.) coupled to the wireless antenna 542 and coupled to the processor 501.

[0079] In some aspects, one or more of the processor 501 (e.g., SoC, application processor (AP), central processing unit (CPU), digital signal processor (DSP), etc.), display controller 526, memory 532, codec 534, and wireless circuit 540 (e.g., baseband interface) include an IC device packaged as an IC package and include embedded bump structures according to various aspects described in this disclosure.

[0080] It should be pointed out that, although Figure 5 Mobile device 500 is described, but similar architectures can be used to implement devices including microprocessors, servers, set-top boxes, music players, video players, entertainment units, navigation devices, personal digital assistants (PDAs), fixed-location data units, computers, laptops, tablets, communication devices, mobile phones, or other similar devices.

[0081] Figure 6 Various electronic devices 610, 620 and 630 that can be incorporated with IC devices 612, 622 and 632 according to aspects of this disclosure are illustrated, and these IC devices can be packaged as IC packages having an embedded bump structure as disclosed herein.

[0082] For example, mobile phone device 610, laptop computer device 620, and fixed-location terminal device 630 can each generally be considered as user equipment (UE) and may include one or more IC devices (such as IC devices 612, 622, and 632) and a power supply for providing a supply voltage to power the IC devices. IC devices 612, 622, and 632 may, for example, correspond to IC device packages having an embedded bump structure as described herein.

[0083] Figure 6 The devices 610, 620, and 630 illustrated herein are merely non-limiting examples. Other electronic devices may also feature IC devices on a packaged substrate as described in this disclosure, including, but not limited to, devices comprising the following group (e.g., electronic devices): mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed-location data units (such as instrument reading devices), communication devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), Internet of Things (IoT) devices, access points, base stations, or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0084] It should be understood that the various aspects disclosed herein can be described as functional equivalents of structures, materials, and / or devices as described and / or understood by those skilled in the art. For example, in one aspect, the apparatus may include components for performing the various functions discussed above. It should be understood that the foregoing aspects are provided by way of example only, and the claimed aspects are not limited to the specific references and / or illustrations cited as examples.

[0085] Figures 1A to 6 One or more of the components, processes, features, and / or functions illustrated herein may be rearranged and / or combined into a single component, process, feature, or function, or incorporated into several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. In some specific embodiments, Figures 1A to 6 The corresponding descriptions can be used to manufacture, create, supply, and / or produce integrated devices. In some specific implementations, the equipment may include dies, integrated devices, die packages, ICs, device packages, IC packages, wafers, semiconductor devices, system-in-package (SiP), system-on-a-chip (SoC), and stacked package (PoP) devices, etc.

[0086] As can be seen in the detailed description above, different features are grouped together in the examples. This manner of disclosure should not be construed as an intention to have more features than those explicitly mentioned in each clause. Rather, the various aspects of this disclosure may include fewer features than those in the individual example clauses disclosed. Therefore, the following clauses should be regarded accordingly as incorporated into the description, where each clause may serve as a separate example. Although each dependent clause may refer in the clause to a specific combination with one of the other clauses, the aspect of that dependent clause is not limited to that specific combination. It should be understood that other example clauses may also include combinations of aspects of a dependent clause with the subject matter of any other dependent or independent clause, or combinations of any feature with other dependent and independent clauses. The various aspects disclosed herein explicitly include these combinations unless explicitly stated or readily inferred that a particular combination is not intended for use (e.g., contradictory aspects, such as defining an element as both an electrical insulator and an electrical conductor). Furthermore, it is contemplated that aspects of a clause may be included in any other independent clause, even if that clause does not directly depend on the independent clause.

[0087] Specific implementation examples are described in the following numbered clauses: Clause 1. An apparatus comprising: a die including a plurality of die connectors; and a package substrate including a first metallization structure disposed beneath the die, the first metallization structure including: a plurality of dielectric layers; a plurality of metal layers disposed in the plurality of dielectric layers; a plurality of vias configured to couple adjacent metal layers among the plurality of metal layers through the plurality of dielectric layers; and a plurality of embedded bump structures disposed in a top dielectric layer among the plurality of dielectric layers, wherein the plurality of embedded bump structures are directly coupled to the plurality of die connectors.

[0088] Clause 2. The apparatus according to Clause 1, wherein the plurality of embedded bump structures are flush with the top surface of the top dielectric layer of the plurality of dielectric layers.

[0089] Clause 3. The apparatus according to any one of Clauses 1 to 2, wherein the plurality of embedded bump structures are recessed from the top surface of the top dielectric layer among the plurality of dielectric layers.

[0090] Clause 4. The apparatus according to any one of Clauses 1 to 3, wherein the first metallization structure comprises: a plurality of escape lines disposed between adjacent embedded bump structures in the plurality of embedded bump structures.

[0091] Clause 5. The apparatus according to Clause 4, wherein at least a portion of the plurality of escape lines is configured as a three-line escape pattern.

[0092] Clause 6. The apparatus according to Clause 5, wherein the spacing between one of the adjacent embedded bump structures and the adjacent escape line is approximately 8 micrometers.

[0093] Clause 7. The apparatus according to Clause 6, wherein the width of each of the plurality of escape lines is approximately 6 micrometers.

[0094] Clause 8. The device according to any one of Clauses 1 to 7, wherein the first metallization structure comprises an Ajinomoto laminate (ABF).

[0095] Clause 9. The apparatus according to any one of Clauses 1 to 8, wherein the packaging substrate further comprises: a base substrate, the base substrate including a core, the core including a pre-impregnated reinforcement component embedded therein.

[0096] Clause 10. The apparatus according to Clause 9, wherein the base substrate includes at least one plated through-hole (PTH) disposed through the core, the at least one plated through-hole (PTH) being configured to couple portions of a metal layer on opposite sides of the core.

[0097] Clause 11. The apparatus according to any one of Clauses 9 to 10, wherein the packaging substrate further comprises: a second metallization structure, the second metallization structure comprising a plurality of dielectric layers, a plurality of metal layers and a plurality of vias, and wherein the first metallization structure is disposed on a first side of the base substrate opposite to the die, and the second metallization structure is disposed on a second side of the base substrate opposite to the first metallization structure.

[0098] Clause 12. The apparatus according to Clause 11, wherein the second metallization structure comprises: resin-impregnated glass fiber (prepreg), Ajinomoto laminate (ABF), or resin-coated copper (RCC) laminate.

[0099] Clause 13. The device according to any one of Clauses 1 to 12, wherein the pitch of the plurality of embedded bump structures is approximately 64 micrometers.

[0100] Clause 14. The apparatus according to any one of Clauses 1 to 13, wherein the width of each of the plurality of embedded bump structures is approximately 18 micrometers.

[0101] Clause 15. The device according to any one of Clauses 1 to 14, wherein the device comprises at least one of: a music player, a video player, an entertainment unit; a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, or a device in a motor vehicle.

[0102] Clause 16. A method of manufacturing an apparatus, the method comprising: providing a die, the die including a plurality of die connectors; forming a package substrate, the package substrate including forming a first metallization structure, the first metallization structure including: forming a plurality of dielectric layers; forming a plurality of metal layers disposed in the plurality of dielectric layers; forming a plurality of vias coupling adjacent metal layers among the plurality of metal layers through the plurality of dielectric layers; forming a plurality of embedded bump structures disposed in a top dielectric layer among the plurality of dielectric layers; and directly coupling the plurality of embedded bump structures to the plurality of die connectors.

[0103] Clause 17. The method according to Clause 16, the method further comprising: grinding the top surface of the top dielectric layer until the plurality of embedded bump structures are flush with the top surface of the top dielectric layer.

[0104] Clause 18. The method according to Clause 17, the method further comprising: etching the plurality of embedded bump structures to cause the plurality of embedded bump structures to be recessed from the top surface of the top dielectric layer.

[0105] Clause 19. The method according to any one of Clauses 16 to 18, the method further comprising: forming a plurality of escape lines disposed between adjacent embedded protrusion structures in the plurality of embedded protrusion structures.

[0106] Clause 20. The method according to Clause 19, wherein forming the plurality of escape lines includes a first metal portion of a first metal layer of the plurality of metal layers, and wherein forming the plurality of embedded bump structures includes a second metal portion of the first metal layer, wherein the first metal portion is thinner than the second metal portion.

[0107] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and arts. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0108] Furthermore, those skilled in the art will understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0109] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0110] The methods, sequences, and / or algorithms described in conjunction with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or a combination of both. The software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art. Example storage media are coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal (e.g., a UE). Alternatively, the processor and storage medium may reside as discrete components in the user terminal.

[0111] In one or more examples, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. A storage medium may be any available medium accessible to a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and is accessible to a computer. Furthermore, any connection is appropriately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included within the definition of a medium. As used herein, disks and optical discs include: compact optical discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these should also be included within the scope of computer-readable media.

[0112] Furthermore, as used herein, the terms “set,” “group,” etc., are intended to include one or more of the stated elements. Additionally, as used herein, the terms “having,” “comprising,” “including,” etc., do not exclude the presence of one or more additional elements (e.g., element “having” A may also have B). Furthermore, the phrase “based on” is intended to mean “at least partially based on” unless otherwise explicitly stated. Moreover, as used herein, the term “or” is intended to be open-ended when used in a series and may be used interchangeably with “and / or” unless otherwise explicitly stated (e.g., if used in conjunction with “any” or “only one”), or these alternatives are mutually exclusive (e.g., “one or more” should not be interpreted as “one and more”). Furthermore, although components, functions, actions, and instructions may be described or claimed in the singular form, the plural form may also be considered unless explicitly stated to be limited to the singular. Therefore, as used herein, the articles “a,” “an,” “the,” and “described” are intended to include one or more of the stated elements. Additionally, as used herein, the terms “at least one” and “one or more” include performing or being able to perform “one” component, function, action or instruction of the described or claimed functionality, and also include performing or being able to perform “two or more” components, functions, actions or instructions of the described or claimed functionality in combination.

[0113] While the foregoing disclosure illustrates exemplary aspects of this disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of this disclosure as defined by the appended claims. For example, the functions, steps, and / or actions of the method claims according to aspects of this disclosure described herein need not be performed in any particular order. Furthermore, no component, function, action, or instruction described or claimed herein should be construed as critical or essential unless explicitly stated otherwise.

Claims

1. An apparatus comprising: A bare die, the bare die including a plurality of bare die connectors; and The packaging substrate includes a first metallization structure disposed beneath the bare die, the first metallization structure comprising: Multiple dielectric layers; Multiple metal layers are disposed within multiple dielectric layers; Multiple vias, the multiple vias being configured to couple adjacent metal layers among the multiple metal layers through the multiple dielectric layers; and Multiple embedded bump structures are disposed in the top dielectric layer of the multiple dielectric layers, wherein the multiple embedded bump structures are directly coupled to the multiple die connectors.

2. The apparatus according to claim 1, wherein the plurality of embedded bump structures are flush with the top surface of the top dielectric layer among the plurality of dielectric layers.

3. The apparatus of claim 1, wherein the plurality of embedded bump structures are recessed from the top surface of the top dielectric layer among the plurality of dielectric layers.

4. The apparatus of claim 1, wherein the first metallization structure comprises: Multiple escape lines are provided between adjacent embedded protrusion structures in the plurality of embedded protrusion structures.

5. The apparatus of claim 4, wherein at least a portion of the plurality of escape lines is configured as a three-line escape pattern.

6. The apparatus of claim 5, wherein the spacing between one of the adjacent embedded bump structures and the adjacent escape line is approximately 8 micrometers.

7. The apparatus of claim 6, wherein the width of each of the plurality of escape lines is approximately 6 micrometers.

8. The apparatus of claim 1, wherein the first metallization structure comprises an Ajinomoto multilayer film (ABF).

9. The apparatus of claim 1, wherein the packaging substrate further comprises: A base substrate, the base substrate including a core, the core including a pre-impregnated reinforcement component embedded therein.

10. The apparatus of claim 9, wherein the base substrate comprises: At least one plated through-hole (PTH) is provided through the core, and the at least one plated through-hole (PTH) is configured to couple portions of the metal layer located on opposite sides of the core.

11. The apparatus of claim 9, wherein the packaging substrate further comprises: The second metallization structure includes multiple dielectric layers, multiple metal layers, and multiple vias. The first metallization structure is disposed on a first side of the base substrate opposite to the die, and the second metallization structure is disposed on a second side of the base substrate opposite to the first metallization structure.

12. The apparatus of claim 11, wherein the second metallization structure comprises: Resin-impregnated glass fiber (prepreg), Ajinomoto laminated film (ABF), or resin-coated copper (RCC) laminated film.

13. The apparatus of claim 1, wherein the pitch of the plurality of embedded bump structures is approximately 64 micrometers.

14. The apparatus of claim 1, wherein the width of each of the plurality of embedded bump structures is approximately 18 micrometers.

15. The apparatus of claim 1, wherein the apparatus comprises at least one of: a music player, a video player, an entertainment unit; a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, or a device in a motor vehicle.

16. A method of manufacturing an apparatus, the method comprising: A bare die is provided, the bare die including a plurality of bare die connectors; Forming a packaging substrate, wherein forming the packaging substrate includes forming a first metallization structure, and forming the first metallization structure includes: Multiple dielectric layers are formed; Multiple metal layers are formed, and the multiple metal layers are disposed in the multiple dielectric layers; Multiple vias are formed, wherein the multiple vias are coupled to adjacent metal layers among the multiple metal layers through the multiple dielectric layers; and Multiple embedded bump structures are formed, wherein the multiple embedded bump structures are disposed in the top dielectric layer of the multiple dielectric layers; and The plurality of embedded bump structures are directly coupled to the plurality of bare die connectors.

17. The method according to claim 16, further comprising: Grind the top surface of the top dielectric layer until the plurality of embedded bump structures are flush with the top surface of the top dielectric layer.

18. The method according to claim 17, further comprising: The plurality of embedded bump structures are etched to make the plurality of embedded bump structures recessed from the top surface of the top dielectric layer.

19. The method according to claim 16, further comprising: Multiple escape lines are formed, and the multiple escape lines are arranged between adjacent embedded protrusion structures in the multiple embedded protrusion structures.

20. The method according to claim 19, The formation of the plurality of escape lines includes a first metal portion of the first metal layer among the plurality of metal layers, and The plurality of embedded bump structures include a second metal portion coated with the first metal layer, wherein the first metal portion is thinner than the second metal portion.

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