Intravascular ultrasound imaging system based on annular phased array and control method

Abstract

This invention provides an intravascular ultrasound imaging system and control method based on a ring phased array, comprising: a ring phased array including multiple interconnected ultrasound chips and a transducer array corresponding to each ultrasound chip; the multiple ultrasound chips and transducer arrays are arranged in a ring; each ultrasound chip includes an identification configuration unit, a communication interface module, and a gating control module; the identification configuration unit is used to acquire and latch the local chip ID of the ultrasound chip; the communication interface modules of the multiple ultrasound chips are interconnected through a shared communication link; the communication interface module is used to receive communication control data, which includes the selected ultrasound chip ID and gating channel information; the gating control module is used to determine whether the ultrasound chip is selected and the gating channel based on the chip ID and the communication control data. This invention enables flexible configuration of chips and channels, allowing for multi-cycle configuration of multiple channels, adapting to composite aperture imaging, and increasing the flexibility of intravascular ultrasound imaging.

Description

Technical Field

[0001] This invention relates to ultrasound chips, and more specifically, to an intravascular ultrasound imaging system and control method based on a ring phased array. Background Technology

[0002] The working principle of an ultrasonic transducer is based on the direct and inverse piezoelectric effects of piezoelectric materials. It achieves efficient transmission and reception of ultrasonic signals through the periodic vibration of a piezoelectric thin film. When the ultrasonic transducer acts as a transmitter, it essentially converts electrical signals into mechanical vibration energy. Under the action of a driving voltage, the piezoelectric thin film deforms due to the inverse piezoelectric effect, radiating ultrasonic waves into the medium. When acting as a receiver, it becomes a sensor that captures mechanical vibration energy. External ultrasonic waves cause the piezoelectric thin film to vibrate, converting the acoustic signal into an electrical signal through the direct piezoelectric effect for subsequent processing.

[0003] Complementary Metal Oxide Semiconductor (CMOS) technology, as a core technology in the semiconductor field, is widely used in integrated circuit manufacturing and many other areas. It can integrate a large number of transistors onto a small chip, continuously developing in accordance with Moore's Law, and driving the evolution of semiconductors towards miniaturization and high performance.

[0004] In ultrasound imaging systems, CMOS integrated circuits at the transmitting end precisely control the excitation signal of the ultrasound transducer. For example, they can generate electrical pulse signals with specific frequencies, pulse widths, and amplitudes to drive the ultrasound transducer to emit ultrasonic waves. In some medical ultrasound diagnostic devices, CMOS integrated circuits optimize the emitted waveform, improving the emission efficiency and directivity of ultrasound waves, thereby enhancing the resolution and clarity of the imaging. At the receiving end, CMOS integrated circuits are responsible for receiving the echo signals received by the ultrasound transducer and performing preprocessing such as pre-amplification and filtering. CMOS integrated circuits can integrate high-performance, low-noise amplifiers to reduce noise interference in the received signal, while simultaneously processing echo signals of different frequencies and amplitudes quickly and accurately, providing high-quality data for subsequent signal processing and image reconstruction.

[0005] Scientific research shows that as fatty substances accumulate on the walls of blood vessels, the arterial walls thicken, and eventually, fatty tissue invades the lumen, forming plaques. As plaques accumulate, the lumen narrows, obstructing blood flow. If the arterial stenosis is too severe, or if a thrombus forms at the site of the damaged plaque (lesion), blood supply will be severely reduced or even interrupted, and the muscles it supplies may be damaged or necrotic due to lack of oxygen. Nowadays, minimally invasive diagnosis and treatment of lesions can often be achieved through catheter-based interventions. This requires an ultrasound probe to provide electronically converted echo signals to an external imaging system to generate two-dimensional or three-dimensional images of the blood vessel lumen, arterial wall, and surrounding tissues. In intravascular ultrasound imaging systems, catheter diameters are typically only a few millimeters (e.g., 1mm-3mm), severely limiting the number of physical cables connecting to the host. Using traditional parallel independent control lines (one enable line per chip) would increase catheter rigidity, skyrocket manufacturing costs, and become unacceptable. More importantly, beamforming in a ring array is highly dependent on the absolute physical coordinates of each element. Traditional methods based on external pin configuration IDs not only consume pin resources but also fail to achieve rapid internal self-localization during the initial power-up phase, thus failing to meet the low-latency requirements of real-time imaging. Summary of the Invention

[0006] To address the problems in the prior art, the purpose of this invention is to provide an intravascular ultrasound imaging system and control method based on a ring phased array.

[0007] The intravascular ultrasound imaging system based on a ring phased array according to the present invention includes: A ring phased array includes multiple interconnected ultrasonic chips and a transducer array connected to each ultrasonic chip; the multiple ultrasonic chips and the transducer array are arranged in a ring. The ultrasonic chip includes an identification configuration unit, a communication interface module, and a gating control module; the identification configuration unit is used to acquire and latch the unique local chip ID of the ultrasonic chip. The communication interface modules of multiple ultrasound chips are interconnected through a shared communication link; the communication interface module is used to receive communication control data, which includes the selected ultrasound chip ID and selection channel information; the selection control module is used to determine whether the ultrasound chip is selected and the selection channel based on the local chip ID and the communication control data. The local chip ID uniquely represents the physical spatial location information of the ultrasonic chip in the ring phased array, thereby enabling the generation of corresponding delay parameters based on the physical spatial location information to control the ultrasonic wave transmission phase of the corresponding transducer array element, and to perform spatial registration and beamforming processing on the received multi-channel echo signal based on the physical spatial location information.

[0008] Preferably, the identification configuration unit is configured to acquire and latch the local chip ID based solely on the cascaded signal transmission between chips, without requiring an external host to allocate additional pin configuration signals; The numerical order of the local chip ID corresponds to the physical arrangement order of the ultrasonic chips in the ring phased array.

[0009] Preferably, the identifier configuration unit acquires and latches the local chip ID in any of the following ways: Method 1: The identification configuration unit includes a shift register and a counter, and the shift registers of multiple ultrasound chips are cascaded in series; signal transmission is performed between adjacent ultrasound chips, and SR data is transmitted step by step from the first ultrasound chip under the synchronous drive of the SR clock signal, and is accumulated sequentially according to the counter, and the result is stored and latched as the local chip ID. The SR clock signal is used to synchronize the shift register data shifting and transmission between adjacent ultrasound chips. Method 2: The identification configuration unit includes a non-volatile memory element, which has the local chip ID pre-programmed and embedded before chip integration; Method 3: The identification configuration unit includes a shift register, and the shift registers of multiple ultrasound chips are cascaded in series; the ultrasound chip receives an initialization command through the communication interface module to configure an initial ID value, and accumulates the ID value inside the chip and transmits it to the next stage ultrasound chip through the cascaded signal line. After comparison and update, the ID value is latched as the local chip ID. Preferably, the third method specifically includes: the identification configuration unit includes a shift register and a comparison logic circuit, and the shift registers of multiple ultrasound chips are cascaded; the process of acquiring and latching the local chip ID includes: setting the SR data input terminal of the first ultrasound chip to zero; inputting an instruction through the communication interface module to set the shift register of each ultrasound chip to the same initial value; each ultrasound chip incrementing the value of its shift register by one and writing it to the next level ultrasound chip; each ultrasound chip comparing the input chip ID with the value in the current shift register through the comparison logic circuit, if the input chip ID is greater than the current value, then replacing the current value with the input chip ID, otherwise leaving it unchanged; repeating the above shift and comparison operations a preset number of times to complete the ID fixing of all chips, and setting an initialization completion status flag internally for reading, and finally latching it as the local chip ID.

[0010] Method 4: The identification configuration unit includes multiple reserved hardware pins. During chip packaging, the local chip ID is determined and latched in the form of hardware physical encoding by fixing the hardware pins to high or low levels respectively.

[0011] Preferably, the ultrasonic chip includes a data interface and a master clock interface; The data interfaces of multiple interconnected ultrasound chips are interconnected to form a star interface; The clock interfaces of multiple interconnected ultrasound chips are interconnected to form a star-shaped master clock interface to achieve unified reception of the master clock.

[0012] Preferably, the ultrasound chip further includes a data readback circuit, which includes a bidirectional low-voltage differential signal LVDS buffer, a tri-state buffer, and a selection switch; The data readback circuit includes two data readback paths: The first approach is to enable and share the bidirectional LVDS buffer for data readback by configuring the LVDS output enable signal. The second approach is to configure a multiplexer signal so that the digital readback data is output through the tri-state buffer and the data is read back by sharing the output line with the cable driver output via a selector switch.

[0013] In this embodiment of the invention, when data is read back through the bidirectional LVDS buffer via the first path, in the case where the readback data flows back to the chip input terminal because all the ultrasound chips share the same set of LVDS input terminals, the main control state machine inside the ultrasound chip is equipped with an isolation circuit to block the input of invalid data.

[0014] Preferably, the ultrasonic chip is internally configured with a timing control circuit for controlling the sampling timing of serial data output; The timing control circuit is configured to generate a sampling period signal for each ultrasound chip based on the system clock, and to generate a sampling signal offset by half a frequency division period relative to the sampling period signal. The sampling signal is used as a trigger point for data state updates, so that the sampling point of the data is offset by the sampling signal of half a frequency division cycle, so as to ensure the stability of data sampling.

[0015] Preferably, the ultrasonic chip includes multiple transmitting channels and one receiving channel; The transducer array includes multiple transducer array elements; The transmission channel corresponds one-to-one with the transducer array element and is used to generate pulse electrical signals to drive the transducer array element to emit ultrasonic waves. It is configured to be able to activate multiple transmission channels simultaneously for transmission according to instructions. The receiving channel is used to receive echo signals from different transducer channels, so that the ultrasonic chip can traverse all transducer array elements. A switching switch is used to switch the transducer array element connected to or disconnected from the transmit and receive channels.

[0016] Preferably, in the first method, the ultrasound chip further includes an SR clock interface; The SR clock interfaces of multiple interconnected ultrasound chips are interconnected to form a star-shaped SR clock interface for acquiring the SR clock signal.

[0017] Preferably, the ultrasound chip includes an SR input interface and an SR output interface; The SR output interface of the aforementioned ultrasound chip is connected to the SR input interface of the latter ultrasound chip, thereby realizing the serial cascading of the shift registers of multiple ultrasound chips.

[0018] Preferably, the shared communication link is distributed in a star topology; The communication interface module includes a data parser; the data parser is used to parse the received communication control data to determine the transmitter chip ID, transmitter channel, receiver chip ID, and receiver channel.

[0019] The control method based on the ultrasound imaging system provided by the present invention includes the following steps: Step S1: Control or trigger the identification configuration unit so that all ultrasound chips acquire and latch their corresponding local chip IDs; Step S2: Based on the received communication control data, determine the chip ID and transmission channel of the transmitting signal, as well as the chip ID and reception channel of the receiving signal; Step S3: Activate the transmission channel of the target chip according to the chip ID of the transmitted signal and the transmission channel to drive the transducer array element to emit ultrasonic waves; Step S4: Activate the receiving channel of the target chip to receive the echo signal according to the chip ID of the received signal and the receiving channel; Step S5: Dynamically adjust and activate multiple ultrasound chips and transmission channels to regulate the transmission aperture and sound intensity, and then generate a complete ultrasound image by synthesizing the multi-cycle echo signals through the aperture processing.

[0020] Compared with the prior art, the present invention has the following beneficial effects: 1. The ring phased array in this invention comprises multiple interconnected ultrasound chips and transducer arrays. By combining the communication interface module with the gating control module, gating is performed by comparing the local chip ID with the received communication control data. This mechanism breaks the limitations of traditional fixed ultrasound channels, enabling extremely flexible configuration of ultrasound chips and transceiver channels. It supports multi-cycle dynamic configuration of multiple channels, perfectly adapts to the aperture imaging algorithm, and greatly improves the efficiency, resolution, and application flexibility of intravascular ultrasound imaging. 2. The communication interface modules of multiple ultrasound chips in this invention are interconnected through a shared communication link (such as a star interface and a star master clock interface architecture). This invention abandons the traditional design of multiple independent chip select lines (CS). Multiple cascaded ultrasound chips can achieve communication and synchronization with the back-end ultrasound control host with only a very small number of shared cables, which is crucial for intravascular ultrasound (IVUS) catheters with extremely demanding space constraints. At the same time, this shared network topology architecture supports easy expansion of the number of chips and can perfectly adapt to larger-scale transducer arrays. 3. This invention implements four chip ID acquisition schemes through an identification configuration unit (including dynamic accumulation using a shift register and counter, physical programming using eFuse, SSP instruction combined with logic comparison and replacement, and package pin hardening). These schemes not only eliminate the need for dedicated chip select lines, saving chip I / O area and manufacturing costs, but also provide highly flexible redundancy design for ultrasonic chips with different process nodes and packaging conditions, ensuring absolute reliability of chip address allocation after system power-on or reset. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort. Other features, objects, and advantages of the present invention will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic diagram illustrating the application scenario of the intravascular ring ultrasound imaging system in an embodiment of the present invention; Figure 2 This is a schematic diagram of the circuit principle of the intravascular ring ultrasound imaging system in an embodiment of the present invention; Figure 3 This is a cross-sectional schematic diagram of the intravascular ring ultrasound imaging system in an embodiment of the present invention; Figure 4 This is a schematic diagram of a structure of an intravascular ring ultrasound imaging system in an embodiment of the present invention; Figure 5 This is a schematic diagram of another structure of the intravascular ring ultrasound imaging system in an embodiment of the present invention; Figure 6 This is a schematic diagram of the first circuit connection of the intravascular ring ultrasound imaging system in an embodiment of the present invention; Figure 7 This is a schematic diagram of the digital control of the intravascular ring ultrasound imaging system in an embodiment of the present invention; Figure 8 This is a schematic diagram illustrating the logic for implementing chip selection and channel selection in an embodiment of the present invention; Figure 9 This is a schematic diagram of a second circuit connection for the intravascular ring ultrasound imaging system in an embodiment of the present invention; Figure 10 This is a schematic diagram of the third circuit connection of the intravascular ring ultrasound imaging system in an embodiment of the present invention; Figure 11 This is a data readback circuit diagram in an embodiment of the present invention; Figure 12This is a timing diagram of data readback in an embodiment of the present invention; Figure 13 This is a circuit diagram of the BIST module in an embodiment of the present invention; Figure 14 This is a timing diagram of capacitance measurement performed by the BIST module in an embodiment of the present invention; and Figure 15 This is a schematic diagram of the control method of the intravascular ultrasound imaging system in an embodiment of the present invention.

[0022] In the picture: 100 is the probe; 200 is the interventional catheter; 101 is the ultrasound chip; 102 is the flexible substrate; 103 is the outer membrane layer; 104 is the lumen; 105 is the transducer array; 106 is the ground electrode; 107 is the pad. Detailed Implementation

[0023] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0024] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0026] The technical solutions of the present invention and how they solve the above-mentioned technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0027] Figure 1 This is a schematic diagram illustrating the application scenario of the intravascular ring ultrasound imaging system in an embodiment of the present invention, such as... Figure 1 As shown, during intravascular ultrasound, a miniature ultrasound probe 100 is inserted into the blood vessel via an interventional catheter 200. It directly emits and receives ultrasound waves within the vessel lumen, generating a high-definition image of the vessel's cross-section in real time. This helps doctors visualize the vessel wall structure, the nature of plaques (atherosclerotic plaques), and the degree of stenosis. The probe 100 is inserted into the target vessel (primarily the coronary artery) via a peripheral vessel (such as the radial or femoral artery) through the interventional catheter. As the probe 100 rotates or translates within the vessel, it emits high-frequency ultrasound waves. These waves penetrate the vessel wall and are reflected back to the probe, where they are processed to generate a real-time image of the vessel's cross-section. The probe 100 has a diameter of approximately 2-5F (1-3 mm) and is integrated into the tip of the interventional catheter 200. The frequency of the probe 100 is typically 20-60 MHz.

[0028] Figure 2 This is a schematic diagram of the circuit principle of the intravascular ring ultrasound imaging system in an embodiment of the present invention, as shown below. Figure 2 As shown, when ultrasound is transmitted using the intravascular circular ultrasound imaging system provided by this invention, the pulse generator generates a high-voltage pulse based on the delay and phase of the electrical pulse. This high-voltage pulse triggers the transducer to vibrate and transmit ultrasound waves. During ultrasound reception, the ultrasound waves are reflected by tissue and act on the transducer, generating a signal through the positive piezoelectric effect. A low-noise amplifier amplifies the weak electrical signal output by the transducer, increasing the signal amplitude. The target echo is transmitted to the ultrasound control console through the output channel, thereby enabling image reconstruction and real-time display.

[0029] Figure 3 This is a cross-sectional schematic diagram of the intravascular ring ultrasound imaging system in an embodiment of the present invention. Figure 4 This is a schematic diagram of a structure of an intravascular ring ultrasound imaging system according to an embodiment of the present invention, such as... Figure 3 , Figure 4 As shown in the embodiment of the present invention, the intravascular ultrasound imaging system based on a ring phased array provided by the present invention includes: A ring phased array is used to achieve intravascular ultrasound imaging based on ultrasound echo signals through synthetic aperture imaging; the ring phased array includes multiple interconnected ultrasound chips 101 and a transducer array 105 correspondingly connected to each ultrasound chip 101. The multiple ultrasonic chips 101 and the transducer array 105 are arranged in a ring; The ultrasound chip 101 includes an identification configuration unit, a communication interface module, and a gating control module. The identification configuration unit is used to acquire and latch the unique local chip ID of the ultrasound chip. The communication interface modules of multiple ultrasound chips 101 are interconnected through a shared communication link. The communication interface module is used to receive communication control data, which includes the selected ultrasound chip ID and gating channel information. The gating control module is used to determine whether the ultrasound chip is selected and the gating channel based on the local chip ID and the communication control data.

[0030] The local chip ID uniquely represents the physical spatial location information of the ultrasonic chip in the ring phased array, thereby enabling the generation of corresponding delay parameters based on the physical spatial location information to control the ultrasonic wave transmission phase of the corresponding transducer array element, and to perform spatial registration and beamforming processing on the received multi-channel echo signal based on the physical spatial location information.

[0031] In one embodiment of the present invention, the control logic unit built into the ultrasonic chip generates a corresponding delay parameter based on the physical spatial location information to control the ultrasonic wave emission phase of the corresponding transducer array element; the communication interface module or data readback circuit of the ultrasonic chip is also used to associate and output physical spatial location information corresponding to the local chip ID when uploading echo signals to the host, so that the host can perform spatial registration and beamforming processing on the received multi-channel echo signals based on the physical spatial location information of each chip.

[0032] In a variation of this invention, the ultrasonic chip includes a control logic unit and a beamforming unit. The control logic unit generates corresponding delay parameters based on the physical spatial location information to control the ultrasonic wave transmission phase of the corresponding transducer element. The beamforming unit performs spatial registration and beamforming processing on the received multi-channel echo signals based on the physical spatial location information of each chip. Alternatively, the ultrasonic chip uploads physical spatial location information to the host via its communication interface module or data readback circuit, enabling the host to generate corresponding delay parameters based on the physical spatial location information and send the delay parameters to the ultrasonic chip to control the ultrasonic wave transmission phase of the corresponding transducer element. Furthermore, when uploading echo signals to the host, the host outputs physical spatial location information corresponding to the local chip ID, allowing the host to perform spatial registration and beamforming processing on the received multi-channel echo signals based on the physical spatial location information of each chip.

[0033] In one embodiment of the present invention, the ultrasonic chip is an ASIC chip, and there are six ultrasonic chips connected in sequence to form a hexahedral structure; each ASIC chip is provided with 12 transducer array elements, wherein each transducer array element can transmit and receive ultrasonic waves, but only one transducer array element is used to receive ultrasonic waves at a time.

[0034] In one embodiment of the present invention, the ultrasonic chip 101 and the transducer array 105 are disposed on a flexible substrate 102 or a cavity 104 to form a ring array, and the cavity 104 provides physical support for both the ultrasonic chip and the transducer array. In addition, a ground electrode 106 may be disposed on one side of the transducer array 105, and a pad 107 may be disposed on one side of the ultrasonic chip 101 for external electrical connection.

[0035] Figure 5 This is another structural schematic diagram of the intravascular ring ultrasound imaging system in an embodiment of the present invention, as shown below. Figure 5 As shown, the transducer array 105 is disposed on the ultrasonic chip 101.

[0036] In one embodiment of the present invention, the ultrasonic chip 101 and the transducer array 105 are disposed on the cavity 104 to form a ring array, and the cavity 104 provides physical support for the ultrasonic chip 101 and the transducer array 105. The ultrasonic chip 101 and the transducer array 105 are covered by an outer membrane layer 103. The outer membrane layer 103 can be made of PDMS (polydimethylsiloxane), a polymer material based on parylene, or synthetic rubber. The acoustic impedance of the PDMS layer is well-matched to common media such as biological tissues. When the transducer is used in biomedical detection and other fields, it helps the ultrasonic signal to be better transmitted between the device and the external medium, reducing reflections and energy losses caused by acoustic impedance mismatch. For example, in ultrasonic imaging, it makes the transmitted and received ultrasonic signals clearer, improving image quality. The PDMS layer has good chemical stability and flexibility, protecting the transducer from the influence of the external environment, such as preventing water vapor, dust, and other contaminants from corroding the device. It also buffers external mechanical stress, reducing damage to the transducer caused by vibration and impact, thus improving the reliability and service life of the device. Parylene series (such as F-VT4, C, N) can also be used as acoustic impedance matching layers to reduce acoustic energy reflection and improve transducer sensitivity and imaging quality; with excellent film properties, they can isolate external erosion and ensure the service life of transducers in complex environments; at the same time, they have good biocompatibility and are suitable for medical scenarios such as in vivo ultrasound detection and wearable ultrasound patches.

[0037] In one embodiment of the present invention, the ultrasonic chip 101 includes multiple transmitting channels and one receiving channel; The transducer array 105 includes multiple transducer array elements; The transmission channel corresponds one-to-one with the transducer array element and is used to generate pulse electrical signals to drive the transducer array element to emit ultrasonic waves. It is configured to be able to activate multiple transmission channels simultaneously for transmission according to instructions. The receiving channel is configured to receive and process echo signals from different transducer channels according to instructions, so that the ultrasonic chip can traverse all transducer array elements. A switching switch is used to switch the transducer array element connected to or disconnected from the transmit and receive channels.

[0038] In this embodiment of the invention, the transmitting channel includes a pulse generator for transmitting the pulse electrical signal; The receiving channel includes a low-noise amplifier, a cable driver, and a buffer (BUF); the low-noise amplifier is used by the low-noise amplifier (LNA) to reduce noise and amplify the weak electrical signal output by the transducer, thereby improving the signal-to-noise ratio; the cable driver is used to enhance the driving capability of the cable to enhance and stabilize the output signal.

[0039] The cable driver and the buffer are connected in parallel. The cable driver is used for the output of the echo signal, i.e., the output of the analog signal, and the buffer is used for the signal output of the BIST functional module, i.e., the output of the digital signal.

[0040] Combination Figures 6 to 10 The schematic diagram of the serial connection shown illustrates that the ultrasound chip 101 includes a shift register, an SR input interface, an SR output interface, and an SR clock interface. The shift registers of multiple ultrasound chips 101 are serially cascaded, specifically, the SR output interface of the preceding ultrasound chip 101 is connected to the SR input interface of the following ultrasound chip 101, thereby realizing the serial cascading of the shift registers of multiple ultrasound chips 101. Thus, SR data input through the SR input interface of one ultrasound chip 101 can be used to write the chip ID to all ultrasound chips 101.

[0041] Under the synchronous drive of the SR clock signal, the SR data is transmitted step by step from the first ultrasound chip, and is accumulated sequentially according to the counter. The result is stored and latched as the local chip ID. The SR clock signal is used to synchronize the shift register data shifting and transmission between adjacent ultrasound chips.

[0042] In one embodiment of the present invention, the SR clock interfaces of a plurality of interconnected ultrasound chips 101 are interconnected to form a star-shaped SR clock interface, which is used to acquire the SR clock signal transmitted by the inter-chip daisy chain when the shift register read / write operation is activated.

[0043] The SR clock interface is used to receive inter-chip daisy-chain transmission clocks, which are obtained through master frequency division. This improves the reliability of inter-chip transmissions and signal (such as chip ID) readouts.

[0044] In this embodiment of the invention, the chip ID is a unique chip identifier implemented in four ways: Method 1: Temporary writing via shift register. The 17-bit shift register includes 16 bits for the chip ID in the chip identification section and 1 bit for the flag signal. The chip ID source (SR or eFuse) is selected by the sel signal and latched to the latch module.

[0045] When reading the ID through the shift register, the master control state machine enters the "read ID" state, and serially outputs the chip ID and identification signal through the shift register to determine the relative position of the chip.

[0046] Method 2: Electronic fuse (eFuse) programming to permanently store the chip ID; the identification configuration unit includes a non-volatile memory element, which has the local chip ID pre-programmed and fixed before chip integration; Method 3: The identification configuration unit includes a shift register, and the shift registers of multiple ultrasound chips are cascaded in series; the ultrasound chip receives an initialization command through the communication interface module to configure an initial ID value, and accumulates the ID value inside the chip and transmits it to the next stage ultrasound chip through the cascaded signal line. After comparison and update, the ID value is latched as the local chip ID. In this embodiment of the invention, the third method specifically involves: the identifier configuration unit including a shift register and a comparison logic circuit, wherein the shift registers of multiple ultrasound chips are cascaded; for example... Figure 9 As shown, the process of acquiring and latching the local chip ID includes: setting the SR data input terminal of the first ultrasound chip to zero; inputting an instruction through the communication interface module to set the shift register of each ultrasound chip to the same initial value; incrementing the value of each ultrasound chip's shift register by one and writing it to the next-level ultrasound chip; comparing the input chip ID with the value in the current shift register through the comparison logic circuit; if the input chip ID is greater than the current value, replacing the current value with the input chip ID; otherwise, keeping it unchanged; repeating the above shift and comparison operations a preset number of times to complete the ID fixing of all chips, and setting an initialization completion status flag internally for reading, and finally latching it as the local chip ID.

[0047] Method 4: The identification configuration unit includes multiple reserved hardware pins. During chip packaging, the local chip ID is determined and latched in the form of hardware physical encoding by fixing the hardware pins to high or low levels respectively.

[0048] To achieve high-reliability interconnection, the ultrasonic chip 101 includes a data interface and a master clock interface; the data interfaces of multiple interconnected ultrasonic chips 101 are interconnected to form a star interface; the clock interfaces of multiple interconnected ultrasonic chips 101 are interconnected to form a star master clock interface, so as to achieve unified reception of the master clock. The master clock is used for signal transmission of the communication interface module and the clock of the entire ultrasonic chip 101.

[0049] Figure 10 This is a schematic diagram of a third circuit connection for the intravascular ring ultrasound imaging system in an embodiment of the present invention. Figure 11 This is a data readback circuit diagram in an embodiment of the present invention, such as... Figure 10 , Figure 11 As shown, the ultrasound chip also includes a data readback circuit, which includes a bidirectional low-voltage differential signal LVDS buffer, a tri-state buffer, and a selection switch. The data readback circuit includes two data readback paths: The first approach is to enable and share the bidirectional LVDS buffer for data readback by configuring the LVDS output enable signal. The second approach is to configure a multiplexer signal to output digital readback data through the tri-state buffer and to share the output line with the cable driver (CD) output via a selector switch for data readback.

[0050] In this embodiment of the invention, when data is read back through the bidirectional LVDS buffer via the first path, the readback data may flow back to the chip input terminal because all the ultrasound chips share the same set of LVDS input terminals. Therefore, the main control state machine inside the ultrasound chip is equipped with an isolation circuit to block the input of invalid data.

[0051] Combination Figure 12 As shown in the timing diagram of data readback in this embodiment of the invention, the ultrasonic chip 101 is internally configured with a timing control circuit for controlling the sampling timing of serial data output. The timing control circuit is configured to generate a sampling period signal for each ultrasonic chip based on the system clock, and generate a sampling signal offset by half a frequency division period relative to the sampling period signal. The sampling signal is used as a trigger point for data state update, so that the sampling point of the data is offset by the sampling signal of half a frequency division period to ensure the stability of data sampling.

[0052] Figure 8 This is a schematic diagram illustrating the logic of chip selection and channel selection in an embodiment of the present invention, such as... Figure 8 As shown, in one embodiment of the present invention, the ultrasonic chip 101 includes a master state machine (FSM) and a gating control module; The shared communication link is specifically distributed in a star topology; the communication interface module includes a data parser; the data parser is used to parse the received communication control data to determine the transmitting chip ID, transmitting channel, receiving chip ID, and receiving channel.

[0053] In the absence of a CS (Chip Select) line, a 4-bit header needs to be added before the communication control data in order to distinguish the start bit of the data, and the transmitted data is fixed-length data.

[0054] If the header is 4'b1001, the initial 4 bits of the SPI input register on the chip need to perform header detection logic. This logic is only enabled in the idle state. When 4'b1001 is detected in the idle state, an identification signal is output, triggering the state machine to transition to the data loading mode. Then, a 7-bit counter controls the loading of fixed-length data until the data loading is complete.

[0055] In this embodiment of the invention, the gating channel includes a transmitting channel and a receiving channel; the number of gating channels for the transmitting channel and the receiving channel can be set, such as gating two transmitting channels and one receiving channel.

[0056] In this embodiment of the invention, communication control data enters the ultrasonic chip 101 through the data interface, is converted into local control commands by the LVDS receiver, and is then parsed by the communication interface module.

[0057] The master clock enters the ultrasonic chip 101 through the master clock interface and is converted into a local clock by the LVDS receiver.

[0058] The communication interface module includes a parser; The parser is used to parse the local control command to determine the transmitter chip ID, transmitter channel, receiver chip ID, and receiver channel; The gating control module is used to determine whether the ultrasonic chip 101 is selected based on the chip ID latched in the shift register, and to determine the gating channel of the chip based on the channel gating information obtained from the star interface. The master control state machine is used to generate a channel enable signal according to the selected channel, so that the transmitting channel drives the corresponding transducer array element to emit ultrasonic waves.

[0059] In this embodiment of the invention, the master state machine (FSM) is used to coordinate the switching of the ultrasound chip between multiple states, and the core states include: Idle state (IDLE), waiting for the table header to be triggered; The electronic fuse (eFuse) is in the write state. The chip ID is written according to the communication control data 101. After completion, it returns to the idle state. The shift register write status is written to the chip ID through cascaded shift registers and then latched. Read the ID status, activate the cascaded shift register, and serially output the chip ID and identification signal; TR mode controls the transmission and reception timing and activates the channel according to instructions; BIST mode measures the transducer's connection capacitance to achieve hardware calibration.

[0060] In this embodiment of the invention, the gating control module generates a chip select enable (CS) by comparing the target chip ID in the communication control data with the chip ID stored locally. The gating control module can control two ultrasonic chips 101 to generate ultrasonic waves simultaneously and one ultrasonic chip 101 to receive the echo. Each chip has 12 transmit channels, which are continuously activated by commands; Each chip has one receiving channel, which can be directly selected via address.

[0061] Figure 13 The circuit diagram of the BIST module in an embodiment of the present invention is shown below. Figure 2 , Figure 13 As shown, the ultrasound chip 101 includes a BIST module; The BIST function module is used to measure the low-frequency capacitance of the connection node between each transducer element and the ultrasonic chip 101 to determine the connection status of each transducer element and the ultrasonic chip 101.

[0062] In this embodiment of the invention, the BIST module includes: a comparator and a current source I. ref Capacitor C ref Capacitor C x Switches EN_CAL, EN_IN, UP, and DOWN; The current source I ref One end is connected to the non-inverting input of the comparator via a switch UP, and the other end is connected to the power supply terminal V. dd The inverting input of the comparator is connected to the reference voltage terminal V. ref One end of the DOWN switch is connected to the non-inverting input of the comparator, and the other end is connected to the power supply terminal V. ss ; The capacitor C ref One end is connected via switch EN_CAL, and the other end is connected via switch UP to the current source I. ref The other end is connected to the power supply terminal V. ss ; The capacitor C x One end is connected via switch EN_IN, and the other end is connected via switch UP to the current source I.ref The other end is connected to the power supply terminal V. ss ; The transducer array element is connected to the current source I via switch UP. ref .

[0063] In this embodiment of the invention, the device is configured to BIST mode via SPI instructions, the current source is activated, and the measurement is divided into three cycles: Period 1: EN_IN=0, EN_CAL=0, measure transducer capacitance Cp; Period 2: EN_CAL=1, measure Cp+Cref (reference capacitance); Period 3: EN_IN=1, measure Cp+Cx (external capacitor).

[0064] Figure 14 The timing sequence for capacitance measurement by the BIST module in this embodiment of the invention is as follows: Figure 14 As shown, when the BIST function module is enabled, the current source is controlled to charge and discharge, the node voltage is compared with the reference voltage Vref, and the charging and discharging time is calculated. The difference in capacitance leads to different charging and discharging rates, and the comparator COMP outputs pulses of different widths. Then, the output BISTOUT is determined by combining the switching states of the switches UP and DOWN. Subsequently, it can be decoded into a specific capacitance value by digital circuitry.

[0065] In one embodiment of the present invention, the system further includes a watchdog timer module, which is integrated within the ultrasonic chip 101 to prevent host crashes and ASIC malfunctions. When the host fails to trigger the watchdog signal within a specified time, the watchdog timer module automatically generates a reset operation. The watchdog timer module has an enable signal and a watchdog interval, and the watchdog operation is implemented by configuring relevant registers. The interval can be selected between 1 second and 15 seconds, with a step size of 1 second. The watchdog timer module internally includes three counters, used to generate time base signals of 1 microsecond, 1 millisecond, and 1 second, respectively; the use of multi-level counter cascaded design effectively reduces power consumption compared to using a single large-bit-width counter.

[0066] Figure 15 This is a schematic diagram of the control method of the intravascular ultrasound imaging system in an embodiment of the present invention, as shown below. Figure 15 As shown, the control method for the intravascular ultrasound imaging system provided by the present invention includes the following steps: Step S1: Control or trigger the identification configuration unit so that all ultrasound chips acquire and latch their corresponding local chip IDs; Step S2: Based on the received communication control data, determine the chip ID and transmission channel of the transmitting signal, as well as the chip ID and reception channel of the receiving signal; In this embodiment of the invention, communication control data including transmitter chip ID, receiver chip ID, channel address, duration, and waveform sent from the outside is received; The master state machine (FSM) parses the instructions and generates the chip ID for chip selection and the sequence number for channel selection.

[0067] Step S3: Activate the transmission channel of the target chip according to the chip ID of the transmitted signal and the transmission channel to drive the transducer array element to emit ultrasonic waves; Step S4: Activate the receiving channel of the target chip to receive the echo signal according to the chip ID of the received signal and the receiving channel; Step S5: Dynamically adjust and activate multiple ultrasound chips and transmission channels to regulate the transmission aperture and sound intensity, and then generate a complete intravascular ultrasound image by processing the multi-cycle echo signals through the synthetic aperture.

[0068] In this embodiment of the invention, two ultrasound chips can be activated simultaneously to transmit ultrasound waves, and one ultrasound chip can be activated to receive them. The ID1 of the two transmitting chips, the ChipID of the receiving chip, and the channel address are adjusted sequentially via communication control data, traversing all channels of the 64-element transducer. Each set of echo signals is labeled with the chip ID and channel information for easy differentiation by the algorithm layer. By delaying and superimposing multi-cycle data and performing focusing processing, the propagation time difference between different channels is compensated, generating a high-resolution blood vessel wall image.

[0069] In this embodiment of the invention, by combining modular hardware design with precise timing control and algorithmic collaboration, the limitations of traditional intravascular ultrasound are overcome, realizing an integrated system with flexible imaging, simplified connection, and self-calibration, providing a more efficient technical solution for intravascular ultrasound diagnosis.

[0070] In this embodiment of the invention, the ring phased array includes multiple interconnected ultrasound chips and transducer arrays. By combining the communication interface module with the gating control module, gating is performed by comparing the local chip ID with the received communication control data. This mechanism breaks the limitations of traditional fixed ultrasound channels, enabling extremely flexible configuration of ultrasound chips and transceiver channels. It supports multi-cycle dynamic configuration of multiple channels, perfectly adapts to the integrated aperture imaging algorithm, and greatly improves the efficiency, resolution, and application flexibility of intravascular ultrasound imaging. The communication interface modules of multiple ultrasound chips in this invention are interconnected through a shared communication link (such as a star interface and a star master clock interface architecture), thus abandoning the traditional design of multiple independent chip select lines (CS). Multiple cascaded ultrasound chips require only a very small number of shared cables to achieve communication and synchronization with the back-end ultrasound control host, which is crucial for intravascular ultrasound (IVUS) catheters with extremely demanding space constraints. At the same time, this shared network topology architecture supports easy expansion of the number of chips and can perfectly adapt to larger-scale transducer arrays. This invention implements four chip ID acquisition schemes through an identification configuration unit (including dynamic accumulation using a shift register and counter, physical programming using eFuse, SSP instruction combined with logical comparison and replacement, and package pin hardening). These schemes not only eliminate the need for dedicated chip select lines, saving chip I / O area and manufacturing costs, but also provide highly flexible redundancy design for ultrasonic chips with different process nodes and packaging conditions, ensuring absolute reliability of chip address allocation after system power-on or reset.

[0071] This invention addresses the issue of limited pin resources in ultrasonic chips by designing two multiplexing paths for the data readback circuit: a shared bidirectional LVDS buffer or a shared analog CD output line. More importantly, when using the shared bidirectional LVDS for data readback, the internal master state machine (FSM) cleverly integrates an isolation circuit, completely preventing logical errors caused by readback data flowing back to the chip input on the shared bus. This ensures absolute data security and high reliability when switching between pure digital configuration instructions and readback data on the same physical channel. Regarding the timing control of data readback, this invention internally generates a sampling signal offset by half a cycle relative to the frequency divider signal as the trigger point. This design cleverly places the data sampling point in the exact middle of the data transmission cycle, ensuring stable and accurate data sampling and output without adding an additional external synchronization clock line, significantly improving the system's anti-interference capability in complex electromagnetic environments. This invention integrates a BIST (Built-in Self-Test) module, which can quickly and accurately check the health status of each transducer array element and the connection node of the ultrasound chip through internal low-frequency capacitance measurement, realizing self-calibration and fault warning of hardware connection. In addition, the underlying chip adopts BCD technology, which can support high-voltage transmission pulses above 30V, significantly improving the penetration depth of ultrasound signals in human tissue and the echo signal intensity, and significantly improving the signal-to-noise ratio (SNR) of the final image.

[0072] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0073] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. An intravascular ultrasound imaging system based on a ring phased array, characterized in that, include: A ring phased array includes multiple interconnected ultrasonic chips and a transducer array connected to each ultrasonic chip; the multiple ultrasonic chips and the transducer array are arranged in a ring. The ultrasonic chip includes an identification configuration unit, a communication interface module, and a gating control module; the identification configuration unit is used to acquire and latch the unique local chip ID of the ultrasonic chip. The communication interface modules of multiple ultrasound chips are interconnected through a shared communication link; the communication interface module is used to receive communication control data, which includes the selected ultrasound chip ID and selection channel information; the selection control module is used to determine whether the ultrasound chip is selected and the selection channel based on the local chip ID and the communication control data. The local chip ID uniquely represents the physical spatial location information of the ultrasonic chip in the ring phased array, thereby enabling the generation of corresponding delay parameters based on the physical spatial location information to control the ultrasonic wave transmission phase of the corresponding transducer array element, and to perform spatial registration and beamforming processing on the received multi-channel echo signal based on the physical spatial location information.

2. The intravascular ultrasound imaging system based on a ring phased array according to claim 1, characterized in that, The identifier configuration unit acquires and latches the local chip ID through any of the following methods: Method 1: The identification configuration unit includes a shift register and a counter, and the shift registers of multiple ultrasound chips are cascaded in series; signal transmission is performed between adjacent ultrasound chips, and SR data is transmitted step by step from the first ultrasound chip under the synchronous drive of the SR clock signal, and is accumulated sequentially according to the counter, and the result is stored and latched as the local chip ID. The SR clock signal is used to synchronize the shift register data shifting and transmission between adjacent ultrasound chips. Method 2: The identification configuration unit includes a non-volatile memory element, which has the local chip ID pre-programmed and embedded before chip integration; Method 3: The identification configuration unit includes a shift register, and the shift registers of multiple ultrasound chips are cascaded in series; the ultrasound chip receives an initialization command through the communication interface module to configure an initial ID value, and accumulates the ID value inside the chip and transmits it to the next stage ultrasound chip through the cascaded signal line. After comparison and update, the ID value is latched as the local chip ID. Method 4: The identification configuration unit includes multiple reserved hardware pins. During chip packaging, the local chip ID is determined and latched in the form of hardware physical encoding by fixing the hardware pins to high or low levels respectively.

3. The intravascular ultrasound imaging system based on a ring phased array according to claim 1, characterized in that, The ultrasonic chip includes a data interface and a master clock interface; The data interfaces of multiple interconnected ultrasound chips are interconnected to form a star interface; The clock interfaces of multiple interconnected ultrasound chips are interconnected to form a star-shaped master clock interface to achieve unified reception of the master clock.

4. The intravascular ultrasound imaging system based on a ring phased array according to claim 1, characterized in that, The ultrasonic chip also includes a data readback circuit, which includes a bidirectional low-voltage differential signal LVDS buffer, a tri-state buffer, and a selection switch. The data readback circuit includes two data readback paths: The first approach is to enable and share the bidirectional LVDS buffer for data readback by configuring the LVDS output enable signal. The second approach is to configure a multiplexer signal so that the digital readback data is output through the tri-state buffer and the data is read back by sharing the output line with the cable driver output via a selector switch.

5. The intravascular ultrasound imaging system based on a ring phased array according to claim 1, characterized in that, The ultrasonic chip is internally equipped with a timing control circuit for controlling the sampling timing of serial data output; The timing control circuit is configured to generate a sampling period signal for each ultrasound chip based on the system clock, and to generate a sampling signal offset by half a frequency division period relative to the sampling period signal. The sampling signal is used as a trigger point for data state updates, so that the sampling point of the data is offset by the sampling signal of half a frequency division cycle, so as to ensure the stability of data sampling.

6. The intravascular ultrasound imaging system based on a ring phased array according to claim 1, characterized in that, The ultrasonic chip includes multiple transmission channels and one receiving channel; The transducer array includes multiple transducer array elements; The transmission channel corresponds one-to-one with the transducer array element and is used to generate pulse electrical signals to drive the transducer array element to emit ultrasonic waves. It is configured to be able to activate multiple transmission channels simultaneously for transmission according to instructions. The receiving channel is used to receive echo signals from different transducer channels, so that the ultrasonic chip can traverse all transducer array elements. A switching switch is used to switch the transducer array element connected to or disconnected from the transmit and receive channels.

7. The ultrasonic imaging system based on a ring phased array according to claim 2, characterized in that, In the first method, the ultrasound chip further includes an SR clock interface; The SR clock interfaces of multiple interconnected ultrasound chips are interconnected to form a star-shaped SR clock interface for acquiring the SR clock signal.

8. The intravascular ultrasound imaging system based on a ring phased array according to claim 1, characterized in that, The ultrasound chip includes an SR input interface and an SR output interface; The SR output interface of the aforementioned ultrasound chip is connected to the SR input interface of the latter ultrasound chip, thereby realizing the serial cascading of the shift registers of multiple ultrasound chips.

9. The intravascular ultrasound imaging system based on a ring phased array according to claim 1, characterized in that, The shared communication link is specifically distributed in a star topology. The communication interface module includes a data parser; the data parser is used to parse the received communication control data to determine the transmitter chip ID, transmitter channel, receiver chip ID, and receiver channel.

10. A control method based on the ultrasound imaging system according to any one of claims 1-9, characterized in that, Includes the following steps: Step S1: Control or trigger the identification configuration unit so that all ultrasound chips acquire and latch their corresponding local chip IDs; Step S2: Based on the received communication control data, determine the chip ID and transmission channel of the transmitting signal, as well as the chip ID and reception channel of the receiving signal; Step S3: Activate the transmission channel of the target chip according to the chip ID of the transmitted signal and the transmission channel to drive the transducer array element to emit ultrasonic waves; Step S4: Activate the receiving channel of the target chip to receive the echo signal according to the chip ID of the received signal and the receiving channel; Step S5: Dynamically adjust and activate multiple ultrasound chips and transmission channels to regulate the transmission aperture and sound intensity, and then generate a complete ultrasound image by synthesizing the multi-cycle echo signals through the aperture processing.

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